JP3176268B2 - Package for storing semiconductor elements - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device housing package for housing a semiconductor device.

[0002]

2. Description of the Related Art Conventionally, a semiconductor element housing package for housing a semiconductor element, particularly a semiconductor integrated circuit element such as an LSI, is generally formed of an electrically insulating material such as an aluminum oxide sintered body, and has a substantially central upper surface. An insulating base having a plurality of metallized wiring layers made of a refractory metal powder of tungsten, molybdenum, manganese or the like led out from the periphery to the outer periphery of the recess for mounting and housing the semiconductor element, A plurality of external lead terminals attached to the metallized wiring layer via a brazing material such as silver brazing to electrically connect each electrode to an external electric circuit,
A semiconductor element is adhered and fixed to the bottom surface of the concave portion of the insulating base via an adhesive made of glass, resin, brazing material, etc., and each electrode of the semiconductor element is bonded to a predetermined metallized wiring layer by a bonding wire. And a lid is bonded to the upper surface of the insulating base via a sealing material such as glass or resin, and the semiconductor element is hermetically housed in a container including the insulating base and the lid. It becomes a semiconductor device as a product.

[0003]

However, in this conventional package for accommodating a semiconductor element, the metallized wiring layer is usually formed of a refractory metal powder such as tungsten having a particle size of about 1.2 μm. The surface roughness of the layer is about 0.3 μm in center line average roughness (Ra).
m and a maximum height (Rmax) of about 1.2 μm, which is smooth.

Therefore, when an external lead terminal is brazed to this metallized wiring layer via a brazing material such as a silver brazing material, the bonding strength of the brazing material to the metallized wiring layer becomes weak,
There is a disadvantage that the external lead terminal is separated from the metallized wiring layer by applying a small external force.

Particularly, in recent semiconductor package packages, the line width of the metallized wiring layer and the external lead terminals is about 0.5 mm with the increase in the number of electrodes due to the high density and high integration of the semiconductor elements housed therein. And the above-mentioned drawbacks have become more remarkable because the brazing area of both has become narrower.

[0006]

A package for accommodating a semiconductor device according to the present invention comprises: an insulating base having a plurality of metallized wiring layers; and a plurality of external lead terminals brazed to a part of the metallized wiring layers. A semiconductor element housing package for hermetically housing the semiconductor element inside a container formed of an insulating base and a lid, wherein the surface of an area where external lead terminals of the metallized wiring layer are to be brazed. The roughness is center line average roughness (Ra) 0.5 μm ≦ Ra ≦
1 μm, 2 μm ≦ Rmax ≦ 4 at maximum height (Rmax)
μm, and the surface roughness of the metallized wiring layer other than the region where the external lead terminals are to be brazed is 0.2 μm ≦ Ra ≦ 0.4 μm in center line average roughness (Ra), and the maximum height (Rmax). 0.8 μm ≦ Rmax ≦ 1.6 μm
It is characterized by being.

[0007]

According to the package for accommodating a semiconductor element of the present invention, the surface roughness of the region of the metallized wiring layer to which the external lead terminals are to be brazed is 0.5 by the center line average roughness (Ra).
μm ≦ Ra ≦ 1 μm, maximum height (Rmax) 2 μm ≦
By setting Rmax ≦ 4 μm and appropriately roughening, it is possible to increase the bonding area between the metallized wiring layer and the brazing material while improving the wettability of the brazing material with respect to the metallized wiring layer. It becomes possible to very firmly braze the metallized wiring layer.

Further, according to the semiconductor device housing package of the present invention, the surface roughness of the metallized wiring layer other than the region where the external lead terminals are to be brazed is determined by the center line average roughness (Ra).
At 0.2 μm ≦ Ra ≦ 0.4 μm, maximum height (Rma
Since 0.8 μm ≦ Rmax ≦ 1.6 μm in x), when the electrode of the semiconductor element is electrically connected to the metallized wiring layer via the bonding wire, the bonding between the bonding wire and the metallized wiring layer becomes extremely strong. This ensures that each electrode of the semiconductor element is connected to an external electrical circuit,
It is possible to make a strong electrical connection.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the accompanying drawings. 1 and 2 show an embodiment of a package for housing a semiconductor element according to the present invention, wherein 1 is an insulating base,
2 is a lid. The insulating base 1 and the lid 2 constitute a container 4 for housing the semiconductor element 3.

The insulating base 1 has a recess 1a in the center of the upper surface thereof for forming a space for accommodating the semiconductor element 3, and the semiconductor element 3 is mounted on the bottom of the recess 1a.
It is bonded and fixed via an adhesive such as glass, resin, brazing material or the like.

The insulating substrate 1 is made of an electrically insulating material such as an aluminum oxide sintered body, a mullite sintered body, an aluminum nitride sintered body, a silicon carbide sintered body, and a glass ceramic sintered body. When it is made of an aluminum sintered body, a suitable organic binder, a solvent, etc. are added to raw material powders such as aluminum oxide, silicon oxide, magnesium oxide, calcium oxide, etc. to form a slurry, and the slurry is doctor bladed. Ceramic green sheet (ceramic green sheet) by applying the method or calender roll method. Thereafter, the ceramic green sheet is subjected to an appropriate punching process, and a plurality of the green sheets are laminated, and a temperature of about 1600 ° C. It is manufactured by firing.

A plurality of metallized wiring layers 5 are formed on the insulating substrate 1 from the periphery of the concave portion 1a to the outer peripheral edge, and each electrode of the semiconductor element 3 is bonded to the peripheral portion of the metallized wiring layer 5 at the concave portion 1a. External lead terminals 7 electrically connected via wires 6 and connected to an external electric circuit at a portion led out to the upper surface of the insulating base 1 are brazed and attached via a brazing material 8 such as silver brazing. Have been.

The metallized wiring layer 5 functions as a conductive path for connecting each electrode of the semiconductor element 3 to an external electric circuit, and is formed of a high melting point metal powder such as tungsten, molybdenum, manganese or the like.

Further, as shown in FIG. 2, the metallized wiring layer 5 has a surface roughness of a region A where the external lead terminals 7 are to be brazed at a center line average roughness (Ra) of 0.5 μm ≦ Ra ≦ 1.
μm, maximum height (Rmax) 2 μm ≦ Rmax ≦ 4μ
m, whereby the surface of the metallized wiring layer 5 has an appropriate roughness, and the bonding area between the metallized wiring layer 5 and the brazing material 8 is large while improving the wettability of the brazing material 8 to the metallized wiring layer 5. As a result, the external lead terminals 7 can be extremely firmly brazed to the metallized wiring layer 5.

The surface roughness of the region A where the external lead terminals 7 of the metallized wiring layer 5 are to be brazed has a center line average roughness (Ra) of 0.5 μm> Ra and a maximum height (R).
If (max) satisfies 2 μm> Rmax, the surface of the metallized wiring layer 5 becomes smooth, so that the external lead terminals 7 cannot be firmly brazed to the metallized wiring layer 5 and the center line average roughness (Ra) Is 1 μm <Ra,
Further, when the maximum height (Rmax) is 4 μm <Rmax, when the external lead terminals 7 are brazed to the metallized wiring layer 5 via the brazing material 8, the spread of the brazing material 8 on the surface of the metallized wiring layer 5 becomes poor. As a result, the external lead terminals 7 cannot be firmly brazed to the metallized wiring layer 5. Therefore, the surface roughness of the region A where the external lead terminal 7 of the metallized wiring layer 5 is to be brazed is 0.5 μm ≦ Ra ≦ 1 μm in center line average roughness (Ra) and 2 μm ≦ maximum height (Rmax). It is specified in the range of Rmax ≦ 4 μm.

The metallized wiring layer 5 has a surface roughness other than a region A to which the external lead terminals 7 are brazed, specifically, a surface roughness of a region B located around the concave portion 1a to which the bonding wire 6 is bonded. Center line average roughness (Ra)
At 0.2 μm ≦ Ra ≦ 0.4 μm, maximum height (Rma
If 0.8 μm ≦ Rmax ≦ 1.6 μm in x), when each electrode of the semiconductor element 3 is electrically connected to the metallized wiring layer 5 via the bonding wire 6, the bonding between the bonding wire 6 and the metallized wiring layer 5 is performed. Is extremely strong, and each electrode of the semiconductor element 3 can be reliably and firmly electrically connected to an external electric circuit. Therefore, the metallized wiring layer 5 has a surface roughness of 0.2 μm ≦ Ra ≦ 0.4 μm and a maximum height (Rmax) in the center line average roughness (Ra) other than the region A where the external lead terminals 7 are brazed.
Is preferably set to 0.8 μm ≦ Rmax ≦ 1.6 μm.

Further, the metallized wiring layer 5 is provided with a good conductive material such as nickel or gold, a corrosion resistance and a brazing material 8 on its surface.
Metal having good wettability with a plating method of 1 μm to 2 μm.
If it is layered to a thickness of 0 μm, the metallized wiring layer 5
Of the metallized wiring layer 5 and the bonding wires 6 and the brazing of the metallized wiring layer 5 and the external lead terminals 7 via the brazing material 8 more firmly. Can be. Therefore, it is necessary to prevent the metallized wiring layer 5 from being oxidized and corroded, and to make the connection between the metallized wiring layer 5 and the bonding wire 6 and the brazing between the metallized wiring layer 5 and the external lead terminals 7 more firm. It is preferable that nickel, gold, or the like be layered on the surface of the substrate to a thickness of 1 μm to 20 μm.

The metallized wiring layer 5 is made of tungsten,
A metal paste obtained by adding a suitable organic binder, a solvent, a plasticizer, and the like to a high melting point metal powder such as molybdenum and manganese is mixed with a thick film technique such as a conventionally known screen printing method to form an insulating substrate 1. By printing and applying a predetermined pattern on the ceramic green sheet in advance, the ceramic green sheet is formed from the periphery of the concave portion 1a of the insulating base 1 to the outer peripheral end thereof,
In this case, two kinds of metal pastes, one having a high melting point metal powder having a particle diameter of 0.8 μm to 1.3 μm and one having a particle diameter of 1.5 μm to 3 μm, are prepared, and the particle diameter of the high melting point metal powder is 0.8 μm. A pattern on the peripheral side of the concave portion 1a of the insulating substrate 1 is formed with a metal paste having a thickness of 1.5 to 1.3 μm, and a pattern on the outer peripheral end side of the insulating substrate 1 is formed with a metal paste having a particle size of the high melting point metal powder of 1.5 to 3 μm. Is formed, the surface roughness of the region A of the metallized wiring layer 5 to which the external lead terminals 7 are brazed is reduced by the center line average roughness (R
In a), 0.5 μm ≦ Ra ≦ 1 μm, maximum height (Rma
x), 2 μm ≦ Rmax ≦ 4 μm, and the surface roughness other than the region A to which the external lead terminal 7 is brazed is 0.2 μm ≦ Ra ≦ 0.4 μm in the center line average roughness (Ra), and the maximum height ( Rmax) can satisfy 0.8 μm ≦ Rmax ≦ 1.6 μm.

On the other hand, the external lead terminals 7 brazed to the metallized wiring layer 5 serve to connect the semiconductor element 3 housed therein to an external electric circuit, and connect the external lead terminals 7 to the external electric circuit board. Each electrode of the semiconductor element 3 housed therein by bonding to the wiring conductor via solder or the like is electrically connected to an external electric circuit via the bonding wire 6, the metallized wiring layer 5, and the external lead terminal 7. Become.

The external lead terminals 7 are made of a metal material such as an iron-nickel-cobalt alloy or an iron-nickel alloy.
The ingot (lumps) of the iron-nickel-cobalt alloy or the like is formed into a predetermined shape by performing a conventionally known metal working method such as a rolling method or a punching method.

The external lead terminal 7 may be formed by plating a metal having good conductivity and excellent corrosion resistance, such as nickel or gold, to a thickness of 1 μm to 20 μm on its surface by plating. 7 can be effectively prevented, and the electrical connection between the external lead terminal 7 and the external electric circuit can be made good. Therefore, it is preferable that nickel, gold, or the like be layered on the surface of the external lead terminal 7 to a thickness of 1 μm to 20 μm by plating.

Further, the insulating substrate 1 to which the external lead terminals 7 are attached is made of glass, and
The semiconductor elements 3 are joined via a sealing material made of a resin, a brazing material, or the like, so that the semiconductor element 3 is hermetically accommodated in a container 4 formed of the insulating base 1 and the lid 2.

The lid 2 is made of an aluminum oxide sintered body,
Made of electrical insulating material such as mullite sintered compact, aluminum nitride sintered compact, silicon carbide sintered compact, glass ceramic sintered compact, or metallic material such as iron-nickel-cobalt alloy, iron-nickel alloy, copper For example, when it is made of an aluminum oxide-based sintered body, a raw material powder such as aluminum oxide, silicon oxide, magnesium oxide, and calcium oxide is filled in a predetermined press mold, and is pressed at a constant pressure to be molded. Then, the molded article is manufactured by firing at a temperature of about 1500 ° C.,
In the case of a metal material such as an iron-nickel-cobalt alloy, the ingot is manufactured into a predetermined shape by subjecting the ingot of the iron-nickel-cobalt alloy to a conventionally known metal working method such as a rolling method or a punching method. .

Thus, according to the above-described package for accommodating a semiconductor element, the semiconductor element 3
And the semiconductor element 3 is made of glass, resin,
The electrodes of the semiconductor element 3 are connected and fixed to a predetermined metallized wiring layer 5 via bonding wires 6, and then a cover is formed on the upper surface of the insulating base 1. 2 is bonded via a sealing material made of glass, resin, brazing material, or the like, and the semiconductor element 3 is hermetically housed in a container 4 formed of an insulating base 1 and a lid 2 to form a semiconductor device as a product. Become.

It should be noted that the present invention is not limited to the above-described embodiment, and various changes can be made without departing from the scope of the present invention. For example, as shown in FIG. Only the region where the external lead terminal 7 is to be brazed has a two-layer structure, and the surface roughness of the upper layer surface of the metallized wiring layer 5 is 0.5 μm ≦ Ra by center line average roughness (Ra).
≦ 1 μm, maximum height (Rmax) 2 μm ≦ Rmax ≦
It may be 4 μm.

[0027]

According to the semiconductor device housing package of the present invention, the surface roughness of the region of the metallized wiring layer where the external lead terminals are to be brazed is defined as a center line average roughness (Ra) of 0.
5 μm ≦ Ra ≦ 1 μm, 2 μm in maximum height (Rmax)
≦ Rmax ≦ 4 μm, and a moderately roughened surface allows the brazing material to have a good wettability with respect to the metallized wiring layer and a large bonding area between the metallized wiring layer and the brazing material, thereby allowing the external lead terminals to be provided in a predetermined manner. Can be very firmly brazed to the metallized wiring layer.

According to the package for housing a semiconductor element of the present invention, the surface roughness of the metallized wiring layer other than the region where the external lead terminals are to be brazed is determined by the center line average roughness (Ra).
At 0.2 μm ≦ Ra ≦ 0.4 μm, maximum height (Rma
Since 0.8 μm ≦ Rmax ≦ 1.6 μm in x), when the electrode of the semiconductor element is electrically connected to the metallized wiring layer via the bonding wire, the bonding between the bonding wire and the metallized wiring layer becomes extremely strong. This ensures that each electrode of the semiconductor element is connected to an external electrical circuit,
It is possible to make a strong electrical connection.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing one embodiment of a semiconductor element storage package according to the present invention.

2 is an enlarged cross-sectional view of a main part of the package for housing a semiconductor element shown in FIG. 1;

FIG. 3 is an enlarged sectional view of a main part showing another embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Insulating base 1a ... Depression 2 ... Lid 3 ... Semiconductor element 4 ... Container 5 ... Metallization Wiring layer 7 External lead terminal 8 Brazing material

Claims (1)

(57) [Claims] An insulating base having a plurality of metallized wiring layers, a plurality of external lead terminals brazed to a part of the metallized wiring layer, and a lid; A semiconductor element housing package for hermetically housing a semiconductor element inside the container, wherein a surface roughness of a region of the metallized wiring layer to which an external lead terminal is brazed has a center line average roughness (Ra) of 0. 5μm ≦ Ra ≦ 1μ
m, 2 μm ≦ Rmax ≦ 4 μm in maximum height (Rmax)
And the external lead end of the metallized wiring layer
The surface roughness of the area other than the area where
0.2 μm ≦ Ra ≦ 0.4 μm in height (Ra), maximum height
(Rmax) 0.8 μm ≦ Rmax ≦ 1.6 μm
Package for housing semiconductor chip, characterized in that that.