JP3336136B2 - Package for storing semiconductor elements - Google Patents
Package for storing semiconductor elementsInfo
- Publication number
- JP3336136B2 JP3336136B2 JP30472094A JP30472094A JP3336136B2 JP 3336136 B2 JP3336136 B2 JP 3336136B2 JP 30472094 A JP30472094 A JP 30472094A JP 30472094 A JP30472094 A JP 30472094A JP 3336136 B2 JP3336136 B2 JP 3336136B2
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- insulating base
- integrated circuit
- semiconductor integrated
- external electric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体集積回路素子を収
容するための半導体素子収納用パッケージに関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device housing package for housing a semiconductor integrated circuit device.
【０００２】[0002]
【従来の技術】従来、半導体素子、特にＬＳＩ（大規模
集積回路素子）等の半導体集積回路素子を収容するため
の半導体素子収納用パッケージは、一般にアルミナセラ
ミックス等の電気絶縁材料から成り、その上面略中央部
に半導体集積回路素子を収容するための凹所を有する絶
縁基体と、前記絶縁基体の凹所周辺から下面にかけて導
出されるタングステン、モリブデン等の高融点金属粉末
から成る複数個のメタライズ配線層と、前記絶縁基体の
下面に形成され、メタライズ配線層が電気的に接続され
る複数個の接続パッドと、前記接続パッドにロウ付け取
着される半田（鉛と錫の重量比を６：４とした共晶半
田）から成るボール状端子と、蓋体とから構成されてお
り、絶縁基体の凹所底面に半導体集積回路素子をガラ
ス、樹脂等から成る接着剤を介して接着固定させ、半導
体集積回路素子の各電極とメタライズ配線層とをボンデ
ィングワイヤを介して電気的に接続させるとともに絶縁
基体上面に蓋体をガラス、樹脂等の封止材を介して接合
させ、絶縁基体と蓋体とから成る容器内部に半導体集積
回路素子を気密に封止することによって製品としての半
導体装置となる。2. Description of the Related Art Conventionally, a semiconductor element housing package for housing a semiconductor element, especially a semiconductor integrated circuit element such as an LSI (Large Scale Integrated Circuit) is generally made of an electrically insulating material such as alumina ceramics. An insulating base having a recess for accommodating a semiconductor integrated circuit element in a substantially central portion thereof, and a plurality of metallized wirings made of a high melting point metal powder such as tungsten or molybdenum led out from the periphery of the recess to the lower surface of the insulating base. And a plurality of connection pads formed on the lower surface of the insulating base and electrically connected to the metallized wiring layer, and solder soldered to the connection pads (the weight ratio of lead to tin is 6: 4, a ball-shaped terminal made of eutectic solder) and a lid, and the semiconductor integrated circuit element is connected to the bottom surface of the concave portion of the insulating base by glass, resin, or the like. The electrodes of the semiconductor integrated circuit element and the metallized wiring layer are electrically connected via bonding wires, and a lid is formed on the upper surface of the insulating base via a sealing material such as glass or resin. The semiconductor integrated circuit element is hermetically sealed inside a container formed of an insulating base and a lid, thereby forming a semiconductor device as a product.
【０００３】かかる半導体装置は絶縁基体下面の接続パ
ッドにロウ付けされている半田から成るボール状端子を
外部電気回路基板の配線導体上に載置当接させ、しかる
後、前記ボール状端子を約200 〜250 ℃の温度で加熱溶
融し、ボール状端子を配線導体に接合させることによっ
て外部電気回路基板上に実装され、同時に半導体素子収
納用パッケージの内部に収容されている半導体集積回路
素子はその各電極がメタライズ配線層及びボール状端子
を介して外部電気回路に電気的に接続されることとな
る。In such a semiconductor device, a ball-shaped terminal made of solder brazed to a connection pad on the lower surface of an insulating substrate is placed and abutted on a wiring conductor of an external electric circuit board. It is heated and melted at a temperature of 200 to 250 ° C and mounted on an external electric circuit board by joining ball-shaped terminals to wiring conductors, and at the same time, the semiconductor integrated circuit element housed inside the semiconductor element housing package is Each electrode is electrically connected to an external electric circuit via the metallized wiring layer and the ball-shaped terminals.
【０００４】しかしながら、この従来の半導体素子収納
用パッケージにおいては、アルミナセラミックス等から
成る絶縁基体の熱膨張係数が約6.5 ×10-6/ ℃であるの
に対し、外部電気回路基板は一般にガラスエポキシ樹脂
から成り、その熱膨張係数が2 ×10-5/ ℃〜4 ×10-5/
℃で両者大きく相違することから半導体素子収納用パッ
ケージの内部に半導体集積回路素子を収容し、しかる
後、外部電気回路基板に実装した場合、半導体集積回路
素子の作動時に発する熱が絶縁基体と外部電気回路基板
の両方に繰り返し印加されると前記半導体素子収納用パ
ッケージの絶縁基板と外部電気回路基板との間に両者の
熱膨張係数の相違に起因する大きな熱応力が発生すると
ともにこれが絶縁基体下面の接続パッドの外周部に作用
して接続パッドを絶縁基体より剥離させてしまい、その
結果、半導体素子収納用パッケージの内部に収容する半
導体集積回路素子の各電極を長期間にわたり所定の外部
電気回路に電気的に接続させることができないという欠
点を有していた。However, in this conventional package for housing a semiconductor element, the thermal expansion coefficient of an insulating base made of alumina ceramics or the like is about 6.5 × 10 −6 / ° C., whereas the external electric circuit board is generally made of glass epoxy. It is made of resin and has a coefficient of thermal expansion of 2 × 10 -5 / ° C to 4 × 10 -5 /
When the semiconductor integrated circuit element is housed inside the semiconductor element housing package and then mounted on an external electric circuit board, the heat generated during operation of the semiconductor integrated circuit element causes the heat generated by the semiconductor integrated circuit element and the external When repeatedly applied to both of the electric circuit boards, a large thermal stress is generated between the insulating board of the semiconductor element housing package and the external electric circuit board due to a difference in thermal expansion coefficient between the insulating board and the external electric circuit board. Acting on the outer peripheral portion of the connection pad to separate the connection pad from the insulating base. As a result, each electrode of the semiconductor integrated circuit element housed inside the semiconductor element housing package is subjected to a predetermined external electric circuit for a long period of time. However, it has a drawback that it cannot be electrically connected to the
【０００５】そこで上記欠点を解消するために本願出願
人は先に共晶半田から成る端子を、絶縁基体下面に設け
た凹部の底面に被着されている接続パッドに、絶縁基体
下面に突出部が形成されるようにして取着させた半導体
素子収納用パッケージを提案した。かかる半導体素子収
納用パッケージによれば絶縁基体と外部電気回路基板と
の間に発生する両者の熱膨張係数の相違に起因する熱応
力は接続パッドの外周部と絶縁基体の凹部開口領域に位
置する端子に分散されて小さくなり、その結果、接続パ
ッドが絶縁基体より剥離するのが有効に防止される。In order to solve the above-mentioned drawbacks, the applicant of the present application has previously attached a terminal made of eutectic solder to a connection pad attached to the bottom surface of a concave portion provided on the lower surface of the insulating base, and a protruding portion on the lower surface of the insulating base. A package for accommodating a semiconductor element, which is attached in such a manner as to be formed. According to such a package for housing semiconductor elements, the thermal stress generated between the insulating base and the external electric circuit board due to the difference in the thermal expansion coefficient between the insulating base and the external electric circuit board is located in the outer peripheral portion of the connection pad and the recess opening area of the insulating base. As a result, the connection pads are effectively dispersed from the insulating substrate.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、この半
導体素子収納用パッケージにおいては端子が共晶半田で
形成されており、端子全体が同時に加熱溶融、或いは凝
固することから端子を加熱溶融させ、外部電気回路基板
の配線導体に接合させることによって半導体装置を外部
電気回路基板上に実装させる際、端子全体が実質的に同
時に溶融して液状になるとともに絶縁基体の凹部内に位
置する液状半田の一部が表面張力によって絶縁基体下面
の突出部に吸収され、その結果、端子の突出部と凹部内
の領域との間に分断が生じ、半導体集積回路素子の各電
極を外部電気回路に強固に電気的接続することができな
いという欠点を誘発する。However, in this package for housing a semiconductor element, the terminals are formed of eutectic solder, and the entire terminals are simultaneously melted or solidified. When a semiconductor device is mounted on an external electric circuit board by being joined to a wiring conductor of a circuit board, the entire terminal substantially simultaneously melts and becomes liquid, and a portion of the liquid solder located in a concave portion of the insulating base. Is absorbed by the protrusions on the lower surface of the insulating substrate due to surface tension, and as a result, a separation occurs between the protrusions of the terminals and the region in the recess, and each electrode of the semiconductor integrated circuit element is firmly electrically connected to an external electric circuit. Induces the disadvantage of not being able to connect.
【０００７】[0007]
【発明の目的】本発明は上記欠点に鑑み案出されたもの
で、その目的は内部に収容する半導体集積回路素子の各
電極を長期間にわたり所定の外部電気回路に強固に電気
的接続することができる半導体素子収納用パッケージを
提供することにある。SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks, and has as its object to firmly electrically connect each electrode of a semiconductor integrated circuit element housed therein to a predetermined external electric circuit for a long period of time. It is an object of the present invention to provide a package for housing a semiconductor element which can be used.
【０００８】[0008]
【課題を解決するための手段】本発明は電気絶縁材料か
ら成り、上面に半導体素子が載置される載置部を、下面
に多数の凹部を有する絶縁基体と、前記絶縁基体の半導
体素子が載置される載置部周辺から凹部底面にかけて導
出される複数個のメタライズ配線層と、前記絶縁基体の
凹部底面に形成され、メタライズ配線層が電気的に接続
される複数個の接続パッドと、前記接続パッドに取着さ
れ、絶縁基体の下面に球状の突出部を有する端子とから
成る半導体素子収納用パッケージであって、前記端子が
非共晶半田で形成されていることを特徴とするものであ
る。According to the present invention, there is provided an insulating base comprising an electrically insulating material, having a mounting portion on which a semiconductor element is mounted on an upper surface, a plurality of concave portions on a lower surface, and a semiconductor element of the insulating base. A plurality of metallized wiring layers led out from around the mounting portion to be mounted to the bottom surface of the concave portion, and a plurality of connection pads formed on the bottom surface of the concave portion of the insulating base and electrically connected to the metallized wiring layer, A terminal attached to the connection pad and having a spherical projection on a lower surface of an insulating substrate, wherein the terminal is formed of non-eutectic solder. It is.
【０００９】[0009]
【作用】本発明の半導体素子収納用パッケージによれ
ば、絶縁基体下面の凹部底面に接続パッドを設けるとと
もに、該接続パッドに絶縁基体の下面に球状の突出部を
有する端子を取着したことから半導体素子収納用パッケ
ージの内部に半導体集積回路素子を収容するとともに外
部電気回路基板に実装した場合、半導体集積回路素子の
作動時に発する熱が絶縁基体と外部電気回路基板の両方
に繰り返し印加され、半導体素子収納用パッケージの絶
縁基体と外部電気回路基板との間に両者の熱膨張係数の
相違に起因する大きな熱応力が発生したとしてもその熱
応力は接続パッドの外周部と絶縁基体の凹部開口領域に
位置する端子に分散され、その結果、接続パッドが絶縁
基体より剥離することはなく、半導体素子収納用パッケ
ージの内部に収容する半導体集積回路素子の各電極を長
期間にわたり所定の外部電気回路に正確に電気的接続さ
せることが可能となる。According to the semiconductor device housing package of the present invention, the connection pad is provided on the bottom surface of the concave portion on the lower surface of the insulating base, and the terminal having the spherical projection on the lower surface of the insulating base is attached to the connection pad. When a semiconductor integrated circuit element is housed in a package for housing a semiconductor element and mounted on an external electric circuit board, heat generated during operation of the semiconductor integrated circuit element is repeatedly applied to both the insulating base and the external electric circuit board, and Even if a large thermal stress is generated between the insulating base of the element storage package and the external electric circuit board due to the difference in thermal expansion coefficient between the two, the thermal stress is maintained at the outer peripheral portion of the connection pad and the recess opening area of the insulating base. And the connection pads are not peeled off from the insulating base, so that the connection pads are housed inside the semiconductor element housing package. It is possible to precisely electrically connect each electrode of the semiconductor integrated circuit device for a long period of time to a predetermined external electric circuit.
【００１０】また端子を非共晶の半田で形成したことか
ら端子を加熱溶融させ、外部電気回路基板の配線導体に
接合させることによって半導体装置を外部電気回路基板
上に実装させる際、端子に液相と固相が同時に形成さ
れ、絶縁基体の凹部内に位置する液相半田が絶縁基体下
面の突出部に吸収されるのを固相半田が有効に阻止し、
その結果、端子の突出部と凹部内の領域との間には分断
が生じることはなく、これによって半導体集積回路素子
の各電極を外部電気回路に強固に電気的接続することが
できる。In addition, since the terminals are formed of non-eutectic solder, the terminals are heated and melted and joined to the wiring conductors of the external electric circuit board to mount the semiconductor device on the external electric circuit board. A phase and a solid phase are formed at the same time, and the solid phase solder effectively prevents the liquid phase solder located in the concave portion of the insulating base from being absorbed by the protrusion on the lower surface of the insulating base,
As a result, there is no separation between the projecting portion of the terminal and the region in the concave portion, whereby each electrode of the semiconductor integrated circuit element can be firmly electrically connected to an external electric circuit.
【００１１】[0011]
【実施例】次に本発明を添付図面に基づき詳細に説明す
る。BRIEF DESCRIPTION OF THE DRAWINGS FIG.
【００１２】図１は本発明にかかる半導体素子収納用パ
ッケージの一実施例を示し、１は絶縁基体、２は蓋体で
ある。この絶縁基体１と蓋体２とで半導体集積回路素子
３を収容する容器４が構成される。FIG. 1 shows an embodiment of a package for accommodating a semiconductor device according to the present invention, wherein 1 is an insulating base and 2 is a lid. The insulating base 1 and the lid 2 constitute a container 4 for housing the semiconductor integrated circuit element 3.
【００１３】前記絶縁基体１はその上面中央部に半導体
集積回路素子３が載置収容される凹所１ａが設けてあ
り、該凹所１ａ底面には半導体集積回路素子３がガラ
ス、樹脂等の接着剤を介して接着固定される。The insulating substrate 1 is provided with a recess 1a in the center of the upper surface for mounting and housing the semiconductor integrated circuit element 3, and the semiconductor integrated circuit element 3 is made of glass, resin or the like on the bottom of the recess 1a. It is bonded and fixed via an adhesive.
【００１４】前記絶縁基体１は酸化アルミニウム質焼結
体、ムライト質焼結体、炭化珪素質焼結体、窒化アルミ
ニウム質焼結体、ガラスセラミックス焼結体等の電気絶
縁材料から成り、例えば酸化アルミニウム質焼結体から
成る場合は酸化アルミニウム、酸化珪素、酸化マグネシ
ウム、酸化カルシウム等の原料粉末に適当な有機バイン
ダー、可塑剤、溶剤を添加混合して泥漿物を作るととも
に該泥漿物をドクターブレード法やカレンダーロール法
を採用することによってグリーンシート（生シート）と
成し、しかる後、前記グリーンシートに適当な打ち抜き
加工を施すとともにこれを複数枚積層し、約1600℃の温
度で焼成することによって製作される。The insulating substrate 1 is made of an electrically insulating material such as an aluminum oxide sintered body, a mullite sintered body, a silicon carbide sintered body, an aluminum nitride sintered body, a glass ceramic sintered body and the like. In the case of an aluminum sintered body, a suitable organic binder, a plasticizer, and a solvent are added to raw material powders such as aluminum oxide, silicon oxide, magnesium oxide, and calcium oxide to form a slurry, and the slurry is doctor bladed. Green sheet (raw sheet) by adopting the method or calender roll method, and then subjecting the green sheet to appropriate punching and laminating a plurality of these sheets, and firing at a temperature of about 1600 ° C. Produced by
【００１５】また前記絶縁基体1 は半導体集積回路素子
3 が載置収容される凹所1aの周辺から下面にかけて複数
個のメタライズ配線層5 が被着形成されている。The insulating substrate 1 is a semiconductor integrated circuit device.
A plurality of metallized wiring layers 5 are formed from the periphery to the lower surface of the recess 1a in which 3 is placed and accommodated.
【００１６】更に前記絶縁基体1 の下面には凹部1bが設
けられており、該凹部1bの底面には前記メタライズ配線
層5 が電気的に接続される接続パッド5aが被着形成され
ている。Further, a concave portion 1b is provided on the lower surface of the insulating base 1, and a connection pad 5a for electrically connecting the metallized wiring layer 5 is formed on the bottom surface of the concave portion 1b.
【００１７】前記メタライズ配線層5 及び接続パッド5a
はタングステン、モリブデン、マンガン等の高融点金属
粉末から成り、タングステン等の高融点金属粉末に適当
な有機バインダー、可塑剤、溶剤を添加混合して得た金
属ペーストを絶縁基体1 となるグリーンシートに予め従
来周知のスクリーン印刷法により所定パターンに印刷塗
布しておくことによって絶縁基体1 の所定位置に所定パ
ターンに被着形成される。The metallized wiring layer 5 and the connection pad 5a
Is made of a high melting point metal powder such as tungsten, molybdenum, manganese, etc., and a suitable organic binder, a plasticizer, and a solvent are added to the high melting point metal powder such as tungsten and mixed. By printing and applying a predetermined pattern by a conventionally well-known screen printing method in advance, a predetermined pattern is adhered and formed at a predetermined position of the insulating base 1.
【００１８】前記メタライズ配線層5 は半導体集積回路
素子3 の各電極を後述する接続パッド5aに取着される端
子7 に電気的に接続させる作用を為し、絶縁基体1 の凹
所1a周辺に位置する領域には半導体集積回路素子3 の各
電極がボンディングワイヤ6を介して電気的に接続され
る。The metallized wiring layer 5 serves to electrically connect each electrode of the semiconductor integrated circuit element 3 to a terminal 7 attached to a connection pad 5a described later. Each electrode of the semiconductor integrated circuit element 3 is electrically connected to the located region via a bonding wire 6.
【００１９】また前記メタライズ配線層5 と電気的に接
続されている接続パッド5aは絶縁基体1 に端子7 を取着
する際の下地金属層として作用し、接続パッド5aの表面
には非共晶の半田から成る端子7 が取着されている。The connection pad 5a electrically connected to the metallized wiring layer 5 functions as a base metal layer when the terminal 7 is attached to the insulating base 1, and the surface of the connection pad 5a is non-eutectic. A terminal 7 made of solder is attached.
【００２０】前記接続パッド5aに取着されている端子7
はまた絶縁基体1 の下面に球状の突出部7aを有してお
り、該球状突出部7aは端子7 を外部電気回路基板8 の配
線導体8aに接続させる際、その接続を容易、且つ確実と
なす作用をする。The terminal 7 attached to the connection pad 5a
Also has a spherical protrusion 7a on the lower surface of the insulating base 1, and when connecting the terminal 7 to the wiring conductor 8a of the external electric circuit board 8, the connection is easy and reliable. It works.
【００２１】前記端子7 は絶縁基体1 の下面に球状の突
出部7aを有することから端子7 を外部電気回路基板8 の
配線導体8aに接合させた後、半導体集積回路素子3 の作
動時に発する熱が絶縁基体1 と外部電気回路基板8 の両
方に繰り返し印加され、絶縁基体1 と外部電気回路基板
8 との間に両者の熱膨張係数の相違に起因する大きな熱
応力が発生したとしてもその熱応力は接続パッド5aの外
周部と絶縁基体1 の凹部1b開口領域に位置する端子7 の
両領域に分散されて小さくなり、その結果、前記熱応力
によって接続パッド5aが絶縁基体1 より剥離することは
なく、容器4 内部に収容する半導体集積回路素子3 の各
電極を長期間にわたり所定の外部電気回路に電気的に接
続させることができる。Since the terminal 7 has a spherical projection 7a on the lower surface of the insulating base 1, after the terminal 7 is joined to the wiring conductor 8a of the external electric circuit board 8, the heat generated when the semiconductor integrated circuit element 3 is operated. Is repeatedly applied to both the insulating base 1 and the external electric circuit board 8, and the insulating base 1 and the external electric circuit board 8 are applied.
Even if a large thermal stress is generated due to the difference in the coefficient of thermal expansion between the outer peripheral portion of the connection pad 5a and the area of the terminal 7 located in the opening area of the concave portion 1b of the insulating base 1. As a result, the connection pad 5a does not peel off from the insulating base 1 due to the thermal stress, and each electrode of the semiconductor integrated circuit element 3 housed in the container 4 is exposed to a predetermined external electric power for a long time. It can be electrically connected to a circuit.
【００２２】また前記端子7 は非共晶の半田で形成され
ていることから端子7 を加熱溶融させ、外部電気回路基
板8 の配線導体8aに接合させる際、端子7 に液相と固相
が同時に形成され、絶縁基体1 の凹部1b内に位置する液
相半田が絶縁基体1 の下面に突出する突出部7aに吸収さ
れるのが固相半田によって有効に阻止され、その結果、
端子7 の突出部7aと凹部1b内の領域との間に分断が生じ
ることはなく、これによって半導体集積回路素子3 の各
電極を外部電気回路に強固に電気的接続することが可能
となる。Since the terminal 7 is made of non-eutectic solder, the terminal 7 is heated and melted, and when the terminal 7 is joined to the wiring conductor 8a of the external electric circuit board 8, a liquid phase and a solid phase are applied to the terminal 7. At the same time, the solid-phase solder effectively prevents the liquid-phase solder located in the concave portion 1b of the insulating base 1 from being absorbed by the protrusion 7a protruding from the lower surface of the insulating base 1, and as a result,
There is no separation between the protruding portion 7a of the terminal 7 and the region in the concave portion 1b, thereby making it possible to firmly electrically connect each electrode of the semiconductor integrated circuit element 3 to an external electric circuit.
【００２３】かくして本発明の半導体素子収納用パッケ
ージによれば絶縁基体1 の凹所1a底面に半導体集積回路
素子3 を接着剤を介して接着固定するとともに半導体集
積回路素子3 の各電極をメタライズ配線層5 にボンディ
ングワイヤ6 を介して電気的に接続し、しかる後、絶縁
基体1 の上面に蓋体2 をガラス、樹脂等から成る封止材
により接合させ、絶縁基体1 と蓋体2 とから成る容器4
内部に半導体集積回路素子3 を気密に封止することによ
って製品としての半導体装置となる。Thus, according to the semiconductor device housing package of the present invention, the semiconductor integrated circuit device 3 is bonded and fixed to the bottom surface of the recess 1a of the insulating base 1 with an adhesive, and each electrode of the semiconductor integrated circuit device 3 is metallized wiring. It is electrically connected to the layer 5 via bonding wires 6, and then the lid 2 is joined to the upper surface of the insulating base 1 with a sealing material made of glass, resin, or the like. Container consisting of 4
A semiconductor device as a product is obtained by hermetically sealing the semiconductor integrated circuit element 3 inside.
【００２４】また前記半導体素子収納用パッケージに半
導体集積回路素子3 を収容して形成される半導体装置は
絶縁基体1 下面の端子7 を外部電気回路基板8 の配線導
体8aに接合させることによって外部電気回路基板8 上に
実装され、同時に容器4 の内部に収容されている半導体
集積回路素子3 はその各電極がボンディングワイヤ6、
メタライズ配線層5 、接続パッド5a及び端子7 を介して
外部電気回路基板8 の配線導体8aに電気的に接続され
る。A semiconductor device formed by accommodating the semiconductor integrated circuit element 3 in the package for accommodating the semiconductor element is provided by bonding terminals 7 on the lower surface of the insulating base 1 to wiring conductors 8 a of the external electric circuit board 8. The semiconductor integrated circuit device 3 mounted on the circuit board 8 and housed in the container 4 at the same time
It is electrically connected to the wiring conductor 8a of the external electric circuit board 8 via the metallized wiring layer 5, the connection pad 5a and the terminal 7.
【００２５】更に本発明は上述の実施例に限定されるも
のではなく、本発明の要旨を逸脱しない範囲であれば種
々の変更は可能である。Further, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention.
【００２６】[0026]
【発明の効果】本発明の半導体素子収納用パッケージに
よれば、絶縁基体下面の凹部底面に接続パッドを設ける
とともに、該接続パッドに絶縁基体の下面に球状の突出
部を有する端子を取着したことから半導体素子収納用パ
ッケージの内部に半導体集積回路素子を収容するととも
に外部電気回路基板に実装した場合、半導体集積回路素
子の作動時に発する熱が絶縁基体と外部電気回路基板の
両方に繰り返し印加され、半導体素子収納用パッケージ
の絶縁基体と外部電気回路基板との間に両者の熱膨張係
数の相違に起因する大きな熱応力が発生したとしてもそ
の熱応力は接続パッドの外周部と絶縁基体の凹部開口領
域に位置する端子に分散され、その結果、接続パッドが
絶縁基体より剥離することはなく、半導体素子収納用パ
ッケージの内部に収容する半導体集積回路素子の各電極
を長期間にわたり所定の外部電気回路に正確に電気的接
続させることが可能となる。According to the package for housing a semiconductor element of the present invention, a connection pad is provided on the bottom surface of the concave portion on the lower surface of the insulating base, and a terminal having a spherical projection on the lower surface of the insulating base is attached to the connection pad. Therefore, when the semiconductor integrated circuit element is housed inside the semiconductor element housing package and mounted on an external electric circuit board, the heat generated during operation of the semiconductor integrated circuit element is repeatedly applied to both the insulating base and the external electric circuit board. Even if a large thermal stress is generated between the insulating base of the package for housing the semiconductor element and the external electric circuit board due to the difference in thermal expansion coefficient between the two, the thermal stress is reduced to the outer peripheral portion of the connection pad and the concave portion of the insulating base. As a result, the connection pads are not separated from the insulating base, and the connection pads are not separated from the insulating base. It is possible to precisely electrically connected to a predetermined external electric circuit to the electrodes over a long period of the semiconductor integrated circuit device for containers.
【００２７】また端子を非共晶の半田で形成したことか
ら端子を加熱溶融させ、外部電気回路基板の配線導体に
接合させることによって半導体装置を外部電気回路基板
上に実装させる際、端子に液相と固相が同時に形成さ
れ、絶縁基体の凹部内に位置する液相半田が絶縁基体下
面の突出部に吸収されるのを固相半田が有効に阻止し、
その結果、端子の突出部と凹部内の領域との間には分断
が生じることはなく、これによって半導体集積回路素子
の各電極を外部電気回路に強固に電気的接続することが
できる。Further, since the terminals are formed of non-eutectic solder, the terminals are heated and melted, and are bonded to the wiring conductors of the external electric circuit board. A phase and a solid phase are formed at the same time, and the solid phase solder effectively prevents the liquid phase solder located in the concave portion of the insulating base from being absorbed by the protrusion on the lower surface of the insulating base,
As a result, there is no separation between the projecting portion of the terminal and the region in the concave portion, whereby each electrode of the semiconductor integrated circuit element can be firmly electrically connected to an external electric circuit.
【図１】本発明の半導体素子収納用パッケージの一実施
例を示す断面図である。FIG. 1 is a cross-sectional view showing one embodiment of a semiconductor element storage package according to the present invention.
１・・・・・・絶縁基体 １ａ・・・・・凹所 １ｂ・・・・・凹部 ２・・・・・・蓋体 ３・・・・・・半導体集積回路素子 ４・・・・・・容器 ５・・・・・・メタライズ配線層 ５ａ・・・・・接続パッド ７・・・・・・端子 ７ａ・・・・・端子の球状の突出部 ８・・・・・・外部電気回路基板 ８ａ・・・・・配線導体 DESCRIPTION OF SYMBOLS 1 ... Insulating base 1a ... Depression 1b ... Depression 2 ... Lid 3 ... Semiconductor integrated circuit element 4 ... · Container 5 ····· Metallized wiring layer 5a ····· Connection pad 7 ···· Terminal 7a ····· Spherical protrusion of terminal 8 ····· External electric circuit Substrate 8a ..... Wiring conductor
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/12 H01L 23/12 501 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 23/12 H01L 23/12 501
Claims (1)
が載置される載置部を、下面に多数の凹部を有する絶縁
基体と、前記絶縁基体の半導体素子が載置される載置部
周辺から凹部底面にかけて導出される複数個のメタライ
ズ配線層と、前記絶縁基体の凹部底面に形成され、メタ
ライズ配線層が電気的に接続される複数個の接続パッド
と、前記接続パッドに取着され、絶縁基体の下面に球状
の突出部を有する端子とから成る半導体素子収納用パッ
ケージであって、前記端子が非共晶半田で形成されてい
ることを特徴とする半導体素子収納用パッケージ。An insulating base having an upper surface on which a semiconductor element is mounted, an insulating base having a plurality of concave portions on a lower surface, and a mounting part on which the semiconductor element of the insulating base is mounted. A plurality of metallized wiring layers extending from the periphery to the bottom of the concave portion, a plurality of connection pads formed on the bottom surface of the concave portion of the insulating base, and electrically connected to the metallized wiring layer; And a terminal having a spherical projection on the lower surface of the insulating base, wherein the terminal is formed of non-eutectic solder.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30472094A JP3336136B2 (en) | 1994-12-08 | 1994-12-08 | Package for storing semiconductor elements |
| US08/567,949 US6225700B1 (en) | 1994-12-08 | 1995-12-06 | Package for a semiconductor element having depressions containing solder terminals |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30472094A JP3336136B2 (en) | 1994-12-08 | 1994-12-08 | Package for storing semiconductor elements |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08162561A JPH08162561A (en) | 1996-06-21 |
| JP3336136B2 true JP3336136B2 (en) | 2002-10-21 |
Family
ID=17936410
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30472094A Expired - Fee Related JP3336136B2 (en) | 1994-12-08 | 1994-12-08 | Package for storing semiconductor elements |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3336136B2 (en) |
-
1994
- 1994-12-08 JP JP30472094A patent/JP3336136B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08162561A (en) | 1996-06-21 |
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| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |