JP3176251B2 - Package for storing semiconductor elements - Google Patents

Package for storing semiconductor elements

Info

Publication number
JP3176251B2
JP3176251B2 JP12173495A JP12173495A JP3176251B2 JP 3176251 B2 JP3176251 B2 JP 3176251B2 JP 12173495 A JP12173495 A JP 12173495A JP 12173495 A JP12173495 A JP 12173495A JP 3176251 B2 JP3176251 B2 JP 3176251B2
Authority
JP
Japan
Prior art keywords
alloy layer
connection pad
ball
nickel
molybdenum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP12173495A
Other languages
Japanese (ja)
Other versions
JPH08316366A (en
Inventor
雄一 古本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP12173495A priority Critical patent/JP3176251B2/en
Publication of JPH08316366A publication Critical patent/JPH08316366A/en
Application granted granted Critical
Publication of JP3176251B2 publication Critical patent/JP3176251B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092Dispersed materials, e.g. conductive pastes or inks
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/24Reinforcing the conductive pattern

Landscapes

  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は半導体素子を収容するた
めの半導体素子収納用パッケージに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device housing package for housing a semiconductor device.

【0002】[0002]

【従来の技術】従来、半導体素子、特にLSI(大規模
集積回路素子)等の半導体集積回路素子を収容するため
の半導体素子収納用パッケージは、一般にアルミナセラ
ミックス等の電気絶縁材料から成り、その上面の略中央
部に半導体集積回路素子を収容するための凹部を有する
絶縁基体と、前記絶縁基体の凹部周辺から下面にかけて
導出されるタングステン、モリブデン等の高融点金属粉
末から成る複数個のメタライズ配線層と、前記絶縁基体
の下面に形成され、メタライズ配線層が電気的に接続さ
れる複数個の接続パッドと、前記接続パッドに取着され
る半田から成るボール状端子と、蓋体とから構成されて
おり、絶縁基体の凹部底面に半導体集積回路素子をガラ
ス、樹脂等から成る接着剤を介して接着固定させ、半導
体集積回路素子の各電極とメタライズ配線層とをボンデ
ィングワイヤを介して電気的に接続させるとともに絶縁
基体上面に蓋体をガラス、樹脂等の封止材を介して接合
させ、絶縁基体と蓋体とから成る容器内部に半導体集積
回路素子を気密に収容することによって製品としての半
導体装置となる。
2. Description of the Related Art Conventionally, a semiconductor element housing package for housing a semiconductor element, especially a semiconductor integrated circuit element such as an LSI (Large Scale Integrated Circuit) is generally made of an electrically insulating material such as alumina ceramics. And a plurality of metallized wiring layers made of a refractory metal powder such as tungsten, molybdenum or the like drawn out from the periphery of the recess to the lower surface of the insulating base. And a plurality of connection pads formed on the lower surface of the insulating base and electrically connected to the metallized wiring layer, ball-shaped terminals made of solder attached to the connection pads, and a lid. The semiconductor integrated circuit device is bonded and fixed to the bottom surface of the concave portion of the insulating base via an adhesive made of glass, resin, or the like. The electrode and the metallized wiring layer are electrically connected via a bonding wire, and a lid is bonded to the upper surface of the insulating substrate via a sealing material such as glass or resin, so that the inside of the container including the insulating substrate and the lid is formed. A semiconductor device as a product is obtained by housing the semiconductor integrated circuit element in an airtight manner.

【0003】かかる半導体装置は絶縁基体下面の接続パ
ッドに取着されている半田から成るボール状端子を外部
電気回路基板の配線導体上に載置当接させ、しかる後、
前記ボール状端子を約200〜250℃の温度で加熱溶
融し、ボール状端子を配線導体に接合させることによっ
て外部電気回路基板上に実装され、同時に半導体素子収
納用パッケージの内部に収容されている半導体集積回路
素子はその各電極がメタライズ配線層及びボール状端子
を介して外部電気回路に接続されることとなる。
In such a semiconductor device, a ball-shaped terminal made of solder attached to a connection pad on the lower surface of an insulating substrate is placed and contacted on a wiring conductor of an external electric circuit board, and thereafter,
The ball-shaped terminal is heated and melted at a temperature of about 200 to 250 ° C., and is mounted on an external electric circuit board by joining the ball-shaped terminal to a wiring conductor, and is simultaneously housed in a semiconductor element housing package. Each electrode of the semiconductor integrated circuit element is connected to an external electric circuit via a metallized wiring layer and a ball-shaped terminal.

【0004】尚、前記半導体素子収納用パッケージは接
続パッドに半田から成るボール状端子を強固に取着する
ための接続パッド表面には通常、厚さ2μm乃至8μm
程度のニッケルがメッキ法により層着されている。
The semiconductor element housing package usually has a thickness of 2 μm to 8 μm on the surface of a connection pad for firmly attaching a ball-shaped terminal made of solder to the connection pad.
About nickel is layered by plating.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、この従
来の半導体素子収納用パッケージにおいては、接続パッ
ドの表面へのニッケルメッキ層の層着が平面的であるこ
と及びアルミナセラミックス等から成る絶縁基体の熱膨
張係数が約6.5×10-6/℃であるのに対し、外部電
気回路基板は一般にガラスエポキシ樹脂から成り、その
熱膨張係数が2×10-5/℃〜4×10-5/℃で両者大
きく相違することから半導体素子収納用パッケージの内
部に半導体集積回路素子を収容し、しかる後、外部電気
回路基板に実装した場合、半導体集積回路素子の作動時
に発する熱が絶縁基体と外部電気回路基板の両方に繰り
返し印加されると前記半導体素子収納用パッケージの絶
縁基体と外部電気回路基板との間に両者の熱膨張係数の
相違に起因する大きな熱応力が発生するとともにこれが
絶縁基体下面の接続パッドとボール状端子との間に作用
してボール状端子を接続パッド表面に層着されているニ
ッケルメッキ層とともに剥離させてしまい、その結果、
半導体素子収納用パッケージの内部に収容する半導体集
積回路素子の各電極を長期間にわたり所定の外部電気回
路に電気的に接続させることができないという欠点を有
していた。
However, in this conventional package for housing a semiconductor element, the nickel plating layer is flatly attached to the surface of the connection pad, and the heat of the insulating base made of alumina ceramics or the like is not sufficient. The expansion coefficient is about 6.5 × 10 −6 / ° C., whereas the external electric circuit board is generally made of glass epoxy resin and has a thermal expansion coefficient of 2 × 10 −5 / ° C. to 4 × 10 −5 / ° C. When the semiconductor integrated circuit element is housed inside the semiconductor element housing package and then mounted on an external electric circuit board, the heat generated during operation of the semiconductor integrated circuit element causes the heat generated by the semiconductor integrated circuit element and the external When the voltage is repeatedly applied to both of the electric circuit boards, a large difference is caused between the insulating base of the package for housing semiconductor elements and the external electric circuit board due to the difference in thermal expansion coefficient between the two. A the same time thermal stress is generated will by stripping with nickel plating layer are particle course a ball-shaped terminal connection pad surface acts between a connection pad and the ball-shaped terminals of the insulating base lower surface, as a result,
There is a drawback that the electrodes of the semiconductor integrated circuit element housed in the semiconductor element housing package cannot be electrically connected to a predetermined external electric circuit for a long period of time.

【0006】[0006]

【発明の目的】本発明は上記欠点に鑑み案出されたもの
で、その目的は半田からなるボール状端子を接続パッド
に強固に取着させ、内部に収容する半導体集積回路素子
の各電極を長期間にわたり所定の外部電気回路に確実に
電気的接続することができる半導体素子収納用パッケー
ジを提供することにある。
SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks, and has as its object the purpose of firmly attaching a ball-shaped terminal made of solder to a connection pad, and connecting each electrode of a semiconductor integrated circuit element housed therein. An object of the present invention is to provide a semiconductor element housing package that can be reliably electrically connected to a predetermined external electric circuit for a long period of time.

【0007】[0007]

【課題を解決するための手段】本発明はセラミックス焼
結体から成り、上面に半導体素子が載置される載置部を
有する絶縁基体と、該絶縁基体の半導体素子が載置され
る載置部周辺から下面にかけて導出されるタングステン
もしくはモリブデンから成る複数個のメタライズ配線層
と、前記絶縁基体の下面に形成され、前記メタライズ配
線層が電気的に接続される複数個の接続パッドと、半田
から成り、前記接続パッドに取着されるボール状端子と
から成る半導体素子収納用パッケージであって、前記ボ
ール状端子の取着される接続パッド表面に厚みが0.5
μm乃至3μmである、タングステン−ニッケル合金層
もしくはモリブデン−ニッケル合金層を被着させたこと
を特徴とするものである。
According to the present invention, there is provided an insulating base made of a ceramic sintered body and having a mounting part on which a semiconductor element is mounted on an upper surface, and a mounting part on which the semiconductor element of the insulating base is mounted. A plurality of metallized wiring layers made of tungsten or molybdenum led out from the periphery to the lower surface, a plurality of connection pads formed on the lower surface of the insulating base, and electrically connected to the metallized wiring layers, And a ball-shaped terminal attached to the connection pad, wherein the package has a thickness of 0.5 mm on the surface of the connection pad to which the ball-shaped terminal is attached.
A tungsten-nickel alloy layer or a molybdenum-nickel alloy layer having a thickness of from 3 μm to 3 μm is deposited.

【0008】[0008]

【0009】[0009]

【作用】本発明の半導体素子収納用パッケージによれ
ば、ボール状端子が取着される接続パッド表面にタング
ステン−ニッケル合金層もしくはモリブデン−ニッケル
合金層を被着させたことから接続パッドとタングステン
−ニッケル合金層もしくはモリブデン−ニッケル合金
層、及びタングステン−ニッケル合金層もしくはモリブ
デン−ニッケル合金層とボール状端子の接合強度が強固
となり、接続パッド及びボール状端子に半導体素子収納
用パッケージの絶縁基体と外部電気回路基板の熱膨張係
数の相違に起因する大きな熱応力が作用してボール状端
子が接続パッドより剥離することはなく、その結果、半
導体素子収納用パッケージの内部に収容する半導体集積
回路素子の各電極を長期間にわたり所定の外部電気回路
に正確に電気的接続させることが可能となる。
According to the semiconductor device housing package of the present invention, a tungsten-nickel alloy layer or a molybdenum-nickel alloy layer is applied to the surface of the connection pad on which the ball-shaped terminal is to be attached. The bonding strength between the nickel alloy layer or the molybdenum-nickel alloy layer, and the tungsten-nickel alloy layer or the molybdenum-nickel alloy layer and the ball-shaped terminal is strengthened. The large thermal stress caused by the difference in the coefficient of thermal expansion of the electric circuit board does not cause the ball-shaped terminals to separate from the connection pads. As a result, the semiconductor integrated circuit element housed inside the semiconductor element housing package is Each electrode is accurately and electrically connected to a predetermined external electrical circuit for a long period of time. Rukoto is possible.

【0010】また本発明の半導体素子収納用パッケージ
によれば接続パッド表面のタングステン−ニッケル合金
層もしくはモリブデン−ニッケル合金層の厚みを0.5
μm乃至3μmとしていることから、接続パッドとタン
グステン−ニッケル合金層もしくはモリブデン−ニッケ
ル合金層、及びタングステン−ニッケル合金層もしくは
モリブデン−ニッケル合金層とボール状端子の接合がよ
り強固となり、半導体集積回路素子の外部電気回路への
接続がより高信頼性のものとなる。
Further, according to the semiconductor device housing package of the present invention, the thickness of the tungsten-nickel alloy layer or the molybdenum-nickel alloy layer on the surface of the connection pad is set to 0.5.
Since the thickness is set to 3 μm to 3 μm, the bonding between the connection pad and the tungsten-nickel alloy layer or the molybdenum-nickel alloy layer, and the bonding between the tungsten-nickel alloy layer or the molybdenum-nickel alloy layer and the ball-shaped terminal become stronger, and the semiconductor integrated circuit element Connection to an external electric circuit becomes more reliable.

【0011】[0011]

【実施例】次に本発明を添付図面に基づき詳細に説明す
る。図1及び図2は本発明にかかる半導体素子収納用パ
ッケージの一実施例を示し、1は絶縁基体、2は蓋体で
ある。この絶縁基体1と蓋体2とで半導体集積回路素子
3を収容する容器4が構成される。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 and 2 show an embodiment of a package for housing a semiconductor element according to the present invention, wherein 1 is an insulating base, and 2 is a lid. The insulating base 1 and the lid 2 constitute a container 4 for housing the semiconductor integrated circuit element 3.

【0012】前記絶縁基体1はその上面中央部に半導体
集積回路素子3が載置収容される凹状の載置部1aが設
けてあり、該凹状の載置部1aには半導体集積回路素子
3がガラス、樹脂等の接着剤を介して接着固定される。
The insulating substrate 1 is provided with a concave mounting portion 1a in which a semiconductor integrated circuit device 3 is mounted and accommodated in the center of the upper surface thereof, and the semiconductor integrated circuit device 3 is mounted on the concave mounting portion 1a. It is bonded and fixed via an adhesive such as glass or resin.

【0013】前記絶縁基体1は酸化アルミニウム質焼結
体、ムライト質焼結体、窒化アルミニウム質焼結体、炭
化珪素質焼結体、ガラスセラミックス焼結体等の電気絶
縁材料から成り、例えば、酸化アルミニウム質焼結体か
ら成る場合、酸化アルミニウム、酸化珪素、酸化マグネ
シウム、酸化カルシウム等の原料粉末に適当な有機バイ
ンダー、溶剤等を添加混合して泥漿状となすとともにこ
れを従来周知のドクターブレード法やカレンダーロール
法等によりシート状に成形してセラミックグリーンシー
ト(セラミック生シート)を得、しかる後、前記セラミ
ックグリーンシートに適当な打ち抜き加工を施すととも
にこれを複数枚積層し、高温(約1600℃)で焼成す
ることによって製作される。
The insulating substrate 1 is made of an electrical insulating material such as an aluminum oxide sintered body, a mullite sintered body, an aluminum nitride sintered body, a silicon carbide sintered body, a glass ceramic sintered body, etc. When it is made of an aluminum oxide sintered body, an appropriate organic binder, a solvent, etc. are added to raw material powders such as aluminum oxide, silicon oxide, magnesium oxide, calcium oxide and the like to form a slurry, which is mixed with a conventionally known doctor blade. A ceramic green sheet (ceramic green sheet) is obtained by molding into a sheet by a method such as a calendering method or a calendering roll method. Thereafter, the ceramic green sheet is subjected to an appropriate punching process, and a plurality of the ceramic green sheets are laminated. C).

【0014】また前記絶縁基体1は半導体集積回路素子
3が載置収容される凹状の載置部1a周辺から下面にか
けて複数個のメタライズ配線層5が、更に絶縁基体1の
下面には前記メタライズ配線層5が電気的に接続される
複数個の接続パッド6が各々被着形成されている。
The insulating substrate 1 has a plurality of metallized wiring layers 5 extending from the periphery of the concave mounting portion 1a on which the semiconductor integrated circuit element 3 is mounted to the lower surface to the lower surface. A plurality of connection pads 6 to which the layer 5 is electrically connected are formed respectively.

【0015】前記メタライズ配線層5及び接続パッド6
はタングステン、モリブデン等の高融点金属粉末から成
り、タングステン等の高融点金属粉末に適当な有機バイ
ンダー、可塑剤、溶剤を添加混合して得た金属ペースト
を絶縁基体1となるセラミックグリーンシートに予め従
来周知のスクリーン印刷法により所定パターンに印刷塗
布しておくことによって絶縁基体1の所定位置に所定パ
ターンに被着形成される。
The metallized wiring layer 5 and the connection pad 6
Is made of a high melting point metal powder such as tungsten or molybdenum, and a metal paste obtained by adding a suitable organic binder, a plasticizer, and a solvent to the high melting point metal powder such as tungsten is mixed in advance on a ceramic green sheet serving as the insulating substrate 1. By printing and applying a predetermined pattern by a conventionally well-known screen printing method, a predetermined pattern is adhered and formed at a predetermined position of the insulating substrate 1.

【0016】前記メタライズ配線層5は半導体集積回路
素子3の各電極を後述する接続パッド6に取着されるボ
ール状端子7に電気的に接続させる作用を為し、絶縁基
体1の凹状の載置部1a周辺に位置する領域には半導体
集積回路素子3の各電極がボンディングワイヤ8を介し
て電気的に接続される。
The metallized wiring layer 5 serves to electrically connect each electrode of the semiconductor integrated circuit element 3 to a ball-shaped terminal 7 attached to a connection pad 6 to be described later. Each electrode of the semiconductor integrated circuit element 3 is electrically connected to a region located around the mounting portion 1a via a bonding wire 8.

【0017】また前記メタライズ配線層5と電気的に接
続されている接続パッド6は絶縁基体1にボール状端子
7を取着する際の下地金属層として作用し、接続パッド
6の表面には半田から成るボール状端子7が取着され
る。
The connection pad 6 electrically connected to the metallized wiring layer 5 functions as a base metal layer when the ball-shaped terminal 7 is attached to the insulating base 1, and the surface of the connection pad 6 is soldered. Is mounted.

【0018】前記ボール状端子7が取着される接続パッ
ド6はまたその表面に図2に示す如くタングステン−ニ
ッケルもしくはモリブデン−ニッケルから成る合金層9
が被着されており、該合金層9は接続パッド6の表面に
ニッケルをメッキ法より層着させ、しかる後、これを8
50〜1000℃の温度に加熱することによって接続パ
ッド6の表面に所定厚みに被着形成される。この場合、
タングステン−ニッケルもしくはモリブデン−ニッケル
から成る合金層9は接続パッド6とニッケル層とを加熱
により合金化させることによって形成されることから接
続パッド6に極めて強固に被着し、例えば絶縁基体1と
外部電気回路基板10との熱膨張係数の相違に起因する
熱応力等が作用しても接続パッド6より剥離することは
ない。またこのタングステン−ニッケルもしくはモリブ
デン−ニッケルから成る合金層9は半田に対する濡れ性
(反応性)が極めて良く、これによって半田から成るボ
ール状端子7は合金層9を介して接続パッド6に強固に
取着される。
The connection pad 6 to which the ball-shaped terminal 7 is attached is also provided on its surface with an alloy layer 9 of tungsten-nickel or molybdenum-nickel as shown in FIG.
The alloy layer 9 is formed by plating nickel on the surface of the connection pad 6 by a plating method.
By heating to a temperature of 50 to 1000 [deg.] C., a predetermined thickness is formed on the surface of the connection pad 6. in this case,
Since the alloy layer 9 made of tungsten-nickel or molybdenum-nickel is formed by alloying the connection pad 6 and the nickel layer by heating, the alloy layer 9 is very firmly adhered to the connection pad 6, for example, the insulating base 1 and the outside. Even if a thermal stress or the like due to a difference in thermal expansion coefficient from the electric circuit board 10 acts, it does not separate from the connection pad 6. The alloy layer 9 made of tungsten-nickel or molybdenum-nickel has extremely good wettability (reactivity) with respect to solder, so that the ball-shaped terminal 7 made of solder is firmly attached to the connection pad 6 via the alloy layer 9. Be worn.

【0019】尚、前記接続パッド6表面に被着されるタ
ングステン−ニッケルもしくはモリブデン−ニッケルか
ら成る合金層9はその厚みが0.5μm未満であると接
続パッド6との被着強度が弱くなって熱応力等により剥
離し易くなり、また3μmを越えるとタングステン−ニ
ッケルもしくはモリブデン−ニッケルから成る合金層9
は脆弱であることから外力よって破損し接続パッド6よ
り剥離し易くなる傾向にある。従って、前記接続パッド
6表面に被着されるタングステン−ニッケルもしくはモ
リブデン−ニッケルから成る合金層9はその厚みを0.
5μm乃至3μmの範囲とするものである。
If the thickness of the alloy layer 9 made of tungsten-nickel or molybdenum-nickel deposited on the surface of the connection pad 6 is less than 0.5 μm, the strength of adhesion to the connection pad 6 is reduced. If the thickness exceeds 3 μm, the alloy layer 9 made of tungsten-nickel or molybdenum-nickel becomes easy to peel.
Are fragile and tend to be broken by an external force and easily peeled off from the connection pad 6. Therefore, the alloy layer 9 made of tungsten-nickel or molybdenum-nickel deposited on the surface of the connection pad 6 has a thickness of 0.1 mm.
The thickness is in the range of 5 μm to 3 μm.

【0020】更に前記接続パッド6に取着されている半
田から成るボール状端子7は接続パッド6を外部電気回
路基板10の配線導体11に容易、且つ確実に接続させ
る作用を為し、接続パッド6の表面にボール状の半田を
載置させ、しかる後、その一部を加熱溶融させることに
よって接続パッド6の表面に取着される。
Further, the ball-shaped terminals 7 made of solder attached to the connection pads 6 serve to easily and surely connect the connection pads 6 to the wiring conductors 11 of the external electric circuit board 10. A ball-shaped solder is placed on the surface of the connection pad 6, and then a part of the solder is heated and melted to be attached to the surface of the connection pad 6.

【0021】かくして本発明の半導体素子収納用パッケ
ージによれば、絶縁基体1の凹状の載置部1a底面に半
導体集積回路素子3を接着剤を介して接着固定するとと
もに半導体集積回路素子3の各電極をメタライズ配線層
5にボンディングワイヤ8を介して電気的に接続し、し
かる後、絶縁基体1の上面に蓋体2をガラス、樹脂等か
ら成る封止材により接合させ、絶縁基体1と蓋体2とか
ら成る容器4内部に半導体集積回路素子3を気密に収容
することによって製品としての半導体装置となる。
Thus, according to the semiconductor device housing package of the present invention, the semiconductor integrated circuit device 3 is bonded and fixed to the bottom surface of the concave mounting portion 1a of the insulating base 1 with an adhesive, and each of the semiconductor integrated circuit devices 3 The electrodes are electrically connected to the metallized wiring layer 5 via bonding wires 8, and then the lid 2 is joined to the upper surface of the insulating base 1 with a sealing material made of glass, resin, or the like. The semiconductor integrated circuit element 3 is hermetically accommodated inside the container 4 formed of the body 2 to provide a semiconductor device as a product.

【0022】また前記半導体素子収納用パッケージに半
導体集積回路素子3を収容して形成される半導体装置は
絶縁基体1下面のボール状端子7を外部電気回路基板1
0の配線導体11に接合させることよって外部電気回路
基板10上に実装され、同時に容器4の内部に収容され
ている半導体集積回路素子3はその電極がボンディング
ワイヤ8、メタライズ配線層5、接続パッド6及びボー
ル状端子7を介して外部電気回路基板10の配線導体1
1に電気的に接続される。
In the semiconductor device formed by housing the semiconductor integrated circuit element 3 in the semiconductor element housing package, the ball-shaped terminals 7 on the lower surface of the insulating base 1 are connected to the external electric circuit board 1.
The semiconductor integrated circuit element 3 mounted on the external electric circuit board 10 by being joined to the wiring conductor 11 of the semiconductor integrated circuit 10 and simultaneously housed in the container 4 has the bonding wire 8, the metallized wiring layer 5, and the connection pad. 6 and the wiring conductor 1 of the external electric circuit board 10 via the ball-shaped terminal 7
1 electrically.

【0023】更に本発明は上述の実施例に限定されるも
のではなく、本発明の要旨を逸脱しない範囲であれば種
々の変更は可能である。
Further, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention.

【0024】[0024]

【発明の効果】本発明の半導体素子収納用パッケージに
よれば、ボール状端子が取着される接続パッド表面にタ
ングステン−ニッケル合金層もしくはモリブデン−ニッ
ケル合金層を被着させたことから接続パッドとタングス
テン−ニッケル合金層もしくはモリブデン−ニッケル合
金層、及びタングステン−ニッケル合金層もしくはモリ
ブデン−ニッケル合金層とボール状端子の接合強度が強
固となり、接続パッド及びボール状端子に半導体素子収
納用パッケージの絶縁基体と外部電気回路基板の熱膨張
係数の相違に起因する大きな熱応力が作用してボール状
端子が接続パッドより剥離することはなく、その結果、
半導体素子収納用パッケージの内部に収容する半導体集
積回路素子の各電極を長期間にわたり所定の外部電気回
路に正確に電気的接続させることが可能となる。
According to the package for housing a semiconductor element of the present invention, a tungsten-nickel alloy layer or a molybdenum-nickel alloy layer is applied to the surface of the connection pad on which the ball-shaped terminal is attached. The bonding strength between the tungsten-nickel alloy layer or the molybdenum-nickel alloy layer, and the tungsten-nickel alloy layer or the molybdenum-nickel alloy layer and the ball-shaped terminal is strengthened, and the connection pad and the ball-shaped terminal are provided on the insulating substrate of the semiconductor element housing package. The large thermal stress caused by the difference in the thermal expansion coefficient of the external electric circuit board and the external electric circuit board does not cause the ball-shaped terminal to peel off from the connection pad. As a result,
The electrodes of the semiconductor integrated circuit device housed in the semiconductor device housing package can be accurately and electrically connected to a predetermined external electric circuit for a long period of time.

【0025】また本発明の半導体素子収納用パッケージ
によれば接続パッド表面のタングステン−ニッケル合金
層もしくはモリブデン−ニッケル合金層の厚みを0.5
μm乃至3μmとすると接続パッドとタングステン−ニ
ッケル合金層もしくはモリブデン−ニッケル合金層、及
びタングステン−ニッケル合金層もしくはモリブデン−
ニッケル合金層とボール状端子の接合がより強固とな
り、半導体集積回路素子の外部電気回路への接続がより
高信頼性のものとなる。
According to the package for housing a semiconductor element of the present invention, the thickness of the tungsten-nickel alloy layer or the molybdenum-nickel alloy layer on the surface of the connection pad is set to 0.5.
When the thickness is 3 μm to 3 μm, the connection pad and the tungsten-nickel alloy layer or molybdenum-nickel alloy layer, and the tungsten-nickel alloy layer or molybdenum
The bonding between the nickel alloy layer and the ball-shaped terminal becomes stronger, and the connection of the semiconductor integrated circuit element to the external electric circuit becomes more reliable.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体素子収納用パッケージの一実施
例を示す断面図である。
FIG. 1 is a cross-sectional view showing one embodiment of a semiconductor element storage package according to the present invention.

【図2】図1に示す半導体素子収納用パッケージの要部
拡大断面図である。
2 is an enlarged cross-sectional view of a main part of the package for housing a semiconductor element shown in FIG. 1;

【符号の説明】[Explanation of symbols]

1・・・・・・絶縁基体 1a・・・・・半導体集積回路素子が載置される凹状の
載置部 2・・・・・・蓋体 3・・・・・・半導体集積回路素子 4・・・・・・容器 5・・・・・・メタライズ配線層 6・・・・・・接続パッド 7・・・・・・ボール状端子 9・・・・・・タングステン−ニッケルもしくはモリブ
デン−ニッケル合金層
DESCRIPTION OF SYMBOLS 1 ... Insulating base 1a ... Concave mounting part on which a semiconductor integrated circuit element is mounted 2 ... Cover 3 ... Semiconductor integrated circuit element 4 ··························································································································· Alloy layer

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】セラミックス焼結体から成り、上面に半導
体素子が載置される載置部を有する絶縁基体と、該絶縁
基体の半導体素子が載置される載置部周辺から下面にか
けて導出されるタングステンもしくはモリブデンから成
る複数個のメタライズ配線層と、前記絶縁基体の下面に
形成され、前記メタライズ配線層が電気的に接続される
複数個の接続パッドと、半田から成り、前記接続パッド
に取着されるボール状端子とから成る半導体素子収納用
パッケージであって、前記ボール状端子の取着される接
続パッド表面に厚みが0.5μm乃至3μmである、
ングステン−ニッケル合金層もしくはモリブデン−ニッ
ケル合金層を被着させたことを特徴とする半導体素子収
納用パッケージ。
1. An insulating base made of a ceramic sintered body and having a mounting portion on which a semiconductor element is mounted on an upper surface, and being led out from the vicinity of the mounting portion on which the semiconductor element is mounted on the insulating base to the lower surface. A plurality of metallized wiring layers made of tungsten or molybdenum, a plurality of connection pads formed on a lower surface of the insulating base, and electrically connected to the metallized wiring layers, and a solder. A tungsten-nickel alloy layer or molybdenum-nickel having a thickness of 0.5 μm to 3 μm on a surface of a connection pad to which the ball-shaped terminal is attached. A package for storing a semiconductor element, wherein an alloy layer is applied.
JP12173495A 1995-05-19 1995-05-19 Package for storing semiconductor elements Expired - Fee Related JP3176251B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12173495A JP3176251B2 (en) 1995-05-19 1995-05-19 Package for storing semiconductor elements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12173495A JP3176251B2 (en) 1995-05-19 1995-05-19 Package for storing semiconductor elements

Publications (2)

Publication Number Publication Date
JPH08316366A JPH08316366A (en) 1996-11-29
JP3176251B2 true JP3176251B2 (en) 2001-06-11

Family

ID=14818568

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12173495A Expired - Fee Related JP3176251B2 (en) 1995-05-19 1995-05-19 Package for storing semiconductor elements

Country Status (1)

Country Link
JP (1) JP3176251B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW484101B (en) 1998-12-17 2002-04-21 Hitachi Ltd Semiconductor device and its manufacturing method

Also Published As

Publication number Publication date
JPH08316366A (en) 1996-11-29

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