JP2514911Y2 - Package for storing semiconductor devices - Google Patents

Package for storing semiconductor devices

Info

Publication number
JP2514911Y2
JP2514911Y2 JP1990128569U JP12856990U JP2514911Y2 JP 2514911 Y2 JP2514911 Y2 JP 2514911Y2 JP 1990128569 U JP1990128569 U JP 1990128569U JP 12856990 U JP12856990 U JP 12856990U JP 2514911 Y2 JP2514911 Y2 JP 2514911Y2
Authority
JP
Japan
Prior art keywords
semiconductor element
package
insulating substrate
frame
sintered body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1990128569U
Other languages
Japanese (ja)
Other versions
JPH0485733U (en
Inventor
達海 坂元
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP1990128569U priority Critical patent/JP2514911Y2/en
Publication of JPH0485733U publication Critical patent/JPH0485733U/ja
Application granted granted Critical
Publication of JP2514911Y2 publication Critical patent/JP2514911Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【考案の詳細な説明】 (産業上の利用分野) 本考案は半導体素子を収容するための半導体素子収納
用パッケージの改良に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention relates to an improvement of a semiconductor element housing package for housing a semiconductor element.

(従来の技術) 従来、半導体素子、特に半導体集積回路素子(LSI)
等を収容するための半導体素子収納用パッケージは、一
般にアルミナセラミックス等の電気絶縁材料から成り、
その上面中央部に半導体素子を載置収容するための凹部
及び該凹部周辺より外周端にかけて導出されたタングス
テン、モリブデン、マンガン等の高融点金属粉末から成
るメタライズ配線層を有する絶縁基体と、半導体素子を
外部電気回路に電気的に接続するために前記メタライズ
配線層にロウ材を介し取着された外部リード端子と、蓋
体とから構成されており、絶縁基体の凹部底面に半導体
素子を載置固定するとともに該半導体素子の各電極をボ
ンディングワイヤを介してメタライズ配線層に接続し、
しかる後、絶縁基体上面に蓋体をガラス、樹脂等から成
る封止部材を介して接合させ、絶縁基体と蓋体とから成
る容器内部に半導体素子を気密封止にすることによって
最終製品としての半導体装置となる。
(Prior Art) Conventionally, a semiconductor element, particularly a semiconductor integrated circuit element (LSI)
The semiconductor element housing package for housing etc. is generally made of an electrically insulating material such as alumina ceramics,
An insulating substrate having a recess for mounting and accommodating a semiconductor element in the center of its upper surface and a metallized wiring layer made of a high melting point metal powder such as tungsten, molybdenum, or manganese led out from the periphery of the recess to the outer peripheral edge; External lead terminals, which are attached to the metallized wiring layer via a brazing material to electrically connect the semiconductor element to an external electric circuit, and a lid body. While fixing, each electrode of the semiconductor element is connected to the metallized wiring layer via a bonding wire,
After that, a lid is bonded to the upper surface of the insulating base through a sealing member made of glass, resin, or the like, and the semiconductor element is hermetically sealed inside the container made of the insulating base and the lid, thereby obtaining a final product. It becomes a semiconductor device.

しかしながら、近時、半導体素子は高密度化、高集積
化、高速駆動化が急激に進み、該半導体素子を上記従来
の半導体素子収納用パッケージに収容した場合、以下に
述べる欠点を有したものとなる。
However, in recent years, semiconductor devices have been rapidly increased in density, integration, and driving speed, and when the semiconductor device is housed in the conventional semiconductor device housing package, it has the following drawbacks. Become.

即ち、 (1)半導体素子を構成するシリコンとパッケージの絶
縁基体を構成するアルミナセラミックスの熱膨張係数が
それぞれ3.0〜3.5×10-6/℃、6.0〜7.5×10-6/℃であ
り、大きく相違することから両者に半導体素子を作動さ
せた際等に発生する熱が印加されると両者間に大きな熱
応力が発生し、該熱応力によって半導体素子が破損した
り、絶縁基体より剥離して半導体装置としての機能を喪
失させてしまう。
That is, (1) thermal expansion coefficient of the alumina ceramic constituting the silicon and package insulating substrate of the semiconductor device are each 3.0~3.5 × 10 -6 /℃,6.0~7.5×10 -6 / ℃ , large Due to the difference, when heat generated when the semiconductor element is operated is applied to both, a large thermal stress is generated between the two, and the semiconductor element is damaged by the thermal stress or peeled from the insulating substrate. The function as a semiconductor device is lost.

(2)パッケージの絶縁基体を構成するアルミナセラミ
ックスはその誘電率が9〜10(室温1MHz)と高いため絶
縁基体に設けたメタライズ配線層を伝わる電気信号の伝
播速度が遅く、そのため電気信号の高速伝播を要求する
半導体素子はその収容が不可となる。
(2) Since the alumina ceramics that constitutes the insulating base of the package has a high dielectric constant of 9 to 10 (room temperature 1MHz), the propagation speed of the electric signal transmitted through the metallized wiring layer provided on the insulating base is slow, and therefore the high speed of the electric signal. A semiconductor element that requires propagation cannot be accommodated.

(3)パッケージの絶縁基体を構成するアルミナセラミ
ックスはその熱伝導率が17W/m・K程度と低いため半導
体素子が作動時に発生する熱を大気中に良好に放散させ
ることができず、その結果、半導体素子を該素子自身が
発生する熱によって高温とし、誤動作を起こさせてしま
う。
(3) The thermal conductivity of the alumina ceramics that constitutes the insulating base of the package is as low as about 17 W / m · K, so the heat generated during the operation of the semiconductor element cannot be dissipated into the atmosphere satisfactorily. The semiconductor element is heated to a high temperature by the heat generated by the element itself, causing a malfunction.

等の欠点を有していた。It had a defect such as.

そこで上記欠点を解消するために半導体素子が載固定
される部分を熱伝導率が100W/m/K以上、熱膨張係数が半
導体素子の熱膨張係数に近い4.6×10-6/℃である窒化
アルミニウム質焼結体で、またメタライズ配線層を施す
部分を誘電率が6.4(室温1MHz)と低いムライト質焼結
体で形成し、各々を銀ロウ等のロウ材を介して取着した
構造の半導体素子収納用パッケージが提案されている。
Therefore, in order to eliminate the above-mentioned drawbacks, the portion where the semiconductor element is mounted and fixed has a thermal conductivity of 100 W / m / K or more and a thermal expansion coefficient of 4.6 × 10 −6 / ° C. close to that of the semiconductor element. With a structure in which aluminum-based sintered material is used, and the metallized wiring layer part is made of mullite-based sintered material with a low dielectric constant of 6.4 (room temperature 1 MHz), and each is attached via a brazing material such as silver solder. A package for housing a semiconductor device has been proposed.

しかしながら、窒化アルミニウム質焼結体とムライト
質焼結体とを銀ロウ材を介して取着した場合、銀ロウ材
のびビッカース硬度(Hv)がHv≧83と硬いこと及び窒化
アルミニウム質焼結体とムライト質焼結体はその各々の
熱膨張係数が4.6×10-6/℃、4.2×10-6/℃と近似する
ものの若干の差を有していること等から両者をロウ付け
する際、ロウ付け面積が4.0mm2以上の広いものとなると
両者間に大きな熱応力が発生し、該熱応力によって窒化
アルミニウム質焼結体とムライト質焼結体との取着強度
が低下したり、機械的強度の弱いムライト質焼結体が破
損したりするという欠点を誘発してしまう。
However, when the aluminum nitride sintered body and the mullite sintered body are attached via the silver brazing material, the silver brazing material has a high Vickers hardness (Hv) of Hv ≧ 83 and the aluminum nitride sintering body when the mullite sintered material is brazing both from like to have a slight difference in that the thermal expansion coefficient of each of which approximates a 4.6 × 10 -6 /℃,4.2×10 -6 / ℃ When the brazing area is as wide as 4.0 mm 2 or more, a large thermal stress is generated between the two, and the bonding strength between the aluminum nitride sintered body and the mullite sintered body is reduced by the thermal stress, or This causes a defect that the mullite sintered body having low mechanical strength is damaged.

(考案の目的) 本考案は上記欠点に鑑み案出されたもので、その目的
は窒化アルミニウム質焼結体とムライト質焼結体とを強
固に取着し、内部に高密度化、高集積化、高速駆動化し
た半導体素子を気密に収容することができる半導体素子
収納用パッケージを提供することにある。
(Purpose of the Invention) The present invention has been devised in view of the above-mentioned drawbacks, and the purpose thereof is to firmly attach the aluminum nitride sintered body and the mullite sintered body, and to achieve high density and high integration inside. Another object of the present invention is to provide a semiconductor element housing package capable of hermetically housing a semiconductor element that has been driven at high speed and driven at high speed.

(課題を解決するための手段) 本考案は窒化アルミニウム質焼結体から成り、上面に
半導体素子が載置される載置部を有する絶縁基体に、前
記載置部を囲繞するようにしてムライト質焼結体から成
る枠体をロウ材を介し取着した構造の半導体素子収納用
パッケージにおいて、前記ロウ材のビッカース硬度(H
v)がHv≦70であることを特徴とするものである。
(Means for Solving the Problems) The present invention is made of an aluminum nitride sintered body, and an insulating substrate having a mounting portion on which a semiconductor element is mounted is surrounded by an insulating substrate. In a package for storing a semiconductor element, in which a frame made of a quality sintered body is attached via a brazing material, the Vickers hardness (H
v) is Hv ≦ 70.

(実施例) 次に本考案を添付図面に基づき詳細に説明する。(Example) Next, this invention is demonstrated in detail based on an accompanying drawing.

第1図は本考案の半導体素子収納用パッケージの一実
施例を示し、1は絶縁基体、2は枠体である。
FIG. 1 shows an embodiment of a package for housing a semiconductor device of the present invention, in which 1 is an insulating base and 2 is a frame.

前記絶縁基体1はその上面中央部に半導体素子3が載
置される凸状の載置部1aが設けてあり、該凸状載置部1a
上には半導体素子3が接着材を介し取着される。
The insulating base 1 is provided with a convex mounting portion 1a on which the semiconductor element 3 is mounted, in the center of the upper surface thereof.
The semiconductor element 3 is attached to the upper side with an adhesive.

前記絶縁基体1は窒化アルミニウム質焼結体から成
り、該窒化アルミニウム質焼結体はその熱伝導率が100W
/m・K以上と高く、熱を伝導し易い材質であることから
絶縁基体1上に半導体素子3を載置固定した場合、絶縁
基体1は半導体素子3が発する熱を吸収するとともに該
吸収した熱を大気中に良好に拡散させることができ、そ
の結果、半導体素子3を常に低温となし、半導体素子3
を長期間にわたり正常、且つ安定に作動させることが可
能となる。
The insulating substrate 1 is made of an aluminum nitride sintered body, and the aluminum nitride sintered body has a thermal conductivity of 100 W.
When the semiconductor element 3 is mounted and fixed on the insulating substrate 1, the insulating substrate 1 absorbs the heat generated by the semiconductor element 3 and absorbs the heat, because the material is as high as / m · K or more and easily conducts heat. The heat can be well diffused into the atmosphere, and as a result, the semiconductor element 3 is always kept at a low temperature,
Can be operated normally and stably for a long period of time.

また前記絶縁基体1を構成する窒化アルミニウム質焼
結体はその熱膨張係数が4.6×10-6/℃であり、半導体
素子3の熱膨張係数に近く、且つ両者の接合部面積が狭
いことから絶縁基体1の載置部1a上に半導体素子3を載
置固定した後、両者に半導体素子3を作動させた際等に
発生する熱が印加されたとしても両者間には大きな熱応
力が発生することはなく、該熱応力によって半導体素子
3が破損したり、絶縁基体1より剥離したりすることは
ない。
Further, since the aluminum nitride sintered body constituting the insulating substrate 1 has a thermal expansion coefficient of 4.6 × 10 −6 / ° C., which is close to the thermal expansion coefficient of the semiconductor element 3 and has a small joint area between them. After mounting and fixing the semiconductor element 3 on the mounting portion 1a of the insulating substrate 1, even if heat generated when the semiconductor element 3 is operated is applied to both, a large thermal stress is generated between them. The semiconductor element 3 is not damaged or peeled off from the insulating substrate 1 due to the thermal stress.

尚、前記窒化アルミニウム質焼結体から成る絶縁基体
1は例えば、主原料としての窒化アルミニウム粉末に焼
結助剤としての酸化イットリウム、カルシア等の粉末及
び適当な有機溶剤、溶媒を添加混合して泥漿物を作ると
ともに該泥漿物をドクターブレード法を採用することに
よってグリーンシート(生シート)を形成し、しかる
後、前記グリーンシートに適当な打ち抜き加工を施すと
ともにこれを複数枚積層し、約1800℃の高温で焼成する
ことによって製作される。
The insulating substrate 1 made of the aluminum nitride sintered body is prepared by adding aluminum nitride powder as a main material, powders of yttrium oxide, calcia, etc. as a sintering aid, and an appropriate organic solvent, and a solvent. A green sheet (raw sheet) is formed by making a sludge and adopting a doctor blade method to the sludge, and thereafter, the green sheet is subjected to an appropriate punching process and a plurality of these are laminated to each other, and about 1800 It is manufactured by firing at a high temperature of ℃.

また前記絶縁基体1の上面外周端には該絶縁基体1上
面に設けた凸状の載置部1aを囲繞するようにして枠体2
がロウ付け取着されており、絶縁基体1と枠体2とで半
導体素子3を収容するための空所が内部に形成される。
Further, the outer peripheral edge of the upper surface of the insulating base 1 is surrounded by a convex mounting portion 1a provided on the upper surface of the insulating base 1 so as to surround the frame 2
Are brazed and attached, and a space for accommodating the semiconductor element 3 is formed inside by the insulating base 1 and the frame 2.

前記絶縁基体1と枠体2との取着は、枠体2の下面に
予めメタライズ金属層7を被着させておき、該メタライ
ズ金属層7を絶縁基体1の上面に予め被着させておいた
メタライズ金属層8にロウ材9を介し取着することによ
って行われる。
The insulating base 1 and the frame 2 are attached to each other by depositing a metallized metal layer 7 on the lower surface of the frame 2 in advance and then depositing the metallized metal layer 7 on the upper surface of the insulating substrate 1 in advance. The brazing material 9 is attached to the metallized metal layer 8 which has been formed.

前記絶縁基体1及び枠体2の各々に被着させたメタラ
イズ金属層7、8はタングステン、モリブデン、マンガ
ン等の高融点金属粉末から成り、該高融点金属粉末に有
機溶剤、溶媒を添加混合して得た金属ペーストを絶縁基
体1上面及び枠体2の下面に従来周知のスクリーン印刷
法により印刷塗布し、しかる後、これを高温で焼き付け
ることよって絶縁基体1及び枠体2の各々に被着され
る。
The metallized metal layers 7 and 8 deposited on the insulating substrate 1 and the frame 2 are made of refractory metal powder such as tungsten, molybdenum, and manganese. An organic solvent and a solvent are added to and mixed with the refractory metal powder. The metal paste thus obtained is applied by printing to the upper surface of the insulating substrate 1 and the lower surface of the frame body 2 by a conventionally known screen printing method, and then baked at a high temperature to adhere to each of the insulating substrate 1 and the frame body 2. To be done.

また前記絶縁基体1と枠体2とを取着するロウ材9は
例えば金、銀、あるいは金、銀を主成分とする金属から
成り、そのビッカース硬度(Hv)はHv≦70のものであ
る。
The brazing material 9 for attaching the insulating base 1 and the frame 2 is made of, for example, gold, silver, or a metal containing gold or silver as a main component, and its Vickers hardness (Hv) is Hv ≦ 70. .

前記ロウ材9はそのビッカース硬度(Hv)がHv≦70で
軟質なものであることから絶縁基体1と枠体2とをロウ
付け取着する際、ロウ付け面積が4.0mm2以上の広いもと
なり、絶縁基体1と枠体2との間に大きな熱応力が発生
したとしても該熱応力はロウ材9を変形させることによ
って吸収され、これによって絶縁基体1と枠体2との取
着強度が低下したり、枠体2が破損したりすることはな
い。
Since the brazing material 9 has a Vickers hardness (Hv) of Hv ≦ 70 and is soft, the brazing area is 4.0 mm 2 or more when the insulating base body 1 and the frame body 2 are brazed and attached. Therefore, even if a large thermal stress is generated between the insulating base 1 and the frame body 2, the thermal stress is absorbed by deforming the brazing material 9, whereby the attachment strength between the insulating base body 1 and the frame body 2 is increased. Does not decrease and the frame 2 is not damaged.

尚、前記ロウ材9はそのビッカース硬度(Hv)がHv>
70となるとロウ材9が硬くなりすぎ、ロウ材9が絶縁基
体1と枠体2との間に発生する熱応力を完全に吸収する
ことができなくなって絶縁基体1と枠体2との取着強度
が低下したり、枠体2が破損したりしてしまう。従っ
て、絶縁基体1と枠体2とを取着するロウ材9はそのビ
ッカース硬度(Hv)がHv≦70に特定される。
The brazing material 9 has a Vickers hardness (Hv) of Hv>
When it becomes 70, the brazing material 9 becomes too hard, and the brazing material 9 cannot completely absorb the thermal stress generated between the insulating base 1 and the frame 2, so that the insulating base 1 and the frame 2 are separated from each other. The wearing strength may be reduced, or the frame body 2 may be damaged. Therefore, the Vickers hardness (Hv) of the brazing material 9 for attaching the insulating base body 1 and the frame body 2 is specified as Hv ≦ 70.

また前記絶縁基体1に取着される枠体2はムライト質
焼結体から成り、例えばムライト、シリカ、マグネシ
ア、カルシア等の原料粉末に適当な有機溶剤、溶媒を添
加混合して泥漿状となすとともにこれをドクターブレー
ド法を採用することによってグリーンシート(生シー
ト)を形成し、しかる後、前記グリーンシートに適当な
打ち抜き加工を施すとともに複数枚積層し、約1400〜18
00℃の温度で焼成することによって製作される。
The frame 2 attached to the insulating substrate 1 is made of a mullite sintered body. For example, mullite, silica, magnesia, calcia, and other raw material powders are mixed with an appropriate organic solvent and a solvent to form a slurry. A green sheet (green sheet) is formed by adopting this together with the doctor blade method, and then the green sheet is subjected to appropriate punching processing and a plurality of layers are laminated, and about 1400 to 18
It is manufactured by firing at a temperature of 00 ° C.

前記枠体2はその内部にモリブデン、タングステン等
の高融点金属粉末から成るメタライズ配線層4が埋設し
てあり、該メタライズ配線層4は半導体素子3の電極を
外部リードピン5に接続する作用を為し、その一端に外
部リードピン5が、また他端には半導体素子3の電極に
接続されるボンディングワイヤ6が取着される。
The frame body 2 has a metallized wiring layer 4 made of a high melting point metal powder such as molybdenum or tungsten embedded therein, and the metallized wiring layer 4 serves to connect the electrode of the semiconductor element 3 to the external lead pin 5. The external lead pin 5 is attached to one end thereof, and the bonding wire 6 connected to the electrode of the semiconductor element 3 is attached to the other end thereof.

前記枠体2はそれを構成するムライト質焼結体の誘導
率が6.3(室温1MHz)と低いことから枠体2に埋設した
メタライズ配線層4を伝わる電気信号の伝播速度を極め
て速いものとなすことができ、これによってパッケージ
内に電気信号の伝播速度が速い高速駆動を行う半導体素
子の収容も可能となる。
Since the frame body 2 has a low induction rate of 6.3 (room temperature 1 MHz) of the mullite sintered body constituting the frame body 2, the propagation speed of the electric signal transmitted through the metallized wiring layer 4 embedded in the frame body 2 is extremely high. As a result, it becomes possible to accommodate a semiconductor element which is driven at high speed and has a high electric signal propagation speed in the package.

また前記枠体2に埋設したメタライズ配線層4に取着
される外部リードピン5は内部に収容する半導体素子3
の各電極を外部電気回路に電気的に接続する作用を為
し、コバール金属、42Alloy等の金属をピン状に成した
ものが使用される。
In addition, the external lead pin 5 attached to the metallized wiring layer 4 embedded in the frame 2 has the semiconductor element 3 housed therein.
The electrodes are used to electrically connect each electrode to an external electric circuit, and a metal such as Kovar metal or 42Alloy is formed into a pin shape.

尚、前記外部リードピン5の外表面にニッケル、金等
から成る良導電性で、且つ耐蝕性に優れた金属を従来周
知のメッキ法により2.0乃至10.0μmの厚みに層着させ
ておくと、外部リードピン5と外部電気回路との電気的
接続が良好となり、また外部リードピン5の酸化腐食が
有効に防止される。従って、外部リードピン5の外表面
にはニッケル、金等から成る良導電性で、且つ耐蝕性に
優れた金属を2.0乃至10.0μmの厚みに層着させておく
ことが好ましい。
It should be noted that when a metal having good conductivity and excellent corrosion resistance made of nickel, gold, or the like is layered on the outer surface of the external lead pin 5 to a thickness of 2.0 to 10.0 μm by a conventionally known plating method, The electrical connection between the lead pin 5 and the external electric circuit is improved, and the oxidative corrosion of the external lead pin 5 is effectively prevented. Therefore, it is preferable to deposit a metal, such as nickel or gold, having good conductivity and excellent corrosion resistance on the outer surface of the external lead pin 5 in a thickness of 2.0 to 10.0 μm.

かくして本考案の半導体素子収納用パッケージによれ
ば、枠体2が取着された絶縁基体1の凸状載置部1a上に
半導体素子3を取着固定し、半導体素子3の各電極をボ
ンディングワイヤ6を介してメタライズ配線層4に接続
するとともに蓋体10を枠体2の上面に封止部材を介して
取着することによって最終製品としての半導体装置とな
る。
Thus, according to the semiconductor element housing package of the present invention, the semiconductor element 3 is fixedly mounted on the convex mounting portion 1a of the insulating substrate 1 to which the frame body 2 is mounted, and each electrode of the semiconductor element 3 is bonded. The semiconductor device as a final product is obtained by connecting to the metallized wiring layer 4 via the wire 6 and attaching the lid 10 to the upper surface of the frame 2 via a sealing member.

(考案の効果) 本考案の半導体素子収納用パッケージによれば半導体
素子が載置固定される絶縁基体を熱伝導率が100w/m・K
以上の窒化アルミニウム質焼結体で形成したことから内
部に収容する半導体素子の発する熱は絶縁基体を介して
大気中に良好に放散させ、その結果、半導体素子を常に
低温となし、半導体素子を長期間にわたり正常、且つ安
定に作動させることができる。
(Effect of the Invention) According to the package for housing a semiconductor device of the present invention, the thermal conductivity of the insulating substrate on which the semiconductor device is mounted and fixed is 100 w / mK.
The heat generated by the semiconductor element housed inside, which is formed of the aluminum nitride sintered body described above, is satisfactorily dissipated to the atmosphere through the insulating substrate, and as a result, the semiconductor element is always kept at a low temperature and It can operate normally and stably for a long period of time.

また半導体素子が載置固定される絶縁基体は該半導体
素子の熱膨張係数に近い熱膨張係数を有する窒化アルミ
ニウム質焼結体より成っていることから絶縁基体に半導
体素子を載置固定した後、絶縁基体と半導体素子の両者
に半導体素子を作動させた際等に発生する熱が印加され
たとしても両者間には大きな熱応力が発生することはな
く、該熱応力によって半導体素子が破損したり、絶縁基
体より剥離したりすることはない。
Since the insulating substrate on which the semiconductor element is mounted and fixed is made of an aluminum nitride sintered body having a thermal expansion coefficient close to that of the semiconductor element, after mounting and fixing the semiconductor element on the insulating substrate, Even if heat generated when the semiconductor element is actuated is applied to both the insulating substrate and the semiconductor element, a large thermal stress does not occur between the two, and the semiconductor element may be damaged by the thermal stress. It does not peel off from the insulating substrate.

更に内部に収容した半導体素子の各電極を外部電気回
路に接続するメタライズ配線層を誘電率が6.3(室温1MH
z)と低いムライト質焼結体から成る枠体に形成したこ
とからメタライズ配線層4を伝わる電気信号の伝播速度
を極めて速いものとなすことができ、その結果、パッケ
ージ内部に電気信号の伝播速度が速い高速駆動を行う半
導体素子の収容も可能となる。
Furthermore, the metallized wiring layer that connects each electrode of the semiconductor element housed inside to the external electric circuit has a dielectric constant of 6.3 (room temperature 1 MH
z) and a frame body made of a low mullite sintered body, the propagation speed of the electric signal transmitted through the metallized wiring layer 4 can be made extremely fast. As a result, the propagation speed of the electric signal inside the package can be increased. It is also possible to accommodate a semiconductor element that drives at high speed and at high speed.

また更に窒化アルミニウム質焼結体から成る絶縁基体
とムライト質焼結体から成る枠体とをビッカース硬度
(Hv)がHv≦70のロウ材を使用して取着したことから絶
縁基体と枠体とをロウ付け取着する際、ロウ付け面積が
4.0mm2以上の広いもとなり、絶縁基体と枠体との間に大
きな熱応力が発生したとしても該熱応力はロウ材を変形
させることによって吸収され、これによって絶縁基体と
枠体との取着強度が低下したり、機械的強度の弱い枠体
が破損したりすることもない。
Furthermore, since the insulating base body made of the aluminum nitride sintered body and the frame body made of the mullite sintered body were attached by using the brazing material having the Vickers hardness (Hv) of Hv ≦ 70, the insulating base body and the frame body were attached. When brazing and attaching and, the brazing area
4.0 mm 2 or more wide basis becomes, heat stress as a large thermal stress is generated between the insulating substrate and the frame is absorbed by deforming the brazing material, whereby preparative between the insulating substrate and the frame The adhesion strength does not decrease, and the frame having weak mechanical strength is not damaged.

【図面の簡単な説明】[Brief description of drawings]

第1図は本考案の半導体素子収納用パッケージの一実施
例を示す断面図である。 1…絶縁基体、1a…凸状の載置部 2…枠体、9…ロウ材
FIG. 1 is a sectional view showing an embodiment of a package for housing a semiconductor device of the present invention. DESCRIPTION OF SYMBOLS 1 ... Insulating base body, 1a ... Convex mounting part 2 ... Frame body, 9 ... Brazing material

Claims (1)

(57)【実用新案登録請求の範囲】(57) [Scope of utility model registration request] 【請求項1】窒化アルミニウム質焼結体から成り、上面
に半導体素子が載置される載置部を有する絶縁基体に、
前記載置部を囲繞するようにしてムライト質焼結体から
成る枠体をロウ材を介し取着した構造の半導体素子収納
用パッケージにおいて、前記ロウ材のビッカース硬度
(Hv)がHv≦70であることを特徴とする半導体素子収納
用パッケージ。
1. An insulating substrate made of an aluminum nitride sintered body, having an upper surface on which a semiconductor element is mounted,
In a package for storing a semiconductor device, in which a frame made of a mullite sintered body is attached via a brazing material so as to surround the mounting portion, the Vickers hardness (Hv) of the brazing material is Hv ≦ 70. A package for housing a semiconductor element, which is characterized in that
JP1990128569U 1990-11-29 1990-11-29 Package for storing semiconductor devices Expired - Lifetime JP2514911Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990128569U JP2514911Y2 (en) 1990-11-29 1990-11-29 Package for storing semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990128569U JP2514911Y2 (en) 1990-11-29 1990-11-29 Package for storing semiconductor devices

Publications (2)

Publication Number Publication Date
JPH0485733U JPH0485733U (en) 1992-07-24
JP2514911Y2 true JP2514911Y2 (en) 1996-10-23

Family

ID=31876024

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990128569U Expired - Lifetime JP2514911Y2 (en) 1990-11-29 1990-11-29 Package for storing semiconductor devices

Country Status (1)

Country Link
JP (1) JP2514911Y2 (en)

Also Published As

Publication number Publication date
JPH0485733U (en) 1992-07-24

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