JPH08316366A - Package for semiconductor element - Google Patents
Package for semiconductor elementInfo
- Publication number
- JPH08316366A JPH08316366A JP12173495A JP12173495A JPH08316366A JP H08316366 A JPH08316366 A JP H08316366A JP 12173495 A JP12173495 A JP 12173495A JP 12173495 A JP12173495 A JP 12173495A JP H08316366 A JPH08316366 A JP H08316366A
- Authority
- JP
- Japan
- Prior art keywords
- alloy layer
- ball
- tungsten
- molybdenum
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
- H05K1/092—Dispersed materials, e.g. conductive pastes or inks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体素子を収容するた
めの半導体素子収納用パッケージに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element housing package for housing a semiconductor element.
【０００２】[0002]
【従来の技術】従来、半導体素子、特にＬＳＩ（大規模
集積回路素子）等の半導体集積回路素子を収容するため
の半導体素子収納用パッケージは、一般にアルミナセラ
ミックス等の電気絶縁材料から成り、その上面の略中央
部に半導体集積回路素子を収容するための凹部を有する
絶縁基体と、前記絶縁基体の凹部周辺から下面にかけて
導出されるタングステン、モリブデン等の高融点金属粉
末から成る複数個のメタライズ配線層と、前記絶縁基体
の下面に形成され、メタライズ配線層が電気的に接続さ
れる複数個の接続パッドと、前記接続パッドに取着され
る半田から成るボール状端子と、蓋体とから構成されて
おり、絶縁基体の凹部底面に半導体集積回路素子をガラ
ス、樹脂等から成る接着剤を介して接着固定させ、半導
体集積回路素子の各電極とメタライズ配線層とをボンデ
ィングワイヤを介して電気的に接続させるとともに絶縁
基体上面に蓋体をガラス、樹脂等の封止材を介して接合
させ、絶縁基体と蓋体とから成る容器内部に半導体集積
回路素子を気密に収容することによって製品としての半
導体装置となる。2. Description of the Related Art Conventionally, a semiconductor element housing package for housing a semiconductor element, in particular, a semiconductor integrated circuit element such as an LSI (Large Scale Integrated Circuit Element) is generally made of an electrically insulating material such as alumina ceramics and has an upper surface. An insulating base having a recess for accommodating a semiconductor integrated circuit element in the substantially central part of the base, and a plurality of metallized wiring layers made of refractory metal powder such as tungsten and molybdenum led out from the periphery of the recess to the lower surface of the insulating base. And a plurality of connection pads formed on the lower surface of the insulating substrate and electrically connected to the metallized wiring layer, ball-shaped terminals made of solder attached to the connection pads, and a lid. The semiconductor integrated circuit element is adhered and fixed to the bottom surface of the recess of the insulating substrate with an adhesive made of glass, resin, or the like. The electrode and the metallized wiring layer are electrically connected via a bonding wire, and the lid is joined to the upper surface of the insulating base through a sealing material such as glass or resin, and the inside of the container including the insulating base and the lid is joined. A semiconductor device as a product is obtained by hermetically housing the semiconductor integrated circuit element.
【０００３】かかる半導体装置は絶縁基体下面の接続パ
ッドに取着されている半田から成るボール状端子を外部
電気回路基板の配線導体上に載置当接させ、しかる後、
前記ボール状端子を約２００〜２５０℃の温度で加熱溶
融し、ボール状端子を配線導体に接合させることによっ
て外部電気回路基板上に実装され、同時に半導体素子収
納用パッケージの内部に収容されている半導体集積回路
素子はその各電極がメタライズ配線層及びボール状端子
を介して外部電気回路に接続されることとなる。In such a semiconductor device, ball-shaped terminals made of solder attached to the connection pads on the lower surface of the insulating substrate are placed and abutted on the wiring conductors of the external electric circuit board, and thereafter,
The ball-shaped terminal is heated and melted at a temperature of about 200 to 250 ° C., and the ball-shaped terminal is bonded to a wiring conductor to be mounted on an external electric circuit board, and at the same time, housed inside a semiconductor element housing package. Each electrode of the semiconductor integrated circuit element is connected to an external electric circuit via the metallized wiring layer and the ball-shaped terminal.
【０００４】尚、前記半導体素子収納用パッケージは接
続パッドに半田から成るボール状端子を強固に取着する
ための接続パッド表面には通常、厚さ２μｍ乃至８μｍ
程度のニッケルがメッキ法により層着されている。In the package for accommodating semiconductor elements, the thickness of the connecting pad for firmly attaching the ball-shaped terminal made of solder to the connecting pad is usually 2 μm to 8 μm.
Some nickel is layered by the plating method.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、この従
来の半導体素子収納用パッケージにおいては、接続パッ
ドの表面へのニッケルメッキ層の層着が平面的であるこ
と及びアルミナセラミックス等から成る絶縁基体の熱膨
張係数が約６．５×１０-6／℃であるのに対し、外部電
気回路基板は一般にガラスエポキシ樹脂から成り、その
熱膨張係数が２×１０-5／℃〜４×１０-5／℃で両者大
きく相違することから半導体素子収納用パッケージの内
部に半導体集積回路素子を収容し、しかる後、外部電気
回路基板に実装した場合、半導体集積回路素子の作動時
に発する熱が絶縁基体と外部電気回路基板の両方に繰り
返し印加されると前記半導体素子収納用パッケージの絶
縁基体と外部電気回路基板との間に両者の熱膨張係数の
相違に起因する大きな熱応力が発生するとともにこれが
絶縁基体下面の接続パッドとボール状端子との間に作用
してボール状端子を接続パッド表面に層着されているニ
ッケルメッキ層とともに剥離させてしまい、その結果、
半導体素子収納用パッケージの内部に収容する半導体集
積回路素子の各電極を長期間にわたり所定の外部電気回
路に電気的に接続させることができないという欠点を有
していた。However, in this conventional package for accommodating semiconductor elements, the nickel plating layer is layered flat on the surface of the connection pad and the heat of the insulating substrate made of alumina ceramics or the like is used. While the expansion coefficient is about 6.5 × 10 −6 / ° C., the external electric circuit board is generally made of glass epoxy resin and has a thermal expansion coefficient of 2 × 10 −5 / ° C. to 4 × 10 −5 / Since the two greatly differ at ℃, when the semiconductor integrated circuit device is housed inside the semiconductor device housing package and then mounted on the external electric circuit board, the heat generated during the operation of the semiconductor integrated circuit device is generated by the insulating substrate and the outside. When repeatedly applied to both of the electric circuit boards, a large difference is caused between the insulating base of the semiconductor element housing package and the external electric circuit board due to the difference in thermal expansion coefficient between the two. A the same time thermal stress is generated will by stripping with nickel plating layer are particle course a ball-shaped terminal connection pad surface acts between a connection pad and the ball-shaped terminals of the insulating base lower surface, as a result,
It has a drawback that each electrode of the semiconductor integrated circuit device accommodated in the semiconductor device accommodation package cannot be electrically connected to a predetermined external electric circuit for a long period of time.
【０００６】[0006]
【発明の目的】本発明は上記欠点に鑑み案出されたもの
で、その目的は半田からなるボール状端子を接続パッド
に強固に取着させ、内部に収容する半導体集積回路素子
の各電極を長期間にわたり所定の外部電気回路に確実に
電気的接続することができる半導体素子収納用パッケー
ジを提供することにある。SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks, and an object of the invention is to firmly attach a ball-shaped terminal made of solder to a connection pad and to mount each electrode of a semiconductor integrated circuit element to be housed inside. An object of the present invention is to provide a package for accommodating a semiconductor element that can be reliably electrically connected to a predetermined external electric circuit for a long period of time.
【０００７】[0007]
【課題を解決するための手段】本発明はセラミックス焼
結体から成り、上面に半導体素子が載置される載置部を
有する絶縁基体と、該絶縁基体の半導体素子が載置され
る載置部周辺から下面にかけて導出されるタングステン
もしくはモリブデンから成る複数個のメタライズ配線層
と、前記絶縁基体の下面に形成され、前記メタライズ配
線層が電気的に接続される複数個の接続パッドと、半田
から成り、前記接続パッドに取着されるボール状端子と
から成る半導体素子収納用パッケージであって、前記ボ
ール状端子の取着される接続パッド表面にタングステン
ーニッケル合金層もしくはモリブデンーニッケル合金層
を被着させたことを特徴とするのである。SUMMARY OF THE INVENTION The present invention is made of a ceramic sintered body and has an insulating base having a mounting portion on which a semiconductor element is mounted, and a mounting on which the semiconductor element of the insulating base is mounted. A plurality of metallized wiring layers made of tungsten or molybdenum from the periphery of the portion to the lower surface, a plurality of connection pads formed on the lower surface of the insulating substrate and electrically connected to the metallized wiring layer, and from solder. A package for storing a semiconductor element, which comprises a ball-shaped terminal attached to the connection pad, wherein a tungsten-nickel alloy layer or a molybdenum-nickel alloy layer is formed on the surface of the connection pad to which the ball-shaped terminal is attached. It is characterized by being attached.
【０００８】また本発明は前記接続パッド表面のタング
ステンーニッケル合金層もしくはモリブデンーニッケル
合金層の厚みを０．５μｍ乃至３μｍとすることを特徴
とするものである。Further, the present invention is characterized in that the thickness of the tungsten-nickel alloy layer or the molybdenum-nickel alloy layer on the surface of the connection pad is 0.5 μm to 3 μm.
【０００９】[0009]
【作用】本発明の半導体素子収納用パッケージによれ
ば、ボール状端子が取着される接続パッド表面にタング
ステンーニッケル合金層もしくはモリブデンーニッケル
合金層を被着させたことから接続パッドとタングステン
ーニッケル合金層もしくはモリブデンーニッケル合金
層、及びタングステンーニッケル合金層もしくはモリブ
デンーニッケル合金層とボール状端子の接合強度が強固
となり、接続パッド及びボール状端子に半導体素子収納
用パッケージの絶縁基体と外部電気回路基板の熱膨張係
数の相違に起因する大きな熱応力が作用してボール状端
子が接続パッドより剥離することはなく、その結果、半
導体素子収納用パッケージの内部に収容する半導体集積
回路素子の各電極を長期間にわたり所定の外部電気回路
に正確に電気的接続させることが可能となる。According to the package for housing a semiconductor element of the present invention, since the tungsten-nickel alloy layer or the molybdenum-nickel alloy layer is deposited on the surface of the connection pad to which the ball-shaped terminal is attached, the connection pad and the tungsten- The bonding strength between the nickel alloy layer or the molybdenum-nickel alloy layer, the tungsten-nickel alloy layer or the molybdenum-nickel alloy layer and the ball-shaped terminal becomes strong, and the insulating base of the package for storing the semiconductor element and the outside are connected to the connection pad and the ball-shaped terminal. The ball-shaped terminal does not peel off from the connection pad due to the large thermal stress caused by the difference in the thermal expansion coefficient of the electric circuit board, and as a result, the semiconductor integrated circuit element accommodated in the semiconductor element accommodation package is Precise electrical connection of each electrode to the specified external electrical circuit over a long period of time Rukoto is possible.
【００１０】また本発明の半導体素子収納用パッケージ
によれば接続パッド表面のタングステンーニッケル合金
層もしくはモリブデンーニッケル合金層の厚みを０．５
μｍ乃至３μｍとすると接続パッドとタングステンーニ
ッケル合金層もしくはモリブデンーニッケル合金層、及
びタングステンーニッケル合金層もしくはモリブデンー
ニッケル合金層とボール状端子の接合がより強固とな
り、半導体集積回路素子の外部電気回路への接続がより
高信頼性のものとなる。According to the package for housing a semiconductor device of the present invention, the thickness of the tungsten-nickel alloy layer or the molybdenum-nickel alloy layer on the surface of the connection pad is 0.5.
When the thickness is from 3 μm to 3 μm, the connection pad and the tungsten-nickel alloy layer or molybdenum-nickel alloy layer, and the tungsten-nickel alloy layer or molybdenum-nickel alloy layer and the ball-shaped terminal are more strongly bonded, and the external electric power of the semiconductor integrated circuit device is increased. The connection to the circuit is more reliable.
【００１１】[0011]
【実施例】次に本発明を添付図面に基づき詳細に説明す
る。図１及び図２は本発明にかかる半導体素子収納用パ
ッケージの一実施例を示し、１は絶縁基体、２は蓋体で
ある。この絶縁基体１と蓋体２とで半導体集積回路素子
３を収容する容器４が構成される。The present invention will now be described in detail with reference to the accompanying drawings. 1 and 2 show an embodiment of a package for housing a semiconductor device according to the present invention, in which 1 is an insulating base and 2 is a lid. The insulating base 1 and the lid 2 constitute a container 4 for housing the semiconductor integrated circuit element 3.
【００１２】前記絶縁基体１はその上面中央部に半導体
集積回路素子３が載置収容される凹状の載置部１ａが設
けてあり、該凹状の載置部１ａには半導体集積回路素子
３がガラス、樹脂等の接着剤を介して接着固定される。The insulating base 1 is provided with a concave mounting portion 1a in which the semiconductor integrated circuit element 3 is mounted and accommodated in the central portion of the upper surface thereof, and the semiconductor mounting circuit element 3 is mounted on the concave mounting portion 1a. It is fixed by adhesion through an adhesive such as glass or resin.
【００１３】前記絶縁基体１は酸化アルミニウム質焼結
体、ムライト質焼結体、窒化アルミニウム質焼結体、炭
化珪素質焼結体、ガラスセラミックス焼結体等の電気絶
縁材料から成り、例えば、酸化アルミニウム質焼結体か
ら成る場合、酸化アルミニウム、酸化珪素、酸化マグネ
シウム、酸化カルシウム等の原料粉末に適当な有機バイ
ンダー、溶剤等を添加混合して泥漿状となすとともにこ
れを従来周知のドクターブレード法やカレンダーロール
法等によりシート状に成形してセラミックグリーンシー
ト（セラミック生シート）を得、しかる後、前記セラミ
ックグリーンシートに適当な打ち抜き加工を施すととも
にこれを複数枚積層し、高温（約１６００℃）で焼成す
ることによって製作される。The insulating substrate 1 is made of an electrically insulating material such as an aluminum oxide sintered body, a mullite sintered body, an aluminum nitride sintered body, a silicon carbide sintered body, and a glass ceramic sintered body. When it is made of an aluminum oxide sintered body, it is made into a sludge form by adding and mixing an appropriate organic binder, a solvent, etc. to raw material powders of aluminum oxide, silicon oxide, magnesium oxide, calcium oxide, etc. Method to obtain a ceramic green sheet (ceramic green sheet) by a method such as a calendering method or a calender roll method. After that, the ceramic green sheet is appropriately punched and a plurality of layers are laminated at a high temperature (about 1600). It is manufactured by firing at (° C).
【００１４】また前記絶縁基体１は半導体集積回路素子
３が載置収容される凹状の載置部１ａ周辺から下面にか
けて複数個のメタライズ配線層５が、更に絶縁基体１の
下面には前記メタライズ配線層５が電気的に接続される
複数個の接続パッド６が各々被着形成されている。The insulating base 1 is provided with a plurality of metallized wiring layers 5 from the periphery of the concave mounting portion 1a in which the semiconductor integrated circuit device 3 is mounted and accommodated to the lower surface, and further, the lower surface of the insulating base 1 is provided with the metallized wiring. A plurality of connection pads 6 to which the layer 5 is electrically connected are respectively deposited.
【００１５】前記メタライズ配線層５及び接続パッド６
はタングステン、モリブデン等の高融点金属粉末から成
り、タングステン等の高融点金属粉末に適当な有機バイ
ンダー、可塑剤、溶剤を添加混合して得た金属ペースト
を絶縁基体１となるセラミックグリーンシートに予め従
来周知のスクリーン印刷法により所定パターンに印刷塗
布しておくことによって絶縁基体１の所定位置に所定パ
ターンに被着形成される。The metallized wiring layer 5 and the connection pad 6
Is a refractory metal powder such as tungsten or molybdenum, and a metal paste obtained by adding and mixing an appropriate organic binder, a plasticizer, and a solvent to the refractory metal powder such as tungsten is preliminarily applied to the ceramic green sheet serving as the insulating substrate 1. A predetermined pattern is printed and applied by a well-known screen printing method to form a predetermined pattern on the insulating substrate 1 at a predetermined position.
【００１６】前記メタライズ配線層５は半導体集積回路
素子３の各電極を後述する接続パッド６に取着されるボ
ール状端子７に電気的に接続させる作用を為し、絶縁基
体１の凹状の載置部１ａ周辺に位置する領域には半導体
集積回路素子３の各電極がボンディングワイヤ８を介し
て電気的に接続される。The metallized wiring layer 5 serves to electrically connect each electrode of the semiconductor integrated circuit element 3 to a ball-shaped terminal 7 attached to a connection pad 6 which will be described later, so that the insulating substrate 1 is mounted in a concave shape. Each electrode of the semiconductor integrated circuit element 3 is electrically connected to the region located around the mounting portion 1a via the bonding wire 8.
【００１７】また前記メタライズ配線層５と電気的に接
続されている接続パッド６は絶縁基体１にボール状端子
７を取着する際の下地金属層として作用し、接続パッド
６の表面には半田から成るボール状端子７が取着され
る。Further, the connection pad 6 electrically connected to the metallized wiring layer 5 acts as a base metal layer when the ball-shaped terminal 7 is attached to the insulating substrate 1, and the surface of the connection pad 6 is soldered. The ball-shaped terminal 7 consisting of is attached.
【００１８】前記ボール状端子７が取着される接続パッ
ド６はまたその表面に図２に示す如くタングステンーニ
ッケルもしくはモリブデンーニッケルから成る合金層９
が被着されており、該合金層９は接続パッド６の表面に
ニッケルをメッキ法より層着させ、しかる後、これを８
５０〜１０００℃の温度に加熱することによって接続パ
ッド６の表面に所定厚みに被着形成される。この場合、
タングステンーニッケルもしくはモリブデンーニッケル
から成る合金層９は接続パッド６とニッケル層とを加熱
により合金化させることによって形成されることから接
続パッド６に極めて強固に被着し、例えば絶縁基体１と
外部電気回路基板１０との熱膨張係数の相違に起因する
熱応力等が作用しても接続パッド６より剥離することは
ない。またこのタングステンーニッケルもしくはモリブ
デンーニッケルから成る合金層９は半田に対する濡れ性
（反応性）が極めて良く、これによって半田から成るボ
ール状端子７は合金層９を介して接続パッド６に強固に
取着される。The connection pad 6 to which the ball-shaped terminal 7 is attached also has an alloy layer 9 made of tungsten-nickel or molybdenum-nickel on the surface thereof as shown in FIG.
The alloy layer 9 is formed by depositing nickel on the surface of the connection pad 6 by a plating method.
By heating to a temperature of 50 to 1000 ° C., the surface of the connection pad 6 is adhered and formed to a predetermined thickness. in this case,
Since the alloy layer 9 made of tungsten-nickel or molybdenum-nickel is formed by alloying the connection pad 6 and the nickel layer by heating, the alloy layer 9 is adhered to the connection pad 6 extremely strongly, for example, the insulating substrate 1 and the outside. Even if thermal stress or the like due to the difference in thermal expansion coefficient from the electric circuit board 10 is applied, it does not separate from the connection pad 6. Further, the alloy layer 9 made of tungsten-nickel or molybdenum-nickel has an extremely good wettability (reactivity) with respect to solder, whereby the ball-shaped terminal 7 made of solder is firmly attached to the connection pad 6 via the alloy layer 9. Be worn.
【００１９】尚、前記接続パッド６表面に被着されるタ
ングステンーニッケルもしくはモリブデンーニッケルか
ら成る合金層９はその厚みが０．５μｍ未満であると接
続ッド６との被着強度が弱くなって熱応力等により剥離
し易くなり、また３μｍを越えるとタングステンーニッ
ケルもしくはモリブデンーニッケルから成る合金層９は
脆弱であることから外力印加よって破損し接続パッド６
より剥離し易くなる傾向にある。従って、前記接続パッ
ド６表面に被着されるタングステンーニッケルもしくは
モリブデンーニッケルから成る合金層９はその厚みを
０．５μｍ乃至３μｍの範囲としておくことが好まし
い。When the thickness of the alloy layer 9 made of tungsten-nickel or molybdenum-nickel deposited on the surface of the connection pad 6 is less than 0.5 μm, the adhesion strength with the connection pad 6 becomes weak. When the thickness exceeds 3 μm, the alloy layer 9 made of tungsten-nickel or molybdenum-nickel is fragile and is damaged by the application of an external force.
It tends to peel more easily. Therefore, the thickness of the alloy layer 9 made of tungsten-nickel or molybdenum-nickel deposited on the surface of the connection pad 6 is preferably set in the range of 0.5 μm to 3 μm.
【００２０】更に前記接続パッド６に取着されている半
田から成るボール状端子７は接続パッド６を外部電気回
路基板１０の配線導体１１に容易、且つ確実に接続させ
る作用を為し、接続パッド６の表面にボール状の半田を
載置させ、しかる後、その一部を加熱溶融させることに
よって接続パッド６の表面に取着される。Further, the ball-shaped terminals 7 made of solder attached to the connection pads 6 have the function of connecting the connection pads 6 to the wiring conductors 11 of the external electric circuit board 10 easily and surely. A ball-shaped solder is placed on the surface of 6, and then a part of it is heated and melted to be attached to the surface of the connection pad 6.
【００２１】かくして本発明の半導体素子収納用パッケ
ージによれば、絶縁基体１の凹状の載置部１ａ底面に半
導体集積回路素子３を接着剤を介して接着固定するとと
もに半導体集積回路素子３の各電極をメタライズ配線層
５にボンディングワイヤ８を介して電気的に接続し、し
かる後、絶縁基体１の上面に蓋体２をガラス、樹脂等か
ら成る封止材により接合させ、絶縁基体１と蓋体２とか
ら成る容器４内部に半導体集積回路素子３を気密に収容
することによって製品としての半導体装置となる。Thus, according to the semiconductor element housing package of the present invention, the semiconductor integrated circuit element 3 is adhered and fixed to the bottom surface of the concave mounting portion 1a of the insulating substrate 1 with an adhesive agent, and each semiconductor integrated circuit element 3 is attached. The electrodes are electrically connected to the metallized wiring layer 5 via the bonding wires 8. After that, the lid 2 is joined to the upper surface of the insulating base 1 by a sealing material made of glass, resin, or the like, and the insulating base 1 and the lid are connected. A semiconductor device as a product is obtained by hermetically housing the semiconductor integrated circuit element 3 in a container 4 composed of the body 2.
【００２２】また前記半導体素子収納用パッケージに半
導体集積回路素子３を収容して形成される半導体装置は
絶縁基体１下面のボール状端子７を外部電気回路基板１
０の配線導体１１に接合させることよって外部電気回路
基板１０上に実装され、同時に容器４の内部に収容され
ている半導体集積回路素子３はその電極がボンディング
ワイヤ８、メタライズ配線層５、接続パッド６及びボー
ル状端子７を介して外部電気回路基板１０の配線導体１
１に電気的に接続される。In the semiconductor device formed by accommodating the semiconductor integrated circuit element 3 in the semiconductor element accommodating package, the ball-shaped terminals 7 on the lower surface of the insulating substrate 1 are connected to the external electric circuit board 1.
The semiconductor integrated circuit element 3 mounted on the external electric circuit board 10 by being bonded to the wiring conductor 11 of 0 and accommodated inside the container 4 at the same time has electrodes such as the bonding wire 8, the metallized wiring layer 5, and the connection pad. Wiring conductor 1 of external electric circuit board 10 via 6 and ball-shaped terminal 7
Electrically connected to 1.
【００２３】更に本発明は上述の実施例に限定されるも
のではなく、本発明の要旨を逸脱しない範囲であれば種
々の変更は可能である。Furthermore, the present invention is not limited to the above-mentioned embodiments, but various modifications can be made without departing from the gist of the present invention.
【００２４】[0024]
【発明の効果】本発明の半導体素子収納用パッケージに
よれば、ボール状端子が取着される接続パッド表面にタ
ングステンーニッケル合金層もしくはモリブデンーニッ
ケル合金層を被着させたことから接続パッドとタングス
テンーニッケル合金層もしくはモリブデンーニッケル合
金層、及びタングステンーニッケル合金層もしくはモリ
ブデンーニッケル合金層とボール状端子の接合強度が強
固となり、接続パッド及びボール状端子に半導体素子収
納用パッケージの絶縁基体と外部電気回路基板の熱膨張
係数の相違に起因する大きな熱応力が作用してボール状
端子が接続パッドより剥離することはなく、その結果、
半導体素子収納用パッケージの内部に収容する半導体集
積回路素子の各電極を長期間にわたり所定の外部電気回
路に正確に電気的接続させることが可能となる。According to the package for accommodating semiconductor elements of the present invention, since the tungsten-nickel alloy layer or the molybdenum-nickel alloy layer is deposited on the surface of the connection pad to which the ball-shaped terminal is attached, the connection pad is formed. The bonding strength between the tungsten-nickel alloy layer or molybdenum-nickel alloy layer, and the tungsten-nickel alloy layer or molybdenum-nickel alloy layer and the ball-shaped terminal becomes strong, and the insulating base of the package for storing the semiconductor element is formed on the connection pad and the ball-shaped terminal. And the large thermal stress resulting from the difference in the coefficient of thermal expansion of the external electric circuit board does not act to separate the ball-shaped terminals from the connection pads.
It becomes possible to accurately electrically connect the electrodes of the semiconductor integrated circuit element housed in the semiconductor element housing package to a predetermined external electric circuit for a long period of time.
【００２５】また本発明の半導体素子収納用パッケージ
によれば接続パッド表面のタングステンーニッケル合金
層もしくはモリブデンーニッケル合金層の厚みを０．５
μｍ乃至３μｍとすると接続パッドとタングステンーニ
ッケル合金層もしくはモリブデンーニッケル合金層、及
びタングステンーニッケル合金層もしくはモリブデンー
ニッケル合金層とボール状端子の接合がより強固とな
り、半導体集積回路素子の外部電気回路への接続がより
高信頼性のものとなる。According to the package for accommodating semiconductor elements of the present invention, the thickness of the tungsten-nickel alloy layer or the molybdenum-nickel alloy layer on the surface of the connection pad is 0.5.
When the thickness is from 3 μm to 3 μm, the connection pad and the tungsten-nickel alloy layer or molybdenum-nickel alloy layer, and the tungsten-nickel alloy layer or molybdenum-nickel alloy layer and the ball-shaped terminal are more strongly bonded, and the external electric power of the semiconductor integrated circuit device is increased. The connection to the circuit is more reliable.
【図１】本発明の半導体素子収納用パッケージの一実施
例を示す断面図である。FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor element housing package of the present invention.
【図２】図１に示す半導体素子収納用パッケージの要部
拡大断面図である。FIG. 2 is an enlarged cross-sectional view of a main part of the semiconductor element storage package shown in FIG.
１・・・・・・絶縁基体 １ａ・・・・・半導体集積回路素子が載置される凹状の
載置部 ２・・・・・・蓋体 ３・・・・・・半導体集積回路素子 ４・・・・・・容器 ５・・・・・・メタライズ配線層 ６・・・・・・接続パッド ７・・・・・・ボール状端子 ９・・・・・・タングステンーニッケルもしくはモリブ
デンーニッケル合金層1 ... Insulating substrate 1a ... Recessed mounting portion on which semiconductor integrated circuit element is mounted 2 ... Lid 3 ... Semiconductor integrated circuit element 4 ··· Container 5 ··· Metallized wiring layer 6 ··· Connection pad 7 ··· Ball-shaped terminal 9 ··· Tungsten-nickel or molybdenum-nickel Alloy layer
Claims (2)
体素子が載置される載置部を有する絶縁基体と、該絶縁
基体の半導体素子が載置される載置部周辺から下面にか
けて導出されるタングステンもしくはモリブデンから成
る複数個のメタライズ配線層と、前記絶縁基体の下面に
形成され、前記メタライズ配線層が電気的に接続される
複数個の接続パッドと、半田から成り、前記接続パッド
に取着されるボール状端子とから成る半導体素子収納用
パッケージであって、前記ボール状端子の取着される接
続パッド表面にタングステンーニッケル合金層もしくは
モリブデンーニッケル合金層を被着させたことを特徴と
する半導体素子収納用パッケージ。1. An insulating base made of a ceramics sintered body, having an upper surface on which a semiconductor element is mounted, and an insulating base on which a semiconductor element is mounted and extending from the periphery of the mounting portion to the lower surface. A plurality of metallized wiring layers made of tungsten or molybdenum, a plurality of connection pads formed on the lower surface of the insulating substrate and electrically connected to the metallized wiring layers, and made of solder. A package for accommodating a semiconductor device, comprising a ball-shaped terminal to be attached, wherein a tungsten-nickel alloy layer or a molybdenum-nickel alloy layer is attached to a surface of a connection pad to which the ball-shaped terminal is attached. Package for semiconductor device storage.
ケル合金層もしくはモリブデンーニッケル合金層の厚み
が０．５μｍ乃至３μｍであることを特徴とする請求項
１に記載の半導体素子収納用パッケージ。2. The package for housing a semiconductor element according to claim 1, wherein the thickness of the tungsten-nickel alloy layer or the molybdenum-nickel alloy layer on the surface of the connection pad is 0.5 μm to 3 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12173495A JP3176251B2 (en) | 1995-05-19 | 1995-05-19 | Package for storing semiconductor elements |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12173495A JP3176251B2 (en) | 1995-05-19 | 1995-05-19 | Package for storing semiconductor elements |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08316366A true JPH08316366A (en) | 1996-11-29 |
| JP3176251B2 JP3176251B2 (en) | 2001-06-11 |
Family
ID=14818568
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12173495A Expired - Fee Related JP3176251B2 (en) | 1995-05-19 | 1995-05-19 | Package for storing semiconductor elements |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3176251B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1148440A4 (en) * | 1998-12-17 | 2004-12-29 | Hitachi Ltd | Semiconductor device and production method thereof |
-
1995
- 1995-05-19 JP JP12173495A patent/JP3176251B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1148440A4 (en) * | 1998-12-17 | 2004-12-29 | Hitachi Ltd | Semiconductor device and production method thereof |
| US7061083B1 (en) | 1998-12-17 | 2006-06-13 | Hitachi, Ltd. | Semiconductor devices |
| US7298029B2 (en) | 1998-12-17 | 2007-11-20 | Hitachi, Ltd. | Semiconductor devices and manufacturing method therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3176251B2 (en) | 2001-06-11 |
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