JP2014220305A - Multilayer substrate and electronic device using the same, method of manufacturing electronic device - Google Patents

Multilayer substrate and electronic device using the same, method of manufacturing electronic device Download PDF

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Publication number
JP2014220305A
JP2014220305A JP2013097227A JP2013097227A JP2014220305A JP 2014220305 A JP2014220305 A JP 2014220305A JP 2013097227 A JP2013097227 A JP 2013097227A JP 2013097227 A JP2013097227 A JP 2013097227A JP 2014220305 A JP2014220305 A JP 2014220305A
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Japan
Prior art keywords
surface
layer
mold
land
formed
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JP2013097227A
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Japanese (ja)
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JP6111832B2 (en
Inventor
俊浩 中村
Toshihiro Nakamura
俊浩 中村
正英 辰己
Masahide Tatsumi
正英 辰己
英二 藪田
Eiji Yabuta
英二 藪田
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株式会社デンソー
Denso Corp
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0201Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203Cooling of mounted components
    • H05K1/0204Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
    • H05K1/0206Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1305Moulding and encapsulation
    • H05K2203/1316Moulded encapsulation of mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • H05K3/284Applying non-metallic protective coatings for encapsulating mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4602Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Abstract

A surface pattern is prevented from being covered with a mold resin. A frame-like surface conductor 64a is formed on one surface 30a of a buildup layer 30 so as to be insulated from a land 61 and a surface pattern 63 and surround the land 61 and formed between the land 61 and the surface pattern 63. A mold step 64 having a protective film 110 covering the surface conductor 64a is formed. And the height from the one surface 30a of the build-up layer 30 of the protective film 110 in the type | mold step part 64 is made more than the height from the one surface 30a of the build-up layer 30 of the part which covers the surface pattern 63 among the protective films 110. [Selection] Figure 1

Description

  The present invention relates to a land on which electronic components are mounted and a multilayer substrate having a surface pattern electrically connected to an external circuit, an electronic device using the same, and a method for manufacturing the electronic device.

  Conventionally, an electronic device in which an electronic component is mounted on one side of a substrate has been proposed (see, for example, Patent Document 1). Specifically, in this electronic device, a surface pattern that is electrically connected to lands and external circuits is formed on one surface of the substrate, and a solder resist that covers the surface pattern is formed. The solder resist has an opening for exposing a portion of the surface pattern that is connected to an external circuit. The electronic component is mounted on the land via solder or the like. In addition, one surface side of the substrate including the electronic component is sealed with a mold resin so that at least a portion of the surface pattern connected to the external circuit is exposed.

  Such an electronic device is manufactured as follows. That is, first, a land and a surface pattern are formed on one surface of the substrate. And after forming the solder resist which covers a surface pattern, the opening part which exposes a part of surface pattern to a solder resist is formed. Next, the electronic component is mounted on the land via solder or the like. Subsequently, a mold having a recess formed on one surface is prepared, and one surface of the mold is pressed against one surface of the substrate so that the electronic component is disposed in the recess. Thereafter, the space between the substrate and the concave portion of the mold is filled with mold resin, whereby the electronic device in which one surface side of the substrate including the electronic component is sealed is manufactured.

Japanese Patent Laid-Open No. 7-22538

  However, in such a method for manufacturing an electronic device, the height of the portion of the solder resist that covers the surface pattern from the substrate surface is higher than the height of the portion of the solder resist that does not cover the surface pattern from the substrate surface. That is, the height of the solder resist from the substrate surface is different in each part in the part not sealed with the mold resin.

  For this reason, when one surface of the mold is pressed against one surface of the substrate, the one surface of the mold contacts with a portion of the solder resist that covers the surface pattern, and does not contact with a portion of the solder resist that does not cover the surface pattern. Sometimes. That is, a gap may be formed between one surface of the mold and a portion of the solder resist that does not cover the surface pattern. Therefore, when the gap and the space between the substrate and the concave portion of the mold communicate with each other, the mold resin flows out of the gap when the space between the substrate and the concave portion of the mold is filled with the mold resin. There is a problem of end up. And the part exposed from a soldering resist among surface patterns may be covered with mold resin.

  An object of this invention is to provide the multilayer substrate which can suppress that a surface pattern is covered with mold resin, the electronic device using the same, and the manufacturing method of an electronic device in view of the said point.

  In order to achieve the above object, in the invention according to claim 1, the core layer (20) having the surface (20a), the inner layer wiring (51) formed on the surface of the core layer, and the inner layer on the surface of the core layer. A buildup layer (30) arranged in a state of covering the wiring, and a land (61) formed on one surface (30a) on the opposite side of the core layer of the buildup layer, on which electronic components (121 to 123) are mounted A surface pattern (63) formed on one surface of the build-up layer, electrically connected to the land via the inner layer wiring and electrically connected to the external circuit, and covering the surface pattern, A multilayer substrate including a protective film (110) having an opening (110a) for exposing a part thereof is characterized by the following points.

  That is, on one side of the build-up layer, a frame-shaped surface conductor (64a) that is insulated from the land and the surface pattern, surrounds the land and is formed between the land and the surface pattern, and a protective film that covers the surface conductor , And the height of the protective film from the one surface of the build-up layer in the mold step portion from the one surface of the build-up layer of the portion of the protective film covering the surface pattern. It is characterized by being above the height.

  In such a multilayer substrate, after mounting electronic components on a land, when manufacturing an electronic device including a mold resin by pressing a mold against one side of the multilayer substrate, the mold step is always pressed against the mold. . The mold step portion is formed in a frame shape surrounding the land and is formed between the land and the surface pattern. Therefore, the mold resin can be prevented from flowing out of the space between the multilayer substrate and the mold, and the portion of the surface pattern exposed from the opening of the protective film can be prevented from being covered with the mold resin.

  According to a third aspect of the present invention, the multilayer substrate according to the first or second aspect, the electronic component mounted on the land, and the inner edge side of the protective film in the electronic component, the land, and the mold step portion are sealed. It is an electronic device provided with mold resin (150).

  According to a fourth aspect of the present invention, there is provided an electronic device manufacturing method according to the third aspect of the invention, the step of preparing a multilayer substrate, the step of mounting an electronic component on a land in the multilayer substrate, and the electronic component And a step of forming a mold resin for sealing the inner edge side of the protective film in the land and the mold step portion, and in the step of forming the mold resin, a mold having a recess (201) formed on one surface (200a) ( 200), and after pressing one surface of the mold against the mold step so that the electronic component is placed in the recess, the space between the multilayer substrate and the recess is filled with mold resin. .

  According to this, since the mold step is always pressed against the mold, the mold resin can be prevented from flowing out from the space between the multilayer substrate and the concave portion of the mold, and the opening of the protective film in the surface pattern It can suppress that the part exposed from is covered with mold resin.

  In addition, the code | symbol in the bracket | parenthesis of each means described in this column and the claim shows the correspondence with the specific means as described in embodiment mentioned later.

It is sectional drawing of the electronic device in 1st Embodiment of this invention. It is a top view of the electronic device shown in FIG. FIG. 7 is a cross-sectional view showing a manufacturing process of the electronic device shown in FIG. 1. FIG. 4 is a cross-sectional view showing a manufacturing step of the electronic device following FIG. 3. FIG. 5 is a cross-sectional view showing a manufacturing step of the electronic device following FIG. 4. FIG. 6 is a cross-sectional view showing a manufacturing step of the electronic device following FIG. 5. It is an enlarged view of the electronic device in 2nd Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
A first embodiment of the present invention will be described. Note that the electronic device of the present embodiment is preferably mounted on a vehicle such as an automobile, for example, and applied to drive various electronic devices for the vehicle.

  As shown in FIG. 1, the electronic device includes a multilayer substrate 10 having one surface 10 a and another surface 10 b, and electronic components 121 to 123 mounted on one surface 10 a of the multilayer substrate 10. And the electronic device is comprised by sealing the one surface 10a side of the multilayer substrate 10 with the mold resin 150 with the electronic components 121-123.

  The multilayer substrate 10 includes a core layer 20 as an insulating resin layer, a build-up layer 30 on the surface 20a side disposed on the surface 20a of the core layer 20, and a back surface 20b side disposed on the back surface 20b side of the core layer 20. A multilayer substrate including a build-up layer 40.

  In addition, the core layer 20 and the buildup layers 30 and 40 are comprised by the prepreg etc. which seal both surfaces of glass cloth with resin, and epoxy resin etc. are mentioned as resin of a prepreg. In addition, the prepreg resin may contain a filler having excellent electrical insulation and heat dissipation, such as alumina and silica, as necessary.

  A patterned surface-side inner layer wiring 51 (hereinafter simply referred to as an inner layer wiring 51) is formed at the interface between the core layer 20 and the buildup layer 30. Similarly, at the interface between the core layer 20 and the buildup layer 40, a patterned back side inner layer wiring 52 (hereinafter simply referred to as an inner layer wiring 52) is formed.

  Further, patterned surface-side surface wirings 61 to 63 (hereinafter simply referred to as surface layer wirings 61 to 63) are formed on the surface 30 a of the buildup layer 30. In the present embodiment, the surface layer wirings 61 to 63 are used for bonding electrically connected to the mounting lands 61 on which the electronic components 121 to 123 are mounted and the electronic components 121 and 122 via the bonding wires 141 and 142. The land 62 is a surface pattern 63 that is electrically connected to an external circuit.

  On the front surface 40a of the buildup layer 40, patterned back surface side wirings 71 and 72 (hereinafter simply referred to as surface wirings 71 and 72) are formed. In the present embodiment, the surface layer wirings 71 and 72 are a back surface pattern 71 connected to the inner layer wiring 52 through a filled via described later, a heat sink pattern 72 provided with a heat sink for heat dissipation (hereinafter simply referred to as an HS pattern 72). ).

  Note that the surface 30 a of the buildup layer 30 is one surface of the buildup layer 30 opposite to the core layer 20, and is a surface that becomes the one surface 10 a of the multilayer substrate 10. Further, the surface 40 a of the buildup layer 40 is one surface of the buildup layer 40 opposite to the core layer 20, and is a surface that becomes the other surface 10 b of the multilayer substrate 10. The inner layer wirings 51 and 52, the surface layer wirings 61 to 63, and the surface layer wirings 71 and 72 are specifically described later, and are configured by appropriately laminating metal foil such as copper or metal plating.

  The inner layer wiring 51 and the inner layer wiring 52 are electrically and thermally connected through a through via 81 provided through the core layer 20. Specifically, the through via 81 is configured such that a through electrode 81b such as copper is formed on the wall surface of the through hole 81a penetrating the core layer 20 in the thickness direction, and a filler 81c is filled in the through hole 81a. Has been.

  Further, the inner layer wiring 51 and the surface layer wirings 61 to 63, and the inner layer wiring 52 and the surface layer wirings 71 and 72 pass through the filled vias 91 and 101 provided through the respective buildup layers 30 and 40 in the thickness direction as appropriate. Connected electrically and thermally. Accordingly, the lands 61 and 62 and the surface layer wiring 63 are appropriately electrically connected via the inner layer wirings 51 and 52, the back surface pattern 71, the through via 81, and the filled vias 91 and 101.

  The filled vias 91 and 101 are configured such that through holes 91a and 101a penetrating the build-up layers 30 and 40 in the thickness direction are filled with through electrodes 91b and 101b such as copper. The filler 81c is made of resin, ceramic, metal, or the like, but is an epoxy resin in this embodiment. The through electrodes 81b, 91b, 101b are configured by metal plating such as copper.

  And the solder resist 110 which covers the surface pattern 63 and the back surface pattern 71 is formed in the surface 30a, 40a of each buildup layer 30,40. The solder resist 110 that covers the surface pattern 63 is formed with an opening 110a that exposes a portion of the surface pattern 63 that is connected to an external circuit. In this embodiment, the solder resist 110 covering the surface pattern 63 corresponds to the protective film of the present invention.

  The electronic components 121 to 123 include a power element 121 such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), a control element 122 such as a microcomputer, and a passive such as a chip capacitor or a resistor. Element 123. Each electronic component 121 to 123 is mounted on the land 61 via the solder 130 and is electrically and mechanically connected to the land 61. The power element 121 and the control element 122 are also electrically connected to the land 62 formed in the periphery via bonding wires 141 and 142 such as aluminum and gold.

  In addition, although the power element 121, the control element 122, and the passive element 123 were mentioned as an example and demonstrated here as the electronic components 121-123, the electronic components 121-123 are not limited to these.

  The mold resin 150 seals the lands 61 and 62 and the electronic components 121 to 123, and a general mold material such as an epoxy resin is formed by a transfer molding method using a mold, a compression molding method, or the like. Is.

  In the present embodiment, the mold resin 150 is formed only on the one surface 10 a of the multilayer substrate 10. That is, the electronic device of this embodiment has a so-called half mold structure. Further, on the other surface 10 b side of the multilayer substrate 10, although not particularly shown, a heat sink is provided on the HS pattern 72 via heat dissipation grease or the like.

  The above is the basic configuration of the electronic device according to this embodiment. And in the electronic device of this embodiment, the mold step part 64 is formed in the surface 30 of the buildup layer 30. Below, the structure of the type | mold tread part 64 which is the feature point of this embodiment is demonstrated, referring FIG. 1 and FIG. In FIG. 2, the solder resist 110 is omitted for easy understanding. 1 corresponds to a cross section taken along line II in FIG.

  The mold step portion 64 is a portion to which a mold constituting the outer shape of the mold resin 150 is pressed when the mold resin 150 is formed, and a surface layer conductor 64 a formed on the surface 30 a of the buildup layer 30, and a surface layer conductor The solder resist 110 covers the 64a.

  Specifically, as shown in FIGS. 1 and 2, the surface layer conductor 64 a has a frame shape surrounding the lands 61 and 62, and is formed between the lands 61 and 62 and the surface pattern 63. Further, the surface layer conductor 64 a is insulated from the lands 61 and 62 and the surface pattern 63. That is, the surface layer conductor 64a is a so-called dummy pattern for adjusting the height of the mold step 64.

  The surface layer conductor 64 a is completely covered with the solder resist 110 that covers the surface pattern 63. That is, the height of the solder resist 110 from the surface 30a of the buildup layer 30 in the mold step 64 is constant in the circumferential direction.

  Moreover, the height from the surface 30a of the build-up layer 30 of the solder resist 110 in the mold step portion 64 is set to be equal to or higher than the height from the surface 30a of the build-up layer 30 in the part covering the surface pattern 63 in the solder resist 110. ing. In the present embodiment, the film thickness of the surface pattern 63 and the surface layer conductor 64a is made equal, and the film thickness of each part of the solder resist 110 is also made equal. For this reason, the height from the surface 30a of the build-up layer 30 of the solder resist 110 in the mold step 64 is made equal to the height from the surface 30a of the build-up layer 30 in the portion of the solder resist 110 that covers the surface pattern 63. ing.

  The mold resin 150 seals the inner edge side portion of the solder resist 110 constituting the mold step portion 64 while exposing the outer edge side portion of the solder resist 110 constituting the die step portion 64. That is, it can be said that the mold step 64 is formed at the interface between the portion sealed with the mold resin 150 and the portion not sealed on the one surface 10 a of the multilayer substrate 10.

  In addition, the height from the surface 30a of the build-up layer 30 of the solder resist 110 in the mold step 64 is, in other words, the build-up layer 30 from the surface opposite to the surface layer conductor 64a in the solder resist 110 covering the surface layer conductor 64a. It is the length to the surface 30a. In FIG. 1, the surface pattern 63 and the surface layer conductor 64a are covered with the same solder resist 110. However, the solder resist 110 that covers the surface pattern 63 and the solder resist 110 that covers the surface layer conductor 64a are separated. Good.

  The above is the configuration of the electronic device in this embodiment. Next, a method for manufacturing the electronic device will be described with reference to FIGS. 3 to 5 are cross-sectional views in the vicinity of a portion of the multilayer substrate 10 on which the power element 121 is mounted.

  First, as shown in FIG. 3A, one in which metal foils 161 and 162 such as copper foil are arranged on the front surface 20 a and the back surface 20 b of the core layer 20 is prepared. Then, as shown in FIG. 3B, a through hole 81a penetrating the metal foil 161, the core layer 20, and the metal foil 162 is formed by a drill or the like.

  Thereafter, as shown in FIG. 3C, electroless plating or electroplating is performed to form a metal plating 163 such as copper on the wall surface of the through hole 81 a and the metal foils 161 and 162. As a result, a through electrode 81b composed of the metal plating 163 is formed on the wall surface of the through hole 81a. In addition, when performing electroless plating and electroplating, it is preferable to carry out using catalysts, such as palladium.

  Subsequently, as illustrated in FIG. 3D, a filler 81 c is disposed in a space surrounded by the metal plating 163. Thus, the through via 81 having the through hole 81a, the through electrode 81b, and the filler 81c is formed.

  Thereafter, as shown in FIG. 4A, so-called lid plating is performed by electroless plating, electroplating, or the like, and metal plating 164, 165 such as copper is formed on the metal plating 163 and the filler 81c.

  Next, as shown in FIG. 4B, a resist (not shown) is disposed on the metal platings 164 and 165. Then, wet etching or the like is performed using the resist as a mask, and the metal plating 164, the metal plating 163, and the metal foil 161 are appropriately patterned to form the inner layer wiring 51, and the metal plating 165, the metal plating 163, and the metal foil 162 are appropriately formed. The inner layer wiring 52 is formed by patterning. That is, in this embodiment, the inner layer wiring 51 is configured by laminating the metal foil 161, the metal plating 163, and the metal plating 164, and the inner layer wiring 52 is configured by laminating the metal foil 162, the metal plating 163, and the metal plating 165. It is configured.

  In FIG. 4C and subsequent figures, the metal foil 161, the metal plating 163, the metal plating 164, the metal foil 162, the metal plating 163, and the metal plating 165 are collectively shown as one layer.

  Thereafter, as shown in FIG. 4C, the buildup layer 30 and a metal plate 166 such as copper are laminated on the inner layer wiring 51 on the surface 20 a side in the core layer 20. Further, the buildup layer 40 and a metal plate 167 such as copper are laminated on the inner layer wiring 52 on the back surface 20 b side in the core layer 20. In this way, a stacked body 168 is configured in which the metal plate 166, the buildup layer 30, the inner layer wiring 51, the core layer 20, the inner layer wiring 52, the buildup layer 30, and the metal plate 167 are sequentially stacked from the top.

  Subsequently, as illustrated in FIG. 4D, the stacked body 168 is integrated by heating while pressing from the stacking direction of the stacked body 168. Specifically, by pressurizing the laminate 168, the resin constituting the buildup layer 30 is caused to flow to embed between the inner layer wirings 51, and the resin constituting the buildup layer 40 is caused to flow to cause the inner layer wirings 52 to flow. Embed between. And the buildup layers 30 and 40 are hardened by heating the laminated body 168, and the laminated body 168 is integrated.

  Next, as shown in FIG. 5A, a through hole 91 a that penetrates the metal plate 166 and the buildup layer 30 and reaches the inner layer wiring 51 is formed by a laser or the like. Similarly, as shown in FIG. 1, a through hole 101 a that penetrates the metal plate 167 and the buildup layer 40 and reaches the inner layer wiring 52 is formed in a cross section different from FIG.

  Then, as shown in FIG. 5B, so-called filled plating is performed by electroless plating, electroplating, or the like, and the through holes 91 a and 101 a are embedded with metal plating 169. Thus, the through electrode 91b and the through electrode 101b shown in FIG. 1 are configured by the metal plating 169 embedded in the through holes 91a and 101a formed in the buildup layers 30 and 40. Further, filled vias 91 and 101 in which through electrodes 91b and 101b are embedded in the through holes 91a and 101a are formed. In FIG. 5C and subsequent figures, the metal plate 166 and the metal plating 169 are collectively shown as one layer.

  Subsequently, as shown in FIG. 5C, a resist (not shown) is disposed on the metal plate 166. Then, by performing wet etching or the like using the resist as a mask and patterning the metal plate 166, the surface layer wirings 61 to 63 and the surface layer conductor 64a are formed. For this reason, the surface layer wirings 61 to 63 and the surface layer conductor 64 a have the same height from the surface 30 a of the buildup layer 30.

  Similarly, a resist (not shown) is arranged on the metal plate 167, and wet etching or the like is performed using the resist as a mask to pattern the metal plate 167, thereby forming the surface layer wirings 71 and 72.

  That is, in the present embodiment, the surface layer wirings 61 to 63 are configured to have the metal plate 166 and the metal plating 169, and the surface layer wirings 71 and 72 are configured to have the metal plate 167 and the metal plating 169. Note that the surface layer conductor 64 a is not electrically connected to the inner layer wiring 51, and the filled via 91 is not formed between the inner layer wiring 51, and thus is constituted only by the metal plate 166.

  Next, as shown in FIG. 6A, solder resists 110 are arranged on the surfaces 30a and 40a of the build-up layers 30 and 40, respectively, and patterned appropriately. Thereby, the multilayer substrate 10 in which the mold step 64 is formed by the surface layer conductor 64a and the solder resist 110 is manufactured. Note that, as described above, the mold step portion 64 is such that the height from the surface 30a of the build-up layer 30 of the solder resist 110 in the mold step portion 64 is a part of the build-up layer that covers the surface pattern 63 in the solder resist 110. 30 is equal to the height from the surface 30a.

  Subsequently, as illustrated in FIG. 6B, the electronic components 121 to 123 are mounted on the land 61 via the solder 130. Then, wire bonding is performed between the power element 121 and the control element 122 and the land 62, and the power element 121 and the control element 122 and the land 62 are electrically connected.

  Thereafter, as shown in FIG. 6C, a molding resin 150 is formed by a transfer molding method using a mold, a compression molding method, or the like so that the lands 61 and 62 and the electronic components 121 to 123 are sealed. To do.

  Specifically, a mold 200 having a recess 201 that forms the outer shape of the mold resin 150 on one surface 200 a is prepared, and the surface 200 a is multilayered so that the electronic components 121 to 123 are disposed in the recess 201. The substrate 10 is in pressure contact with the one surface 10a side.

  At this time, as described above, the height from the surface 30a of the build-up layer 30 of the solder resist 110 in the mold step portion 64 is from the surface 30a of the build-up layer 30 that covers the surface pattern 63 in the solder resist 110. Is equal to the height. For this reason, the mold step 64 is pressed against the mold 200. Moreover, since the height from the surface 30a of the build-up layer 30 of the solder resist 110 in the mold step 64 is constant in the circumferential direction, no gap is formed between the mold step 64 and the mold 200. .

  And the said electronic device is manufactured by filling the space between the multilayer substrate 10 and the recessed part 201 of the metal mold | die 200 with the mold resin 150. FIG.

  Note that when the one surface 200a of the mold 200 is pressed against the one surface 10a side of the multilayer substrate 10, the portion of the solder resist 110 that covers the surface pattern 63 is also pressed into the mold 200, but there is no particular problem.

  As described above, in the multilayer substrate 10, the height from the surface 30 a of the buildup layer 30 is set to be equal to or higher than the height from the surface 30 a of the buildup layer 30 in the part of the solder resist 110 that covers the surface pattern 63. The mold step 64 is formed. For this reason, when the one surface 200 a of the mold 200 is pressed against the one surface 10 a side of the multilayer substrate 10, the mold step 64 is always pressed against the mold 200. The mold step 64 has a frame shape surrounding the lands 61 and 62 and is formed between the lands 61 and 62 and the surface pattern 63. Therefore, it is possible to suppress the mold resin 150 from flowing out of the space between the multilayer substrate 10 and the concave portion 201 of the mold 200, and the portion of the surface pattern 63 exposed from the opening 110 a of the solder resist 110 is the mold resin 150. It can suppress being covered.

(Second Embodiment)
A second embodiment of the present invention will be described. In the present embodiment, the shape of the surface conductor 64a is changed with respect to the first embodiment, and the other aspects are the same as those in the first embodiment, and thus the description thereof is omitted here.

  As shown in FIG. 7, the surface layer conductor 64a of the present embodiment has a rounded corner on the opposite side to the buildup layer 30 side in the cross section in the thickness direction. On the other hand, the lands 61 and 62 and the surface pattern 63 are portions for electrically connecting the electronic components 121 to 123 and the external circuit, and it is preferable to increase the current capacity. Therefore, as shown in FIG. The cross section in the thickness direction is rectangular. That is, the lands 61 and 62 and the surface pattern 63 have a right-angled corner in the cross section opposite to the buildup layer 30 side in the cross section in the thickness direction. FIG. 7 is an enlarged view corresponding to the area A in FIG.

  According to this, when the one surface 200a of the mold 200 is pressed against the mold stepping portion 64 in the step of FIG. 6C, it is possible to prevent stress from concentrating on the corner portion of the surface layer conductor 64a. For this reason, generation | occurrence | production of a crack in the soldering resist 110 can be suppressed.

(Other embodiments)
The present invention is not limited to the embodiment described above, and can be appropriately changed within the scope described in the claims.

  For example, in each of the above-described embodiments, the core layer 20 and the buildup layers 30 and 40 are illustrated as being composed of a single prepreg layer, but the core layer 20 and the buildup layers 30 and 40 are formed of a prepreg multilayer. It is good also as what is comprised from.

  Moreover, in each said embodiment, the height from the surface 30a of the buildup layer 30 of the solder resist 110 in the type | mold step part 64 is made from the surface 30a of the buildup layer 30 of the part which covers the surface pattern 63 among the solder resists 110. When the height is to be exceeded, the following may be performed. For example, when the surface pattern 63 and the surface layer conductor 64a are patterned in the step of FIG. 5C, metal plating or the like may be formed only on the surface layer conductor 64a.

  Further, in each of the above embodiments, the mold step 64 has been described in which the height from the surface 30a of the buildup layer 30 is constant in the circumferential direction. That is, even if a depression is formed in the solder resist 110 constituting the mold step 64, the height of the portion where the depression is formed in the mold depression 64 is slightly lower than the height of the other portions. Good. According to this, when forming mold resin 150, the void which may be generated in mold resin 150 can be discharged from a hollow part. In the case where such a mold step portion 64 is configured, even if the mold resin 150 flows out of the recess portion, a portion of the surface pattern 63 exposed from the solder resist 110 is not covered with the mold resin 150. It is preferable to form a depression.

DESCRIPTION OF SYMBOLS 10 Multilayer substrate 20 Core layer 20a Surface 30 Buildup layer 30a One side 51 Inner layer wiring 61 Land 63 Surface pattern 64 Type stepping part 64a Surface layer conductor 110 Protective film (solder resist)
110a opening 121-123 electronic component

Claims (4)

  1. A core layer (20) having a surface (20a);
    An inner wiring (51) formed on the surface of the core layer;
    A buildup layer (30) arranged in a state of covering the inner layer wiring on the surface of the core layer;
    A land (61) formed on one surface (30a) opposite to the core layer of the build-up layer, on which electronic components (121 to 123) are mounted;
    A surface pattern (63) formed on the one surface of the build-up layer, electrically connected to the land via the inner layer wiring and electrically connected to an external circuit;
    A multilayer substrate having a protective film (110) that covers the surface pattern and has an opening (110a) that exposes a part of the surface pattern.
    The one surface of the build-up layer is insulated from the land and the surface pattern, surrounds the land and is formed between the land and the surface pattern, and a frame-shaped surface conductor (64a), and the surface layer A mold step (64) having the protective film covering the conductor is formed,
    The height of the protective film from the one surface of the build-up layer in the stepping portion is equal to or higher than the height of the part of the protective film covering the surface pattern from the one surface of the build-up layer. A multilayer substrate characterized by that.
  2. In the surface layer conductor, in the cross section in the thickness direction of the surface layer conductor, the corner on the opposite side to the buildup layer side is rounded,
    2. The corner of the land and the surface pattern opposite to the build-up layer side is a right angle in a cross section in the thickness direction of the land and the surface pattern. Multilayer board.
  3. The multilayer substrate according to claim 1 or 2,
    The electronic component mounted on the land;
    An electronic device comprising: a mold resin (150) that seals an inner edge side of the protective film in the electronic component, the land, and the stepping portion.
  4. In the manufacturing method of the electronic device according to claim 3,
    Preparing the multilayer substrate;
    Mounting the electronic component on the land in the multilayer substrate;
    Forming the mold resin that seals an inner edge side of the protective film in the electronic component, the land, and the mold step portion;
    In the step of forming the mold resin, a mold (200) having a recess (201) formed on one surface (200a) is prepared, and the one surface of the mold is disposed so that the electronic component is disposed in the recess. A method of manufacturing an electronic device, wherein the mold resin is filled in a space between the multilayer substrate and the recess after being pressed against the mold step.
JP2013097227A 2013-05-06 2013-05-06 Multilayer substrate, electronic device using the same, and method for manufacturing electronic device Active JP6111832B2 (en)

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PCT/JP2014/002248 WO2014181509A1 (en) 2013-05-06 2014-04-22 Multilayer substrate and electronic device using same, and method for manufacturing electronic device

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