JP3618060B2 - Wiring board for mounting semiconductor element and semiconductor device using the same - Google Patents

Wiring board for mounting semiconductor element and semiconductor device using the same Download PDF

Info

Publication number
JP3618060B2
JP3618060B2 JP15157299A JP15157299A JP3618060B2 JP 3618060 B2 JP3618060 B2 JP 3618060B2 JP 15157299 A JP15157299 A JP 15157299A JP 15157299 A JP15157299 A JP 15157299A JP 3618060 B2 JP3618060 B2 JP 3618060B2
Authority
JP
Japan
Prior art keywords
semiconductor element
mounting
resin filler
dam
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP15157299A
Other languages
Japanese (ja)
Other versions
JP2000340715A (en
Inventor
尚孝 太田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP15157299A priority Critical patent/JP3618060B2/en
Publication of JP2000340715A publication Critical patent/JP2000340715A/en
Application granted granted Critical
Publication of JP3618060B2 publication Critical patent/JP3618060B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83051—Forming additional members, e.g. dam structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01012—Magnesium [Mg]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01088—Radium [Ra]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、配線導体を有する絶縁基体上に半導体素子をフリップチップ接続法により搭載するようになした半導体素子搭載用配線基板およびこの半導体素子搭載用配線基板に半導体素子をフリップチップ接続法により搭載するとともに半導体素子と絶縁基体との間に樹脂製充填材を充填して成る半導体装置に関するものである。
【０００２】
【従来の技術】
近時、コンピュータ等の電子機器の小型化や薄型化に対応した半導体装置として、例えば酸化アルミニウム質焼結体や窒化アルミニウム質焼結体・ムライト質焼結体・炭化珪素質焼結体・窒化珪素質焼結体・ガラスセラミックス等のセラミックスから成る絶縁基体の上面中央部に半導体素子が搭載される搭載部を有するとともにその搭載部から下面にかけて配線導体が配設されて成る半導体素子搭載用配線基板を準備し、この半導体素子搭載用配線基板の搭載部に半導体素子を半田や金等から成るバンプを介してフリップチップ接続法により搭載して、しかる後、この半導体素子と絶縁基体との間にアンダーフィルと呼ばれる液状の樹脂製充填材を充填するとともにこれを熱硬化させ、この熱硬化した樹脂製充填材により半導体素子を保護するとともに絶縁基体と半導体素子とを固着して成る半導体装置が知られている。
【０００３】
なお、この半導体装置における半導体素子搭載用配線基板は、いわゆるセラミックグリーンシート積層法によって製作されている。具体的には、セラミックス原料粉末を有機バインダで結合して成るセラミックグリーンシートに適当な打ち抜き加工を施すとともに配線導体となる金属ペーストを所定のパターンに印刷塗布し、このセラミックグリーンシートを複数枚積層するとともに高温で焼成することによって製作されている。
【０００４】
しかしながら、この半導体装置によると、半導体素子搭載用配線基板の搭載部に半導体素子を半田や金から成るバンプを介してフリップチップ接続法により搭載した後、絶縁基体と半導体素子との間に液状の樹脂製充填材を充填することから、充填した液状の樹脂がその流動性により絶縁基体上で樹脂製充填材が不要な部分にまで流れ広がり、これが半導体装置としての機能に悪影響を及ぼしたり、半導体装置の外観を著しく損ねたりするという問題点があった。
【０００５】
そこで、上記問題点を解決するために、図３に断面図で示すように、絶縁基体１１の上面中央部に半導体素子１２がフリップチップ接続法により搭載される搭載部１１ａおよびこの搭載部１１ａから下面に導出する配線導体１３を有するとともに、この搭載部１１ａを取り囲むようにして形成された所定高さの枠状のダム部１４を有する半導体素子搭載用配線基板を準備し、この半導体素子搭載用配線基板の搭載部１１ａに半導体素子１２を半田や金等から成るバンプ１５を介してフリップチップ接続法により搭載し、その後、ダム部１４の内側で絶縁基体１１と半導体素子１２との間に液状の樹脂製充填材１６を充填し、これを熱硬化させて成る半導体装置が提案されている。
【０００６】
このような半導体装置によると、搭載部１１ａを取り囲むダム部１４の内側で絶縁基体１１と半導体素子１２との間に液状の樹脂製充填材１６を充填すると、液状の樹脂製充填材１６が不要な部分にまで流れ広がるのがダム部１４により有効に防止される。
【０００７】
【発明が解決しようとする課題】
しかしながら、上述の半導体素子搭載用配線基板においては、ダム部１４は通常、枠状に打ち抜いたセラミックグリーンシートを半導体素子搭載用配線基板となるセラミックグリーンシートの積層体の最上層に積層し、それを焼成することによって搭載部１１ａを取り囲むように形成されている。
【０００８】
このようにして形成されたダム部１４は、セラミックグリーンシートを打ち抜き、これを焼成することにより形成されていることから、その内側の側面が絶縁基体１１の上面に対して略垂直となっている。
【０００９】
そして、このダム部１４の内側で絶縁基体１１と半導体素子１２との間に液状の樹脂製充填材１６を充填してこの樹脂製充填材１６を熱硬化させると、樹脂製充填材１６が熱硬化する際に収縮することによりダム部１４と樹脂製充填材１６との間に大きな引っ張り応力が発生する。
【００１０】
さらに、絶縁基体１１を形成するセラミックスの熱膨張係数が４×１０−６〜１０×１０−６／℃程度であるのに対して樹脂製充填材１６の熱膨張係数が３０×１０−６〜５０×１０−６／℃程度であり、両者の熱膨張係数が大きく相違することから、半導体素子１２を作動させると、その作動時に発生する熱により絶縁基体１１と樹脂製充填材１６との間に両者の熱膨張係数の相違に起因して大きな熱応力が発生する。
【００１１】
このような応力は、互いに重畳してダム部１４と樹脂製充填材１６との接合面に対して作用し、この応力が最も集中する部位であるダム部１４と樹脂製充填材１６との接合面の上端部からダム部１４と樹脂製充填材１６との間に剥離を発生させる。なお、ダム部１４と樹脂製充填材１６との間に作用する応力は、ダム部１４と樹脂製充填材１６との接合面に対して垂直な方向に作用する成分が大きい程、ダム部１４と樹脂製充填材１６とを引き剥がす力が大きくなるのでダム部１４と樹脂製充填材１６とが剥離しやすくなる。
【００１２】
そして、ダム部１４と樹脂製充填材１６との間に剥離が発生すると、半導体素子１２の作動および停止の繰り返しに伴って、この剥離が次第に絶縁基体１１の中心部に向かって徐々に進行していき、ついには樹脂製充填材１６が絶縁基体１１から完全に剥離してしまい、半導体素子１２を良好に保護することができなくなってしまうという問題点があった。また、半導体素子１２の電極と半導体素子搭載用配線基板の配線導体１３とを接合している半田や金等の接続用バンプ１５の剥離を誘発させることによって、半導体素子１２の電極と絶縁基体１１の配線導体１３との電気的な接続が切断され、その結果、半導体素子１２を長期間にわたり安定に作動させることができなくなってしまうという問題点を有していた。
【００１３】
本発明は上記問題点に鑑み案出されたものであり、その目的は、絶縁基体と半導体素子とを樹脂製充填材により強固に固着させ、半導体素子を良好に保護するとともに半導体素子の電極と配線導体との電気的な接続を完全なものとして半導体素子を長期間にわたり安定に作動させることができる半導体素子搭載用配線基板およびこれを用いた半導体装置を提供することにある。
【００１４】
【課題を解決するための手段】
本発明の半導体素子搭載用配線基板は、配線導体が配設された絶縁基体上に、半導体素子が搭載される搭載部および該搭載部を取り囲むようにして形成された枠状のダム部を有する半導体素子搭載用配線基板であって、前記ダム部は、内側の側面が階段状であり、各段の側面と上面との間に丸みを有することを特徴とするものである。
【００１５】
また、本発明の半導体素子搭載用配線基板は、好ましくは、前記ダム部は、高さが０．０５〜０．５ｍｍであり、前記各段の厚みが１０〜１００μｍであることを特徴とするものである。
【００１６】
本発明の半導体装置は、本発明の半導体素子搭載用配線基板と、前記搭載部に搭載された半導体素子と、前記ダム部の内側で前記絶縁基体と前記半導体素子との間に充填された樹脂製充填材とを備えていることを特徴とするものである。
【００１７】
【発明の実施の形態】
次に、本発明の半導体素子搭載用配線基板および半導体装置について添付の図面を基にして詳細に説明する。
【００１８】
図１は、本発明の半導体素子搭載用配線基板およびこれを用いた半導体装置の実施の形態の一例を示す断面図である。図１において、１は絶縁基体、２は配線導体、３はダム部、４は半導体素子、５は樹脂製充填材である。これらのうち、絶縁基体１と配線導体２とダム部３とで本発明の半導体素子搭載用配線基板が構成されており、この半導体素子搭載用配線基板と半導体素子４および樹脂製充填材５とにより本発明の半導体装置が構成されている。
【００１９】
絶縁基体１は、例えば大きさが数ｍｍ〜数ｃｍ角程度の略四角形の平板であり、酸化アルミニウム質焼結体や窒化アルミニウム質焼結体・ムライト質焼結体・炭化珪素質焼結体・窒化珪素質焼結体・ガラスセラミックス等のセラミックスから形成されている。
【００２０】
この絶縁基体１は、例えば酸化アルミニウム質焼結体から成る場合であれば、酸化アルミニウム・酸化珪素・酸化マグネシウム・酸化カルシウム等の原料粉末に適当な有機バインダ・溶剤を添加混合して泥漿状となすとともに、これを従来周知のドクタブレード法を採用することによってシート状となすことによりセラミックグリーンシートを得、このセラミックグリーンシートに適当な打ち抜き加工を施すとともに必要に応じて複数枚を積層して生セラミック積層体となし、最後にこの生セラミック体を還元雰囲気中、約１６００℃の温度で焼成することによって製作される。
【００２１】
絶縁基体１は、半導体素子４を支持するための支持基板として機能し、その上面中央部に半導体素子４を搭載するための搭載部１ａを有している。この搭載部１ａには半導体素子４が半田や金から成るバンプ６を介してフリップチップ接続法により搭載される。
なお、半導体素子４は、例えばシリコンやガリウム砒素等の半導体材料から形成されている集積回路素子等の電子回路用素子である。
【００２２】
そして半導体素子４の搭載部１ａへの搭載は、半導体素子４の能動面に形成された入出力用の各電極に半田や金から成るバンプ６を溶着や圧着により予め取着させておくとともにこのバンプ６を後述する配線導体２の搭載部１ａに導出した部位に当接させ、両者を溶着や圧着により接合することによって行なわれる。
【００２３】
半導体素子４が搭載される絶縁基体１の搭載部１ａにはタングステンやモリブデン・銅・銀等の金属粉末メタライズから成る配線導体２の一端部が導出しており、この配線導体２の他端部は絶縁基体１の内部を介して絶縁基体１の下面に導出している。
【００２４】
この配線導体２は半導体素子４の各電極を外部電気回路に電気的に接続するための導電路として機能し、上述したように、その搭載部１ａに導出した部位には半導体素子４の各電極が半田や金等の接続用バンプ６を介して電気的に接続される。また、配線導体２の絶縁基体１の下面に導出した他端部は、図示しない外部電気回路基板の接続用導体に半田等を介して接続され、これによって、半導体素子４の各電極が外部の電気回路に接続されることとなる。
【００２５】
このような配線導体２は、例えばタングステンメタライズから成る場合であれば、タングステン粉末に適当な有機バインダ・溶剤を添加混合して得た金属ペーストを絶縁基体１となるセラミックグリーンシートに従来周知のスクリーン印刷法を採用して所定のパターンに印刷塗布し、これをセラミックグリーンシートとともに焼成することによって、絶縁基体１の搭載部１ａから下面に導出するようにして所定のパターンに被着形成される。なお、配線導体２の表面には、通常、この配線導体２が酸化腐食するのを防止するとともに配線導体２とバンプ６との接続および配線導体２の外部電気回路基板の接続用導体との半田を介した接続を容易かつ強固なものとするために、ニッケルめっき膜および金めっき膜が順次被着されている。
【００２６】
また、絶縁基体１の搭載部１ａに半導体素子４をバンプ６を介してフリップチップ接続法により搭載した後は、後述するダム部３の内側で絶縁基体１と半導体素子４との間に例えばエポキシ樹脂から成る樹脂製充填材５が液状で充填された後、熱硬化されて半導体装置が完成する。
【００２７】
この樹脂製充填材５は、その厚さが例えば数十μｍ〜数百μｍ程度であり、絶縁基体１と半導体素子４との間に充填されることにより、半導体素子４を保護するとともに半導体素子４を絶縁基体１に強固に固着させる作用をなす。また、半導体装置の仕様に応じて、熱膨張率の調整や熱伝導性向上のための各種フィラーを含有してもよい。
【００２８】
なお、絶縁基体１と半導体素子４との間への液状の樹脂製充填材６の充填は、例えば従来周知のディスペンサを用いて行なえばよい。また、樹脂製充填材５の熱硬化は、例えばオーブン等により１００ 〜１５０ ℃の温度に加熱することにより行なえばよい。
【００２９】
さらに、絶縁基体１の上面外周部には、搭載部１ａを取り囲むようにして枠状のダム部３が形成されている。
【００３０】
ダム部３は、例えば酸化アルミニウム質焼結体や窒化アルミニウム質焼結体・ムライト質焼結体・炭化珪素質焼結体・窒化珪素質焼結体・ガラスセラミックス等のセラミックスから成る５層の厚膜３ａ〜３ｅをその内側の側面が階段状となるように積層して成る。そして、絶縁基体１の搭載部１ａに半導体素子４をバンプ６を介してフリップチップ接続法により搭載した後、絶縁基体１と半導体素子４との間に液状の樹脂製充填材５を充填する際に、液状の樹脂製充填材５がその流動性により絶縁基体１上で樹脂製充填材５が不要な部分にまで流れ広がるのを防止する作用をなす。
【００３１】
このダム部３は、例えば５層のセラミック厚膜３ａ〜３ｅをその内周面である内側の側面が階段状となるように積層してなることから、絶縁基体１の搭載部１ａに半導体素子４をバンプ６を介してフリップチップ接続法により搭載し、絶縁基体１と半導体素子４との間に液状の樹脂製充填材５を充填してこれを硬化させた後、樹脂製充填材５の硬化時の収縮による応力や半導体素子４が作動時に発生する熱による応力がダム部３と樹脂製充填材５との間に印加されたとしても、その応力は階段状となっているダム部３の内側の側面によりダム部３と樹脂製充填材５との接合面に対して垂直方向に作用する成分が良好に低減分散され、これによりダム部３と樹脂製充填材５との間における剥離の発生を有効に防止することができる。
【００３２】
ダム部３は、例えばその幅が１〜１０ｍｍ程度であり、その高さが０．０５〜０．５ ｍｍ程度である。そして、各セラミック厚膜３ａ〜３ｅの厚みは、それぞれ１０〜１００ μｍ程度である。また、その内側の側面に形成される各段の幅は０．０１〜１ｍｍ程度としておけばよい。
【００３３】
なお、ダム部３は、その表面の中心線平均粗さ（Ｒａ）をＲａ≧０．６５μｍとしておくと、ダム部３の表面の凹凸と樹脂製充填材５とが係止し合って両者をさらに強固に接合させることが可能となる。したがって、ダム部３は、その表面の中心線平均粗さ（Ｒａ）をＲａ≧０．６５μｍとしておくことが好ましい。
【００３４】
一方、この中心線平均粗さ（Ｒａ）がＲａ＞１０μｍとなると、ダム部３をセラミック厚膜３ａ〜３ｅで形成することが困難となる傾向にあり、またダム部３の表面の微細な凹凸が樹脂性充填材５で十分に濡れない部分が生じる傾向もあるため、ダム部３の表面の中心線平均粗さ（Ｒａ）はＲａ≦１０μｍとしておくことが好ましい。
【００３５】
さらに、ダム部３は、絶縁基体１と実質的に同じ組成のセラミックスで形成しておくと、絶縁基体１とダム部３との熱膨張係数が略同一となり、絶縁基体１とダム部３とに例えば半導体素子４が作動時に発生する熱が繰り返し印加されたとしても、両者間に熱膨張係数の相違に起因する熱応力が発生することはなく、ダム部３に剥離やクラックが発生することを有効に防止できる。従って、ダム部３は絶縁基体１と実質的に同じ組成のセラミックスで形成することが好ましい。
【００３６】
このようなダム部３は、例えば各セラミック厚膜３ａ〜３ｅが酸化アルミニウム質焼結体から成る場合であれば、酸化アルミニウム・酸化珪素・酸化カルシウム・酸化マグネシウム等の原料粉末に適当な有機バインダ・溶剤を添加混合して得たセラミックペーストを、絶縁基体１となるセラミックグリーンシート上に従来周知のスクリーン印刷法を採用して各セラミック厚膜３ａ〜３ｂに対応した枠状のパターンとなるように順次印刷して積層し、これをセラミックグリーンシートとともに焼成することによって絶縁基体１の上面の封止部１ｂに所定の枠状に被着形成される。
【００３７】
なお、セラミックペーストをスクリーン印刷法により印刷塗布するとともに、これを焼成することによって得られるダム部３の表面の表面粗さは、セラミックグリーンシートを焼成して得られる絶縁基体１と比較して粗いものとなりやすいため、中心線平均粗さ（Ｒａ）でＲａ≧０．６５μｍとなる表面粗さを容易に得ることができる。
【００３８】
また、絶縁基体１となるセラミックグリーンシート上に印刷された各セラミック厚膜３ａ〜３ｅとなる各セラミックペーストは、その側面と上面との間がセラミックペーストの表面張力に起因して丸みを呈したものとなり、この丸みによってもダム部３と樹脂製充填材５との接合面に印加される応力を良好に分散することができる。
【００３９】
かくして、本発明の半導体素子搭載用配線基板および半導体装置によれば、樹脂製充填材５が絶縁基体１上の不要な部分に流れ広がることがなく、かつ半導体素子４を樹脂製充填材５により良好に保護することができるとともに、半導体素子４の電極と絶縁基体１の配線導体２との電気的な接続を完全なものとして半導体素子４を長期間にわたり安定に作動させることができる。
【００４０】
なお、本発明は上述の実施の形態の一例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能である。例えば、上述の実施の形態の一例ではダム部３はその内側の側面が階段状となっていたが、ダム部３は必ずしもその内側の側面が階段状となっている必要はなく、例えば図２に要部拡大断面図で示すように、ダム部３はその内側の側面が傾斜面となっていてもよい。この場合であっても、樹脂製充填材５の硬化時の収縮による応力や半導体素子４が作動時に発生する熱による応力がダム部３と樹脂製充填材５との間に印加されたとしても、その応力は傾斜面となっているダム部３の内側の側面によりダム部３と樹脂製充填材５との接合面に対して垂直方向に作用する成分が良好に低減分散され、これによりダム部３と樹脂製充填材５との間に剥離が発生することを有効に防止することができる。このような傾斜面は、ダム部３を構成する各セラミック厚膜３ａ〜３ｅとなるセラミックペーストを絶縁基体１となるセラミックグリーンシート上にスクリーン印刷法を採用して順次印刷塗布する際に、各セラミック厚膜３ａ〜３ｅとなるセラミックペーストの厚みと幅ならびに粘度を適宜調整することによって形成可能である。
【００４１】
さらに、上述の実施の形態の一例ではダム部３は５層のセラミック厚膜３ａ〜３ｅを積層することによって形成されていたが、ダム部３は２〜４層のセラミック厚膜を積層することによって形成されていてもよいし、さらには６層以上のセラミック厚膜を積層することによって形成されていてもよい。
【００４２】
【発明の効果】
本発明の半導体素子搭載用配線基板および半導体装置によれば、絶縁基体に形成されたダム部が複数層のセラミック厚膜を積層して成り、その内側の側面が階段状または傾斜面となっていることから、絶縁基体の搭載部に半導体素子をフリップチップ接続法により搭載し、ダム部の内側で絶縁基体と半導体素子との間に液状の樹脂製充填材を充填してこれを熱硬化させた後、樹脂製充填材の硬化時の収縮による応力や半導体素子が作動時に発生する熱による応力がダム部と樹脂製充填材との間に印加されたとしても、その応力は階段状または傾斜面となっているダム部の内側の側面によりダム部と樹脂製充填材との接合面に対して垂直方向に作用する成分が良好に低減分散されるため、ダム部と樹脂製充填材との間における剥離の発生を有効に防止することができ、その結果、樹脂製充填材が絶縁基体上の不要な部分に流れ広がることがなく、かつ半導体素子を樹脂製充填材により良好に保護することができるとともに、半導体素子の電極と絶縁基体の配線導体との電気的な接続を完全なものとして半導体素子を長期間にわたり安定に作動させることが可能となる。
【図面の簡単な説明】
【図１】本発明の半導体素子搭載用配線基板およびこれを用いた半導体装置の実施の形態の一例を示す断面図である。
【図２】本発明の半導体素子搭載用配線基板およびこれを用いた半導体装置の実施の形態の他の例を示す要部拡大断面図である。
【図３】従来の半導体素子搭載用配線基板およびこれを用いた半導体装置の断面図である。
【符号の説明】
１・・・・絶縁基体
１ａ・・・・搭載部
２・・・・配線導体
３・・・・ダム部
４・・・・半導体素子
５・・・・樹脂製充填材[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor element mounting wiring board in which a semiconductor element is mounted on an insulating substrate having a wiring conductor by a flip chip connection method, and mounting the semiconductor element on the semiconductor element mounting wiring board by a flip chip connection method. In addition, the present invention relates to a semiconductor device in which a resin filler is filled between a semiconductor element and an insulating substrate.
[0002]
[Prior art]
Recently, as semiconductor devices corresponding to miniaturization and thinning of electronic devices such as computers, for example, aluminum oxide sintered bodies, aluminum nitride sintered bodies, mullite sintered bodies, silicon carbide sintered bodies, nitriding A wiring for mounting a semiconductor element having a mounting portion on which a semiconductor element is mounted at the center of the upper surface of an insulating base made of ceramics such as a silicon-based sintered body and glass ceramics, and a wiring conductor is disposed from the mounting portion to the lower surface. A substrate is prepared, and the semiconductor element is mounted on the mounting portion of the wiring board for mounting the semiconductor element by a flip chip connection method via a bump made of solder, gold, or the like, and then between the semiconductor element and the insulating substrate. Is filled with a liquid resin filler called underfill and thermally cured, and the semiconductor element is protected by the heat-cured resin filler. The semiconductor device formed by sticking is known an insulating substrate and the semiconductor element together.
[0003]
The semiconductor element mounting wiring board in this semiconductor device is manufactured by a so-called ceramic green sheet lamination method. Specifically, a ceramic green sheet formed by bonding ceramic raw material powder with an organic binder is appropriately stamped, and a metal paste serving as a wiring conductor is printed and applied in a predetermined pattern, and a plurality of ceramic green sheets are laminated. And baked at a high temperature.
[0004]
However, according to this semiconductor device, after the semiconductor element is mounted on the mounting portion of the wiring board for mounting the semiconductor element by the flip-chip connection method via the bump made of solder or gold, the liquid is placed between the insulating substrate and the semiconductor element. Since the resin filler is filled, the filled liquid resin flows to the part where the resin filler is unnecessary on the insulating base due to its fluidity, which adversely affects the function as a semiconductor device, or the semiconductor There has been a problem that the appearance of the apparatus is remarkably impaired.
[0005]
Therefore, in order to solve the above problem, as shown in a cross-sectional view in FIG. 3, the mounting portion 11a in which the semiconductor element 12 is mounted at the center of the upper surface of the insulating base 11 by the flip chip connection method and the mounting portion 11a. A semiconductor element mounting wiring board having a wiring conductor 13 leading out to the lower surface and a frame-shaped dam portion 14 having a predetermined height formed so as to surround the mounting portion 11a is prepared. The semiconductor element 12 is mounted on the mounting portion 11a of the wiring board by the flip chip connection method via the bumps 15 made of solder, gold or the like, and then the liquid is formed between the insulating base 11 and the semiconductor element 12 inside the dam portion 14. There has been proposed a semiconductor device in which the resin filler 16 is filled and thermally cured.
[0006]
According to such a semiconductor device, when the liquid resin filler 16 is filled between the insulating base 11 and the semiconductor element 12 inside the dam portion 14 surrounding the mounting portion 11a, the liquid resin filler 16 is unnecessary. It is effectively prevented by the dam part 14 from spreading to the proper part.
[0007]
[Problems to be solved by the invention]
However, in the semiconductor element mounting wiring board described above, the dam portion 14 is usually formed by laminating a ceramic green sheet punched into a frame shape on the uppermost layer of a ceramic green sheet laminate that becomes the semiconductor element mounting wiring board. Is formed so as to surround the mounting portion 11a.
[0008]
Since the dam portion 14 formed in this manner is formed by punching out a ceramic green sheet and firing it, the inner side surface thereof is substantially perpendicular to the upper surface of the insulating substrate 11. .
[0009]
Then, when the liquid resin filler 16 is filled between the insulating substrate 11 and the semiconductor element 12 inside the dam portion 14 and the resin filler 16 is thermally cured, the resin filler 16 is heated. A large tensile stress is generated between the dam portion 14 and the resin filler 16 due to contraction during curing.
[0010]
Furthermore, the thermal expansion coefficient of the ceramic material forming the insulating substrate 11 is about 4 × 10 −6 to 10 × 10 −6 / ° C., whereas the thermal expansion coefficient of the resin filler 16 is about 30 × 10 −6 to a 50 × 10 -6 / ℃ about, between the coefficient of thermal expansion of the both are greatly different, activating the semiconductor element 12, the heat by the insulating base 11 and the resin filler 16 that occurs during the operation In addition, a large thermal stress is generated due to the difference in thermal expansion coefficient between the two.
[0011]
Such stress overlaps each other and acts on the joint surface between the dam portion 14 and the resin filler 16, and the joint between the dam portion 14 and the resin filler 16, which is the most concentrated portion of the stress. Peeling is generated between the dam portion 14 and the resin filler 16 from the upper end of the surface. The stress acting between the dam portion 14 and the resin filler 16 increases as the component acting in the direction perpendicular to the joint surface between the dam portion 14 and the resin filler 16 increases. Since the force to peel off the resin filler 16 is increased, the dam portion 14 and the resin filler 16 are easily separated.
[0012]
When peeling occurs between the dam portion 14 and the resin filler 16, the peeling gradually proceeds toward the center of the insulating substrate 11 as the semiconductor element 12 is repeatedly activated and stopped. Eventually, the resin filler 16 was completely peeled off from the insulating substrate 11, and the semiconductor element 12 could not be well protected. In addition, the electrodes of the semiconductor element 12 and the insulating substrate 11 are induced by inducing peeling of the connection bumps 15 such as solder and gold joining the electrodes of the semiconductor element 12 and the wiring conductors 13 of the wiring board for mounting the semiconductor element. As a result, the electrical connection with the wiring conductor 13 is disconnected, and as a result, the semiconductor element 12 cannot be stably operated over a long period of time.
[0013]
The present invention has been devised in view of the above problems, and its purpose is to firmly fix an insulating substrate and a semiconductor element with a resin filler, to protect the semiconductor element well, and to provide an electrode for the semiconductor element. It is an object of the present invention to provide a wiring board for mounting a semiconductor element and a semiconductor device using the same, which can operate the semiconductor element stably over a long period of time with perfect electrical connection with the wiring conductor.
[0014]
[Means for Solving the Problems]
A wiring board for mounting a semiconductor element according to the present invention has a mounting portion on which a semiconductor element is mounted and a frame-shaped dam portion formed so as to surround the mounting portion on an insulating substrate on which a wiring conductor is disposed. A wiring board for mounting a semiconductor element, wherein the dam portion has a stepped inner side surface, and is rounded between a side surface and an upper surface of each step.
[0015]
In the semiconductor element mounting wiring board of the present invention, preferably, the dam portion has a height of 0.05 to 0.5 mm, and a thickness of each of the steps is 10 to 100 μm. Is.
[0016]
The semiconductor device of the present invention includes a wiring board for mounting a semiconductor element of the present invention, a semiconductor element mounted on the mounting portion, and a resin filled between the insulating base and the semiconductor element inside the dam portion. It is characterized by comprising a filler.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Next, a semiconductor element mounting wiring board and a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
[0018]
FIG. 1 is a cross-sectional view showing an example of an embodiment of a semiconductor element mounting wiring board and a semiconductor device using the same according to the present invention. In FIG. 1, 1 is an insulating substrate, 2 is a wiring conductor, 3 is a dam part, 4 is a semiconductor element, and 5 is a resin filler. Among these, the insulating substrate 1, the wiring conductor 2, and the dam portion 3 constitute a semiconductor element mounting wiring board of the present invention. The semiconductor element mounting wiring board, the semiconductor element 4, and the resin filler 5 Thus, the semiconductor device of the present invention is configured.
[0019]
The insulating substrate 1 is, for example, a substantially rectangular flat plate having a size of about several mm to several cm square, and is an aluminum oxide sintered body, an aluminum nitride sintered body, a mullite sintered body, or a silicon carbide sintered body. -It is formed from ceramics, such as a silicon nitride sintered body and glass ceramics.
[0020]
If the insulating substrate 1 is made of, for example, an aluminum oxide sintered body, a suitable organic binder / solvent is added to and mixed with a raw material powder such as aluminum oxide, silicon oxide, magnesium oxide, calcium oxide, etc. In addition, a ceramic green sheet is obtained by adopting a conventionally known doctor blade method to obtain a ceramic green sheet, and an appropriate punching process is performed on the ceramic green sheet and a plurality of sheets are laminated as necessary. A green ceramic laminate is formed, and finally this green ceramic body is produced by firing at a temperature of about 1600 ° C. in a reducing atmosphere.
[0021]
The insulating base 1 functions as a support substrate for supporting the semiconductor element 4, and has a mounting portion 1 a for mounting the semiconductor element 4 at the center of the upper surface thereof. The semiconductor element 4 is mounted on the mounting portion 1a by a flip chip connection method via bumps 6 made of solder or gold.
The semiconductor element 4 is an electronic circuit element such as an integrated circuit element formed of a semiconductor material such as silicon or gallium arsenide.
[0022]
The semiconductor element 4 is mounted on the mounting portion 1a by preliminarily attaching a bump 6 made of solder or gold to each input / output electrode formed on the active surface of the semiconductor element 4 by welding or pressure bonding. The bump 6 is brought into contact with a portion led out to the mounting portion 1a of the wiring conductor 2 described later, and both are joined by welding or pressure bonding.
[0023]
One end portion of a wiring conductor 2 made of metal powder metallization such as tungsten, molybdenum, copper, or silver is led out to the mounting portion 1a of the insulating base 1 on which the semiconductor element 4 is mounted. Is led to the lower surface of the insulating base 1 through the inside of the insulating base 1.
[0024]
The wiring conductor 2 functions as a conductive path for electrically connecting each electrode of the semiconductor element 4 to an external electric circuit. As described above, each electrode of the semiconductor element 4 is provided at a portion led to the mounting portion 1a. Are electrically connected through connection bumps 6 such as solder and gold. Further, the other end portion of the wiring conductor 2 led out to the lower surface of the insulating base 1 is connected to a connection conductor of an external electric circuit board (not shown) via solder or the like, so that each electrode of the semiconductor element 4 is externally connected. It will be connected to the electric circuit.
[0025]
If such a wiring conductor 2 is made of, for example, tungsten metallization, a conventionally known screen is applied to a ceramic green sheet serving as an insulating base 1 by adding a metal paste obtained by adding and mixing an appropriate organic binder and solvent to tungsten powder. By applying a printing method to a predetermined pattern, and applying it to a ceramic green sheet, it is baked together with the ceramic green sheet to be deposited on the predetermined pattern so as to be led out from the mounting portion 1a of the insulating substrate 1. The surface of the wiring conductor 2 is usually soldered to prevent the wiring conductor 2 from being oxidized and corroded, and to connect the wiring conductor 2 and the bump 6 and the connection conductor of the wiring conductor 2 to the external electric circuit board. A nickel plating film and a gold plating film are sequentially deposited in order to facilitate and strengthen the connection via the.
[0026]
Further, after the semiconductor element 4 is mounted on the mounting portion 1 a of the insulating base 1 by the flip chip connection method via the bumps 6, an epoxy, for example, is interposed between the insulating base 1 and the semiconductor element 4 inside the dam portion 3 to be described later. After the resin filler 5 made of resin is filled in a liquid state, it is cured by heat to complete the semiconductor device.
[0027]
The resin filler 5 has a thickness of, for example, about several tens of μm to several hundreds of μm, and is filled between the insulating base 1 and the semiconductor element 4 to protect the semiconductor element 4 and the semiconductor element. 4 is firmly fixed to the insulating substrate 1. Moreover, according to the specification of a semiconductor device, you may contain the various fillers for adjustment of a thermal expansion coefficient and thermal conductivity improvement.
[0028]
The filling of the liquid resin filler 6 between the insulating substrate 1 and the semiconductor element 4 may be performed using, for example, a conventionally known dispenser. Moreover, what is necessary is just to perform the thermosetting of the resin filler 5 by heating to the temperature of 100-150 degreeC, for example by oven etc.
[0029]
Further, a frame-shaped dam portion 3 is formed on the outer peripheral portion of the upper surface of the insulating base 1 so as to surround the mounting portion 1a.
[0030]
The dam part 3 is made of, for example, an aluminum oxide sintered body, an aluminum nitride sintered body, a mullite sintered body, a silicon carbide sintered body, a silicon nitride sintered body, or a five-layered ceramic made of glass ceramics. Thick films 3a to 3e are laminated so that the inner side faces are stepped. Then, after the semiconductor element 4 is mounted on the mounting portion 1 a of the insulating base 1 via the bump 6 by the flip chip connection method, the liquid resin filler 5 is filled between the insulating base 1 and the semiconductor element 4. In addition, the liquid resin filler 5 acts to prevent the resin filler 5 from flowing to an unnecessary portion on the insulating substrate 1 due to its fluidity.
[0031]
The dam portion 3 is formed by stacking, for example, five layers of ceramic thick films 3a to 3e so that the inner side surface, which is the inner peripheral surface thereof, is stepped, so that the semiconductor element is mounted on the mounting portion 1a of the insulating base 1. 4 is mounted by a flip chip connection method via bumps 6, a liquid resin filler 5 is filled between the insulating substrate 1 and the semiconductor element 4 and cured, and then the resin filler 5 Even if stress due to shrinkage during curing or stress due to heat generated when the semiconductor element 4 operates is applied between the dam portion 3 and the resin filler 5, the stress is a stepped dam portion 3. The components acting in the vertical direction with respect to the joint surface between the dam portion 3 and the resin filler 5 are well reduced and dispersed by the inner side surfaces of the dam portion 3, thereby peeling between the dam portion 3 and the resin filler 5. Can be effectively prevented.
[0032]
The dam part 3 has, for example, a width of about 1 to 10 mm and a height of about 0.05 to 0.5 mm. And the thickness of each ceramic thick film 3a-3e is about 10-100 micrometers, respectively. The width of each step formed on the inner side surface may be about 0.01 to 1 mm.
[0033]
In addition, when the center line average roughness (Ra) of the surface of the dam portion 3 is set to Ra ≧ 0.65 μm, the unevenness of the surface of the dam portion 3 and the resin filler 5 are engaged with each other, so that both Furthermore, it becomes possible to make it join firmly. Therefore, it is preferable that the dam portion 3 has a surface centerline average roughness (Ra) of Ra ≧ 0.65 μm.
[0034]
On the other hand, when the center line average roughness (Ra) becomes Ra> 10 μm, it tends to be difficult to form the dam portion 3 with the ceramic thick films 3a to 3e, and the surface of the dam portion 3 has fine irregularities. However, there is a tendency that a portion that is not sufficiently wetted by the resinous filler 5 is generated. Therefore, the center line average roughness (Ra) of the surface of the dam portion 3 is preferably set to Ra ≦ 10 μm.
[0035]
Furthermore, if the dam part 3 is formed of ceramics having substantially the same composition as that of the insulating base 1, the insulating base 1 and the dam part 3 have substantially the same thermal expansion coefficient, and the insulating base 1 and the dam part 3 For example, even if the heat generated during operation of the semiconductor element 4 is repeatedly applied, thermal stress due to the difference in thermal expansion coefficient does not occur between the two, and peeling or cracking occurs in the dam portion 3. Can be effectively prevented. Therefore, the dam portion 3 is preferably formed of ceramics having substantially the same composition as that of the insulating substrate 1.
[0036]
Such a dam portion 3 is, for example, an organic binder suitable for a raw material powder such as aluminum oxide, silicon oxide, calcium oxide, and magnesium oxide if the ceramic thick films 3a to 3e are made of an aluminum oxide sintered body. A ceramic paste obtained by adding and mixing a solvent is formed on a ceramic green sheet serving as an insulating substrate 1 to form a frame-like pattern corresponding to each of the ceramic thick films 3a to 3b by employing a conventionally known screen printing method. Are sequentially printed and laminated, and are fired together with the ceramic green sheet to form a predetermined frame shape on the sealing portion 1b on the upper surface of the insulating substrate 1.
[0037]
The surface roughness of the surface of the dam portion 3 obtained by printing and applying the ceramic paste by screen printing and firing the ceramic paste is rougher than that of the insulating substrate 1 obtained by firing the ceramic green sheet. Since it becomes easy to become a thing, the surface roughness which becomes Ra> = 0.65 micrometer by centerline average roughness (Ra) can be obtained easily.
[0038]
Moreover, each ceramic paste used as each ceramic thick film 3a-3e printed on the ceramic green sheet used as the insulation base | substrate 1 exhibited the roundness between the side surface and the upper surface due to the surface tension of the ceramic paste. This roundness can also disperse well the stress applied to the joint surface between the dam portion 3 and the resin filler 5.
[0039]
Thus, according to the wiring board for semiconductor element mounting and the semiconductor device of the present invention, the resin filler 5 does not flow and spread over unnecessary portions on the insulating base 1, and the semiconductor element 4 is made of the resin filler 5. The semiconductor element 4 can be protected well, and the electrical connection between the electrode of the semiconductor element 4 and the wiring conductor 2 of the insulating base 1 can be made perfect and the semiconductor element 4 can be stably operated over a long period of time.
[0040]
Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention. For example, in the example of the embodiment described above, the inner side surface of the dam portion 3 has a stepped shape, but the inner side surface of the dam portion 3 does not necessarily have a stepped shape. As shown in the enlarged sectional view of the main part, the inner surface of the dam part 3 may be an inclined surface. Even in this case, even if stress due to shrinkage during curing of the resin filler 5 or stress due to heat generated when the semiconductor element 4 is activated is applied between the dam portion 3 and the resin filler 5. The stress acts to reduce and disperse the component acting in the vertical direction with respect to the joint surface between the dam portion 3 and the resin filler 5 by the inner side surface of the dam portion 3 having an inclined surface. It is possible to effectively prevent peeling between the portion 3 and the resin filler 5. Such an inclined surface is formed when a ceramic paste to be the ceramic thick films 3a to 3e constituting the dam portion 3 is sequentially printed and applied onto a ceramic green sheet to be the insulating base 1 by using a screen printing method. It can be formed by appropriately adjusting the thickness, width and viscosity of the ceramic paste to be the ceramic thick films 3a to 3e.
[0041]
Furthermore, in the example of the above-described embodiment, the dam part 3 is formed by laminating five layers of ceramic thick films 3a to 3e. However, the dam part 3 is composed of two to four layers of ceramic thick films. Or may be formed by laminating 6 or more ceramic thick films.
[0042]
【The invention's effect】
According to the semiconductor element mounting wiring board and the semiconductor device of the present invention, the dam portion formed on the insulating base is formed by laminating a plurality of layers of ceramic thick films, and the inner side surface is stepped or inclined. Therefore, a semiconductor element is mounted on the mounting portion of the insulating base by a flip chip connection method, and a liquid resin filler is filled between the insulating base and the semiconductor element inside the dam portion and is thermally cured. After that, even if stress due to shrinkage during curing of the resin filler or stress due to heat generated during operation of the semiconductor element is applied between the dam part and the resin filler, the stress is stepped or inclined. The component acting in the vertical direction with respect to the joint surface between the dam part and the resin filler is satisfactorily reduced and dispersed by the inner side surface of the dam part which is the surface, so that the dam part and the resin filler Effective generation of delamination As a result, the resin filler does not flow and spread over unnecessary portions on the insulating substrate, and the semiconductor element can be well protected by the resin filler, and the electrode of the semiconductor element As a result, the semiconductor element can be stably operated over a long period of time with the complete electrical connection between the wiring substrate and the wiring conductor of the insulating base.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing an example of an embodiment of a semiconductor element mounting wiring board and a semiconductor device using the same according to the present invention.
FIG. 2 is an enlarged cross-sectional view of a main part showing another example of an embodiment of a semiconductor element mounting wiring board and a semiconductor device using the same according to the present invention.
FIG. 3 is a cross-sectional view of a conventional semiconductor element mounting wiring board and a semiconductor device using the same.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Insulating base | substrate 1a ... Mounting part 2 ... Wiring conductor 3 ... Dam part 4 ... Semiconductor element 5 ... Resin filler

Claims (3)

配線導体が配設された絶縁基体上に、半導体素子が搭載される搭載部および該搭載部を取り囲むようにして形成された枠状のダム部を有する半導体素子搭載用配線基板であって、前記ダム部は、内側の側面が階段状であり、各段の側面と上面との間に丸みを有することを特徴とする半導体素子搭載用配線基板。A semiconductor element mounting wiring board having a mounting portion on which a semiconductor element is mounted and a frame-shaped dam portion formed so as to surround the mounting portion on an insulating substrate on which a wiring conductor is disposed, The dam portion has a stepped inner side surface, and has a roundness between the side surface and the upper surface of each step . 前記ダム部は、高さが０．０５〜０．５ｍｍであり、前記各段の厚みが１０〜１００μｍであることを特徴とする請求項１記載の半導体素子搭載用配線基板。2. The wiring board for mounting a semiconductor element according to claim 1, wherein the dam portion has a height of 0.05 to 0.5 mm, and a thickness of each step is 10 to 100 [mu] m. 請求項１または請求項２に記載された半導体素子搭載用配線基板と、前記搭載部に搭載された半導体素子と、前記ダム部の内側で前記絶縁基体と前記半導体素子との間に充填された樹脂製充填材とを備えていることを特徴とする半導体装置。 A wiring board for mounting a semiconductor element according to claim 1, a semiconductor element mounted on the mounting part, and a space between the insulating base and the semiconductor element inside the dam part. a semiconductor device characterized by comprising a resin filler.
JP15157299A 1999-05-31 1999-05-31 Wiring board for mounting semiconductor element and semiconductor device using the same Expired - Fee Related JP3618060B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15157299A JP3618060B2 (en) 1999-05-31 1999-05-31 Wiring board for mounting semiconductor element and semiconductor device using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15157299A JP3618060B2 (en) 1999-05-31 1999-05-31 Wiring board for mounting semiconductor element and semiconductor device using the same

Publications (2)

Publication Number Publication Date
JP2000340715A JP2000340715A (en) 2000-12-08
JP3618060B2 true JP3618060B2 (en) 2005-02-09

Family

ID=15521464

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15157299A Expired - Fee Related JP3618060B2 (en) 1999-05-31 1999-05-31 Wiring board for mounting semiconductor element and semiconductor device using the same

Country Status (1)

Country Link
JP (1) JP3618060B2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6399425B1 (en) * 1998-09-02 2002-06-04 Micron Technology, Inc. Method of encapsulating semiconductor devices utilizing a dispensing apparatus with rotating orifices
US11842972B2 (en) 2004-09-28 2023-12-12 Rohm Co., Ltd. Semiconductor device with a semiconductor chip connected in a flip chip manner
JP2006100385A (en) 2004-09-28 2006-04-13 Rohm Co Ltd Semiconductor device
JP6111832B2 (en) * 2013-05-06 2017-04-12 株式会社デンソー Multilayer substrate, electronic device using the same, and method for manufacturing electronic device
CN105870075A (en) * 2015-01-22 2016-08-17 恒劲科技股份有限公司 Substrate structure
US10586716B2 (en) * 2017-06-09 2020-03-10 Advanced Semiconductor Engineering, Inc. Semiconductor device package

Also Published As

Publication number Publication date
JP2000340715A (en) 2000-12-08

Similar Documents

Publication Publication Date Title
US7358445B1 (en) Circuit substrate and apparatus including the circuit substrate
CN100568489C (en) Circuit module and manufacture method thereof
TWI257832B (en) Intermediate substrate, intermediate substrate with semiconductor element, substrate with intermediate substrate, and structure having semiconductor element, intermediate substrate and substrate
WO2013035337A1 (en) Semiconductor module, circuit board
JP2002170921A (en) Semiconductor device and its manufacturing method
JP3618060B2 (en) Wiring board for mounting semiconductor element and semiconductor device using the same
JP2013197258A (en) Circuit board and manufacturing method for semiconductor module
JP2013051389A (en) Circuit board, semiconductor power module and manufacturing method
JP2005322659A (en) Wiring board, its manufacturing method and semiconductor device
KR20210133069A (en) Adhesive transfer film and method for manufacturing power module substrate using the same
JPH07162157A (en) Multilayered board
JP2016092018A (en) Wiring board, electronic device and electronic module
JP2008172176A (en) Semiconductor element mounting substrate and its manufacturing method
JPH11274372A (en) Semiconductor device and its semiconductor package
JP6818457B2 (en) Wiring boards, electronics and electronic modules
JP2010263056A (en) Circuit board, circuit board with bump, and electronic device
JPH10275878A (en) Semiconductor package
JP3950950B2 (en) Manufacturing method of ceramic wiring board
JP2008091650A (en) Flip-chip packaging method and semiconductor package
JP2004281470A (en) Wiring board
JP5058071B2 (en) Electronic component mounting board
JP4416269B2 (en) Electronic equipment
KR20210135025A (en) Adhesive transfer film and method for manufacturing power module substrate using the same
JPH04119644A (en) Mounting of semicondctor element
JP2004281471A (en) Wiring board

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20040804

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20040810

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20041012

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20041102

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20041108

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20071119

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081119

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091119

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101119

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101119

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111119

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111119

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121119

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121119

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131119

Year of fee payment: 9

LAPS Cancellation because of no payment of annual fees