JP2005322659A - Wiring board, its manufacturing method and semiconductor device - Google Patents

Wiring board, its manufacturing method and semiconductor device Download PDF

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Publication number
JP2005322659A
JP2005322659A JP2004136954A JP2004136954A JP2005322659A JP 2005322659 A JP2005322659 A JP 2005322659A JP 2004136954 A JP2004136954 A JP 2004136954A JP 2004136954 A JP2004136954 A JP 2004136954A JP 2005322659 A JP2005322659 A JP 2005322659A
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Prior art keywords
wiring board
sealing resin
semiconductor element
mounting
filled
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JP2004136954A
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Japanese (ja)
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Manabu Onishi
学 大西
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority to JP2004136954A priority Critical patent/JP2005322659A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high quality semiconductor device in a flip chip system and a wiring board, with which adhesiveness of the interface of the wiring board and sealing resin can be raised and the interface is not peeled on mounting in high temperature of lead-free solder without cost rise. <P>SOLUTION: In the wiring board 1 in which a semiconductor element 6 is flip-chip mounted, dummy vias 8 are formed where a region mounting the semiconductor element 6 is not filled with conductive paste 3, and adhesiveness of the wiring board 1 and sealing resin 9 is improved by filling the dummy vias 8 with sealing resin 9. Thus, (1) use regulation of an environmental load burden substance becomes strong, and use of lead-free solder in which lead acting as the environmental load substance is not used is spread in solder used when an electronic component is mounted. (2) Since a melting temperature of lead free solder is high compared to conventional lead solder, the electronic component in which a quality problem such as peeling of the interface between a semiconductor carrier and sealing resin is not caused at the time of mounting the electronic component where the problem is solved that the mounting temperature of the electronic material becomes high. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明はエレクトロニクス産業で用いられるＬＳＩやＩＣ、チップ部品などの半導体素子を搭載する半導体装置に関し、特に半導体素子をフェースダウン実装方式により搭載する半導体装置に関する。また、詳しくは、半導体装置において、突起電極を有する半導体素子がフェースダウン実装され、実装された半導体素子との間に熱硬化性の封止樹脂が充填される配線基板に関する。   The present invention relates to a semiconductor device on which semiconductor elements such as LSIs, ICs, and chip components used in the electronics industry are mounted, and more particularly to a semiconductor device on which semiconductor elements are mounted by a face-down mounting method. More specifically, the present invention relates to a wiring substrate in which a semiconductor element having a protruding electrode is mounted face-down in a semiconductor device, and a thermosetting sealing resin is filled between the mounted semiconductor element.

一般にフェースダウン実装方式の半導体装置は、半導体素子の回路形成面の電極パッドにＡｕバンプ等により突起電極を形成した後、絶縁性基体からなり、その上面に複数の電極を有するとともに底面に格子状に配列された外部電極端子を有して半導体キャリアとして機能する配線基板の所定位置に、前記半導体素子の突起電極を位置合わせしてフリップチップ実装を行い、その後、半導体素子と配線基板との間および前記半導体素子の周辺部にエポキシ系の熱硬化性を有する封止樹脂を充填塗布する工程を経て製造されている。   In general, a face-down mounting type semiconductor device is formed of an insulating base after forming a bump electrode on an electrode pad of a circuit formation surface of a semiconductor element by an Au bump or the like, and has a plurality of electrodes on its upper surface and a lattice shape on its bottom surface. The projecting electrode of the semiconductor element is aligned with a predetermined position of the wiring board that functions as a semiconductor carrier having external electrode terminals arranged in the flip-chip mounting, and then between the semiconductor element and the wiring board In addition, it is manufactured through a step of filling and applying an epoxy-based sealing resin having thermosetting properties to the peripheral portion of the semiconductor element.

前記フリップ実装工法を用いた半導体装置は例えば特許文献１に示されている。
半導体素子を保持する半導体キャリアなどとして用いられる多層の配線基板の絶縁性基体としてはセラミックや有機材料が使用されている。ここでは絶縁性基体がセラミックである多層の配線基板（セラミック多層配線基板と称す）の一般的な製造方法について説明する。この種のセラミック多層配線基板の製造方法としてグリーンシート積層法が一般に知られている。半導体素子収納用パッケージや回路基板等に使用されるセラミック多層配線基板は、アルミナセラミックス等の電気絶縁材料より成る絶縁性基体と該絶縁性基体の表面及び内部に埋設、焼き付けられているタングステン（Ｗ）、モリブデン（Ｍｏ）等の高融点金属より成る配線導体とにより構成されている。即ち、まずアルミナ等の電気絶縁性に優れたセラミック原料粉末に適当な有機溶剤、溶媒を添加混合して泥漿状となすと共に、該泥漿状物を従来から周知のドクターブレード法を採用することによってシート状とし、複数枚のセラミック生シート（グリーンシート）を得る。次に前記グリーンシートに接続配線用のスルーホールからなる導通用ビアを形成し、該導通用ビア内にタングステン（Ｗ）、モリブデン（Ｍｏ）等の高融点金属から成る導電性ペーストを充填すると共に、前記グリーンシートの上面にスクリーン印刷法等の厚膜手法により配線用導体を印刷塗布して所定パターン形状に被着させる。そして最後に前記各グリーンシートを上下に積層すると共に加圧して生積層体を得、この後、該生積層体を還元雰囲気中の約１５００℃の温度で焼成して各グリーンシート（セラミック生シート）と配線用導電層とを焼結一体化させる。このようにしてセラミック多層配線基板が製造される。 A semiconductor device using the flip mounting method is disclosed in Patent Document 1, for example.
Ceramics and organic materials are used as insulating bases of multilayer wiring boards used as semiconductor carriers for holding semiconductor elements. Here, a general manufacturing method of a multilayer wiring board (referred to as a ceramic multilayer wiring board) whose insulating base is ceramic will be described. A green sheet laminating method is generally known as a method for manufacturing this type of ceramic multilayer wiring board. A ceramic multilayer wiring board used for a package for semiconductor element storage, a circuit board, and the like includes an insulating base made of an electrically insulating material such as alumina ceramic and tungsten (W) embedded and burned in the surface and inside of the insulating base. ) And a wiring conductor made of a refractory metal such as molybdenum (Mo). That is, first, by adding a suitable organic solvent and solvent to a ceramic raw material powder having excellent electrical insulation such as alumina to form a mud, and using the doctor blade method known in the art. A sheet is formed to obtain a plurality of green ceramic sheets (green sheets). Next, a conductive via made of a through hole for connection wiring is formed on the green sheet, and the conductive via is filled with a conductive paste made of a refractory metal such as tungsten (W) or molybdenum (Mo). Then, a conductor for wiring is printed and applied on the upper surface of the green sheet by a thick film method such as a screen printing method, and is applied in a predetermined pattern shape. Finally, the green sheets are laminated one above the other and pressed to obtain a green laminate, and then the green laminate is fired at a temperature of about 1500 ° C. in a reducing atmosphere to obtain each green sheet (ceramic green sheet). ) And the conductive layer for wiring are sintered and integrated. In this way, a ceramic multilayer wiring board is manufactured.

ところで、近年環境問題に対する意識の高まりから環境負荷物質の使用規制が強まっており、電子部品を実装する際に使用される半田も環境負荷物質である鉛を使用しない鉛フリー半田の使用が広がっている。しかしながら鉛フリー半田は従来の鉛半田に比べて溶融温度が高いため電子材料の実装温度も高温になっている。しかし、実装温度が従来よりも高い場合には、電子部品の実装の際に配線基板と熱硬化性の封止樹脂との界面で剥離を生じたり樹脂クラック等を生じたりすることがあるので、このように実装温度が従来よりも高い場合でも、実装の際に配線基板と封止樹脂との界面剥離や樹脂クラック等の品質問題が生じない半導体装置の開発が求められている。   By the way, in recent years, regulations on the use of environmentally hazardous substances have been strengthened due to increased awareness of environmental issues, and the use of lead-free solder that does not use lead, which is an environmentally hazardous substance, has also spread as solder used when mounting electronic components. Yes. However, since lead-free solder has a higher melting temperature than conventional lead solder, the mounting temperature of electronic materials is also high. However, if the mounting temperature is higher than conventional, it may cause peeling or resin cracks at the interface between the wiring board and the thermosetting sealing resin when mounting electronic components. Thus, even when the mounting temperature is higher than before, development of a semiconductor device that does not cause quality problems such as interface peeling between the wiring board and the sealing resin and resin cracks during the mounting is required.

この問題に対処し得る技術として、配線基板の表面に微視的に数μｍ単位の凹凸をつけて、配線基板と封止樹脂との界面での密着力を高める工法が特許文献２に開示されている。
特開平６−２２４２５９号公報 特開２００４−６８２９ As a technique capable of coping with this problem, Patent Document 2 discloses a method for microscopically providing unevenness of several μm on the surface of the wiring board to increase the adhesion at the interface between the wiring board and the sealing resin. ing.
JP-A-6-224259 JP 2004-6829 A

しかしながら、特許文献２に開示されているように、微視的に配線基板の表面に凹凸をつける工法を採用しても、凹凸が数μｍ単位であるので密着力向上の効果が小さくて配線基板と封止樹脂との界面での剥離を確実に防止することは困難であり、また凹凸を形成するための製造工程が増加することとなって、製造工程が複雑になるため、コストアップを招くおそれがある。   However, as disclosed in Patent Document 2, even if a method of microscopically forming the unevenness on the surface of the wiring board is adopted, since the unevenness is on the order of several μm, the effect of improving the adhesion is small, and the wiring board It is difficult to reliably prevent peeling at the interface between the sealing resin and the sealing resin, and the manufacturing process for forming the irregularities increases, which complicates the manufacturing process and increases costs. There is a fear.

本発明は上記課題を解決するもので、コストアップを招くことなく、配線基板と封止樹脂との界面の密着性を向上させることができ、鉛フリー半田などの高温実装にも界面剥離の発生しない高品質なフリップチップ方式の半導体装置ならびに配線基板を提供することを目的とする。   The present invention solves the above-mentioned problems, and can improve the adhesion of the interface between the wiring board and the sealing resin without increasing the cost, and the occurrence of interface peeling even in high-temperature mounting such as lead-free solder. An object of the present invention is to provide a high-quality flip-chip semiconductor device and a wiring board that do not.

前記課題を解決するために本発明における配線基板ならびに半導体装置は、以下のような構成を有している。突起電極を有する半導体素子が配線基板にフェースダウンによりフリップチップ実装され、半導体素子と該半導体素子が実装された配線基板との間に封止樹脂が充填される半導体装置において、配線基板における半導体素子に臨む領域に、導電性ペーストは充填させずに、封止樹脂を充填させるダミービアを形成することを特徴とする。   In order to solve the above problems, a wiring board and a semiconductor device according to the present invention have the following configurations. In a semiconductor device in which a semiconductor element having a protruding electrode is flip-chip mounted on a wiring board by face-down and a sealing resin is filled between the semiconductor element and the wiring board on which the semiconductor element is mounted, the semiconductor element in the wiring board A dummy via that fills with a sealing resin is formed in the region facing the surface without filling with a conductive paste.

前記構成により、封止樹脂を配線基板と半導体素子との間に充填する際に、封止樹脂が配線基板のダミービアに充填される。これにより、ダミービアを設けない場合に比べて、配線基板と封止樹脂とが広い面積でかつ凹凸を有する形状で接合されることとなり密着性が向上する。この結果、鉛フリー半田などの高温実装の場合でも界面剥離の発生しない高品質なフリップチップ方式の半導体装置を実現させることができる。   With the above configuration, when the sealing resin is filled between the wiring board and the semiconductor element, the sealing resin is filled into the dummy vias of the wiring board. Thereby, compared with the case where a dummy via is not provided, the wiring board and the sealing resin are bonded in a wide area and in a shape having irregularities, thereby improving the adhesion. As a result, it is possible to realize a high-quality flip-chip semiconductor device in which interface peeling does not occur even in the case of high-temperature mounting such as lead-free solder.

また、導電性ペーストが充填される導通ビアと、導電性ペーストが充填されずに封止樹脂が充填されるダミービアとを一括形成することで、製造工程が増加しないので、製造工程の複雑によるコストアップを防止できる。   In addition, the manufacturing process is not increased by forming the conductive via filled with the conductive paste and the dummy via filled with the sealing resin without being filled with the conductive paste. Can prevent up.

本発明の配線基板ならびに半導体装置によれば、封止樹脂が充填されるダミービアを配線基板に形成したことにより、封止樹脂と配線基板との密着性を向上することができ、コストアップなしに、高温の鉛フリー半田実装の場合でも配線基板と封止樹脂との界面剥離を起こすことなく高品質なフェースダウン方式の半導体装置の作成を容易に行うことが可能となる。   According to the wiring board and the semiconductor device of the present invention, since the dummy via filled with the sealing resin is formed in the wiring board, the adhesion between the sealing resin and the wiring board can be improved, and the cost is not increased. Even in the case of high-temperature lead-free solder mounting, it is possible to easily produce a high-quality face-down type semiconductor device without causing interface peeling between the wiring board and the sealing resin.

以下、本発明の実施の形態について図面を参照しながら説明する。
まず、本発明の実施の形態に係る配線基板について説明する。図１（ａ）は本実施の形態に係る配線基板の平面図である。図１（ｂ）は同配線基板の断面図であり、図１（ａ）のＡ−Ａ’線部分の断面を示している。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, a wiring board according to an embodiment of the present invention will be described. FIG. 1A is a plan view of a wiring board according to the present embodiment. FIG. 1B is a cross-sectional view of the same wiring board, and shows a cross section taken along line AA ′ of FIG.

図１（ａ）、（ｂ）に示すように、配線基板１は、絶縁性材料（後述するグリーンシート）で構成された板状の絶縁層２の所定箇所に、導電性ペースト３が充填された導電ビア４が設けられるとともに、導電ビア４により接続されるように片面側または両面に導電配線層５が形成された配線基板体が、複数枚積層されて構成されている。そして、図１（ａ）、（ｂ）に示す実施の形態に係る配線基板１においては、後述する半導体素子６（図２参照）が搭載される半導体素子搭載領域７（半導体素子６に対向して臨む領域）のコーナー部分に、導電性ペースト３を充填しないダミービア８がカギ型に複数個形成されている。図１（ａ）ではダミービア８は１列に配列されているが、搭載される半導体素子６の大きさによっては２列または３列に配置してもよい。前記ダミービア８のサイズは導電性ペースト３を充填する配線接続用の導通ビア４と同等か大きめのサイズが好ましく、直径７５μｍから１５０μｍ程度が適当である。これはダミービア８のサイズが小さすぎると、後述する封止樹脂９が充填されずに品質低下の原因となり、逆に大きすぎると配線基板１の表層での配線領域を狭めることになり適当ではないからである。なお、この配線基板１は半導体素子６を保持する半導体キャリア用として用いられる。   As shown in FIGS. 1A and 1B, the wiring board 1 is filled with a conductive paste 3 in a predetermined portion of a plate-like insulating layer 2 made of an insulating material (green sheet to be described later). In addition, a plurality of wiring substrate bodies each having a conductive wiring layer 5 formed on one side or both sides so as to be connected by the conductive via 4 are laminated. In the wiring substrate 1 according to the embodiment shown in FIGS. 1A and 1B, a semiconductor element mounting region 7 (to face the semiconductor element 6) on which a semiconductor element 6 (see FIG. 2) described later is mounted. A plurality of dummy vias 8 that are not filled with the conductive paste 3 are formed in a key shape at the corner portion of the area facing the head. In FIG. 1A, the dummy vias 8 are arranged in one row, but may be arranged in two or three rows depending on the size of the semiconductor element 6 to be mounted. The size of the dummy via 8 is preferably equal to or larger than that of the conductive via 4 for wiring connection filled with the conductive paste 3, and a diameter of about 75 μm to 150 μm is appropriate. If the size of the dummy via 8 is too small, the sealing resin 9 to be described later is not filled, resulting in deterioration of the quality. Conversely, if the size is too large, the wiring area on the surface layer of the wiring board 1 is narrowed, which is not appropriate. Because. The wiring board 1 is used for a semiconductor carrier that holds the semiconductor element 6.

図２（ａ）、（ｂ）は前記配線基板１を使用した半導体装置の一例で、平面図および断面図を示している。図２（ａ）、（ｂ）に示すように、Ａｕバンプ等により形成された金属突起１０を備えた半導体素子６が回路面を下向きに（すなわち、フェースダウン状態で）前記配線基板１にフリップチップ実装され、前記配線基板１と前記半導体素子６との間の隙間および半導体素子６の周辺部に封止樹脂（熱硬化性樹脂）９が充填塗布されている。そして、前記ダミービア８にも封止樹脂９が充填されており、これにより前記配線基板１と前記封止樹脂９との間の密着性を向上させている。つまり、ダミービア８を設けない場合に比べて、配線基板１と封止樹脂９とが広い面積でかつ凹凸を有する形状で接合されるので密着性が大幅に向上する。この結果、鉛フリー半田などの高温実装の場合でも界面剥離の発生しない高品質なフリップチップ方式の半導体装置を実現させることができる。また、図２に示すようにダミービア８の下に下層の導電配線層５や配線接続用の導通ビア４が存在してもダミービア８には封止樹脂９が充填されるため、ダミービア８が外部に露出することはなく、信頼性上なんら問題は無い。   2A and 2B are an example of a semiconductor device using the wiring substrate 1, and a plan view and a cross-sectional view are shown. As shown in FIGS. 2A and 2B, the semiconductor element 6 having the metal protrusions 10 formed by Au bumps or the like is flipped to the wiring board 1 with the circuit surface facing downward (that is, in a face-down state). It is mounted in a chip, and a sealing resin (thermosetting resin) 9 is filled and applied to the gap between the wiring substrate 1 and the semiconductor element 6 and the peripheral part of the semiconductor element 6. The dummy via 8 is also filled with a sealing resin 9, thereby improving the adhesion between the wiring substrate 1 and the sealing resin 9. That is, as compared with the case where the dummy via 8 is not provided, the wiring substrate 1 and the sealing resin 9 are joined in a wide area and a shape having irregularities, so that the adhesion is greatly improved. As a result, it is possible to realize a high-quality flip-chip semiconductor device in which interface peeling does not occur even in the case of high-temperature mounting such as lead-free solder. Further, as shown in FIG. 2, even if the lower conductive wiring layer 5 and the conductive via 4 for wiring connection exist below the dummy via 8, the dummy via 8 is filled with the sealing resin 9, so that the dummy via 8 is externally provided. There is no problem in reliability.

次に、図３（ａ）〜（ｄ）により本発明に係る配線基板の製造方法の一例を示す。
絶縁性基体であるグリーンシート（セラミック生シート）１１に配線接続用の導通ビア４を、また、半導体素子６に対向する表層のグリーンシート１１の半導体素子搭載領域７にはダミービア５を、それぞれ周知の金型等を用いた打ち抜き加工法により各グリーンシート１１においてそれぞれ厚み方向に貫通するように同時形成する（図３（ａ）参照）。そしてこの後、配線接続用の導通ビア４に導電性ペースト３を充填し（図３（ｂ）参照）、次に、グリーンシート１１の表面に導電配線層５を被着させる（図３（ｃ）参照）。前記導電配線層５はタングステン（Ｗ）、モリブデン（Ｍｏ）、マンガン（Ｍｎ）等の高融点金属よりなり、該高融点金属粉末に適当な有機溶剤、溶媒を添加混合して得た金属ペーストをスクリーン印刷等の厚膜手法を採用することによってグリーンシート１１に印刷塗布させる。これらの複数枚のグリーンシート１１を積層することによりセラミック生積層体を得る。次に、前記生積層体を還元雰囲気中において、約１５００℃の温度で焼成させ、グリーンシート１１とこのグリーンシート１１に設けられた導電性ペースト３及び導電配線層５を一括焼成することにより配線基板（セラミック多層配線基板）１を得ることができる（図３（ｄ）参照）。このように、導電性ペースト３を充填させる導通ビア４と、後工程で封止樹脂９が充填されるダミービア５とを金型等を用いて一括形成することで、従来の製造工程と比較した場合でも製造工程が増加しないので、製造工程の複雑によるコストアップを防止できる。なお、ここでは、セラミック多層配線基板の製造方法を説明したが本発明はセラミック多層配線基板に限定するものではなく、絶縁層２が有機材料で形成された多層配線基板を使用しても問題ない。また、基板が多層でなくて、一層のものにも適用可能である。 Next, an example of the method for manufacturing a wiring board according to the present invention will be described with reference to FIGS.
A conductive via 4 for wiring connection is provided in a green sheet (ceramic raw sheet) 11 as an insulating substrate, and a dummy via 5 is provided in a semiconductor element mounting region 7 of the surface green sheet 11 opposite to the semiconductor element 6. The green sheets 11 are simultaneously formed so as to penetrate in the thickness direction by a punching method using a metal mold (see FIG. 3A). Thereafter, the conductive paste 3 is filled in the conductive via 4 for wiring connection (see FIG. 3B), and then the conductive wiring layer 5 is deposited on the surface of the green sheet 11 (FIG. 3C). )reference). The conductive wiring layer 5 is made of a refractory metal such as tungsten (W), molybdenum (Mo), manganese (Mn), and a metal paste obtained by adding and mixing an appropriate organic solvent and solvent to the refractory metal powder. The green sheet 11 is printed and applied by employing a thick film technique such as screen printing. A ceramic green laminate is obtained by laminating a plurality of these green sheets 11. Next, the green laminate is fired at a temperature of about 1500 ° C. in a reducing atmosphere, and the green sheet 11 and the conductive paste 3 and the conductive wiring layer 5 provided on the green sheet 11 are fired at once. A substrate (ceramic multilayer wiring substrate) 1 can be obtained (see FIG. 3D). In this way, the conductive via 4 filled with the conductive paste 3 and the dummy via 5 filled with the sealing resin 9 in a subsequent process are collectively formed using a mold or the like, and compared with the conventional manufacturing process. Even in this case, the number of manufacturing processes does not increase, so that an increase in cost due to complicated manufacturing processes can be prevented. Although a method for manufacturing a ceramic multilayer wiring board has been described here, the present invention is not limited to the ceramic multilayer wiring board, and there is no problem even if a multilayer wiring board in which the insulating layer 2 is formed of an organic material is used. . Further, the present invention can be applied to a single-layer substrate instead of a multilayer substrate.

図４は本発明の他の実施の形態に係る配線基板１の平面図である。図４に示すように、この配線基板１は、ダミービア８が、半導体素子６に対向する半導体素子搭載領域７の中央部分に格子状に配置されていることを特徴とする。このような構造の多層配線基板１としては、半導体素子６が５ｍｍ□以上の比較的大きな場合に有効で、このときもダミービア８のサイズは直径７５μｍ〜１５０μｍ程度の大きさが適当であり、ダミービア８の数は２行×２列以上設けることが有効である。   FIG. 4 is a plan view of a wiring board 1 according to another embodiment of the present invention. As shown in FIG. 4, the wiring substrate 1 is characterized in that the dummy vias 8 are arranged in a lattice shape at the central portion of the semiconductor element mounting region 7 facing the semiconductor element 6. The multilayer wiring board 1 having such a structure is effective when the semiconductor element 6 is relatively large of 5 mm □ or more. In this case, the size of the dummy via 8 is suitably about 75 μm to 150 μm in diameter. It is effective to provide the number of 8 by 2 rows x 2 columns or more.

以上のように本発明によれば、配線基板１における半導体素子搭載領域７にダミービア８を設けて、このダミービア８に封止樹脂９が充填されるように構成したので、ダミービア８を設けない場合に比べて、配線基板１と封止樹脂９とが広い面積でかつ凹凸を有する形状で接合されて密着性が向上する。また、ダミービア８は、半導体素子６に対向する表層のグリーンシート（表層の配線基板）１１において、導通ビア４と同様にその厚み方向に貫通するように設けられており、図１や図４に示すように、その直径や配置場所、個数なども自由に設定できるので、配線基板１と封止樹脂９との密着性を効果的にかつ任意に向上させることができて、この結果、鉛フリー半田などの高温実装の場合でも界面剥離の発生しない高品質なフリップチップ方式の半導体装置を確実に実現させることができる。しかも、導通ビア４とダミービア５とを一括形成することで、製造工程の複雑によるコストアップを防止できる。   As described above, according to the present invention, the dummy via 8 is provided in the semiconductor element mounting region 7 in the wiring board 1 and the dummy via 8 is filled with the sealing resin 9. Therefore, the dummy via 8 is not provided. In comparison with the above, the wiring substrate 1 and the sealing resin 9 are bonded in a wide area and in a shape having irregularities, so that the adhesion is improved. Further, the dummy via 8 is provided in the surface green sheet (surface wiring board) 11 facing the semiconductor element 6 so as to penetrate in the thickness direction similarly to the conductive via 4. As shown, the diameter, location, number, etc. can be freely set, so that the adhesion between the wiring board 1 and the sealing resin 9 can be effectively and arbitrarily improved. As a result, lead-free Even in the case of high-temperature mounting such as solder, a high-quality flip-chip semiconductor device that does not cause interface peeling can be reliably realized. In addition, by forming the conductive via 4 and the dummy via 5 at once, it is possible to prevent an increase in cost due to a complicated manufacturing process.

（ａ）は本実施の形態に係る配線基板の平面図、（ｂ）は同配線基板の図１（ａ）のＡ−Ａ’線部分の断面図1A is a plan view of a wiring board according to the present embodiment, and FIG. 1B is a cross-sectional view of the wiring board taken along the line A-A ′ of FIG. （ａ）および（ｂ）は同配線基板を使用した半導体装置の平面図および断面図(A) And (b) is a plan view and a cross-sectional view of a semiconductor device using the same wiring board （ａ）〜（ｄ）はそれぞれ同配線基板の製造方法の各工程を示す断面図(A)-(d) is sectional drawing which shows each process of the manufacturing method of the same wiring board, respectively. 本発明の他の実施の形態に係る配線基板の平面図The top view of the wiring board which concerns on other embodiment of this invention.

符号の説明Explanation of symbols

１ 配線基板
２ 絶縁層
３ 導電性ペースト
４ 導通ビア
５ 導電配線層
６ 半導体素子
７ 半導体素子搭載領域
８ ダミービア
９ 封止樹脂
１０ 金属突起（バンプ）
１１ グリーンシート DESCRIPTION OF SYMBOLS 1 Wiring board 2 Insulating layer 3 Conductive paste 4 Conductive via 5 Conductive wiring layer 6 Semiconductor element 7 Semiconductor element mounting area 8 Dummy via 9 Sealing resin 10 Metal protrusion (bump)
11 Green sheet

Claims (4)

突起電極を有する半導体素子がフェースダウン実装され、実装された半導体素子との間に封止樹脂が充填される配線基板であって、封止樹脂が充填されるダミービアが半導体素子に臨む領域に形成されていることを特徴とする配線基板。   A wiring board in which a semiconductor element having a protruding electrode is mounted facedown and filled with sealing resin between the mounted semiconductor element and a dummy via filled with sealing resin is formed in a region facing the semiconductor element A wiring board characterized by being made. 配線基板が多層に形成され、半導体素子に臨む層の配線基板にダミービアが形成されていることを特徴とする請求項１記載の配線基板。   2. The wiring board according to claim 1, wherein the wiring board is formed in multiple layers, and dummy vias are formed in the wiring board in a layer facing the semiconductor element. 突起電極を有する半導体素子が配線基板にフェースダウン実装され、半導体素子とこの半導体素子が実装された配線基板との間に封止樹脂が充填された半導体装置であって、配線基板における半導体素子に臨む領域にダミービアが形成され、このダミービアに封止樹脂が充填されていることを特徴とする半導体装置。   A semiconductor device in which a semiconductor element having a protruding electrode is mounted face-down on a wiring board, and a sealing resin is filled between the semiconductor element and the wiring board on which the semiconductor element is mounted. A semiconductor device characterized in that a dummy via is formed in a facing region, and the dummy via is filled with a sealing resin. 請求項１または２に記載の配線基板の製造方法であって、封止樹脂が充填されるダミービアを、導電性ペーストが充填される導通ビアと一括形成することを特徴とする配線基板の製造方法。   3. The method of manufacturing a wiring board according to claim 1, wherein dummy vias filled with a sealing resin are collectively formed with conductive vias filled with a conductive paste. .
JP2004136954A 2004-05-06 2004-05-06 Wiring board, its manufacturing method and semiconductor device Pending JP2005322659A (en)

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KR100876899B1 (en) * 2007-10-10 2009-01-07 주식회사 하이닉스반도체 Semiconductor package
JP2010502011A (en) * 2006-08-18 2010-01-21 ハイブリッド・プラスティックス・インコーポレイテッド Nanoscopic guarantee coating for lead-free solder
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Publication number Priority date Publication date Assignee Title
JP2010502011A (en) * 2006-08-18 2010-01-21 ハイブリッド・プラスティックス・インコーポレイテッド Nanoscopic guarantee coating for lead-free solder
JP2008235368A (en) * 2007-03-16 2008-10-02 Fujitsu Ltd Semiconductor device and its manufacturing process
US7872360B2 (en) 2007-03-16 2011-01-18 Fujitsu Semiconductor Limited Semiconductor device and method of manufacturing the same
JP2008244062A (en) * 2007-03-27 2008-10-09 Kojima Press Co Ltd Circuit board
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US9219021B2 (en) * 2012-07-30 2015-12-22 Panasonic Corporation Semiconductor device including heat dissipating structure
JP2016139804A (en) * 2015-01-26 2016-08-04 日立化成株式会社 Semiconductor device and manufacturing method of the same
JP2020113609A (en) * 2019-01-09 2020-07-27 新光電気工業株式会社 Multilayer substrate and multilayer substrate manufacturing method
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