JP2008091650A - Flip-chip packaging method and semiconductor package - Google Patents

Flip-chip packaging method and semiconductor package Download PDF

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JP2008091650A
JP2008091650A JP2006271340A JP2006271340A JP2008091650A JP 2008091650 A JP2008091650 A JP 2008091650A JP 2006271340 A JP2006271340 A JP 2006271340A JP 2006271340 A JP2006271340 A JP 2006271340A JP 2008091650 A JP2008091650 A JP 2008091650A
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mounting method
chip mounting
solder
circuit board
flip
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Toshio Fujii
俊夫 藤井
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a flip-chip packaging method capable of manufacturing a highly reliable semiconductor package coping with a narrower packaging pitch and a thinner semiconductor chip with high manufacturing yield. <P>SOLUTION: The flip-chip packaging method comprises the steps of alignment mounting a solder bump 2 formed on a pad of a semiconductor chip 1 to a connection pad 4 of a circuit board 6 through a resin filler 3, applying a load from above the semiconductor chip 1 (Fig. 1(b)), then heating to melt and to bond the solder bump 2 to the connection pad 4 of the circuit board 6, and dispersing a resin filler 3 into the solder (Fig. 1(c)). <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半田接合方式のフリップチップ実装方法と、そのフリップチップ実装方法を用いて製造される半導体パッケージに関する。   The present invention relates to a solder bonding type flip chip mounting method and a semiconductor package manufactured using the flip chip mounting method.

近年、携帯情報機器等の電子機器の更なる小型、薄型、軽量化が要請されており、それに伴い、電子機器に搭載する半導体パッケージの更なる高密度化、高機能化が要請されている。また、同時に、半導体チップの高性能化に伴い、半導体パッケージは多ピン化の傾向が著しく、動作周波数に関しても益々高周波数化してきている。このような要請に応えるために、半導体チップをフリップチップ実装した半導体パッケージが開発されている。   In recent years, electronic devices such as portable information devices have been required to be further reduced in size, thickness, and weight, and accordingly, semiconductor packages mounted on the electronic devices have been required to have higher density and higher functionality. At the same time, as the performance of semiconductor chips increases, semiconductor packages tend to have a higher number of pins, and the operating frequency is becoming higher and higher. In order to meet such a demand, a semiconductor package in which a semiconductor chip is flip-chip mounted has been developed.

フリップチップ実装は、半導体チップの出力電極を下向きにして回路基板の電極と電気的に接続する工法である。このフリップチップ実装方法によれば、実装面積を最小限にすることができる。さらに、半導体チップと回路基板とを最短距離で接続するため、高周波特性等の電気的特性に優れた半導体パッケージを製造できる。フリップチップ実装方法としては、現在、多種多様な方法が提案されている。それぞれ生産性やコストの点で工夫が凝らされ、大きくは接触接合型と金属接合型に分類される。   Flip chip mounting is a method of electrically connecting with an electrode of a circuit board with an output electrode of a semiconductor chip facing downward. According to this flip chip mounting method, the mounting area can be minimized. Furthermore, since the semiconductor chip and the circuit board are connected at the shortest distance, a semiconductor package having excellent electrical characteristics such as high frequency characteristics can be manufactured. Various flip-chip mounting methods are currently proposed. Each device is devised in terms of productivity and cost, and is roughly classified into contact bonding type and metal bonding type.

接触接合型は、電気的接続を接触で得るため、接続抵抗値は高くなるが、各種基板材料への適用が容易で、環境にやさしい接合方法であるという長所がある。一方、金属接合型は、主に、半田接合方式で代表され、接続抵抗値が低く、高信頼性を有するという長所がある。   The contact bonding type has an advantage that it is an environment-friendly bonding method that is easy to apply to various substrate materials, although the connection resistance value is high because electrical connection is obtained by contact. On the other hand, the metal bonding type is mainly represented by a solder bonding method, and has an advantage of having a low connection resistance value and high reliability.

半田接合方式のフリップチップ実装方法としては、Ｃ４（Ｃｏｎｔｒｏｌｌｅｄ Ｃｏｌｌａｐｓｅ Ｃｈｉｐ Ｃｏｎｎｅｃｔｉｏｎ）プロセスが代表的な方法として挙げられる。   A typical example of the solder bonding type flip chip mounting method is a C4 (Controlled Collapse Chip Connection) process.

図４は、従来の半田接合方式のフリップチップ実装方法の工程説明図である。
図４において、１は半導体チップ、２は半田バンプ、４は接続パッド、５はソルダレジスト、６は回路基板、７は封止樹脂、１０はフラックスである。 FIG. 4 is a process explanatory diagram of a conventional solder bonding type flip chip mounting method.
In FIG. 4, 1 is a semiconductor chip, 2 is a solder bump, 4 is a connection pad, 5 is a solder resist, 6 is a circuit board, 7 is a sealing resin, and 10 is a flux.

まず図４（ａ）に示すように、半導体チップ１と回路基板６を用意し、回路基板６にフラックス１０を塗布する。半導体チップ１の図示しないパッド上には半田バンプ２が形成されている。一方、回路基板６の表面には接続パッド４、ソルダレジスト５、および図示しない配線パターンが形成されている。   First, as shown in FIG. 4A, a semiconductor chip 1 and a circuit board 6 are prepared, and a flux 10 is applied to the circuit board 6. Solder bumps 2 are formed on pads (not shown) of the semiconductor chip 1. On the other hand, a connection pad 4, a solder resist 5, and a wiring pattern (not shown) are formed on the surface of the circuit board 6.

次に図４（ｂ）に示すように、半導体チップ１のパッドと回路基板６の接続パッド４を位置合わせして、半田バンプ２を接続パッド４にアライメント搭載する。次に図４（ｃ）に示すように、リフロー炉にて半導体チップ１、半田バンプ２、回路基板６等の構成部材全体を加熱し、半田バンプ２を溶融させることで半導体チップ１のパッドと回路基板６の接続パッド４とを半田を介して電気的に接続する。   Next, as shown in FIG. 4B, the pads of the semiconductor chip 1 and the connection pads 4 of the circuit board 6 are aligned, and the solder bumps 2 are aligned and mounted on the connection pads 4. Next, as shown in FIG. 4C, the entire components such as the semiconductor chip 1, the solder bumps 2, and the circuit board 6 are heated in a reflow furnace to melt the solder bumps 2. The connection pads 4 of the circuit board 6 are electrically connected via solder.

次に図４（ｄ）に示すように、フラックス洗浄を行い、フラックス１０の残渣を除去した後、図４（ｅ）に示すように、半導体チップ１と回路基板６との間に形成される空間を封止樹脂７で封止する。   Next, as shown in FIG. 4 (d), flux cleaning is performed to remove the residue of the flux 10, and thereafter, a gap is formed between the semiconductor chip 1 and the circuit board 6 as shown in FIG. 4 (e). The space is sealed with a sealing resin 7.

しかしながら、上記従来のフリップチップ実装方法では、リフロー時に構成部材全体が加熱され、高温時に半導体チップの半田バンプが溶融接合してから常温に戻る過程で、半導体チップと回路基板の熱膨張率の違いから、ひずみが生じ、半田バンプに応力が集中して、半導体チップと回路基板間の接続部、あるいは半導体チップの回路素子や層間絶縁膜等へダメージを与え、半導体パッケージの信頼性を低下させるという問題があった。   However, in the above conventional flip chip mounting method, the entire component is heated at the time of reflow, the difference in thermal expansion coefficient between the semiconductor chip and the circuit board in the process of returning to room temperature after the solder bumps of the semiconductor chip are melt bonded at high temperature Therefore, distortion occurs, stress concentrates on the solder bump, damages the connection part between the semiconductor chip and the circuit board, or the circuit element of the semiconductor chip, the interlayer insulating film, etc., and reduces the reliability of the semiconductor package. There was a problem.

また、半田バンプのリフローによる溶融接合に際して、フラックスが酸化膜除去等の作用により接合に寄与する一方で、そのフラックスの残渣をフラックス洗浄で全て除去できず、その残渣が、その後の樹脂封止の工程において封止樹脂の流動性を阻害したり、回路基板のパターン間、半導体チップのバンプ間の絶縁信頼性を低下させ、半導体パッケージの信頼性を低下させるという問題があった。この問題は、特に実装ピッチの狭小化が進むにつれて顕著に現れる。   Also, during the melt bonding by reflow of solder bumps, the flux contributes to the bonding by the action of oxide film removal, etc., but the residue of the flux cannot be removed entirely by the flux cleaning, and the residue is not used for the subsequent resin sealing. In the process, there is a problem that the fluidity of the sealing resin is hindered, the insulation reliability between circuit board patterns and between semiconductor chip bumps is lowered, and the reliability of the semiconductor package is lowered. This problem is particularly noticeable as the mounting pitch becomes narrower.

さらに、近年、実装ピッチの狭小化および半導体チップの薄型化が要請されているが、従来のフリップチップ実装方法では、実装ピッチの狭小化および半導体チップの薄型化が進むと、半田バンプの高さばらつきや、実装時の半導体チップおよび回路基板の平坦性（コプラナリティ）の変動の影響を回避することができず、そのため接続が安定せず、実装歩留まりが低下するという問題があった。   Furthermore, in recent years, there has been a demand for narrowing the mounting pitch and reducing the thickness of the semiconductor chip. However, in the conventional flip chip mounting method, as the mounting pitch becomes narrower and the semiconductor chip becomes thinner, the height of the solder bumps increases. There is a problem that the influence of variations and fluctuations in the flatness (coplanarity) of the semiconductor chip and the circuit board during mounting cannot be avoided, so that the connection is not stable and the mounting yield is lowered.

これらに対しては、バンプ表面に金属層を散在させるように形成しておき、半導体チップを回路基板上に搭載して半導体チップを上方から押圧することで、バンプ表面の酸化膜を金属層で破壊する方法が開示されている（例えば、特許文献１参照。）。この方法によれば、フラックスを使用せずに接合を実現することができる。さらには、半導体チップを上方から押圧するので、半田バンプを押しつぶしてそのばらつきを無くすとともに、半導体チップおよび回路基板を平坦な状態に戻すことができる。しかしながら、この方法では、バンプ表面に金属層を形成しなければならず、蒸着等のプロセスにより形成することから、高コストになるという問題があった。
特開平９−１６７７７３号公報 For these, metal layers are scattered on the bump surface, the semiconductor chip is mounted on the circuit board, and the semiconductor chip is pressed from above, so that the oxide film on the bump surface is made of the metal layer. A method of destruction is disclosed (for example, refer to Patent Document 1). According to this method, joining can be realized without using a flux. Furthermore, since the semiconductor chip is pressed from above, the solder bumps can be crushed to eliminate the variation, and the semiconductor chip and the circuit board can be returned to a flat state. However, this method has a problem that the metal layer must be formed on the bump surface and is formed by a process such as vapor deposition, resulting in high cost.
JP-A-9-167773

本発明は、上記問題点に鑑み、半導体チップのパッド上に形成された半田バンプを樹脂フィラーを介して回路基板の接続パッドにアライメント搭載し、半導体チップのパッドが形成されている面とは反対側の面から荷重を負荷した後、加熱を行い半田バンプを溶融して回路基板の接続パッドに接合するとともに半田中に樹脂フィラーを分散させることにより、狭実装ピッチ、薄型半導体チップに対応した高信頼性を有する半導体パッケージを高歩留りで製造することが可能となるフリップチップ実装方法、およびフリップチップ実装方法を用いて製造される半導体パッケージを提供することを目的とする。   In view of the above problems, the present invention is such that a solder bump formed on a pad of a semiconductor chip is aligned and mounted on a connection pad of a circuit board through a resin filler, and is opposite to the surface on which the pad of the semiconductor chip is formed. After applying a load from the side surface, heating is performed to melt the solder bumps and bond them to the connection pads of the circuit board and disperse the resin filler in the solder. It is an object of the present invention to provide a flip chip mounting method capable of manufacturing a semiconductor package having reliability with high yield, and a semiconductor package manufactured using the flip chip mounting method.

本発明の請求項１記載のフリップチップ実装方法は、半導体チップのパッド上に形成された半田バンプを回路基板の接続パッドに溶融接合するフリップチップ実装方法であって、前記半田バンプを樹脂フィラーを介して前記回路基板の前記接続パッドにアライメント搭載し、前記半導体チップの前記パッドが形成されている面とは反対側の面から荷重を負荷する荷重負荷工程と、加熱を行い前記半田バンプを溶融して前記回路基板の前記接続パッドに接合するとともに、半田中に前記樹脂フィラーを分散させる接合工程と、前記半導体チップと前記回路基板との間に形成される空間に樹脂を封止する封止工程と、を備えることを特徴とする。   The flip chip mounting method according to claim 1 of the present invention is a flip chip mounting method in which a solder bump formed on a pad of a semiconductor chip is melt-bonded to a connection pad of a circuit board, and the solder bump is bonded with a resin filler. Through which the load is loaded from the surface of the semiconductor chip opposite to the surface on which the pad is formed, and the solder bumps are melted by heating. Bonding to the connection pads of the circuit board and dispersing the resin filler in the solder, and sealing to seal the resin in a space formed between the semiconductor chip and the circuit board And a process.

また、本発明の請求項２記載のフリップチップ実装方法は、請求項１記載のフリップチップ実装方法であって、前記荷重負荷工程よりも前に、前記半田バンプに前記樹脂フィラーを付着させる工程を備えたことを特徴とする。   Moreover, the flip chip mounting method according to claim 2 of the present invention is the flip chip mounting method according to claim 1, wherein the step of attaching the resin filler to the solder bumps prior to the load loading step. It is characterized by having.

また、本発明の請求項３記載のフリップチップ実装方法は、請求項１記載のフリップチップ実装方法であって、前記荷重負荷工程よりも前に、前記回路基板の前記接続パッドに前記樹脂フィラーを付着させる工程を備えたことを特徴とする。   Moreover, the flip-chip mounting method according to claim 3 of the present invention is the flip-chip mounting method according to claim 1, wherein the resin filler is applied to the connection pads of the circuit board before the load loading step. It is characterized by comprising a step of attaching.

また、本発明の請求項４記載のフリップチップ実装方法は、請求項１記載のフリップチップ実装方法であって、前記荷重負荷工程よりも前に、前記半田バンプの先端形状を平坦化させる工程を備えたことを特徴とする。   The flip chip mounting method according to claim 4 of the present invention is the flip chip mounting method according to claim 1, wherein the step of flattening the tip shape of the solder bump is performed before the load loading step. It is characterized by having.

また、本発明の請求項５記載のフリップチップ実装方法は、請求項２記載のフリップチップ実装方法であって、前記半田バンプに前記樹脂フィラーを付着させる工程よりも前に、前記半田バンプの先端形状を平坦化させる工程を備えたことを特徴とする。   The flip chip mounting method according to claim 5 of the present invention is the flip chip mounting method according to claim 2, wherein the tip of the solder bump is placed before the step of attaching the resin filler to the solder bump. A step of flattening the shape is provided.

また、本発明の請求項６記載のフリップチップ実装方法は、請求項３記載のフリップチップ実装方法であって、前記荷重負荷工程よりも前に、前記半田バンプの先端形状を平坦化させる工程を備えたことを特徴とする。   The flip chip mounting method according to claim 6 of the present invention is the flip chip mounting method according to claim 3, wherein the step of flattening the tip shape of the solder bump is performed before the load loading step. It is characterized by having.

また、本発明の請求項７記載のフリップチップ実装方法は、請求項１記載のフリップチップ実装方法であって、前記荷重負荷工程よりも前に、前記半田バンプの先端形状を平坦化させると同時に、あるいは平坦化後に、その平坦化された面に凹凸を形成する工程を備えたことを特徴とする。   The flip chip mounting method according to claim 7 of the present invention is the flip chip mounting method according to claim 1, wherein the tip shape of the solder bump is flattened before the load loading step. Alternatively, a step of forming irregularities on the planarized surface after the planarization is provided.

また、本発明の請求項８記載のフリップチップ実装方法は、請求項２記載のフリップチップ実装方法であって、前記半田バンプに前記樹脂フィラーを付着させる工程よりも前に、前記半田バンプの先端形状を平坦化させると同時に、あるいは平坦化後に、その平坦化された面に凹凸を形成する工程を備えたことを特徴とする。   The flip chip mounting method according to claim 8 of the present invention is the flip chip mounting method according to claim 2, wherein the tip of the solder bump is placed before the step of attaching the resin filler to the solder bump. At the same time as or after the flattening of the shape, there is provided a step of forming irregularities on the flattened surface.

また、本発明の請求項９記載のフリップチップ実装方法は、請求項３記載のフリップチップ実装方法であって、前記荷重負荷工程よりも前に、前記半田バンプの先端形状を平坦化させると同時に、あるいは平坦化後に、その平坦化された面に凹凸を形成する工程を備えたことを特徴とする。   The flip-chip mounting method according to claim 9 of the present invention is the flip-chip mounting method according to claim 3, wherein the tip shape of the solder bump is flattened before the load loading step. Alternatively, a step of forming irregularities on the planarized surface after the planarization is provided.

また、本発明の請求項１０記載の半導体パッケージは、半導体チップのパッドと回路基板の接続パッドが半田を介して電気的に接続されている半導体パッケージであって、接続部の半田中に樹脂フィラーが分散していることを特徴とする。   The semiconductor package according to claim 10 of the present invention is a semiconductor package in which the pads of the semiconductor chip and the connection pads of the circuit board are electrically connected via solder, and the resin filler is contained in the solder of the connection portion. Are dispersed.

本発明によれば、狭実装ピッチ、薄型半導体チップに対応した高信頼性を有する半導体パッケージを高歩留りで製造することが可能となる。   According to the present invention, it is possible to manufacture a highly reliable semiconductor package corresponding to a narrow mounting pitch and a thin semiconductor chip with a high yield.

（実施の形態１）
以下、本発明の実施の形態１について図面とともに詳細に説明する。
図１は、本発明の実施の形態１におけるフリップチップ実装方法の工程説明図である。図１において、１は半導体チップ、２は半田バンプ、３は樹脂フィラー、４は接続パッド、５はソルダレジスト、６は回路基板、７は封止樹脂、８はボンディングツールである。 (Embodiment 1)
Embodiment 1 of the present invention will be described below in detail with reference to the drawings.
FIG. 1 is a process explanatory diagram of a flip chip mounting method according to Embodiment 1 of the present invention. In FIG. 1, 1 is a semiconductor chip, 2 is a solder bump, 3 is a resin filler, 4 is a connection pad, 5 is a solder resist, 6 is a circuit board, 7 is a sealing resin, and 8 is a bonding tool.

まず図１（ａ）に示すように、半導体チップ１と回路基板６を用意し、半導体チップ１の図示しないパッド上に形成されている半田バンプ２に樹脂フィラー３を付着させる。回路基板６は例えばガラス織布エポキシ樹脂製配線基板であり、その表面には接続パッド４、ソルダレジスト５、および図示しない配線パターンが形成されている。このように半田バンプ２に樹脂フィラー３を付着させることで、必要な部分にのみ、無駄なく、効率よく、樹脂フィラーを付着させることができる。   First, as shown in FIG. 1A, a semiconductor chip 1 and a circuit board 6 are prepared, and a resin filler 3 is attached to solder bumps 2 formed on pads (not shown) of the semiconductor chip 1. The circuit board 6 is, for example, a wiring board made of a glass woven epoxy resin, and has a connection pad 4, a solder resist 5, and a wiring pattern (not shown) formed on the surface thereof. By attaching the resin filler 3 to the solder bumps 2 in this way, the resin filler can be efficiently attached to only necessary portions without waste.

ここで、樹脂フィラーを半導体チップのパッド上に形成された半田バンプに付着させる方法は、特に限定されるものではないが、例えば、樹脂フィラーと溶剤とを少なくとも含むペーストを製膜し、形成された膜上に半田バンプを押し付けて樹脂フィラーを付着させる転写法を用いることができる。図１（ａ）では、樹脂フィラー３と溶剤とを少なくとも含むペースト膜が半田バンプ２上に付着している様子を表している。   Here, the method of attaching the resin filler to the solder bump formed on the pad of the semiconductor chip is not particularly limited. For example, the resin filler is formed by forming a paste containing at least a resin filler and a solvent. It is possible to use a transfer method in which a solder bump is pressed onto the coated film to attach a resin filler. FIG. 1A shows a state in which a paste film containing at least a resin filler 3 and a solvent is attached on the solder bump 2.

次に図１（ｂ）に示すように、半導体チップ１のパッドと回路基板６の接続パッド４を位置合わせして、半田バンプ２を樹脂フィラー３を介して回路基板６の接続パッド４にアライメント搭載するとともに、ボンディングツール８により半導体チップ１のパッド形成面とは反対側の面から荷重を負荷して、樹脂フィラー３を変形させる（荷重負荷工程）。   Next, as shown in FIG. 1B, the pads of the semiconductor chip 1 and the connection pads 4 of the circuit board 6 are aligned, and the solder bumps 2 are aligned with the connection pads 4 of the circuit board 6 through the resin filler 3. While being mounted, a load is applied from the surface opposite to the pad forming surface of the semiconductor chip 1 by the bonding tool 8 to deform the resin filler 3 (load loading step).

ここで、荷重は、半田バンプ２の高さばらつきや、実装時の半導体チップ１および回路基板６の平坦性（コプラナリティ）の変動の影響を回避するために、ある一定値以上負荷する必要があるが、少なくとも半導体チップ１及び半田バンプ２にダメージが加わらない程度には制限する。   Here, in order to avoid the influence of variations in the height of the solder bumps 2 and variations in the flatness (coplanarity) of the semiconductor chip 1 and the circuit board 6 during mounting, it is necessary to apply a load of a certain value or more. However, it is limited to the extent that the semiconductor chip 1 and the solder bump 2 are not damaged.

続いて、一定荷重値に到達したら、ボンディングツール８による加熱を行い、図１（ｃ）に示すように、半田バンプ２を溶融して接続パッド４に接合させることで、半導体チップ１のパッドと回路基板６の接続パッド４とを半田を介して電気的に接続する（接合工程）。この半田バンプ２の溶融時に、樹脂フィラー３が上記荷重による変形の反発として移動することにより半田バンプ２表面の酸化膜が破壊され接合される。このとき、半田バンプ中に絶縁性を有する樹脂フィラー３が分散する。   Subsequently, when a certain load value is reached, heating by the bonding tool 8 is performed, and the solder bumps 2 are melted and bonded to the connection pads 4 as shown in FIG. The connection pads 4 of the circuit board 6 are electrically connected via solder (bonding process). When the solder bump 2 is melted, the resin filler 3 moves as a repulsion of deformation due to the load, whereby the oxide film on the surface of the solder bump 2 is broken and bonded. At this time, the resin filler 3 having insulating properties is dispersed in the solder bumps.

次に図１（ｄ）に示すように、半導体チップ１と回路基板６との間に形成される空間を封止樹脂７で封止する（封止工程）。以上の工程により、図１（ｄ）に示す、半導体チップ１のパッドと回路基板６の接続パッド４とが半田を介して電気的に接続された半導体パッケージを製造することができる。なお、半導体パッケージの構造としては、これに限らず、本発明は、例えばチップが積層された構造の半導体パッケージや、パッケージが積層された構造の半導体パッケージや、モールド樹脂がチップを覆う構造の半導体パッケージなどにも適用できる。   Next, as shown in FIG. 1D, the space formed between the semiconductor chip 1 and the circuit board 6 is sealed with a sealing resin 7 (sealing step). Through the above steps, a semiconductor package in which the pads of the semiconductor chip 1 and the connection pads 4 of the circuit board 6 shown in FIG. 1D are electrically connected via solder can be manufactured. The structure of the semiconductor package is not limited to this. For example, the present invention is a semiconductor package having a structure in which chips are stacked, a semiconductor package having a structure in which packages are stacked, or a semiconductor having a structure in which a mold resin covers a chip. It can also be applied to packages.

本実施の形態１におけるフリップチップ実装方法によれば、樹脂フィラー３を介した状態で半田バンプ１を回路基板６の接続パッド４にアライメント搭載するとともに荷重を負荷することで、半田バンプ２の高さばらつきや、実装時の半導体チップ１および回路基板６の平坦性（コプラナリティ）の変動の影響を回避でき、実装歩留まりが向上する。すなわち、半導体チップ１の裏面側（上方）から荷重を負荷するので、半田バンプ２を押しつぶしてそのばらつきを無くすとともに、半導体チップ１および回路基板６を平坦な状態に戻すことができる。   According to the flip chip mounting method in the first embodiment, the solder bumps 1 are aligned and mounted on the connection pads 4 of the circuit board 6 with the resin filler 3 interposed therebetween, and the load of the solder bumps 2 is increased by applying a load. It is possible to avoid the influence of variations in the size and fluctuations in the flatness (coplanarity) of the semiconductor chip 1 and the circuit board 6 during mounting, and the mounting yield is improved. That is, since a load is applied from the back side (upper side) of the semiconductor chip 1, the solder bumps 2 can be crushed to eliminate variations thereof, and the semiconductor chip 1 and the circuit board 6 can be returned to a flat state.

さらに、フィラーが樹脂であるので、荷重による変形の反発として半田バンプの溶融時に樹脂フィラーが移動することにより半田バンプ表面の酸化膜を破壊することができ、より低荷重（低ストレス）で、効率よく酸化膜を破壊でき、フラックスレスでの接続を実現することができる。   In addition, since the filler is resin, the oxide film on the solder bump surface can be destroyed by moving the resin filler when the solder bump melts as a repulsion of the load due to the load. The oxide film can be destroyed well and a fluxless connection can be realized.

また、半田バンプの溶融接合時に半田バンプ中に樹脂フィラーが分散するので、半田バンプの溶融接合時の加熱冷却過程で、半導体チップと回路基板の熱膨張率の違いから、ひずみが生じ、半田バンプに応力が集中しても、その応力は半田バンプ内に分散された樹脂フィラー部で緩和されるので、半導体チップと回路基板間の接続部、あるいは半導体チップの回路素子や層間絶縁膜等へのダメージを減少させることができ、高信頼性を有する半導体パッケージを製造することができる。   In addition, since the resin filler is dispersed in the solder bumps when the solder bumps are melt bonded, distortion occurs due to the difference in the thermal expansion coefficient between the semiconductor chip and the circuit board during the heating and cooling process during the solder bump melting bonding. Even if stress concentrates on the surface, the stress is relieved by the resin filler part dispersed in the solder bump, so that the connection between the semiconductor chip and the circuit board, or the circuit element of the semiconductor chip, the interlayer insulating film, etc. Damage can be reduced and a highly reliable semiconductor package can be manufactured.

また、封止樹脂７により、半導体チップ１と回路基板６との熱膨張率の違いにより半導体チップ１と回路基板６との間で応力が生じたとしても、半田バンプ２のみに応力が集中することが防止され、実装信頼性を向上させることができる。   Even if stress is generated between the semiconductor chip 1 and the circuit board 6 due to the difference in thermal expansion coefficient between the semiconductor chip 1 and the circuit board 6 due to the sealing resin 7, the stress is concentrated only on the solder bump 2. Can be prevented and the mounting reliability can be improved.

以上のように、本実施の形態１におけるフリップチップ実装方法によれば、狭実装ピッチ、薄型半導体チップに対応した半導体パッケージを、低ストレス、高歩留まりで製造できる。   As described above, according to the flip chip mounting method in the first embodiment, a semiconductor package corresponding to a narrow mounting pitch and a thin semiconductor chip can be manufactured with low stress and high yield.

（実施の形態２）
以下、本発明の実施の形態２について図面とともに詳細に説明する。
図２は、本発明の実施の形態２におけるフリップチップ実装方法の工程説明図である。但し、前述の実施の形態１で説明した部材と同一の部材については同一符号を付してその説明を省略する。 (Embodiment 2)
Hereinafter, Embodiment 2 of the present invention will be described in detail with reference to the drawings.
FIG. 2 is a process explanatory diagram of the flip chip mounting method according to the second embodiment of the present invention. However, the same members as those described in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

本実施の形態２では、半田バンプに樹脂フィラーを付着させるのではなく、図２（ａ）に示すように回路基板６の接続パッド４に樹脂フィラー３を付着させる点が前述の実施の形態１と異なる（図１（ａ）を参照。）。   In the second embodiment, the resin filler 3 is not attached to the solder bumps, but the resin filler 3 is attached to the connection pads 4 of the circuit board 6 as shown in FIG. 2A. (Refer to FIG. 1A).

ここで、樹脂フィラーを回路基板の接続パッドに付着させる方法は、特に限定されるものではないが、例えば、樹脂フィラーと溶剤とを少なくとも含むペーストを作製し、スクリーン印刷法、ステンシル印刷法で所定の接続パッド上に付着させることができる。図２（ａ）では、樹脂フィラー３と溶剤とを少なくとも含むペースト膜が回路基板上に付着している様子を表している。   Here, the method of attaching the resin filler to the connection pad of the circuit board is not particularly limited. For example, a paste containing at least the resin filler and the solvent is prepared, and predetermined by screen printing method or stencil printing method. Can be deposited on the connection pads. FIG. 2A shows a state in which a paste film including at least the resin filler 3 and the solvent is attached on the circuit board.

図２（ｂ）〜図２（ｄ）に示す工程は、図１（ｂ）〜図１（ｄ）を用いて説明した工程と同じであるので、説明を省略する。以上の工程により、図２（ｄ）に示す実施の形態１と同様の半導体パッケージを製造することができる。   The steps shown in FIGS. 2B to 2D are the same as the steps described with reference to FIGS. 1B to 1D, and thus the description thereof is omitted. Through the above steps, a semiconductor package similar to that of the first embodiment shown in FIG. 2D can be manufactured.

本実施の形態２におけるフリップチップ実装方法によれば、樹脂フィラー３を付着させる動作を、半田バンプ２と回路基板６の接続パッド４とを接合させる動作と分離できるので、実装タクトの短縮が可能となり、より高い生産性を実現できる。   According to the flip chip mounting method in the second embodiment, the operation of attaching the resin filler 3 can be separated from the operation of bonding the solder bump 2 and the connection pad 4 of the circuit board 6, so that the mounting tact can be shortened. And higher productivity can be realized.

（実施の形態３）
以下、本発明の実施の形態３について図面とともに詳細に説明する。
図３は、本発明の実施の形態３におけるフリップチップ実装方法の工程説明図である。但し、前述の実施の形態１で説明した部材と同一の部材については同一符号を付してその説明を省略する。図３において、９はレベリングステージである。 (Embodiment 3)
Hereinafter, Embodiment 3 of the present invention will be described in detail with reference to the drawings.
FIG. 3 is a process explanatory diagram of the flip chip mounting method according to the third embodiment of the present invention. However, the same members as those described in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. In FIG. 3, 9 is a leveling stage.

本実施の形態３では、半田バンプ２に樹脂フィラー３を付着させる工程よりも前に、図３（ａ）に示すように半田バンプ２の先端形状を平坦化させる工程を含む点が前述の実施の形態１と異なる。   In the third embodiment, before the step of attaching the resin filler 3 to the solder bump 2, the above-described implementation includes the step of flattening the tip shape of the solder bump 2 as shown in FIG. This is different from Form 1.

ここで、半田バンプの先端形状を平坦化させる方法は、特に限定されるものではないが、例えば図３（ａ）に示すように、常温もしくは一定温度に設定したレベリングステージ９上に半導体チップ１の半田バンプ２を一定荷重で押し付けることで実現できる。あるいは、金属接合しない、例えばセラミック基板上に、従来の半田接合方式と同様に半導体チップ１を実装し、半田バンプ２の融点以下で半導体チップを取り出すことでも実現できる。また、図示しないが、半田バンプ２の先端形状を平坦化させると同時に、平坦化された面に凹凸を形成することが望ましい。なお、半田バンプ２の先端形状を平坦化させた後に、平坦化された面に凹凸を形成してもよい。   Here, the method for flattening the tip shape of the solder bump is not particularly limited. For example, as shown in FIG. 3A, the semiconductor chip 1 is placed on a leveling stage 9 set to a normal temperature or a constant temperature. This can be realized by pressing the solder bump 2 with a constant load. Alternatively, it can be realized by mounting the semiconductor chip 1 on a ceramic substrate that is not metal-bonded, for example, similarly to the conventional solder bonding method, and taking out the semiconductor chip below the melting point of the solder bump 2. Further, although not shown, it is desirable to flatten the tip shape of the solder bump 2 and at the same time form irregularities on the flattened surface. Note that, after the tip shape of the solder bump 2 is flattened, irregularities may be formed on the flattened surface.

図３（ｂ）〜図３（ｅ）に示す工程は、図１（ａ）〜図１（ｄ）を用いて説明した工程と同じであるので、説明を省略する。以上の工程により、図３（ｅ）に示す実施の形態１と同様の半導体パッケージを製造することができる。   The process shown in FIGS. 3B to 3E is the same as the process described with reference to FIGS. Through the above steps, a semiconductor package similar to that of the first embodiment shown in FIG. 3E can be manufactured.

なお、ここでは先端形状が平坦化された半田バンプに樹脂フィラーを付着させる場合を例に説明したが、前述の実施の形態２と同様に、樹脂フィラーを回路基板の接続パッドに付着させてもよい。この場合、荷重負荷工程（図２（ｂ））よりも前に半田バンプの先端形状を平坦化しておけばよい。   Here, the case where the resin filler is attached to the solder bump whose tip shape is flattened has been described as an example. However, as in the second embodiment, the resin filler may be attached to the connection pad of the circuit board. Good. In this case, the tip shape of the solder bump may be flattened before the load application step (FIG. 2B).

本実施の形態３におけるフリップチップ実装方法によれば、半田バンプ２の平坦化された面に対して垂直方向に樹脂フィラー３を押し付けることになるので、樹脂フィラー３による酸化膜破壊を効率よく行うことが可能になる。よって、酸化膜除去を効率よく行うことができるので、余分な荷重を負荷することなく、より低ストレスで半導体チップを実装することができ、実装歩留まりの向上を実現することができる。また、半田バンプ２の平坦化された面に凹凸を形成することで、前述した実施の形態１のように半田バンプ２へ樹脂フィラー３を付着させる時に（図１（ａ）参照。）、効率よく樹脂フィラー３を付着させることが可能になる。   According to the flip chip mounting method in the third embodiment, the resin filler 3 is pressed in the vertical direction against the flattened surface of the solder bump 2, so that the oxide film is efficiently destroyed by the resin filler 3. It becomes possible. Therefore, since the oxide film can be removed efficiently, the semiconductor chip can be mounted with lower stress without applying an extra load, and the mounting yield can be improved. Further, by forming irregularities on the flattened surface of the solder bump 2, when the resin filler 3 is attached to the solder bump 2 as in the first embodiment (see FIG. 1A), the efficiency is increased. It becomes possible to adhere the resin filler 3 well.

また、本実施の形態１ないし３におけるフリップチップ実装方法により製造した半導体パッケージは、図１（ｄ）、図２（ｄ）、図３（ｅ）に示すように、接続部の半田中に絶縁性を有する樹脂フィラー部が分散している構成となる。この構成により、荷重負荷時に接続部に加わる応力が半田バンプ２内に分散された樹脂フィラー部で緩和されるので、結果、接続部周辺の半導体チップ等へのストレスを緩和することができる。   In addition, the semiconductor package manufactured by the flip chip mounting method according to the first to third embodiments is insulated in the solder of the connection portion as shown in FIGS. 1 (d), 2 (d), and 3 (e). The resin filler part having the property is dispersed. With this configuration, the stress applied to the connection portion when a load is applied is relieved by the resin filler portion dispersed in the solder bumps 2. As a result, the stress on the semiconductor chip and the like around the connection portion can be relieved.

本発明にかかるフリップチップ実装方法、および半導体パッケージは、狭実装ピッチ、薄型半導体チップに対応した高信頼性を有する半導体パッケージを高歩留りで実現でき、電子機器の更なる小型、軽量、薄型化のために有用である。   The flip chip mounting method and the semiconductor package according to the present invention can realize a highly reliable semiconductor package corresponding to a narrow mounting pitch and a thin semiconductor chip with a high yield, and further reduce the size, weight, and thickness of electronic devices. Useful for.

本発明の実施の形態１におけるフリップチップ実装方法の工程説明図Process explanatory drawing of the flip chip mounting method in Embodiment 1 of this invention 本発明の実施の形態２におけるフリップチップ実装方法の工程説明図Process explanatory drawing of the flip chip mounting method in Embodiment 2 of this invention 本発明の実施の形態３におけるフリップチップ実装方法の工程説明図Process explanatory drawing of the flip-chip mounting method in Embodiment 3 of this invention 従来の半田接合方式のフリップチップ実装方法の工程説明図Process explanatory diagram of conventional solder bonding type flip chip mounting method

符号の説明Explanation of symbols

１ 半導体チップ
２ 半田バンプ
３ 樹脂フィラー
４ 接続パッド
５ ソルダレジスト
６ 回路基板
７ 封止樹脂
８ ボンディングツール
９ レベリングステージ
１０ フラックス DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Solder bump 3 Resin filler 4 Connection pad 5 Solder resist 6 Circuit board 7 Sealing resin 8 Bonding tool 9 Leveling stage 10 Flux

Claims (10)

半導体チップのパッド上に形成された半田バンプを回路基板の接続パッドに溶融接合するフリップチップ実装方法であって、
前記半田バンプを樹脂フィラーを介して前記回路基板の前記接続パッドにアライメント搭載し、前記半導体チップの前記パッドが形成されている面とは反対側の面から荷重を負荷する荷重負荷工程と、
加熱を行い前記半田バンプを溶融して前記回路基板の前記接続パッドに接合するとともに、半田中に前記樹脂フィラーを分散させる接合工程と、
前記半導体チップと前記回路基板との間に形成される空間に樹脂を封止する封止工程と、
を備えることを特徴とするフリップチップ実装方法。 A flip chip mounting method in which a solder bump formed on a pad of a semiconductor chip is melt bonded to a connection pad of a circuit board,
The solder bump is aligned and mounted on the connection pad of the circuit board through a resin filler, and a load loading step of applying a load from a surface opposite to the surface on which the pad of the semiconductor chip is formed,
Joining the connection pads of the circuit board by heating and melting the solder bumps, and dispersing the resin filler in the solder; and
A sealing step of sealing a resin in a space formed between the semiconductor chip and the circuit board;
A flip-chip mounting method comprising: 請求項１記載のフリップチップ実装方法であって、前記荷重負荷工程よりも前に、前記半田バンプに前記樹脂フィラーを付着させる工程を備えたことを特徴とするフリップチップ実装方法。   2. The flip chip mounting method according to claim 1, further comprising a step of attaching the resin filler to the solder bumps prior to the load application step. 請求項１記載のフリップチップ実装方法であって、前記荷重負荷工程よりも前に、前記回路基板の前記接続パッドに前記樹脂フィラーを付着させる工程を備えたことを特徴とするフリップチップ実装方法。   2. The flip chip mounting method according to claim 1, further comprising a step of attaching the resin filler to the connection pads of the circuit board prior to the load application step. 請求項１記載のフリップチップ実装方法であって、前記荷重負荷工程よりも前に、前記半田バンプの先端形状を平坦化させる工程を備えたことを特徴とするフリップチップ実装方法。   2. The flip chip mounting method according to claim 1, further comprising a step of flattening a tip shape of the solder bump prior to the load applying step. 請求項２記載のフリップチップ実装方法であって、前記半田バンプに前記樹脂フィラーを付着させる工程よりも前に、前記半田バンプの先端形状を平坦化させる工程を備えたことを特徴とするフリップチップ実装方法。   3. The flip chip mounting method according to claim 2, further comprising a step of flattening a tip shape of the solder bump before the step of attaching the resin filler to the solder bump. Implementation method. 請求項３記載のフリップチップ実装方法であって、前記荷重負荷工程よりも前に、前記半田バンプの先端形状を平坦化させる工程を備えたことを特徴とするフリップチップ実装方法。   4. The flip chip mounting method according to claim 3, further comprising a step of flattening a tip shape of the solder bump prior to the load applying step. 請求項１記載のフリップチップ実装方法であって、前記荷重負荷工程よりも前に、前記半田バンプの先端形状を平坦化させると同時に、あるいは平坦化後に、その平坦化された面に凹凸を形成する工程を備えたことを特徴とするフリップチップ実装方法。   2. The flip chip mounting method according to claim 1, wherein an unevenness is formed on the flattened surface simultaneously with or after flattening a tip shape of the solder bump before the load applying step. A flip-chip mounting method comprising the step of: 請求項２記載のフリップチップ実装方法であって、前記半田バンプに前記樹脂フィラーを付着させる工程よりも前に、前記半田バンプの先端形状を平坦化させると同時に、あるいは平坦化後に、その平坦化された面に凹凸を形成する工程を備えたことを特徴とするフリップチップ実装方法。   3. The flip chip mounting method according to claim 2, wherein the front end shape of the solder bump is flattened before or after the step of attaching the resin filler to the solder bump. A flip-chip mounting method comprising a step of forming irregularities on a processed surface. 請求項３記載のフリップチップ実装方法であって、前記荷重負荷工程よりも前に、前記半田バンプの先端形状を平坦化させると同時に、あるいは平坦化後に、その平坦化された面に凹凸を形成する工程を備えたことを特徴とするフリップチップ実装方法。   4. The flip chip mounting method according to claim 3, wherein the solder bumps are formed with irregularities on the flattened surface at the same time as or after flattening the tip shape of the solder bump before the load application step. A flip-chip mounting method comprising the step of: 半導体チップのパッドと回路基板の接続パッドが半田を介して電気的に接続されている半導体パッケージであって、接続部の半田中に樹脂フィラーが分散していることを特徴とする半導体パッケージ。   A semiconductor package, wherein a pad of a semiconductor chip and a connection pad of a circuit board are electrically connected via solder, and a resin filler is dispersed in the solder of the connection portion.
JP2006271340A 2006-10-03 2006-10-03 Flip-chip packaging method and semiconductor package Pending JP2008091650A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8154123B2 (en) 2009-02-20 2012-04-10 Panasonic Corporation Solder bump, semiconductor chip, method of manufacturing the semiconductor chip, conductive connection structure, and method of manufacturing the conductive connection structure
JP2016082001A (en) * 2014-10-14 2016-05-16 住友ベークライト株式会社 Method for manufacturing semiconductor device and method for manufacturing electronic parts

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8154123B2 (en) 2009-02-20 2012-04-10 Panasonic Corporation Solder bump, semiconductor chip, method of manufacturing the semiconductor chip, conductive connection structure, and method of manufacturing the conductive connection structure
JP2016082001A (en) * 2014-10-14 2016-05-16 住友ベークライト株式会社 Method for manufacturing semiconductor device and method for manufacturing electronic parts

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