JP2907188B2 - Semiconductor device, method of mounting semiconductor device, and method of manufacturing semiconductor device - Google Patents
Semiconductor device, method of mounting semiconductor device, and method of manufacturing semiconductor deviceInfo
- Publication number
- JP2907188B2 JP2907188B2 JP9142113A JP14211397A JP2907188B2 JP 2907188 B2 JP2907188 B2 JP 2907188B2 JP 9142113 A JP9142113 A JP 9142113A JP 14211397 A JP14211397 A JP 14211397A JP 2907188 B2 JP2907188 B2 JP 2907188B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- mounting
- bump
- barrier
- bumps
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
- H01L2224/10145—Flow barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
- H01L2224/1148—Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
- H01L2224/11849—Reflowing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/731—Location prior to the connecting process
- H01L2224/73101—Location prior to the connecting process on the same surface
- H01L2224/73103—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【発明の属する技術分野】本発明は、フリップチップや
ＢＧＡ等の、バンプを用いて実装基板に実装する半導体
装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a flip chip or a BGA mounted on a mounting substrate using bumps.
【０００２】[0002]
【従来の技術】近年、電子機器の小型化やＩＣの多ピン
化に伴い、半導体パッケージの形態も従来のＱＦＰ（Qu
ad Flat Package）等から、ＢＧＡ（Ball Grid Arra
y）、ＬＧＡ（Land Grid Array）等のエリアアレイの入
出力端子を持つ半導体装置が主流になりつつある。2. Description of the Related Art In recent years, with the miniaturization of electronic devices and the increase in the number of pins of ICs, the form of semiconductor packages has also been changed to that of conventional QFPs (Quad
ad Flat Package), BGA (Ball Grid Arra)
y), a semiconductor device having an input / output terminal of an area array such as an LGA (Land Grid Array) is becoming mainstream.
【０００３】例えば、従来の半導体装置の一例としてＢ
ＧＡの典型的な構造を以下に説明する。図５（ａ）は従
来のＢＧＡタイプの半導体装置におけるバンプ周辺部分
の断面図であり、図５（ｂ）は、実装した図５（ａ）の
半導体装置のバンプ周辺部分の断面を示す。従来の典型
的なＢＧＡ構造において、プラスチックやフレキシブル
テープで構成されたチップキャリア、あるいはフリップ
チップの場合は、図５（ａ）及び（ｂ）に示すように、
フリップチップもしくはパッケージ１０１の下面にアレ
イ状に形成された外部入出力端子である電極パッド１０
２上に半田ボール１０３を形成した構造を採り、半田ボ
ールを実装基板１０６の電極パッド１０７に融着するこ
とで実装していた。For example, as an example of a conventional semiconductor device, B
A typical structure of the GA will be described below. FIG. 5A is a cross-sectional view of a peripheral portion of a bump in a conventional BGA type semiconductor device, and FIG. 5B is a cross-sectional view of a peripheral portion of the bump of the mounted semiconductor device of FIG. In a typical conventional BGA structure, in the case of a chip carrier made of plastic or flexible tape, or in the case of a flip chip, as shown in FIGS.
Electrode pad 10 which is an external input / output terminal formed in an array on the lower surface of flip chip or package 101
2, a solder ball 103 is formed on the substrate 2, and the solder ball is mounted on the electrode pad 107 of the mounting board 106 by fusing.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、上記従
来の構成において、実装基板とフリップチップ（或いは
パッケージ）の間に熱膨張係数に大きな差がある場合、
実装基板とフリップチップ（或いはパッケージ）の間を
絶縁樹脂により封止して、実装後の熱サイクルで接続部
に発生する応力を分散しなければならなかった。この樹
脂封止の工程は、工数的にもコスト的にもユーザーにと
って大きな負担であった。However, in the above conventional configuration, when there is a large difference in the thermal expansion coefficient between the mounting substrate and the flip chip (or package),
The space between the mounting substrate and the flip chip (or package) must be sealed with an insulating resin to disperse the stress generated in the connection part in the thermal cycle after mounting. This resin sealing step puts a heavy burden on the user in terms of man-hour and cost.
【０００５】また多ピン化に伴い、多くの半田ボールを
形成するためにも、精密な位置精度を有するボールプレ
ーサーなど高価な製造装置が必要であった。[0005] In addition, with the increase in the number of pins, an expensive manufacturing apparatus such as a ball placer having precise positional accuracy is required to form a large number of solder balls.
【０００６】また、多ピン化、狭ピッチ化が進むと、実
装時に半田ボールが横方向に変形し、隣のボールとショ
ートするなどの不良も発生しやすかった。これを防止す
るために、例えば特開昭６１−１４５８３８号公報のよ
うに、半田ボール相互間を耐熱性絶縁層で被覆する構造
が用いられている。ところが、この構造では、半田ボー
ルの先端を除いて半田ボール相互間を絶縁層で埋めてい
るため、半田ボールの先端部は融着時に絶縁層を越えて
変形する事になり、ボール間ショートの危険性は逃れら
れない。Further, as the number of pins increases and the pitch decreases, solder balls are deformed in the horizontal direction during mounting, and defects such as short-circuiting with adjacent balls are likely to occur. In order to prevent this, for example, a structure in which a space between solder balls is covered with a heat-resistant insulating layer is used as disclosed in Japanese Patent Application Laid-Open No. 61-145838. However, in this structure, the gap between the solder balls is filled with an insulating layer except for the tip of the solder ball, so that the tip of the solder ball is deformed beyond the insulating layer at the time of fusion, resulting in a short circuit between the balls. Danger cannot be escaped.
【０００７】加えて、特開平８−１８１２４０号公報に
示されるように、セラミック多層基板をＢＧＡ方式のＩ
Ｃチップキャリア基板として使用した半導体装置におい
て、そのセラミック多層基板の一方の主面に複数の凹部
を形成し、その凹部の底部に位置する電極に、一部がセ
ラミック多層基板の主面より突出するように半田ボール
を搭載した構造もある。しかし、この構造ではプラスチ
ックの実装基板に実装する場合、セラミック製のキャリ
ア基板とプラスチックの実装基板との熱膨張係数の差が
大きく、キャリア基板の凹部内の半田ボール部に大きな
熱応力がかかり、実装信頼性が非常に低くなってしま
う。In addition, as disclosed in Japanese Patent Application Laid-Open No. 8-181240, a ceramic multi-layer substrate is
In a semiconductor device used as a C chip carrier substrate, a plurality of recesses are formed on one main surface of the ceramic multilayer substrate, and a part of the electrode located at the bottom of the recess protrudes from the main surface of the ceramic multilayer substrate. There is also a structure in which solder balls are mounted. However, with this structure, when mounting on a plastic mounting board, the difference in thermal expansion coefficient between the ceramic carrier board and the plastic mounting board is large, and a large thermal stress is applied to the solder ball portion in the recess of the carrier board, The mounting reliability becomes very low.
【０００８】本発明の目的は、上記従来技術の課題に鑑
み、一括リフローにより容易に実装が行え、実装時の不
良を抑制でき、かつ実装信頼性が高く、さらに生産性の
高い、半導体装置、該半導体装置の製造方法および前記
半導体装置の実装方法を提供することにある。In view of the above-mentioned problems of the prior art, an object of the present invention is to provide a semiconductor device which can be easily mounted by batch reflow, can suppress defects at the time of mounting, has high mounting reliability, and has high productivity. An object of the present invention is to provide a method for manufacturing the semiconductor device and a method for mounting the semiconductor device.
【０００９】[0009]
【課題を解決するための手段】上記目的を達成するため
に本発明は、バンプを用いて実装基板に実装する半導体
装置であって、該バンプ間に絶縁体の障壁が前記バンプ
と離間して配置され、該障壁の前記実装基板と対向する
面の全体または一部に熱可塑性の接着層が形成されたこ
とを特徴とする。このような構成の半導体装置では、実
装時にバンプを溶融させて実装基板の電極パッドとの電
気的接続を図るが、この際、バンプが狭ピッチで配設さ
れている場合でも、障壁によりバンプ間ショートが起き
ない。しかも、溶融実装時に障壁の接着層が実装基板に
当接して接着されるので、半導体装置本体の自重で必要
以上にバンプがつぶれずバンプ高さが保持される。さら
には、半導体装置本体に設けられた障壁と実装基板とが
接着剤により接着されることにより、半導体装置本体と
実装基板との熱膨張係数の違いによる熱応力が接着剤に
分散されてバンプ部にかかりにくいため、実装信頼性が
高い。In order to achieve the above object, the present invention provides a semiconductor device mounted on a mounting substrate using bumps, wherein an insulator barrier is provided between the bumps so as to be separated from the bumps. A thermoplastic adhesive layer is formed on the entire surface or a part of a surface of the barrier facing the mounting substrate. In a semiconductor device having such a configuration, the bumps are melted at the time of mounting to achieve electrical connection with the electrode pads of the mounting board. At this time, even if the bumps are arranged at a narrow pitch, the gap between the bumps is reduced by a barrier. No shorts occur. In addition, since the adhesive layer of the barrier comes into contact with and is adhered to the mounting substrate during the fusion mounting, the bump height is maintained without the bumps being crushed more than necessary by the weight of the semiconductor device main body. Furthermore, the barrier provided on the semiconductor device main body and the mounting substrate are bonded to each other with an adhesive, so that the thermal stress due to the difference in the thermal expansion coefficient between the semiconductor device main body and the mounting substrate is dispersed in the adhesive and the bump portion is formed. Mounting reliability is high.
【００１０】上記の半導体装置の実装方法としては、バ
ンプとして半田バンプを用いた場合、該半田バンプと前
記実装基板の電極パッドとを位置合わせし、リフロー処
理により前記半田バンプと前記実装基板の電極パッドと
を融着した後に、前記半田バンプが溶融した状態におい
て前記半導体装置の上方より押圧する事により前記接着
層を前記実装基板に接着することが実装信頼性を向上さ
せる上で好ましい。この場合、前記の押圧の方法が風圧
を用いたものであると、多数の半導体装置を容易に一括
で実装できる。In the method of mounting a semiconductor device, when a solder bump is used as a bump, the solder bump and the electrode pad of the mounting board are aligned with each other, and the solder bump and the electrode of the mounting board are reflowed. It is preferable that the bonding layer is bonded to the mounting substrate by pressing from above the semiconductor device in a state where the solder bumps are melted after the bonding with the pad, in order to improve mounting reliability. In this case, if the pressing method uses wind pressure, a large number of semiconductor devices can be easily mounted at once.
【００１１】また、上記の半導体装置の製造方法として
は、バンプを形成するために設けられた電極パッドの形
成面に、該電極パッドに当たる位置に貫通孔を持つと同
時に両面に熱可塑性の接着層を形成してなる絶縁体の平
板あるいはテープを位置合わせし、貼り付けて、前記パ
ンプ間に絶縁体の障壁を形成することが考えられる。こ
の方法によれば、バンプ間に容易に障壁を形成すること
ができる。さらには、バンプを形成するために設けられ
た電極パッドの形成面と障壁とで形成される凹部に、半
田ペーストを充填し、リフロー処理を行うことにより、
バンプを形成することが考えられる。この方法は、多数
のバンプが一度に容易に作製できるため、量産性に優れ
る。In the method of manufacturing a semiconductor device, the surface of the electrode pad provided for forming the bump has a through hole at a position corresponding to the electrode pad, and a thermoplastic adhesive layer is formed on both surfaces. It is conceivable that a flat plate or tape of an insulator formed by forming the above is aligned and attached to form an insulator barrier between the pumps. According to this method, a barrier can be easily formed between the bumps. Furthermore, by filling the solder paste into the recess formed by the formation surface of the electrode pad and the barrier provided for forming the bump, and performing a reflow process,
It is conceivable to form a bump. This method is excellent in mass productivity because a large number of bumps can be easily manufactured at once.
【００１２】[0012]
【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照して説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００１３】図１は、本発明の半導体装置の一実施形態
におけるバンプ周辺部分を示す断面図である。FIG. 1 is a sectional view showing a bump peripheral portion in one embodiment of the semiconductor device of the present invention.
【００１４】本形態の半導体装置は、バンプを用いて実
装基板に実装するものであって、図１に示すようにフリ
ップチップ（或いはパッケージ）１の複数の電極パッド
２に各々融着された半田バンプ３の間を絶縁体の障壁４
により仕切ると共に、障壁４を半田バンプ３と離間させ
た構造からなる。そして、障壁４の実装基板６と対向す
る面の一部あるいは全面には熱可塑性の接着層５が形成
されている。この場合の絶縁体の障壁４と接着層５の合
計の厚さは半田バンプ３の径に比較してある程度小さい
ことが、融着実装時の半田バンプ３による水平あるいは
垂直方向のセルフアライメントを実現するためには必要
である。なお、この明細書でパッケージとは、内部に半
導体チップを樹脂等で封じ込めたものや、基板に半導体
チップを搭載したものを言い、例えばＢＧＡ（Ball Gri
d Array）、ＣＳＰ（Chip Size Package）等の形態が挙
げられる。The semiconductor device according to the present embodiment is mounted on a mounting substrate using bumps, and as shown in FIG. 1, solders respectively fused to a plurality of electrode pads 2 of a flip chip (or package) 1. Insulator barrier 4 between bumps 3
And the barrier 4 is separated from the solder bumps 3. Then, a thermoplastic adhesive layer 5 is formed on a part or the entire surface of the barrier 4 facing the mounting substrate 6. In this case, the total thickness of the insulator barrier 4 and the adhesive layer 5 is somewhat smaller than the diameter of the solder bumps 3, thereby realizing horizontal or vertical self-alignment by the solder bumps 3 during fusion mounting. It is necessary to do. In this specification, a package refers to a package in which a semiconductor chip is sealed with resin or the like, or a package in which a semiconductor chip is mounted on a substrate.
d Array), CSP (Chip Size Package) and the like.
【００１５】次に、上記構成の半導体装置の実装方法に
ついて説明する。図２は本発明の半導体装置の一実施形
態の実装方法を説明するための工程図である。Next, a method of mounting the semiconductor device having the above configuration will be described. FIG. 2 is a process chart for explaining a mounting method of one embodiment of the semiconductor device of the present invention.
【００１６】フリップチップ（或いはパッケージ）１の
実装基板６への実装は、図２の（ａ）及び（ｂ）に示す
ように、半田バンプ３を実装基板６の相当する電極パッ
ド７に目合わせし、その後、リフロー処理を行い、半田
バンプ３を電極パッド７に融着する事により行う。この
とき、実装基板６の電極パッド７上への半田バンプ３の
融着に伴い、フリップチップ（或いはパッケージ）１の
重量によりバンプ３が変形し、フリップチップ（或いは
パッケージ）１と実装基板６の間はある間隔に減少す
る。そして絶縁体障壁４と接着層５の合計の厚さが、前
記の間隔よりも厚い場合、接着層５は実装基板６に接触
する。また接触しない場合や、接触が不十分である場合
は、半導体装置の上方からの適度な機械的圧力、あるい
は風圧等の適度な押圧により接着層５を実装基板６に接
触させることができる。特に、風圧を用いることによ
り、多数のフリップチップ（或いはパッケージ）１を一
括で容易に実装できる。このときの温度が、熱可塑性の
接着層５の融点以下であると、接着剤の作用により、図
２（ｃ）に示すように、フリップチップ（或いはパッケ
ージ）１と実装基板６とは接着される。但し、前記の接
着の工程は、リフロー工程中で行うことも、別工程にし
て行うことも可能である。The flip chip (or package) 1 is mounted on the mounting substrate 6 by aligning the solder bumps 3 with the corresponding electrode pads 7 of the mounting substrate 6 as shown in FIGS. Thereafter, a reflow process is performed to fuse the solder bumps 3 to the electrode pads 7. At this time, with the fusion of the solder bumps 3 on the electrode pads 7 of the mounting board 6, the bumps 3 are deformed by the weight of the flip chip (or package) 1, and the flip chip (or package) 1 and the mounting board 6 The interval decreases at certain intervals. When the total thickness of the insulator barrier 4 and the adhesive layer 5 is larger than the above-mentioned distance, the adhesive layer 5 comes into contact with the mounting substrate 6. When there is no contact or insufficient contact, the adhesive layer 5 can be brought into contact with the mounting substrate 6 by an appropriate mechanical pressure from above the semiconductor device or an appropriate pressure such as a wind pressure. In particular, by using wind pressure, a large number of flip chips (or packages) 1 can be easily mounted collectively. If the temperature at this time is equal to or lower than the melting point of the thermoplastic adhesive layer 5, the flip chip (or package) 1 and the mounting substrate 6 are bonded by the action of the adhesive as shown in FIG. You. However, the bonding step can be performed during the reflow step or as a separate step.
【００１７】また、上記のような接着工程後、フリップ
チップ１と実装基板６と障壁４とで囲まれた密閉空間が
形成されると、該密閉空間内の気体の熱膨張により障壁
４に圧力がかかってしまう。この事を防ぐために、接着
後に障壁４により密閉空間が形成されないように障壁４
の一部を取り除いた構成する事が好ましい。After the above-described bonding step, when a sealed space surrounded by the flip chip 1, the mounting substrate 6, and the barrier 4 is formed, a pressure is applied to the barrier 4 by thermal expansion of gas in the sealed space. Will take. In order to prevent this, a barrier 4 is formed so that a sealed space is not formed by the barrier 4 after bonding.
It is preferable to remove a part of the structure.
【００１８】次に、上記構成の半導体装置の製造方法、
特に、絶縁体障壁４の製造方法について説明する。図３
は本発明の半導体装置の一実施形態における障壁の製造
方法を説明するための図である。Next, a method of manufacturing the semiconductor device having the above structure,
In particular, a method for manufacturing the insulator barrier 4 will be described. FIG.
FIG. 3 is a diagram for explaining a method for manufacturing a barrier in one embodiment of the semiconductor device of the present invention.
【００１９】図１に示した障壁４をフリップチップ（或
いはパッケージ）１に作り込むには、例えば、フリップ
チップ（或いはパッケージ）１に形成されている電極パ
ッド２に相当する位置に貫通孔８が形成され、かつ両面
に熱可塑性の接着層５、９が形成されたポリイミド、エ
ポキシ等の材料よりなるフレキシブルテープ１０を用い
る。そして、フリップチップ（或いはパッケージ）１に
形成されている電極パッド２に図３（ａ）に示すように
フレキシブルテープ１０の貫通孔８を目合わせし、図３
（ｂ）に示すようにフレキシブルテープ１０を熱と圧力
によりフリップチップ（或いはパッケージ）１に接着す
る。このとき、フリップチップ（或いはパッケージ）１
側の接着剤９の融点を実装基板側の接着剤５の融点より
低くすることにより、この接着工程において実装基板側
の接着剤５が溶融する事を防ぐことができる。In order to form the barrier 4 shown in FIG. 1 in the flip chip (or package) 1, for example, a through hole 8 is formed at a position corresponding to the electrode pad 2 formed in the flip chip (or package) 1. A flexible tape 10 made of a material such as polyimide or epoxy and having thermoplastic adhesive layers 5 and 9 formed on both surfaces is used. Then, the through holes 8 of the flexible tape 10 are aligned with the electrode pads 2 formed on the flip chip (or package) 1 as shown in FIG.
As shown in (b), the flexible tape 10 is bonded to the flip chip (or package) 1 by heat and pressure. At this time, flip chip (or package) 1
By making the melting point of the adhesive 9 on the side lower than the melting point of the adhesive 5 on the mounting board, it is possible to prevent the adhesive 5 on the mounting board from melting in this bonding step.
【００２０】障壁４の製造方法としてはこの他に、フォ
トエッチング法や樹脂モールド法やを利用することも可
能である。即ち、フリップチップ（或いはパッケージ）
１の電極パッド形成面全体にソルダーレジストを厚く形
成し、電極パッド２が露出するようにフォトエッチング
によりレジストを除去することで、電極パッド２間に絶
縁障壁を構成してもよい。あるいは、障壁となる凹部を
彫り込んだ型材をフリップチップ（或いはパッケージ）
１の電極パッド形成面に密着させ、該電極パッド形成面
と型材の凹部とで囲まれた空間内に絶縁性樹脂を注入し
硬化させることで、電極パッド２間に絶縁障壁を構成し
てもよい。As a method for manufacturing the barrier 4, a photo-etching method or a resin molding method can be used. That is, flip chip (or package)
An insulating barrier may be formed between the electrode pads 2 by forming a thick solder resist on the entire surface of the electrode pad 1 and removing the resist by photoetching so that the electrode pads 2 are exposed. Or, flip-chip (or package) a mold material engraved with a concave part that becomes a barrier
Even if an insulating barrier is formed between the electrode pads 2 by bringing the insulating resin into close contact with the electrode pad forming surface and injecting and curing an insulating resin in a space surrounded by the electrode pad forming surface and the concave portion of the mold material. Good.
【００２１】さらに、バンプ３の製造方法について説明
する。図４は本発明の半導体装置の一実施形態における
バンプの製造方法を説明するための工程図である。Further, a method of manufacturing the bump 3 will be described. FIG. 4 is a process chart for explaining a bump manufacturing method in one embodiment of the semiconductor device of the present invention.
【００２２】図４に示すように、フリップチップ（或い
はパッケージ）１の電極パッド２の形成面と障壁４とで
形成された凹部に、スキージ１１を用いて半田ペースト
１２を充填し、リフロー処理を行うことにより半田バン
プ３を形成する。具体的には、障壁４と接着層５との合
計の厚さが１００μｍで、電極パッド２の形成面と障壁
４により形成される凹部が直径３００μｍの円柱形状で
ある場合、充填された半田ペーストはリフロー処理によ
り体積が約５０％の半田になり、これは直径約２２０μ
ｍの半田ボールになる。したがって、半田バンプは障壁
４と離間した状態にある。As shown in FIG. 4, a solder paste 12 is filled with a squeegee 11 into a recess formed by the surface of the flip chip (or package) 1 on which the electrode pads 2 are formed and the barrier 4, and a reflow process is performed. By doing so, the solder bumps 3 are formed. Specifically, when the total thickness of the barrier 4 and the adhesive layer 5 is 100 μm, and the concave portion formed by the surface on which the electrode pad 2 is formed and the barrier 4 has a cylindrical shape with a diameter of 300 μm, the filled solder paste Is about 50% solder by reflow treatment, which is about 220μ in diameter.
m solder balls. Therefore, the solder bump is separated from the barrier 4.
【００２３】半田ペースト３の代わりに、電極パッド２
に溶融半田を用いることも可能である。勿論、この場合
はリフロー処理は不要である。Instead of the solder paste 3, the electrode pads 2
It is also possible to use molten solder. Of course, in this case, the reflow process is unnecessary.
【００２４】[0024]
【発明の効果】以上に説明したように、本発明は、バン
プ間に絶縁体の障壁をバンプと離間して配置した構造の
半導体装置であるので、溶融実装時に隣のバンプとの短
絡などの不良が起こりにくい。そして、絶縁障壁により
実装時にバンプがつぶれずバンプ高さを保持することが
できる。As described above, the present invention is a semiconductor device having a structure in which an insulator barrier is arranged between bumps so as to be separated from the bumps. Defects are less likely to occur. Then, the bumps can be maintained at the height of the bumps without being broken by the insulating barrier at the time of mounting.
【００２５】また、バンプ間に配設された障壁の、実装
基板と対向する面の全体または一部に、熱可塑性の接着
層を形成し、実装時に接着剤で半導体装置本体（フリッ
プチップ或いはパッケージ）を接着する構造なので、実
装基板と半導体装置本体との熱膨張係数の違いによる熱
応力によるストレスが接着層で分散されてバンプ部にか
かりにくく、実装信頼性が高い。その結果、従来必要で
あったバンプ部の樹脂封止の工程が不要になり低コスト
である。Further, a thermoplastic adhesive layer is formed on the whole or a part of the surface of the barrier provided between the bumps facing the mounting substrate, and the semiconductor device body (flip chip or package) is bonded with an adhesive during mounting. ), The stress due to the thermal stress due to the difference in the thermal expansion coefficient between the mounting substrate and the semiconductor device main body is dispersed in the adhesive layer and is less likely to be applied to the bump portion, and the mounting reliability is high. As a result, the step of sealing the bump portion with a resin, which has been required conventionally, becomes unnecessary, and the cost is reduced.
【００２６】さらに、接着層による実装基板への実装は
リフロー処理工程中に行えるので、実装工程が単純であ
る。また、リフロー処理により半田バンプと実装基板の
電極パッドとを融着した後に、半田バンプが溶融した状
態において半導体装置本体の上方より押圧する事によ
り、半田ボールの実装基板の電極パッドへの融着の不良
が起こりにくい。Further, since the mounting on the mounting board by the adhesive layer can be performed during the reflow processing step, the mounting step is simple. Further, after the solder bumps and the electrode pads of the mounting board are fused by the reflow process, the solder balls are pressed from above the semiconductor device body in a state where the solder bumps are melted, so that the solder balls are fused to the electrode pads of the mounting board. Is unlikely to occur.
【００２７】そして、バンプを形成するために設けられ
た電極パッドの形成面と障壁とで形成される凹部に、半
田ペーストを充填し、リフロー処理を行うことにより、
バンプを形成することにより、印刷の手法で多数の半田
バンプを一括に形成できるので、多ピンのパッケージ、
フリップチップにおいて低コストで製造できる。[0027] Then, a solder paste is filled in a concave portion formed by a barrier and a surface on which an electrode pad is provided for forming a bump, and a reflow process is performed.
By forming bumps, a large number of solder bumps can be formed at once by a printing method, so that multi-pin packages,
It can be manufactured at low cost in flip chips.
【図１】本発明の半導体装置の一実施形態におけるバン
プ周辺部分を示す断面図である。FIG. 1 is a cross-sectional view showing a bump peripheral portion in one embodiment of a semiconductor device of the present invention.
【図２】本発明の半導体装置の一実施形態の実装方法を
説明するための工程図である。FIG. 2 is a process chart for explaining a mounting method of one embodiment of a semiconductor device of the present invention.
【図３】本発明の半導体装置の一実施形態における障壁
の製造方法を説明するための工程図である。FIG. 3 is a process chart for explaining a method of manufacturing a barrier in one embodiment of the semiconductor device of the present invention.
【図４】本発明の半導体装置の一実施形態におけるバン
プの製造方法を説明するための工程図である。FIG. 4 is a process chart for explaining a bump manufacturing method in one embodiment of the semiconductor device of the present invention.
【図５】従来の、バンプを用いて実装基板に実装する半
導体装置の構成とその実装状態を示す断面図である。FIG. 5 is a cross-sectional view illustrating a configuration of a conventional semiconductor device mounted on a mounting substrate using bumps and a mounting state thereof.
１ フリップチップ（或いはパッケージ） ２ 電極パッド（フリップチップ或いはパッケージの
もの） ３ 半田バンプ ４ 絶縁体障壁 ５ 熱可塑性接着剤 ６ 実装基板 ７ 電極パッド（実装基板のもの） ８ 貫通孔 ９ 熱可塑性接着剤 １０ フレキシブルテープ １１ スキージ １２ 半田ペーストDESCRIPTION OF SYMBOLS 1 Flip chip (or package) 2 Electrode pad (of flip chip or package) 3 Solder bump 4 Insulator barrier 5 Thermoplastic adhesive 6 Mounting board 7 Electrode pad (of mounting board) 8 Through hole 9 Thermoplastic adhesive 10 Flexible tape 11 Squeegee 12 Solder paste
Claims (5)
体装置であって、該バンプ間に絶縁体の障壁が前記バン
プと離間して配置され、該障壁の前記実装基板と対向す
る面の全体または一部に熱可塑性の接着層が形成された
ことを特徴とする半導体装置。1. A semiconductor device mounted on a mounting substrate using bumps, wherein an insulator barrier is arranged between the bumps so as to be separated from the bumps, and the entire surface of the barrier facing the mounting substrate is provided. Alternatively, a semiconductor device in which a thermoplastic adhesive layer is partially formed.
であって、バンプとして半田バンプを用いた場合、該半
田バンプと前記実装基板の電極パッドとを位置合わせ
し、リフロー処理により前記半田バンプと前記実装基板
の電極パッドとを融着した後に、前記半田バンプが溶融
した状態において前記半導体装置の上方より押圧する事
により前記接着層を前記実装基板に接着することを特徴
とする半導体装置の実装方法。2. The method of mounting a semiconductor device according to claim 1, wherein when a solder bump is used as the bump, said solder bump is aligned with an electrode pad of said mounting board, and said solder bump is reflowed. A semiconductor device, wherein after bonding a bump and an electrode pad of the mounting board, the bonding layer is bonded to the mounting board by pressing the solder bump from above the semiconductor device in a molten state. How to implement.
において、前記の押圧の方法が、風圧を用いたものであ
ることを特徴とする半導体装置の実装方法。3. The method of mounting a semiconductor device according to claim 2, wherein said pressing method uses wind pressure.
であって、バンプを形成するために設けられた電極パッ
ドの形成面に、該電極パッドに当たる位置に貫通孔を持
つと同時に両面に熱可塑性の接着層を形成してなる絶縁
体の平板あるいはテープを位置合わせし、貼り付けて、
前記パンプ間に絶縁体の障壁を形成することを特徴とす
る半導体装置の製造方法。4. The method for manufacturing a semiconductor device according to claim 1, wherein a surface of the electrode pad provided for forming the bump has a through hole at a position corresponding to the electrode pad, and at the same time both surfaces have a through hole. Align and paste a flat plate or tape of an insulator formed with a thermoplastic adhesive layer,
A method of manufacturing a semiconductor device, comprising forming an insulator barrier between the pumps.
において、バンプを形成するために設けられた電極パッ
ドの形成面と障壁とで形成される凹部に、半田ペースト
を充填し、リフロー処理を行うことにより、バンプを形
成することを特徴とする半導体装置の製造方法。5. The method for manufacturing a semiconductor device according to claim 1, wherein a solder paste is filled in a recess formed by a surface and a barrier on which an electrode pad is provided for forming a bump, and a reflow process is performed. Forming a bump by performing the method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9142113A JP2907188B2 (en) | 1997-05-30 | 1997-05-30 | Semiconductor device, method of mounting semiconductor device, and method of manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9142113A JP2907188B2 (en) | 1997-05-30 | 1997-05-30 | Semiconductor device, method of mounting semiconductor device, and method of manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10335527A JPH10335527A (en) | 1998-12-18 |
| JP2907188B2 true JP2907188B2 (en) | 1999-06-21 |
Family
ID=15307726
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9142113A Expired - Fee Related JP2907188B2 (en) | 1997-05-30 | 1997-05-30 | Semiconductor device, method of mounting semiconductor device, and method of manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2907188B2 (en) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19831570A1 (en) * | 1998-07-14 | 2000-01-20 | Siemens Ag | Biometrical sensor for fingerprint identification for mobile phone |
| EP1328015A3 (en) * | 2002-01-11 | 2003-12-03 | Hesse & Knipps GmbH | Method of bonding a flip chip |
| WO2003077618A2 (en) * | 2002-03-05 | 2003-09-18 | Resolution Performance Products Llc | Attachment of surface mount devices to printed circuit boards using a thermoplastic adhesive |
| US6906425B2 (en) | 2002-03-05 | 2005-06-14 | Resolution Performance Products Llc | Attachment of surface mount devices to printed circuit boards using a thermoplastic adhesive |
| US6998539B2 (en) * | 2003-05-27 | 2006-02-14 | Xerox Corporation | Standoff/mask structure for electrical interconnect |
| JP4736948B2 (en) * | 2006-05-22 | 2011-07-27 | 株式会社デンソー | Electronic component mounting method |
| KR100855268B1 (en) | 2006-12-29 | 2008-09-01 | 주식회사 하이닉스반도체 | Semiconductor package and manufacturing method of the same |
| US20090127703A1 (en) * | 2007-11-20 | 2009-05-21 | Fujitsu Limited | Method and System for Providing a Low-Profile Semiconductor Assembly |
| US8487428B2 (en) | 2007-11-20 | 2013-07-16 | Fujitsu Limited | Method and system for providing a reliable semiconductor assembly |
| JP2011082318A (en) * | 2009-10-07 | 2011-04-21 | Fujikura Ltd | Circuit board |
| US8424748B2 (en) * | 2009-12-21 | 2013-04-23 | Intel Corporation | Solder in cavity interconnection technology |
| JP2014082281A (en) * | 2012-10-15 | 2014-05-08 | Olympus Corp | Substrate, semiconductor device and substrate manufacturing method |
| TWI606565B (en) * | 2016-08-31 | 2017-11-21 | 金寶電子工業股份有限公司 | Package structure and manufacturing method thereof |
| CN108807428A (en) * | 2018-04-26 | 2018-11-13 | 武汉高芯科技有限公司 | Focal plane arrays (FPA) and preparation method thereof with isolated column |
-
1997
- 1997-05-30 JP JP9142113A patent/JP2907188B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH10335527A (en) | 1998-12-18 |
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