JP2002368038A - Flip-chip mounting method - Google Patents
Flip-chip mounting methodInfo
- Publication number
- JP2002368038A JP2002368038A JP2001171986A JP2001171986A JP2002368038A JP 2002368038 A JP2002368038 A JP 2002368038A JP 2001171986 A JP2001171986 A JP 2001171986A JP 2001171986 A JP2001171986 A JP 2001171986A JP 2002368038 A JP2002368038 A JP 2002368038A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- chip
- gold
- wiring board
- film layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、発展を続けてい
る電子機器の中核と位置づけられるプリント配線板ユニ
ットの製造に際して、プリント配線板等の回路基板上に
ベアＩＣチップを実装するフリップチップ実装方法に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-chip mounting method for mounting a bare IC chip on a circuit board such as a printed wiring board when manufacturing a printed wiring board unit which is positioned as a core of electronic equipment which is continuing to evolve. About.
【０００２】[0002]
【従来の技術】プリント配線板ユニットを製造する際
に、ベアＩＣチップを回路基板上に直接に実装するため
の接合工法（フリップチップ実装方法）としては多くの
工法があるが、代表的な工法としては、図２に示すよう
なクリームはんだを用いる工法や、図３に示すようなは
んだめっき層上にフラックスを塗布してはんだ接合する
工法がある。2. Description of the Related Art When a printed wiring board unit is manufactured, there are many joining methods (flip chip mounting methods) for directly mounting a bare IC chip on a circuit board. As a method, there is a method using a cream solder as shown in FIG. 2 or a method of applying a flux onto a solder plating layer and soldering as shown in FIG.
【０００３】図２にしたがって、クリームはんだを用い
る工法を説明する。回路基板であるプリント配線板１の
銅電極（図２ではCu電極）11上にフラックスを含有する
クリームはんだ層３が、スクリーン印刷法等で供給され
〔図２（ｂ）〕、不図示の電極上に予め金バンプ（図２
ではAuバンプ）21を形成されたＩＣチップ２が、その上
に位置合わせされて搭載され〔図２（ｃ）〕、この状態
で両者間に適当な荷重がかけられて両者が加熱され、銅
電極11と金バンプ21とがはんだ層31ではんだ接合されて
〔図２（ｄ）〕、接合状態となる。Referring to FIG. 2, a method using cream solder will be described. A cream solder layer 3 containing a flux is supplied on a copper electrode (Cu electrode in FIG. 2) 11 of a printed wiring board 1 which is a circuit board by a screen printing method or the like [FIG. 2 (b)]. Gold bumps on top (Fig. 2
Then, the IC chip 2 on which the Au bump 21 is formed is mounted on the IC chip 2 while being aligned (FIG. 2 (c)). In this state, an appropriate load is applied between the two and the two are heated, and the copper is heated. The electrode 11 and the gold bump 21 are solder-joined by the solder layer 31 [FIG. 2 (d)], and a joining state is obtained.
【０００４】次に、図３にしたがって、はんだめっき層
上にフラックスを塗布してはんだ接合する工法を説明す
る。銅電極（図３ではCu電極）11上に予めはんだめっき
層４を形成されたプリント配線板１〔図３（ｂ）〕に、
はんだ接合のためのフラックス５が塗布され〔図３
（ｃ）〕、不図示の電極上に予め金バンプ（図３ではAu
バンプ）21を形成されたＩＣチップ２がその上に位置合
わせされて搭載され〔図３（ｄ）〕、この状態で両者間
に適当な荷重がかけられて両者が加熱され、銅電極11と
金バンプ21とがはんだ層41ではんだ接合されて〔図３
（ｅ）〕、接合状態となる。この場合には、フラックス
５がプリント配線板１とＩＣチップ２との間の空間を埋
めている。[0004] Next, referring to FIG. 3, a method of applying a flux on the solder plating layer and joining the solder by solder will be described. A printed wiring board 1 (FIG. 3B) in which a solder plating layer 4 is formed in advance on a copper electrode (Cu electrode in FIG. 3) 11
A flux 5 for soldering is applied [FIG.
(C)], gold bumps (Au in FIG. 3)
The IC chip 2 having the bumps 21 formed thereon is aligned and mounted thereon (FIG. 3D). In this state, an appropriate load is applied between the two and the two are heated, and the copper electrode 11 and the The gold bump 21 and the solder layer 41 are soldered together [FIG.
(E)], a joining state is obtained. In this case, the flux 5 fills the space between the printed wiring board 1 and the IC chip 2.
【０００５】いずれの接合工法においても、かけられる
荷重は、はんだのはみ出しをできる限り少なくするよう
に制御されている。[0005] In any of the joining methods, the applied load is controlled so as to minimize the protrusion of the solder.
【０００６】[0006]
【発明が解決しようとする課題】従来技術による上記の
２つの接合工法の場合には、はんだを溶融させて接合す
るため、フラックスの使用が不可欠である。ＩＣチップ
２の電極ピッチは 100μm 程度のものが多く、通常の電
子部品に比べて電極間の絶縁距離が短く、その距離は例
えば40μm である。そのため、フラックスを使用した場
合には、接合後に残留したフラックスの残渣によって電
極間の絶縁信頼性が低下するという問題があり、フラッ
クスの洗浄が不可欠であり、このための清浄工程を必要
とする。また、図３に示した接合工法による場合には、
接合に必要な厚さ20μm 程度のはんだめっき層４を形成
するためのめっき工程にコストがかかるという問題があ
る。また、はんだ層の厚さが厚いと、接合時の荷重によ
って溶融したはんだがはみ出して実効的な絶縁距離を短
くして信頼性を低下させる等の問題もある。In the case of the above two joining methods according to the prior art, the use of a flux is indispensable because the solder is melted and joined. The electrode pitch of the IC chip 2 is often about 100 μm, and the insulation distance between the electrodes is shorter than that of a normal electronic component, and the distance is, for example, 40 μm. Therefore, when a flux is used, there is a problem that the reliability of insulation between the electrodes is reduced due to the residue of the flux remaining after bonding, and cleaning of the flux is indispensable, and a cleaning step for this is required. In the case of the joining method shown in FIG.
There is a problem in that the plating process for forming the solder plating layer 4 having a thickness of about 20 μm required for joining is costly. In addition, when the thickness of the solder layer is large, there is another problem that the molten solder protrudes due to the load at the time of joining, shortening the effective insulation distance and lowering the reliability.
【０００７】この発明の課題は、上記のような問題点を
解消して、高い信頼性のプリント配線板ユニットが製造
でき、且つその製造コストが安いフリップチップ実装方
法を提供することである。An object of the present invention is to provide a flip-chip mounting method capable of manufacturing a highly reliable printed wiring board unit and reducing the manufacturing cost by solving the above problems.
【０００８】[0008]
【課題を解決するための手段】請求項１の発明は、回路
基板の電極上に錫を主成分とする薄膜層を形成し、ＩＣ
チップの電極上に金バンプを形成して、前記薄膜層と金
バンプとが直接接触するようにプリント配線板とＩＣチ
ップとを位置合わせし、前記薄膜層及び金バンプを加熱
状態で相互に加圧することによって、前記薄膜層を融解
させてその中に金バンプの金を溶解させ、前記薄膜層を
合金化させることによって、生成された合金層で回路基
板の電極と金バンプとを接合させる。According to a first aspect of the present invention, a thin film layer containing tin as a main component is formed on an electrode of a circuit board.
A gold bump is formed on the electrode of the chip, the printed wiring board and the IC chip are aligned so that the thin film layer and the gold bump are in direct contact, and the thin film layer and the gold bump are applied to each other in a heated state. By pressing, the thin film layer is melted and the gold of the gold bump is dissolved therein, and the thin film layer is alloyed, so that the electrode of the circuit board and the gold bump are joined by the generated alloy layer.
【０００９】融解した薄膜層に金バンプの金が溶解して
生成される金−錫合金層が、回路基板の電極と金バンプ
とを電気的にも機械的にも望ましい状態で接合させる。
しかも、接合が融解した薄い薄膜層への固体の金バンプ
の金の溶解に伴う合金化によるので、従来技術における
はんだのはみだしのような問題が発生することがない。
更に、この実装方法は鉛を使用しないので鉛フリーの接
合となる。A gold-tin alloy layer formed by dissolving the gold of the gold bump in the melted thin film layer joins the electrode of the circuit board and the gold bump in a desirable state both electrically and mechanically.
In addition, since the solid gold bumps are alloyed with the melting of the gold in the thin thin film layer in which the bonding has been melted, problems such as the protrusion of solder in the prior art do not occur.
Furthermore, since this mounting method does not use lead, it is a lead-free joint.
【００１０】請求項２の発明は、請求項１の発明におい
て、回路基板が銅電極を備えたプリント配線板であり、
前記薄膜層が錫または銅を含んだ錫のめっき層である。
プリント配線板ユニットに使用される回路基板の内の大
部分は銅電極を備えたプリント配線板である。そのた
め、請求項１の発明がプリント配線板に適用されること
が最も有効である。また、前記薄膜層の錫に銅を含ませ
ることは、プリント配線板の銅電極の溶解を抑制するの
で有効である。また、めっきは、薄膜層の厚さを容易に
制御でき且つ製造コストの最も安価な薄膜層の形成技術
である。According to a second aspect of the present invention, in the first aspect, the circuit board is a printed wiring board having copper electrodes,
The thin film layer is a tin plating layer containing tin or copper.
Most of the circuit boards used in the printed wiring board unit are printed wiring boards provided with copper electrodes. Therefore, it is most effective that the invention of claim 1 is applied to a printed wiring board. Including copper in the tin of the thin film layer is effective in suppressing the dissolution of the copper electrode of the printed wiring board. Plating is a technique for forming a thin film layer that can easily control the thickness of the thin film layer and has the lowest production cost.
【００１１】請求項３の発明は、請求項１の発明におい
て、前記薄膜層の厚さが 0.3〜1.2μm である。前記薄
膜層の厚さが0.3 μm 未満になると、望ましい接合状態
が得られず、 1.2μm を越えると、不必要な厚さとなる
ため薄膜形成にコストがかかるし、溶融層のはみだしに
伴う問題も発生する。According to a third aspect of the present invention, in the first aspect, the thin film layer has a thickness of 0.3 to 1.2 μm. When the thickness of the thin film layer is less than 0.3 μm, a desired bonding state cannot be obtained. appear.
【００１２】[0012]
【発明の実施の形態】この発明によるフリップチップ実
装方法の実施の形態について実施例を用いて説明する。
なお、従来技術と同じ機能の部分には同じ符号を付け
る。図１は、この発明によるフリップチップ実装方法の
実施例を示す工程毎の断面図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a flip chip mounting method according to the present invention will be described with reference to embodiments.
The parts having the same functions as those of the prior art are denoted by the same reference numerals. FIG. 1 is a sectional view of each step showing an embodiment of a flip chip mounting method according to the present invention.
【００１３】回路基板であるプリント配線板１の銅電極
（図１ではCu電極）11上に厚さ 0.6μm の錫のめっき層
（図１ではSnめっき層）６が形成され〔図１（ｂ）〕、
不図示の電極上に予め金バンプ（図１ではAuバンプ）21
を形成されたＩＣチップ２が、プリント配線板１上に位
置合わせされて搭載され〔図１（ｃ）〕、この状態でバ
ンプ（60×100 μm2）当たり60ｇの荷重がかけられ 280
℃に加熱され、めっき層６の錫と金バンプ21の金とが合
金化して両者の接触部に金−錫合金層（図１ではAuSn合
金層）７を生成し、両者が接合状態となる〔図２
（ｄ）〕。A 0.6 μm thick tin plating layer (Sn plating layer in FIG. 1) 6 is formed on a copper electrode (Cu electrode in FIG. 1) 11 of a printed wiring board 1 as a circuit board [FIG. )],
A gold bump (Au bump in FIG. 1) 21 is placed on an electrode (not shown) in advance.
The IC chip 2 on which is formed is positioned and mounted on the printed wiring board 1 (FIG. 1C). In this state, a load of 60 g is applied per bump (60 × 100 μm 2 ).
C., the tin of the plating layer 6 and the gold of the gold bump 21 are alloyed to form a gold-tin alloy layer (AuSn alloy layer in FIG. 1) 7 at a contact portion between the two, and the two are in a joined state. [Figure 2
(D)].
【００１４】なお、以上の工程は空気中で実施する。接
合時の 280℃加熱は、プリント配線板１側を 150℃に予
備加熱しておき、ＩＣチップ２側を280 ℃以上に加熱す
るという方法によっている。プリント配線板１側の予備
加熱を 150℃に限定しているのは、錫めっき層６の酸化
を抑制するためである。この 280℃という温度は、でき
るだけ薄い錫めっき層６を用いて十分な接合状態を得る
ために決定された温度であって、錫めっき層６を厚くす
ると下げることができるが、その場合には錫めっき層６
の形成コストが高くなり、厚さによっては融解した錫め
っき層６のはみ出しに伴う問題を発生する心配もある。
逆に、加熱温度を高くすると錫めっき層６を薄くするこ
とができるが、ＩＣチップ２の耐熱性能等で上限が抑え
られる。The above steps are performed in air. Heating at 280 ° C. at the time of bonding is performed by preheating the printed wiring board 1 side to 150 ° C. and heating the IC chip 2 side to 280 ° C. or higher. The reason why the preheating of the printed wiring board 1 is limited to 150 ° C. is to suppress oxidation of the tin plating layer 6. The temperature of 280 ° C. is a temperature determined to obtain a sufficient bonding state using the tin plating layer 6 as thin as possible, and can be lowered by increasing the thickness of the tin plating layer 6. Plating layer 6
There is a concern that, depending on the thickness, the problem associated with the protrusion of the molten tin plating layer 6 may occur.
Conversely, when the heating temperature is increased, the tin plating layer 6 can be made thinner, but the upper limit is suppressed by the heat resistance performance of the IC chip 2 and the like.
【００１５】一方、接合時の加圧の上限は、ＩＣチップ
２に損傷を与えないという条件から決められ、例えば上
記の60×100 μm2のバンプの場合には、80ｇである。下
限値は望ましい接合状態が得られるという条件から決め
られ、上記バンプの場合には40ｇである。また、上記の
実施例においては、錫のめっき層の厚さを 0.6μm とし
たが、この厚さは 0.3〜1.2 μm の範囲内が最適であ
る。 0.3μm 未満になると、十分な接合強度をもつ接合
が得られなくなり、 1.2μm を越えると、錫めっき層の
形成コストが高くなり、融解した錫めっき層のはみ出し
の心配も生じる。On the other hand, the upper limit of the pressure at the time of bonding is determined based on the condition that the IC chip 2 is not damaged. For example, in the case of the above-mentioned 60 × 100 μm 2 bump, the upper limit is 80 g. The lower limit is determined based on the condition that a desired bonding state can be obtained, and is 40 g in the case of the bump. Further, in the above embodiment, the thickness of the tin plating layer is 0.6 μm, but the thickness is optimally in the range of 0.3 to 1.2 μm. If the thickness is less than 0.3 μm, it is not possible to obtain a bond having sufficient bonding strength. If the thickness exceeds 1.2 μm, the cost of forming the tin plating layer increases, and there is a concern that the molten tin plating layer may protrude.
【００１６】この接合方法によれば、１μm 程度の薄い
錫めっき層６と金バンプ21とが金−錫合金層を形成する
ことによって接合されるので、従来技術におけるはんだ
接合のような材料のはみ出しの心配がない。また、１μ
m 程度の薄い錫めっき層６で済むので、膜形成の製造コ
ストも安い。更に、鉛を使用しない接合方法であるの
で、環境規制に対応した鉛フリーの接合が可能である。According to this bonding method, the thin tin plating layer 6 of about 1 μm and the gold bumps 21 are bonded by forming a gold-tin alloy layer, so that the material such as solder bonding in the prior art is protruded. No worries. Also, 1μ
Since only a thin tin plating layer 6 having a thickness of about m is required, the manufacturing cost of film formation is low. Furthermore, since the joining method does not use lead, lead-free joining in compliance with environmental regulations is possible.
【００１７】なお、上記の実施例においては、錫めっき
層６を使用しているが、プリント配線板１の銅電極11の
溶解を抑制するために、これを１wt％弱の銅を含んだ錫
のめっき層に置き換えることもできる。また、上記の実
施例はプリント配線板へのフリップチップ実装である
が、他の回路基板、例えばセラミック基板等へのフリッ
プチップ実装にも同様の方法が採用可能である。In the above embodiment, the tin plating layer 6 is used. However, in order to suppress the dissolution of the copper electrode 11 of the printed wiring board 1, the tin plating layer 6 is made of tin containing less than 1% by weight of copper. It can also be replaced with a plating layer. In the above embodiment, flip-chip mounting on a printed wiring board is used. However, the same method can be adopted for flip-chip mounting on another circuit board, for example, a ceramic substrate.
【００１８】[0018]
【発明の効果】請求項１の発明によれば、融解した薄膜
層に金バンプの金が溶解して生成される金−錫合金層
が、回路基板の電極と金バンプとを電気的にも機械的に
も望ましい状態で接合させる。しかも、接合が融解した
薄い薄膜層への固体の金バンプの金の溶解に伴う合金化
によるので、従来技術におけるはんだのはみだしのよう
な問題が発生することがない。更に、この実装方法は鉛
を使用しないので鉛フリーの接合となる。したがって、
この発明によれば、信頼性が高く、且つ製造コストが安
いフリップチップ実装方法を提供することができ、環境
規制に対応した鉛フリーの接合が可能となる。According to the first aspect of the present invention, the gold-tin alloy layer formed by dissolving the gold of the gold bump in the melted thin film layer electrically connects the electrode of the circuit board and the gold bump. The joining is performed mechanically in a desirable state. In addition, since the solid gold bumps are alloyed with the melting of the gold in the thin thin film layer in which the bonding has been melted, problems such as the protrusion of solder in the prior art do not occur. Furthermore, since this mounting method does not use lead, it is a lead-free joint. Therefore,
According to the present invention, a flip-chip mounting method with high reliability and low manufacturing cost can be provided, and lead-free bonding in compliance with environmental regulations can be achieved.
【００１９】請求項２の発明によれば、請求項１の発明
において、回路基板が銅電極を備えたプリント配線板で
あり、前記薄膜層が錫または銅を含んだ錫のめっき層で
ある。プリント配線板ユニットに使用される回路基板の
内の大部分は銅電極を備えたプリント配線板であるた
め、請求項１の発明がプリント配線板に適用されること
が最も有効である。また、前記薄膜層の錫に銅を含ませ
ることは、プリント配線板の銅電極の溶解を抑制するの
で有効である。しかも、めっきは、薄膜層の厚さを容易
に制御でき且つ製造コストの最も安価な薄膜層の形成技
術である。したがって、この発明によれば、プリント配
線板ユニットを安価に製造することができる。According to a second aspect of the present invention, in the first aspect, the circuit board is a printed wiring board provided with copper electrodes, and the thin film layer is tin or a tin plating layer containing copper. Since most of the circuit boards used in the printed wiring board unit are printed wiring boards having copper electrodes, it is most effective that the invention of claim 1 is applied to a printed wiring board. Including copper in the tin of the thin film layer is effective in suppressing the dissolution of the copper electrode of the printed wiring board. In addition, plating is a technique for forming a thin film layer that can easily control the thickness of the thin film layer and has the lowest manufacturing cost. Therefore, according to the present invention, a printed wiring board unit can be manufactured at low cost.
【００２０】請求項３の発明によれば、請求項１の発明
において、前記薄膜層の厚さが 0.3〜1.2 μm である。
前記薄膜層の厚さが0.3 μm 未満になると、望ましい接
合状態が得られず、 1.2μm を越えると、不必要な厚さ
となるため薄膜形成にコストがかかるし、溶融層のはみ
だしに伴う問題も発生する。したがって、この発明によ
れば、不必要に厚くてコストが高くなったり信頼性を低
下させたりする薄膜層を用いることがなく、且つ必要な
性能を得ることができる。According to a third aspect of the present invention, in the first aspect, the thickness of the thin film layer is 0.3 to 1.2 μm.
When the thickness of the thin film layer is less than 0.3 μm, a desired bonding state cannot be obtained. appear. Therefore, according to the present invention, the necessary performance can be obtained without using a thin film layer which is unnecessarily thick, increases the cost, or lowers the reliability.
【図１】この発明によるフリップチップ実装方法の実施
例を示す工程毎の断面図FIG. 1 is a sectional view of each step showing an embodiment of a flip chip mounting method according to the present invention.
【図２】従来技術によるフリップチップ実装方法の一例
を示す工程毎の断面図FIG. 2 is a cross-sectional view of each step showing an example of a flip-chip mounting method according to the related art.
【図３】従来技術によるフリップチップ実装方法の他例
を示す工程毎の断面図FIG. 3 is a cross-sectional view of each step showing another example of the flip-chip mounting method according to the related art
１ プリント配線板 11 銅電極 ２ ＩＣチップ 21 金バンプ ３ クリームはんだ層 31 はんだ層 ４ はんだめっき層 41 はんだ層 ５ フラックス ６ 錫めっき層 ７ 金−錫合金層 DESCRIPTION OF SYMBOLS 1 Printed wiring board 11 Copper electrode 2 IC chip 21 Gold bump 3 Cream solder layer 31 Solder layer 4 Solder plating layer 41 Solder layer 5 Flux 6 Tin plating layer 7 Gold-tin alloy layer
Claims (3)
層を形成し、ＩＣチップの電極上に金バンプを形成し
て、前記薄膜層と金バンプとが直接接触するようにプリ
ント配線板とＩＣチップとを位置合わせし、前記薄膜層
及び金バンプを加熱状態で相互に加圧することによっ
て、前記薄膜層を融解させてその中に金バンプの金を溶
解させ、前記薄膜層を合金化させることによって、生成
された合金層で回路基板の電極と金バンプとを接合させ
る、ことを特徴とするフリップチップ実装方法。1. A thin film layer containing tin as a main component is formed on an electrode of a circuit board, a gold bump is formed on an electrode of an IC chip, and the thin film layer is printed so as to be in direct contact with the gold bump. The wiring board and the IC chip are aligned, and the thin film layer and the gold bumps are pressed against each other in a heated state, thereby melting the thin film layer and dissolving the gold of the gold bumps therein. A flip-chip mounting method, comprising: bonding an electrode of a circuit board and a gold bump with a generated alloy layer by alloying.
であり、前記薄膜層が錫または銅を含んだ錫のめっき層
である、ことを特徴とする請求項１に記載のフリップチ
ップ実装方法。2. The flip-chip mounting according to claim 1, wherein the circuit board is a printed wiring board having copper electrodes, and the thin film layer is a tin plating layer containing tin or copper. Method.
ことを特徴とする請求項１に記載のフリップチップ実装
方法。3. The flip chip mounting method according to claim 1, wherein said thin film layer has a thickness of 0.3 to 1.2 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001171986A JP2002368038A (en) | 2001-06-07 | 2001-06-07 | Flip-chip mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001171986A JP2002368038A (en) | 2001-06-07 | 2001-06-07 | Flip-chip mounting method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002368038A true JP2002368038A (en) | 2002-12-20 |
Family
ID=19013675
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001171986A Withdrawn JP2002368038A (en) | 2001-06-07 | 2001-06-07 | Flip-chip mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002368038A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006016650A1 (en) * | 2004-08-12 | 2006-02-16 | Ricoh Company, Ltd. | Electrode substrate |
| JP2007103618A (en) * | 2005-10-04 | 2007-04-19 | Seiko Instruments Inc | Method and device for manufacturing electronic apparatus |
| KR100749592B1 (en) | 2005-06-09 | 2007-08-14 | 세이코 엡슨 가부시키가이샤 | Semiconductor device and method for manufacturing the same |
-
2001
- 2001-06-07 JP JP2001171986A patent/JP2002368038A/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006016650A1 (en) * | 2004-08-12 | 2006-02-16 | Ricoh Company, Ltd. | Electrode substrate |
| US7732935B2 (en) | 2004-08-12 | 2010-06-08 | Ricoh Company, Ltd. | Wiring board, electronic circuit board, electronic apparatus and manufacturing method of electronic circuit board |
| KR100749592B1 (en) | 2005-06-09 | 2007-08-14 | 세이코 엡슨 가부시키가이샤 | Semiconductor device and method for manufacturing the same |
| JP2007103618A (en) * | 2005-10-04 | 2007-04-19 | Seiko Instruments Inc | Method and device for manufacturing electronic apparatus |
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