JPH08316641A - Multilayer wiring board manufactured by collective connection method - Google Patents

Multilayer wiring board manufactured by collective connection method

Info

Publication number
JPH08316641A
JPH08316641A JP13753795A JP13753795A JPH08316641A JP H08316641 A JPH08316641 A JP H08316641A JP 13753795 A JP13753795 A JP 13753795A JP 13753795 A JP13753795 A JP 13753795A JP H08316641 A JPH08316641 A JP H08316641A
Authority
JP
Japan
Prior art keywords
bonding
wiring board
plating
double
multilayer wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13753795A
Other languages
Japanese (ja)
Inventor
Kazuma Miura
一真 三浦
Tasao Soga
太佐男 曽我
Shozo Nakamura
省三 中村
Masayuki Kyoi
正之 京井
Hideo Togawa
英男 外川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13753795A priority Critical patent/JPH08316641A/en
Publication of JPH08316641A publication Critical patent/JPH08316641A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination

Abstract

PURPOSE: To join the laminated sheets of a multilayer wiring board to each other at a temperature capable of the heat resistance of the sheet being secured and obtain a junction organization with a larger heat resistance than solders, by bonding to each other with resin the portions other than the Au-Sn junctions of the electrode portions of the sheets. CONSTITUTION: Onto the copper conductor of the junction portion of one side of a board, an Sn plating of 1-3μm, preferably 3μm, in thickness is applied, and onto the copper conductor of the other side of the board, an Au plating of 0.3μm in thickness is applied, and double-sided conductor forming films are superimposed on each other in multilayer. Then, in either of the atmosphere, an inert gas atmosphere and a reducing gas atmosphere of 300-350 deg.C in maximum temperature and 10-20MPa in pressure, the junction portions of the double-sided conductor films are joined with metal to each other by a thermo-compression bonding, and the portions other than these Au-Sn junction portions are bonded with resin to each other to be hardened. In the interlayer connective bonding of this multilayer wiring board, when a liquid phase is formed in case of the Au-Sn joining, it is apt to generate bridging faults because of the flowings of alloys into its electrodes. Therefore, by so using bonding resins 5 in the bonding portions other than the metallic junction portions as for them to be bonded to each other and be hardened, the bridging faults are prevented.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】多層配線基板は基板材料の内部導
体回路と表層導体回路を合せて3層以上に導体回路を形
成したものであり、主に産業用電子機器に使用されてい
るが、最近では高機能化された民生用電子機器にも使用
されている。本発明は高密度実装に適した多層配線基板
の層間接続接着法及びそれを用いた多層配線基板および
実装製品に関する。
[Field of Industrial Application] A multilayer wiring board is one in which a conductor circuit is formed in three or more layers by combining an inner conductor circuit of a substrate material and a surface layer conductor circuit, and is mainly used in industrial electronic devices. Recently, it has also been used in highly functional consumer electronic devices. The present invention relates to an interlayer connection adhesion method for a multilayer wiring board suitable for high-density mounting, a multilayer wiring board using the same, and a mounted product.

【0002】[0002]

【従来の技術】電子部品の小型・薄型化、高集積化、高
速化に伴い、多層配線基板においては、配線の高密度
化、基板の薄型化、接続部の耐熱性、低配線抵抗に対す
る要求はますます厳しくなっている。最近では配線基板
にポリイミドシートを用い、エッチングなどによりパタ
ーンを形成した積層基板を加熱プレスにより積層する方
式が採られている。なお、層間の接続は、主にはんだ、
Au−Auが用いられる。
2. Description of the Related Art With the miniaturization, thinning, high integration, and speeding up of electronic components, in multi-layer wiring boards, there are demands for higher wiring density, thinner boards, heat resistance of connecting portions, and lower wiring resistance. Is getting more and more severe. Recently, a method has been adopted in which a polyimide sheet is used as a wiring board, and a laminated board having a pattern formed by etching or the like is laminated by hot pressing. In addition, the connection between layers is mainly solder,
Au-Au is used.

【0003】シートの積層方法として、特開平04−1
62589号公報記載の方法では、シート材料として、
Auフィルムにポリイミドを塗布しその上にAuめっき
を施したものとし、Au−Auを用いて接続し、積層す
るとしているが詳細な接合条件については不明である。
一般的にAu−Au接合は350℃以上の高温領域で行わ
れており、ポリイミドシートの耐熱温度をこえるため問
題である。接続材料をはんだにすると温度を下げること
ができるが、フラックスを使用しないで接合する必要が
あるため、材料構成、条件等が制限され容易には接合で
きず接合部の耐熱温度も低い。
As a method for laminating sheets, Japanese Patent Laid-Open No. 04-1
In the method described in Japanese Patent No. 62589, as the sheet material,
Although it is stated that polyimide is applied to an Au film and Au plating is applied on the Au film, Au-Au is used for connection and lamination is performed, but detailed bonding conditions are unknown.
Au-Au bonding is generally performed in a high temperature region of 350 ° C. or higher, which is a problem because it exceeds the heat resistant temperature of the polyimide sheet. If the connecting material is solder, the temperature can be lowered, but since it is necessary to join without using flux, the material composition, conditions, etc. are limited, and it is not easy to join, and the heat resistant temperature of the joint is low.

【0004】[0004]

【発明が解決しようとする課題】以上の問題を鑑み、本
発明の目的は、シートの積層温度をシートの耐熱性が確
保できる300〜350℃程度の温度で接合でき、しかも、は
んだを上回る耐熱性の高い接合組織を得る一括接続方式
およびそれを用いた多層配線基板を提供することにあ
る。
In view of the above problems, an object of the present invention is to bond sheets at a temperature of about 300 to 350 ° C., which can secure the heat resistance of the sheets, and has a heat resistance higher than that of solder. (EN) It is intended to provide a collective connection method for obtaining a joint structure having high property and a multilayer wiring board using the same.

【0005】[0005]

【課題を解決するための手段】Au−Snめっき接合の
場合、接合部にAu−Snの脆い金属間化合物層が形成
されやすく、接合強度はこの化合物層の厚さで決まる。
接合部の組織・組成は接合温度・圧力・時間といったプ
ロセス条件およびめっき厚さにより大きくかわる。そこ
で、本発明ではプロセス条件やAuおよびSnめっき厚
さと接合強度との関係について実験的に検討し、Au−
Sn化合物層の形成を最小限に抑えるような接合条件
(プロセス、部材)を見出した。なお、Au−Snは接
合時にAu−Sn溶融合金を形成する液相接合である。
したがって、接合部が狭ピッチになると溶けた合金が他
の電極に流れ込み、電極間が短するブリッジと呼ばれる
不良が発生しやすい。そこで、本発明では、電極部のA
u−Sn接合以外の部分は樹脂接着させることにより、
ブリッジ不良を防止した。また、Snめっきのかわりに
Agめっきを用いたAu−Ag接合は固相接合であり、
Au−Sn接合に比べ、接合時に高い圧力を必要とす
るが、接合時に液相を形成しないため、特に樹脂接着の
必要性はない。さらに、Au−Agは金属間化合物を形
成しない系であることから高い接合強度を得ることがで
きる。なお、Auめっきは高コストであるため、低コス
ト化が要求される場合にはAuめっきのかわりにSnめ
っきを用いたSn−Ag接合を用いる。
In the case of Au—Sn plating bonding, a brittle intermetallic compound layer of Au—Sn is easily formed in the bonding portion, and the bonding strength is determined by the thickness of this compound layer.
The structure and composition of the joint vary greatly depending on the process conditions such as joint temperature, pressure and time and the plating thickness. Therefore, in the present invention, the relationship between the process conditions and the Au and Sn plating thickness and the bonding strength is experimentally investigated, and Au-
The bonding conditions (process, member) that minimize the formation of the Sn compound layer have been found. Note that Au-Sn is a liquid phase bonding that forms an Au-Sn molten alloy at the time of bonding.
Therefore, when the joints have a narrow pitch, the melted alloy flows into another electrode, and a defect called a bridge in which the distance between the electrodes is short is likely to occur. Therefore, in the present invention, A of the electrode portion is
By bonding the parts other than the u-Sn junction with resin,
Prevented bridge failure. Also, Au-Ag bonding using Ag plating instead of Sn plating is solid phase bonding,
Compared with Au-Sn joining, a higher pressure is required at the time of joining, but since a liquid phase is not formed at the time of joining, there is no need for resin bonding. Furthermore, since Au-Ag is a system that does not form an intermetallic compound, high bonding strength can be obtained. Since Au plating is expensive, Sn-Ag bonding using Sn plating is used instead of Au plating when cost reduction is required.

【0006】[0006]

【作用】多層配線基板の積層方法にAu−Sn、Au−
Ag、Sn−Agのめっきによる一括接合を採用するこ
とにより、比較的低温で接合することができる。Au−
Sn接合では、接合条件を制御して、接合部に形成され
るAu−Sn化合物層を薄くし、組成をAuリッチにす
ることにより、耐熱性ある接合部を得ることが出来る。
Au−Ag接合は金属間化合物を形成しないため高い強
度を得ることが期待できる。また、めっきによる接合
は、はんだによる接合の場合と異なりフラックスを必要
としない。そのため、洗浄工程は不用であり、コスト的
に有利であるばかりでなく、オゾンを破壊するフロンを
使用しないため、環境問題にも十分配慮した方法である
と考える。
[Operation] Au-Sn, Au-
By adopting collective bonding by plating Ag or Sn-Ag, it is possible to bond at a relatively low temperature. Au-
In the Sn junction, a heat-resistant junction can be obtained by controlling the junction conditions to thin the Au—Sn compound layer formed in the junction and make the composition Au-rich.
Since Au-Ag junction does not form an intermetallic compound, high strength can be expected. Further, the joining by plating does not require flux unlike the joining by soldering. Therefore, the cleaning process is not necessary and cost-effective, and since CFCs that destroy ozone are not used, the method is considered to be environmentally friendly.

【0007】[0007]

【実施例】以下に本発明の一実施例に係わる多層配線基
板の層間接続接着法及びそれを用いた多層配線基板製品
について説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An interlayer connection bonding method for a multilayer wiring board and a multilayer wiring board product using the method according to an embodiment of the present invention will be described below.

【0008】図1は本発明の一実施例である多層配線基
板を示す。これは、ポリイミドテープ1にCuシート2
を貼りあわせたシートにビア穴開けを行った後、Cu2
を陰極としてCuの電気めっきを行い、ビア3内へ導体
金属3の充填を行う。その後、ビア先端部に接合金属の
電気めっきを施す。一方、レジスト5 塗布およびエッ
チングにより形成されたCu箔2パターン上には、Ni
下地めっき6を介して接合金属のめっき7が施されてい
る。なお、ビア穴3の直径が約 0.03mm である。したが
って、接続部の面積は約 0.3×10-2mm2、ピッチは0.1mm
であり非常に微細である。なお、基板一層の厚さは 0.1
mmである。
FIG. 1 shows a multilayer wiring board which is an embodiment of the present invention. This is a polyimide tape 1 with a Cu sheet 2
After drilling a via hole in the sheet where
Is used as a cathode to perform electroplating of Cu to fill the via 3 with the conductive metal 3. Then, the via metal tip is electroplated with a bonding metal. On the other hand, Ni is formed on the Cu foil 2 pattern formed by applying the resist 5 and etching.
The plating 7 of the joining metal is applied via the base plating 6. The diameter of the via hole 3 is about 0.03 mm. Therefore, the area of the connection part is about 0.3 × 10-2mm2 and the pitch is 0.1mm.
And is very fine. The thickness of one layer of the substrate is 0.1
mm.

【0009】一般的に、接合部はピール試験による強度
の測定により評価される。本発明の多層配線基板では一
括評価は可能であるが、微細接合であるため、接合部を
1点ずつ評価することはできず、適正な接合条件および
めっき厚さを選定することが出来ない。
Generally, the joint is evaluated by measuring the strength by a peel test. The multilayer wiring board of the present invention can be evaluated collectively, but since it is fine bonding, it is not possible to evaluate the bonding portions one by one and it is not possible to select an appropriate bonding condition and plating thickness.

【0010】そこで、本発明ではモデルサンプルによ
り、それぞれの基板(シート)で熱圧着により積層する
場合の接合金属組合わせおよびそれぞれの適正な接合条
件を実験的に検討した。
Therefore, in the present invention, a model sample was used to experimentally examine the combination of the joining metals and the appropriate joining conditions when the substrates (sheets) are laminated by thermocompression bonding.

【0011】図2は多層配線基板の層間接続接着法の最
適接合条件を実験的に検討するための接合モデルサンプ
ルおよび加熱ヘッドの側面図である。接合は接合部が均
一に加熱されることを目的に同じ温度に加熱された上下
の加熱ヘッド8、9を用いて行った。実際には、上部ツ
ール8が下降し、シートを加熱・加圧する。接合部材は
厚さ0.1mm、幅3mm、長さ20mmでポリイミドフィルム9に
35um厚さのCuテープ10を張合わせたものを用いた。
上部ツール側8には、接合部材のポリイミドフィルム9
側からビア穴11開けを行った後、Cu10を陰極とし
てCuの電気めっきを行ってビア11内へ導体金属11
の充填を行い、最終的にビア先端部に接合金属めっき1
2を施した部材を配置させた。なお、ビア穴3の穴径は
0.1mm、先端のめっき部12は幅0.2mmである。下部接合
ツール9側にはCuテープ10上に0.5umのNi下地め
っき11を介して、AuあるいはSnめっき12が全面
に施された部材を配置させている。接合雰囲気は大気
中、不活性雰囲気、還元雰囲気のいずれかで行った。接
合強度については、実際の接続幅が0.03mm(実際の多層
配線基板のビア穴径)である積層シート1接続点あたり
10gの強度が必要であると仮定すると、約30N/cmの
ピール強度に相当するので、モデルサンプルで評価した
場合、この強度を必要強度と決定した。
FIG. 2 is a side view of a bonding model sample and a heating head for experimentally examining the optimum bonding conditions of the interlayer connection bonding method for a multilayer wiring board. The joining was performed using the upper and lower heating heads 8 and 9 heated to the same temperature for the purpose of uniformly heating the joined portion. Actually, the upper tool 8 descends to heat and press the sheet. The bonding material is 0.1mm thick, 3mm wide, and 20mm long, and is a polyimide film 9.
A Cu tape 10 having a thickness of 35 μm was used.
The upper tool side 8 has a polyimide film 9 as a joining member.
After forming a via hole 11 from the side, Cu 10 is used as a cathode to perform electroplating of Cu to form a conductor metal 11 in the via 11.
Filling, and finally bonding metal plating to the tip of the via 1
The member subjected to 2 was arranged. The diameter of the via hole 3 is
0.1 mm, and the plated portion 12 at the tip has a width of 0.2 mm. On the lower joining tool 9 side, a member having Au or Sn plating 12 applied to the entire surface of the Cu tape 10 through a 0.5 μm Ni undercoat 11 is arranged. The bonding atmosphere was air, an inert atmosphere, or a reducing atmosphere. Regarding joint strength, per connection point of laminated sheet with actual connection width of 0.03 mm (actual via hole diameter of multilayer wiring board)
Assuming a strength of 10 g is required, which corresponds to a peel strength of about 30 N / cm, this strength was determined to be the required strength when evaluated with a model sample.

【0012】図3は上部ツール側の部材に3umのSnめ
っき、下部ツール側の部材にCuリード上にNi下地を
介して1.2umのAuめっきを施した場合の接合強度の温
度・圧力依存性を示す。他の接合条件は圧力20MPa、時
間は20秒としている。この結果より、接合温度が250℃
以下では強度は低いが、これよりも温度を高くすると強
度は上昇し、300℃以上で平均30N/cmを越える強度
を得ることができた。なお、接合雰囲気は、大気中、不
活性雰囲気、還元雰囲気いずれで行ってもよい。
FIG. 3 shows the temperature / pressure dependence of the bonding strength when the upper tool side member is plated with 3 um Sn and the lower tool side member is plated with 1.2 um Au on the Cu lead via the Ni underlayer. Indicates. Other joining conditions are a pressure of 20 MPa and a time of 20 seconds. From this result, the joining temperature is 250 ℃.
Although the strength was low at the temperature below, the strength increased at a temperature higher than this, and the strength exceeding 30 N / cm on average could be obtained at 300 ° C. or higher. The bonding atmosphere may be air, an inert atmosphere, or a reducing atmosphere.

【0013】接合温度を下げなければならない場合、こ
のめっき厚さ組合わせでは強度が低い。そのような場合
には、Snめっきを厚くし、逆にAuめっきを薄くし
て、接合部の組成をSnリッチにし、融点を下げること
により250℃以下の低い温度で接合することができる。
なお、Snめっき10um、Auめっき0.3umの組合わせ
で、220℃、20秒、20MPaの条件で接合した場合について
もほぼ必要強度に近い値(30N/cm)が得られた。
When the joining temperature must be lowered, this plating thickness combination has low strength. In such a case, the Sn plating can be thickened and the Au plating can be thinned to make the composition of the bonding portion Sn-rich and lower the melting point to bond at a low temperature of 250 ° C. or lower.
A value close to the required strength (30 N / cm) was obtained when the Sn plating was 10 μm and the Au plating was 0.3 μm, and the joining was performed under the conditions of 220 ° C., 20 seconds and 20 MPa.

【0014】図4はAuめっき厚さを1.2umと一定にし、
温度300℃、時間20秒、圧力20MPaの条件で接合した場合
の強度のSnめっき厚さ依存性を示す。この結果、Snめっ
きが3umのとき、接合強度はもっとも高く、Snめっきが
厚い場合および薄い場合は強度は低くなる傾向にある。
FIG. 4 shows that the Au plating thickness is kept constant at 1.2 μm,
The Sn plating thickness dependency of the strength when bonded under the conditions of a temperature of 300 ° C., a time of 20 seconds and a pressure of 20 MPa is shown. As a result, the bonding strength is highest when the Sn plating is 3 μm, and the strength tends to be low when the Sn plating is thick or thin.

【0015】図5にAu−Sn接合の断面組織の例を示
す。Au-Snの場合、接合部が加熱されるとまず、融点の
低いSnめっき部が溶融し、このSnにAuが溶け込み接合さ
れるものと考えられる。Au-Sn系ではSnのめっきを厚
く、Auめっきを薄くして接合温度を下げることにより、
Snリッチな溶融合金をフィレットに形成させ、これが接
合部の強度を維持させる接合方式が多く用いられてい
る。しかし、この接合では接合組織がSnリッチであるた
め耐熱性がない。耐熱性を上げるためには接合温度を高
くする必要があるが、この場合、接合部にAu-Snの脆弱
な化合物層が接合層全域にわたり厚く形成されるため、
強度は大幅に低下する.そこで、本発明ではAuめっきを
厚く、Snめっきを薄くし、接合温度をやや高く、時間を
長く設定することにより、図5に示すように、接合層は
主にAuリッチな合金層14から成り、Au-Snの化合物層
15の形成を抑えることにより、健全で高強度な接合部
を得ることが出来た。
FIG. 5 shows an example of the sectional structure of the Au--Sn junction. In the case of Au-Sn, it is considered that when the joint portion is heated, the Sn-plated portion having a low melting point is first melted, and Au is melted into this Sn to be joined. In Au-Sn system, Sn plating is thick and Au plating is thin to lower the bonding temperature.
A joining method is often used in which a Sn-rich molten alloy is formed into a fillet and this maintains the strength of the joint. However, this joint has no heat resistance because the joint structure is Sn-rich. To increase the heat resistance, it is necessary to raise the bonding temperature, but in this case, since the weak compound layer of Au-Sn is formed thickly over the entire bonding layer in the bonding part,
The strength is greatly reduced. Therefore, in the present invention, the Au plating is thick, the Sn plating is thin, the joining temperature is set to be slightly high, and the time is set to be long, so that the joining layer is mainly composed of the Au-rich alloy layer 14 as shown in FIG. By suppressing the formation of the Au—Sn compound layer 15, it was possible to obtain a sound and strong joint.

【0016】図6はSnめっきのかわりにAgめっきを
用いたAu−Ag接合の強度の温度・圧力依存性を示
す。なお、接合時間は10秒、Auめっきの厚さは0.6um
である。接合強度は温度および圧力に依存する。圧力が
20MPaと低い場合18は温度に関係なく強度は低い。そ
れに対して、接合圧力が50MPa19以上になると温度が
高くなるにつれて強度は上昇し、50MPaで接合させた場
合19では350℃以上で、100MPaの場合20では300℃で
40N/cmを越える強度を得ることができた。なお、A
u−Sn接合の場合に比べると、高い温度、圧力が必要
であるが、接合強度ははるかに高くなっている。
FIG. 6 shows the temperature / pressure dependence of the strength of the Au—Ag joint using Ag plating instead of Sn plating. The bonding time is 10 seconds and the Au plating thickness is 0.6um.
Is. Bond strength depends on temperature and pressure. Pressure is
When it is as low as 20 MPa, 18 has low strength regardless of temperature. On the other hand, when the joining pressure is 50MPa 19 or more, the strength rises as the temperature rises, and when joining at 50MPa, it is 350 ℃ or more at 19 and 100MPa at 20 ℃ at 300 ℃.
A strength exceeding 40 N / cm could be obtained. Note that A
Compared with the case of u-Sn junction, higher temperature and pressure are required, but the joining strength is much higher.

【0017】図7は、接合温度350℃、時間10秒、圧力5
0MPaで接合させた場合のAu−Ag接合部の断面組織の
例である。Au-Ag系は、状態図より金属間化合物を作ら
ない系であることが知られており、Auめっき18とA
gめっき19との界面からも接合部に化合物層を形成し
ないことを確認できた。また、Au−Ag系は液相を形
成しない固相接合である。このような接合では、加熱ツ
ールで接合部を加熱加圧することにより、めっき表面の
酸化膜を破壊してAu、Agの新生面を出し両者が接触
することにより接合するものと考えられる。なお、温度
や圧力が低いためにめっき表面酸化膜の破壊やAu、A
gめっき同士の接触が不十分な場合は接合させず未接合
部として残る。図7の場合は接合温度・圧力が高いた
め、健全に接合され未接合部は存在していない。なお、
未接合部は、温度が低い程、圧力が低い程多くなる傾向
にあり、そのため強度は低くなっている。なお、接合強
度はAgめっきの厚さに依存し、5um以上で安定した強度
が得られるが、これよりもめっき厚さが薄くなると、Ag
めっきの塑性変形による新生面の形成が不十分であり強
度は低くなる。Agめっきの厚さは5um以上が望ましい。
FIG. 7 shows a joining temperature of 350 ° C., a time of 10 seconds and a pressure of 5
It is an example of a cross-sectional structure of an Au-Ag joint when they are joined at 0 MPa. It is known from the phase diagram that the Au-Ag system is a system that does not form an intermetallic compound.
It was confirmed from the interface with the g-plating 19 that the compound layer was not formed at the joint. Further, the Au-Ag system is solid-phase bonding that does not form a liquid phase. In such joining, it is considered that the joining portion is brought into contact by heating and pressurizing the joining portion with a heating tool to destroy the oxide film on the plating surface to expose a new surface of Au and Ag and to bring them into contact with each other. In addition, since the temperature and pressure are low, the oxide film on the plating surface is destroyed and Au, A
When the contact between g plating is insufficient, they are not joined and remain as unjoined portions. In the case of FIG. 7, since the joining temperature and pressure are high, the joining is sound and there is no unjoined portion. In addition,
The unbonded portion tends to increase as the temperature becomes lower and the pressure becomes lower, so that the strength becomes low. The bonding strength depends on the Ag plating thickness, and stable strength can be obtained at 5um or more.
The newly formed surface is insufficiently formed due to the plastic deformation of the plating, resulting in low strength. The thickness of Ag plating is preferably 5um or more.

【0018】図8は、上部ツール側の部材に7umのAg
めっき、下部ツール側の部材にCuリード上に0.6umの
Snめっきを施した場合、すなわち、Sn−Ag接合の
強度の温度依存性を示す。なお、接合圧力は20MPa、接
合時間は20秒としている。これより300℃以上で強度は
急激に上昇し、330℃以上で40N/cm以上の強度の強度を
得ることができた。この方法はAuめっきを含まず、し
かもSnめっきの厚さもAu−Sn系の場合に比べて薄
く、することができるためコスト的に有利な組合わせで
あるが、Snめっきが薄い場合は、接合強度は酸化被膜
の形成等めっきの表面状態を受けやすいため、部材の管
理等の注意が必要である。
FIG. 8 shows that the member on the upper tool side has Ag of 7 μm.
When the plating and the member on the lower tool side are plated with 0.6 μm of Sn on the Cu lead, that is, the temperature dependence of the strength of the Sn—Ag bond is shown. The joining pressure is 20 MPa and the joining time is 20 seconds. As a result, the strength increased sharply at 300 ° C and above, and the strength of 40 N / cm and above could be obtained at 330 ° C and above. This method is a cost-effective combination because it does not include Au plating and the thickness of Sn plating can be made thinner than that of Au-Sn system, but when Sn plating is thin, bonding is performed. Since the strength is easily affected by the surface condition of the plating such as the formation of an oxide film, it is necessary to exercise caution in managing the members.

【0019】図9は本発明の多層配線基板の層間接続接
着法の例を示す。本発明の多層配線基板はAu−Sn、
Sn−Agのような接合時に液相を形成する場合、溶け
た合金が隣接する電極に流れ込み、ブリッジ不良を起こ
しやすい。そこで、本発明では金属接合以外の接着部に
は接着用樹脂5を用い、接着させて硬化させることによ
りブリッジを防いでいる。用いる樹脂としてはエポキシ
系のような有機系の接着剤を用いる。なお、Au−Ag
のような液相を形成しない固相接合の場合は、ブリッジ
不良はおこらないから樹脂接着の必要はない。ただし、
接合部の強度を補強するために樹脂接着は必要と考え
る。
FIG. 9 shows an example of an interlayer connection adhesion method for a multilayer wiring board according to the present invention. The multilayer wiring board of the present invention is made of Au--Sn,
When forming a liquid phase at the time of joining such as Sn-Ag, the melted alloy easily flows into the adjacent electrodes, which easily causes a bridge failure. Therefore, in the present invention, the bonding resin 5 is used for the bonding portion other than the metal bonding, and the bonding resin 5 is bonded and cured to prevent the bridge. As the resin used, an organic adhesive such as epoxy is used. Note that Au-Ag
In the case of solid-phase bonding that does not form a liquid phase as described above, no resin bonding is necessary because no bridging failure occurs. However,
We believe that resin bonding is necessary to reinforce the strength of the joint.

【0020】なお、本発明の多層配線基板は熱圧着によ
る接合である。そのため、基板の面積は熱圧着ツールの
面積で決まる。現状では50×50mmまでが可能である。
The multilayer wiring board of the present invention is joined by thermocompression bonding. Therefore, the area of the substrate is determined by the area of the thermocompression bonding tool. Currently, up to 50 x 50 mm is possible.

【0021】図10、11は本発明の層間接続接着法で
組み立てられた多層配線基板を用いた実装製品の例を示
す。図10はLSIを内蔵した複数のQFP23を搭載
し、本発明の多層配線基板24裏面には入出力ピン25
を取り付けたマルチチップモジュールの構造を示した斜
視図である。図11は本発明の多層配線基板を100〜200
umピッチの狭ピッチ実装にも適用した例であり、本発明
の層間接続接着法で作製した多層配線基板24にLSI
チップ26をフリップチップ(COB)によりベアチッ
プ搭載した例である。また、本発明の多層配線基板は内
部にLSI、抵抗、コンデンサ、等の素子を一個あるい
は複数個を内蔵させることもできる。図12は本発明の
多層配線基板の内部にLSI30を内蔵させた例であ
る。このように、LSIを内部に実装することによっ
て、実装密度が向上することができ、カード等、薄型化
の要求される分野への適用することができる。この場
合、本発明の配線基板33、34を加工してLSI30
を内蔵する空間を確保した後、LSIのバンプ31と基
板32のめっき部を位置合せを行い接合する。次に基板
32、33を積層する。その後でLSIが収納されてい
る空間部36に樹脂を充填し最後に基板34を積層す
る。なお、本発明の多層配線基板にLSIを収納させる
場合、空間はLSIチップに対してある程度余裕を持た
せる。したがって、基板の層数は基板のポリイミドフィ
ルムの厚さおよびLSIの高さで決まる。なお、他の電
子部品を内蔵させることも可能で、基板35の表面に部
品を搭載したりして用途により、組合わせることもでき
る。
10 and 11 show an example of a mounted product using a multilayer wiring board assembled by the interlayer connection bonding method of the present invention. In FIG. 10, a plurality of QFPs 23 each having a built-in LSI are mounted, and input / output pins 25 are provided on the back surface of the multilayer wiring board 24 of the present invention.
It is the perspective view which showed the structure of the multichip module which attached. FIG. 11 shows a multilayer wiring board of the present invention 100-200.
This is also an example applied to a narrow pitch mounting of um pitch, and an LSI is applied to the multilayer wiring board 24 manufactured by the interlayer connection bonding method of the present invention.
This is an example in which the chip 26 is mounted as a bare chip by flip chip (COB). Further, the multilayer wiring board of the present invention may have one or more elements such as LSI, resistors, capacitors, etc. built therein. FIG. 12 shows an example in which the LSI 30 is built in the multilayer wiring board of the present invention. As described above, by mounting the LSI inside, the mounting density can be improved, and the present invention can be applied to a field such as a card, which is required to be thin. In this case, the wiring board 33, 34 of the present invention is processed to produce the LSI 30.
After securing a space for housing the LSI, the bump 31 of the LSI and the plated portion of the substrate 32 are aligned and joined. Next, the substrates 32 and 33 are laminated. After that, a resin is filled in the space 36 in which the LSI is stored, and finally the substrate 34 is laminated. When the LSI is housed in the multilayer wiring board of the present invention, a space is provided to the LSI chip to some extent. Therefore, the number of layers of the substrate is determined by the thickness of the polyimide film of the substrate and the height of the LSI. It should be noted that other electronic components can be incorporated, and the components can be mounted on the surface of the substrate 35 and can be combined depending on the application.

【0022】[0022]

【発明の効果】多層配線基板の積層方法にAu−Sn、
Au−Ag、Sn−Agのめっきによる一括接合を熱圧
着加熱ツールを用いることにより、比較的短時間で低温
で接合することができる。また、いずれもはんだによる
接合に比べ、耐熱性にすぐれている。特に、Au−Sn
接合の場合は、接合条件およびめっき厚さの組合わせを
適正化することにより、接合部の耐熱性を大幅に向上さ
せることができた。
EFFECT OF THE INVENTION A method of stacking multi-layer wiring boards is described in Au-Sn,
By using a thermocompression-bonding heating tool, it is possible to carry out batch bonding by Au-Ag and Sn-Ag plating at a low temperature in a relatively short time. In addition, both have excellent heat resistance as compared with soldering. In particular, Au-Sn
In the case of joining, by optimizing the combination of joining conditions and plating thickness, the heat resistance of the joined part could be greatly improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例である多層配線基板の接合構
造である。
FIG. 1 is a joint structure of a multilayer wiring board according to an embodiment of the present invention.

【図2】層間接続接着法の最適接合条件を調査するため
の接合モデルサンプルである。
FIG. 2 is a joining model sample for investigating the optimal joining conditions of the interlayer connection adhesion method.

【図3】Au−Sn接合における接合強度の温度・圧力
依存性を示すグラフである。
FIG. 3 is a graph showing the temperature / pressure dependence of the bonding strength in an Au—Sn junction.

【図4】Au−Sn接合における接合強度のSnめっき
厚さ依存性を示すグラフである。
FIG. 4 is a graph showing the Sn plating thickness dependence of the bonding strength in Au—Sn bonding.

【図5】Au−Sn接合の断面組織の例である。FIG. 5 is an example of a cross-sectional structure of Au—Sn junction.

【図6】Au−Ag接合の強度の温度、圧力依存性を示
すグラフである。
FIG. 6 is a graph showing temperature-pressure dependency of strength of Au—Ag junction.

【図7】Au−Ag接合部の断面組織の例である。FIG. 7 is an example of a sectional structure of an Au—Ag joint.

【図8】Sn−Ag接合の強度の温度・圧力依存性を示
すグラフである。
FIG. 8 is a graph showing temperature / pressure dependence of strength of Sn—Ag junction.

【図9】本発明の多層配線基板の層間接続接着法の例で
ある。
FIG. 9 is an example of an interlayer connection adhesion method for a multilayer wiring board according to the present invention.

【図10】本発明の層間接続接着法で組み立てられたマ
ルチチップモジュールの構造を示す斜視である。
FIG. 10 is a perspective view showing the structure of a multi-chip module assembled by the interlayer connection bonding method of the present invention.

【図11】本発明の層間接続接着法で作製した多層配線
基板にLSIをフリップチップ(COB)によりベアチ
ップ搭載した例の正面図である。
FIG. 11 is a front view of an example in which an LSI is mounted on a multilayer wiring board manufactured by an interlayer connection bonding method of the present invention by a flip chip (COB) as a bare chip.

【図12】本発明の多層配線基板の内部にLSIを内蔵
させた例の断面図である。
FIG. 12 is a cross-sectional view of an example in which an LSI is built in the multilayer wiring board of the present invention.

【符号の説明】[Explanation of symbols]

1…ポリイミドテープ、 2…Cuシート、 3…ビア穴および導体金属、 4…接合金属めっき層、 5…接着用樹脂、 6…Ni下地めっき、 7…接合金属めっき層、 8…上部加熱ヘッド、 9…下部加熱ヘッド、 10…Cuシート、 11…Ni下地めっき、 12…接合金属めっき、 13…Cu層、 14…Auリッチ層、 15…Au−Sn化合物層、 16…Auの線分析結果、 17…Snの線分析結果、 18…接合圧力20MPaの強度結果、 19…接合圧力50MPaの強度結果、 20…接合圧力100MPaの強度結果、 21…Auめっき層、 22…Agめっき層、 23…LSI内蔵QFPパッケージ、 24…本発明の層間接続接着法で作製した多層配線基
板、 25…入出力ピン、 26…LSIチップ、 27…バンプ、 28…樹脂、 29…ヒートシンク、 30…LSIチップ、 31…バンプ、 32…本発明の配線基板、 33…本発明の配線基板、 34…本発明の配線基板、 35…本発明の配線基板、 36…LSIを収納するための空間部(樹脂充填)、 37…ビア穴(導通部)。
DESCRIPTION OF SYMBOLS 1 ... Polyimide tape, 2 ... Cu sheet, 3 ... Via hole and conductor metal, 4 ... Bonding metal plating layer, 5 ... Adhesive resin, 6 ... Ni underlayer plating, 7 ... Bonding metal plating layer, 8 ... Upper heating head, 9 ... Lower heating head, 10 ... Cu sheet, 11 ... Ni base plating, 12 ... Bonding metal plating, 13 ... Cu layer, 14 ... Au rich layer, 15 ... Au-Sn compound layer, 16 ... Au line analysis result, 17 ... Sn line analysis result, 18 ... Bonding pressure of 20 MPa strength result, 19 ... Bonding pressure of 50 MPa strength result, 20 ... Bonding pressure of 100 MPa strength result, 21 ... Au plating layer, 22 ... Ag plating layer, 23 ... LSI Built-in QFP package, 24 ... Multilayer wiring board manufactured by the interlayer connection adhesion method of the present invention, 25 ... Input / output pins, 26 ... LSI chip, 27 ... Bump, 28 ... Resin, 29 ... Heat shield 30 ... LSI chip, 31 ... Bump, 32 ... Wiring board of the present invention, 33 ... Wiring board of the present invention, 34 ... Wiring board of the present invention, 35 ... Wiring board of the present invention, 36 ... For accommodating LSI Space portion (filled with resin), 37 ... Via hole (conductive portion).

───────────────────────────────────────────────────── フロントページの続き (72)発明者 京井 正之 神奈川県横浜市戸塚区吉田町292番地株式 会社日立製作所生産技術研究所内 (72)発明者 外川 英男 神奈川県横浜市戸塚区吉田町292番地株式 会社日立製作所生産技術研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masayuki Kyoi, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa, Ltd., Institute of Industrial Science, Hitachi, Ltd. (72) Inventor Hideo Togawa, 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd., Production Engineering Laboratory

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】ポリイミド等の耐熱性絶縁フィルムにスル
ーホールを設け、該スルーホールとつながる銅導体を該
フィルムの両面に形成し、少なくとも片面に接着剤を貼
りつけもしくは塗布し、エッチングで接合部を窓開けし
てなる両面導体形成フィルムにおいて、片面の接合部の
銅導体上にSnめっきを1〜3umを施し、望ましくは3um
を施し、他面の銅導体上にAuめっきを0.3um施し、両
面導体形成フィルムを多層に重ねあわせ、最高温度300
〜350℃、圧力10〜20MPaの大気中、不活性雰囲気中、還
元雰囲気中のいずれかで熱圧着して両面導体形成フィル
ム間の接合部間を金属接合させ、それ以外の部分を樹脂
接着させ硬化させることを特徴とする多層配線基板の層
間接続接着法及びそれを用いた多層配線基板およびそれ
を用いた実装製品。
1. A through-hole is formed in a heat-resistant insulating film such as polyimide, copper conductors connected to the through-hole are formed on both sides of the film, and an adhesive is applied or applied to at least one side of the film, and a joint is formed by etching. In a double-sided conductor forming film formed by opening a window, Sn plating is applied to the copper conductor on one side on one side to 1 to 3 μm, preferably 3 μm.
Applying 0.3um Au plating on the copper conductor on the other side, stacking double-sided conductor forming films in multiple layers
~ 350 ° C, pressure 10 ~ 20MPa in air, in inert atmosphere or in reducing atmosphere by thermocompression bonding to bond metal parts between the double-sided conductor forming films and resin bond other parts. A method for bonding interlayer connection of a multilayer wiring board, which is characterized by curing, a multilayer wiring board using the same, and a mounted product using the same.
【請求項2】請求項1の両面導体形成フィルムにおい
て、片面の接合部の銅導体上にSnめっきを10±3um、
他面の銅導体上にAuめっきを0.3±0.1umを施し、両面
導体形成フィルムを多層に重ねあわせ、最高温度300〜3
50℃、圧力10〜20MPaの大気中、不活性雰囲気中、還元
雰囲気中のいずれかで熱圧着して両面導体形成フィルム
間の接合部間を金属接合させ、それ以外の部分を樹脂接
着させ硬化させることを特徴とする多層配線基板の層間
接続接着法およびそれを用いた多層配線基板およびそれ
を用いた実装製品。
2. The double-sided conductor forming film according to claim 1, wherein Sn plating is applied on the copper conductor at one side of the joint by 10 ± 3 μm,
0.3 ± 0.1um of Au plating is applied on the copper conductor on the other side, and the double-sided conductor forming film is laminated in multiple layers, and the maximum temperature is 300 to 3
Thermocompression bonding is performed in the atmosphere of 50 ° C, pressure of 10 to 20 MPa, in an inert atmosphere, or in a reducing atmosphere to perform metal bonding between the joints between the double-sided conductor forming films, and resin-bond the other portions for curing. An interlayer connection adhesion method for a multilayer wiring board, a multilayer wiring board using the same, and a mounted product using the same.
【請求項3】請求項1の両面導体形成フィルムにおい
て、片面の接合部の銅導体上にAgめっきを5〜10um、
望ましくは7umを施し、他面の銅導体上にAuめっきを
0.3〜0.6um、望ましくは0.6umを施し、両面導体形成フ
ィルムを多層に重ねあわせ、温度350℃、圧力50MPa以上
の大気中、不活性雰囲気中、還元雰囲気中のいずれかで
熱圧着して両面導体形成フィルム間の接合部間を金属接
合させることを特徴とする多層配線基板の層間接続接着
法およびそれを用いた多層配線基板およびそれを用いた
実装製品。
3. The double-sided conductor-forming film according to claim 1, wherein the copper conductor at the joint portion on one side is Ag-plated with 5 to 10 μm,
Desirably apply 7um and Au plating on the copper conductor on the other side.
0.3 to 0.6 μm, preferably 0.6 μm, stacking double-sided conductor forming films in multiple layers, and thermocompression bonding in the atmosphere at a temperature of 350 ° C. and a pressure of 50 MPa or more, in an inert atmosphere, or in a reducing atmosphere. A method for interlayer connection and bonding of a multilayer wiring board, wherein a bonding portion between conductor forming films is metal-bonded, a multilayer wiring board using the same, and a mounted product using the same.
【請求項4】請求項3の両面導体形成フィルムおよびめ
っき組合わせにおいて、接合部間を金属接合させ、それ
以外の部分を樹脂接着させ硬化させることを特徴とする
多層配線基板の層間接続接着法およびそれを用いた多層
配線基板およびそれを用いた実装製品。
4. The interlayer connection bonding method for a multilayer wiring board according to claim 3, wherein in the double-sided conductor forming film and the plating combination, the bonding portions are metal-bonded and the other portions are resin-bonded and cured. And a multilayer wiring board using the same and a mounted product using the same.
【請求項5】請求項1の両面導体形成フィルムにおい
て、片面の接合部の銅導体上にAgめっきを5〜10um、
望ましくは7umを施し、他面の銅導体上にSnめっきを
0.4〜1um、望ましくは1umを施し、両面導体形成フィル
ムを多層に重ねあわせ、最高温度300〜350℃、圧力20〜
50MPaの大気中で熱圧着して両面導体形成フィルム間の
接合部間を金属接合させ、それ以外の部分を樹脂接着さ
せ硬化させることを特徴とする多層配線基板の層間接続
接着法およびそれを用いた多層配線基板およびそれを用
いた実装製品。
5. The double-sided conductor-forming film according to claim 1, wherein the copper conductor at the joint portion on one side is Ag-plated at 5 to 10 μm,
Desirably, apply 7um, and Sn plating on the copper conductor on the other side.
0.4 to 1um, preferably 1um, stacking double-sided conductor forming films in multiple layers, maximum temperature 300 to 350 ° C, pressure 20 to
An interlayer connection bonding method for multi-layer wiring boards characterized by thermocompression bonding in the atmosphere of 50 MPa to bond the joints between the double-sided conductor forming films with each other, and then curing the other parts with a resin and using it. Multilayer wiring board and mounted products using the same.
【請求項6】請求項1及至5項において、該両面導体形
成フィルム間にLSI素子、ICセンサー、素子を搭載
したモジュール、抵抗、コンデンサー、コイル等のいず
れかもしくは、複数個を挟み、端子間接続を同時に完成
させ、内蔵させたことを特徴とする多層配線基板。
6. The terminals according to claim 1, wherein one or more of an LSI element, an IC sensor, a module mounting the element, a resistor, a condenser, a coil, or the like is sandwiched between the double-sided conductor-forming films. A multi-layer wiring board characterized by completing connections at the same time and incorporating them.
JP13753795A 1995-05-12 1995-05-12 Multilayer wiring board manufactured by collective connection method Pending JPH08316641A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13753795A JPH08316641A (en) 1995-05-12 1995-05-12 Multilayer wiring board manufactured by collective connection method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13753795A JPH08316641A (en) 1995-05-12 1995-05-12 Multilayer wiring board manufactured by collective connection method

Publications (1)

Publication Number Publication Date
JPH08316641A true JPH08316641A (en) 1996-11-29

Family

ID=15201011

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13753795A Pending JPH08316641A (en) 1995-05-12 1995-05-12 Multilayer wiring board manufactured by collective connection method

Country Status (1)

Country Link
JP (1) JPH08316641A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004012489A1 (en) * 2002-07-30 2004-02-05 Sumitomo Bakelite Company Limited Circuit substrate, multi-layer wiring plate, circuit substrate manufacturing method, and multi-layer wiring plate manufacturing method
US6759258B2 (en) 1997-05-09 2004-07-06 Renesas Technology Corp. Connection device and test system
JP2004343055A (en) * 2003-04-25 2004-12-02 Hitachi Chem Co Ltd Pattern and member for evaluation of fine connection resistance, manufacturing method thereof, and evaluating method using same, and multilayered board
US8168471B2 (en) 2006-03-27 2012-05-01 Fujitsu Limited Semiconductor device and manufacturing method of a semiconductor device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6759258B2 (en) 1997-05-09 2004-07-06 Renesas Technology Corp. Connection device and test system
US7285430B2 (en) 1997-05-09 2007-10-23 Hitachi, Ltd. Connection device and test system
US7541202B2 (en) 1997-05-09 2009-06-02 Renesas Technology Corp. Connection device and test system
WO2004012489A1 (en) * 2002-07-30 2004-02-05 Sumitomo Bakelite Company Limited Circuit substrate, multi-layer wiring plate, circuit substrate manufacturing method, and multi-layer wiring plate manufacturing method
JP2004343055A (en) * 2003-04-25 2004-12-02 Hitachi Chem Co Ltd Pattern and member for evaluation of fine connection resistance, manufacturing method thereof, and evaluating method using same, and multilayered board
JP4506196B2 (en) * 2003-04-25 2010-07-21 日立化成工業株式会社 Multilayer wiring board evaluation method, wiring pattern, and evaluation member
US8168471B2 (en) 2006-03-27 2012-05-01 Fujitsu Limited Semiconductor device and manufacturing method of a semiconductor device

Similar Documents

Publication Publication Date Title
KR100531393B1 (en) Semiconductor device and manufacturing method of the same
EP0097833B1 (en) Substrate for integrated circuit packages
JP3262497B2 (en) Chip mounted circuit card structure
KR101193212B1 (en) Wiring board having built-in semiconductor chip and method for manufacturing the same
JP2005520333A (en) Multilayer substrate stacking technology
KR100335454B1 (en) Multilayered circuit board for semiconductor chip module, and method of manufacturing the same
US6080494A (en) Method to manufacture ball grid arrays with excellent solder ball adhesion for semiconductor packaging and the array
JP3398319B2 (en) Semiconductor device and manufacturing method thereof
US8071472B2 (en) Semiconductor device with solder balls having high reliability
JPH08316641A (en) Multilayer wiring board manufactured by collective connection method
JP4012527B2 (en) Manufacturing method of electronic parts
JPH01147836A (en) Semiconductor device
JPH04212277A (en) Method of connecting terminal to printed wiring board
JPH05327152A (en) Wiring substrate and manufacutring method thereof
JPH0671144B2 (en) Multi-layer high-density mounting module
EP0964446A2 (en) An electronic circuit assembly
US5537739A (en) Method for electoconductively connecting contacts
JP2002368038A (en) Flip-chip mounting method
JP2000294675A (en) Chip carrier, semiconductor device and manufacture of chip carrier
JPH10139559A (en) Glass-ceramic substrate and its manufacture
EP0993034A2 (en) Method for bonding bumped electronic components to a substrate
JPH09148334A (en) Bump, semiconductor chip, package having the bumps, mounting method and semiconductor device
JP2929885B2 (en) Composite lead frame and manufacturing method thereof
JPH08139095A (en) Formation of solder bump
JPH06252215A (en) Film carrier