JPH0671144B2 - Multi-layer high-density mounting module - Google Patents
Multi-layer high-density mounting moduleInfo
- Publication number
- JPH0671144B2 JPH0671144B2 JP1149972A JP14997289A JPH0671144B2 JP H0671144 B2 JPH0671144 B2 JP H0671144B2 JP 1149972 A JP1149972 A JP 1149972A JP 14997289 A JP14997289 A JP 14997289A JP H0671144 B2 JPH0671144 B2 JP H0671144B2
- Authority
- JP
- Japan
- Prior art keywords
- density mounting
- mounting module
- circuit pattern
- substrate
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
Description
【発明の詳細な説明】 (産業上の利用分野) 本発明は回路パターンを有する複数の基板を積層し、基
板の中間層にチップ部品を内蔵した多層高密度実装モジ
ュールに関する。Description: TECHNICAL FIELD The present invention relates to a multilayer high-density mounting module in which a plurality of substrates each having a circuit pattern are stacked and a chip component is built in an intermediate layer of the substrates.
(従来の技術) 回路パターンを有するガラス繊維、エポキシ樹脂基板を
複数積み重ね、中間層の基板に部品埋込み用孔部を設
け、セラミックチップコンデンサなどのチップ部品を内
蔵し、回路の小型化を目的とした高密度実装モジュール
がある。複数の基板の回路パターンは、例えば、錫、
鉛、共晶半田による半田バンプ接合によって行い、その
間に形成された空隙部分へ液状のエポキシ樹脂を充填し
て多層基板は完成される。(Prior Art) Stacking a plurality of glass fiber and epoxy resin boards with circuit patterns, providing holes for embedding parts in the board of the intermediate layer, and incorporating chip parts such as ceramic chip capacitors for the purpose of circuit miniaturization There is a high-density mounting module. The circuit patterns of the plurality of substrates are, for example, tin,
Solder bump bonding with lead or eutectic solder is performed, and liquid epoxy resin is filled into the voids formed therebetween to complete the multilayer substrate.
然し乍ら、従来のこの種の半田バンプを介して各基板の
回路パターンを形成した構造は、例えば、−40°Cから
+80°Cの条件で数千回の繰返し熱サイクルを実施した
際、半田バンプ接合部分に亀裂が発生し、回路を破壊す
る不具合があった。即ちガラス繊維、エポキシ樹脂基板
は銅箔などを接着し、エッチング加工を行い回路パター
ンを形成する。基板の多層化に際しては前述の様に錫、
鉛、共晶半田を使用して半田バンプを介して接合する。
基板の多層化に伴う熱容量の大きなモジュール基板は多
層化のための半田バンプ接合時、銅箔中の銅が錫成分へ
拡散し、脆性を有する金属間化合物を接合部分に形成す
る。他方ガラス繊維エポキシ樹脂基板は、その構造から
基板の厚さ方向は半田金属と比較して極めて大きな熱膨
脹係数を有する。熱サイクルの様に降温、昇温に伴う樹
脂基板の厚さ方向の膨脹変位量は半田バンプ接合部に集
中し、前述の回路パターン半田バンプの脆化接合部分に
亀裂を生じ、回路の破壊現象を発生した。とくにこの傾
向は部品を内蔵するため1.0mm以上の厚い樹脂基板を複
数使用する高密度実装モジュールでは厚さ方向の変位量
が大きく主要な不具合の一つとなっていた。However, the conventional structure in which the circuit pattern of each substrate is formed through the solder bumps of this type is, for example, when the solder bumps are repeatedly heat-treated several thousands times under the condition of -40 ° C to + 80 ° C. There was a problem that a crack was generated at the joint and the circuit was destroyed. That is, a glass fiber or an epoxy resin substrate is adhered with copper foil or the like and etched to form a circuit pattern. As mentioned above, when multilayering the substrate, tin,
Lead and eutectic solder are used to bond via solder bumps.
In a module board having a large heat capacity as the board becomes multilayered, copper in a copper foil diffuses into a tin component at the time of solder bump bonding for multilayering, and a brittle intermetallic compound is formed at a bonded portion. On the other hand, the glass fiber epoxy resin substrate has an extremely large coefficient of thermal expansion in the thickness direction of the substrate as compared with the solder metal due to its structure. The amount of expansion and displacement in the thickness direction of the resin substrate due to temperature drop and temperature rise, such as in a thermal cycle, concentrates at the solder bump joints, causing cracks at the aforementioned embrittlement joints of the circuit pattern solder bumps, causing a circuit destruction phenomenon. Occurred. In particular, this tendency was one of the major problems in the high-density mounting module in which multiple resin boards with a thickness of 1.0 mm or more were used because of the built-in components, and the amount of displacement in the thickness direction was large.
(発明が解決しようとする課題) 本発明は樹脂基板に使用する回路パターン銅箔の表面に
白金、あるいはパラジウムのメッキ層を構成することを
特徴とし、その目的は部品を埋込んだ複数の基板を積層
し半田バンプを介して接合しても長期の熱サイクル試験
を実施しても回路パターンに破壊を生じない高密度実装
モジュールの提供にある。(Problems to be Solved by the Invention) The present invention is characterized in that a plating layer of platinum or palladium is formed on the surface of a circuit pattern copper foil used for a resin substrate, and the purpose thereof is to provide a plurality of substrates in which components are embedded. Another object is to provide a high-density mounting module in which the circuit pattern is not broken even if the layers are laminated and bonded via solder bumps or a long-term thermal cycle test is performed.
(実施例) 図は本発明の実施例の説明図で、高密度実装モジュール
の要部断面拡大図である。1はガラス繊維エポキシ樹脂
材料からなる第1層基板、2は部品埋込み部分の空間を
有する第2層基板、3は表面層にICやトランジスタなど
の機能部品、あるいはコンデンサなどの基板内部へ埋込
みが不可能の部品を搭載する第3層基板、4は樹脂基板
の表面へ接着剤などで貼り付けた銅箔回路パターン、5
は錫、鉛、共晶半田による半田バンプ接合部分、6は基
板間の空隙部分を充填したエポキシ樹脂、7はセラミッ
クチップコンデンサなど基板へ埋込む電気部品である。(Embodiment) FIG. 3 is an explanatory view of an embodiment of the present invention, and is an enlarged cross-sectional view of a main part of a high-density mounting module. Reference numeral 1 is a first layer substrate made of a glass fiber epoxy resin material, 2 is a second layer substrate having a space for embedding a component, and 3 is a functional layer such as an IC or a transistor on a surface layer, or is embedded inside a substrate such as a capacitor The third layer substrate on which impossible components are mounted, 4 is a copper foil circuit pattern which is attached to the surface of the resin substrate with an adhesive or the like, 5
Is a solder bump joint portion made of tin, lead, or eutectic solder, 6 is an epoxy resin filling a void portion between the substrates, and 7 is an electric component embedded in the substrate such as a ceramic chip capacitor.
本発明の実施にあたっては各基板の回路パターンに少く
とも厚さ0.5ミクロン以上の白金あるいはパラジウムを
電気メッキする。錫、鉛、共晶半田クリームを印刷して
昇温し半田バンプを形成する。電気部品7は基板の孔に
予じめ樹脂などを介して回路パターンと同一平面上に固
定化し、他の接合用半田バンプと同様に接合用半田バン
プを形成する。各基板の位置関係を出すため治具などを
介して加圧昇温して半田を溶融して基板の積層化を行
う。基板間の空隙部分へ液状のエポキシ樹脂を含浸し硬
化処理を加えて基板は完成する。斯る構成では、錫は白
金パラジウムと金属間化合物の形成はなく脆性を有する
ことなく、接合強度の安定した半田バンプ接合状態を得
ることが出来る。In practicing the present invention, the circuit pattern on each substrate is electroplated with at least 0.5 microns thick platinum or palladium. Tin, lead and eutectic solder cream are printed and heated to form solder bumps. The electric component 7 is fixed on the same plane as the circuit pattern through a resin or the like in the hole of the substrate, and solder bumps for bonding are formed in the same manner as other solder bumps for bonding. In order to obtain the positional relationship between the substrates, the temperature is increased by pressing through a jig or the like to melt the solder and laminate the substrates. A liquid epoxy resin is impregnated into the voids between the substrates and a curing process is applied to complete the substrate. With such a configuration, tin does not form an intermetallic compound with platinum palladium, does not have brittleness, and a solder bump bonded state with stable bonding strength can be obtained.
白金およびパラジウムは酸素との親和力が低く、その表
面層に半田の濡れ性を低下することもない。複数の基板
を積層した構成では回路パターンの表面に、例えば、同
様の目的で使用されるニッケルでは厚さ2.0ミクロン以
上を必要とするが高周波系の信号を処理する場合、回路
パターンの導体表面損失が大きくモジュールの利得の低
下を発生するが、白金を介した構成では損失はない。更
にニッケルの場合半田への濡れ性改善のため金メッキを
ニッケル層へ被覆する工程が複雑なこと、更に半田成分
中の錫と金の拡散に伴う金属間化合物の形成は僅少では
あるが半田バンプ接合部分の脆性傾向を示す。Platinum and palladium have a low affinity with oxygen, and the surface layer thereof does not deteriorate the wettability of solder. In the structure where multiple substrates are laminated, the surface of the circuit pattern needs to have a thickness of 2.0 μm or more for nickel used for the same purpose, but when processing high frequency signals, the conductor surface loss of the circuit pattern However, there is no loss in the configuration using platinum. Furthermore, in the case of nickel, the process of coating the nickel layer with gold plating to improve the wettability to solder is complicated, and the formation of intermetallic compounds due to the diffusion of tin and gold in the solder components is slight, but solder bump bonding The brittleness tendency of the part is shown.
更につけ加えて説明すると、銅箔表面への白金メッキの
厚さは半田成分への拡散に伴う侵食を発生させぬため僅
少量でもよいが、白金メッキ時の付着量が少くまた回路
パターン構成上複雑な導電経路を経てメッキを行うた
め、この種の目的では少くとも0.5ミクロン以上の値を
必要とする。In addition, the thickness of platinum plating on the surface of copper foil may be very small because it does not cause erosion due to diffusion into solder components, but the amount of platinum plating is small and the circuit pattern configuration is complicated. Since the plating is performed via various conductive paths, a value of at least 0.5 micron or more is required for this type of purpose.
(発明の効果) 以上説明したように複数の樹脂基板を半田バンプを介し
て接合する際回路パターンの表面に白金あるいはパラジ
ウムメッキ層を少くとも0.5ミクロン以上被覆して積層
するから、熱サイクルなど樹脂基板の厚さ方向の熱膨脹
に伴う変位が発生しても回路の破壊のない高密度実装モ
ジュールを提供出来る利点がある。(Effects of the Invention) As described above, when a plurality of resin substrates are joined together via solder bumps, a platinum or palladium plating layer is laminated on the surface of the circuit pattern so as to cover at least 0.5 μm. There is an advantage that it is possible to provide a high-density mounting module in which the circuit is not destroyed even if displacement occurs due to thermal expansion of the substrate in the thickness direction.
図は本発明の実施例図で高密度実装モジュールの要部断
面拡大図である。 1……第1層基板、2……第2層基板、3……第3層基
板、4……銅箔回路パターン、5……半田バンプ接合部
分、6……エポキシ樹脂、7……電気部品。The drawing is an embodiment of the present invention and is an enlarged cross-sectional view of a main part of a high-density mounting module. 1 ... 1st layer substrate, 2 ... 2nd layer substrate, 3 ... 3rd layer substrate, 4 ... Copper foil circuit pattern, 5 ... Solder bump joint part, 6 ... Epoxy resin, 7 ... Electricity parts.
Claims (2)
脂基板から成る多層高密度実装モジュールにおいて、前
記回路パターン上に形成された錫を含む材料からなる、
半田バンプと、前記回路パターンの前記半田バンプと接
する面に白金あるいはパラジウムメッキを被覆すること
を特徴とする多層高密度実装モジュール。1. A multi-layer high-density mounting module comprising a plurality of resin substrates having a circuit pattern made of copper foil, which is made of a material containing tin formed on the circuit pattern.
A multilayer high-density mounting module, characterized in that a solder bump and a surface of the circuit pattern in contact with the solder bump are coated with platinum or palladium plating.
パラジウムメッキの厚さを0.5ミクロン以上としたこと
を特徴とする多層高密度実装モジュール。2. A multilayer high-density mounting module, wherein the platinum or palladium plating according to claim 1 has a thickness of 0.5 μm or more.
Priority Applications (13)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1149972A JPH0671144B2 (en) | 1989-06-13 | 1989-06-13 | Multi-layer high-density mounting module |
US07/456,946 US5031308A (en) | 1988-12-29 | 1989-12-26 | Method of manufacturing multilayered printed-wiring-board |
DE68928150T DE68928150T2 (en) | 1988-12-29 | 1989-12-28 | Manufacturing process of a multilayer printed circuit board |
ES93118943T ES2104023T3 (en) | 1988-12-29 | 1989-12-28 | MANUFACTURING PROCEDURE OF MULTILAYER PRINTED WIRING PLATE. |
EP89124088A EP0379736B1 (en) | 1988-12-29 | 1989-12-28 | Method of manufacturing multilayered printed-wiring-board |
DE68921732T DE68921732T2 (en) | 1988-12-29 | 1989-12-28 | Process for the production of printed multilayer printed circuit boards. |
EP93118917A EP0607532B1 (en) | 1988-12-29 | 1989-12-28 | Method of manufacturing multilayered printed-wiring-board |
DE68926055T DE68926055T2 (en) | 1988-12-29 | 1989-12-28 | Manufacturing process of a multilayer printed circuit board |
ES89124088T ES2069570T3 (en) | 1988-12-29 | 1989-12-28 | MANUFACTURING PROCEDURE OF A PRINTED CONNECTION PLATE WITH MULTIPLE LAYERS. |
CA002006776A CA2006776C (en) | 1988-12-29 | 1989-12-28 | Method of manufacturing multilayered printed-wiring-board |
ES93118917T ES2085098T3 (en) | 1988-12-29 | 1989-12-28 | MANUFACTURING PROCEDURE OF A MULTILAYER PRINTED CIRCUIT. |
EP93118943A EP0607534B1 (en) | 1988-12-29 | 1989-12-28 | Method of manufacturing multilayered printed-wiring-board |
KR1019890020640A KR940009175B1 (en) | 1988-12-29 | 1989-12-29 | Multi-printed wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1149972A JPH0671144B2 (en) | 1989-06-13 | 1989-06-13 | Multi-layer high-density mounting module |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0314293A JPH0314293A (en) | 1991-01-22 |
JPH0671144B2 true JPH0671144B2 (en) | 1994-09-07 |
Family
ID=15486651
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1149972A Expired - Fee Related JPH0671144B2 (en) | 1988-12-29 | 1989-06-13 | Multi-layer high-density mounting module |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0671144B2 (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06120671A (en) * | 1991-03-12 | 1994-04-28 | Japan Radio Co Ltd | Multilayer wiring board embedded with component |
JPH06120670A (en) * | 1991-03-12 | 1994-04-28 | Japan Radio Co Ltd | Multilayer wiring board |
JPH04338541A (en) * | 1991-05-15 | 1992-11-25 | Toyota Motor Corp | Printing machine |
JPH0553269U (en) * | 1991-12-17 | 1993-07-13 | 日本無線株式会社 | Multilayer wiring board with high-frequency shield structure |
JP2749472B2 (en) * | 1991-12-24 | 1998-05-13 | 株式会社日立製作所 | Multilayer thin-film wiring board, module using the board |
JP4978709B2 (en) * | 2010-03-12 | 2012-07-18 | 大日本印刷株式会社 | Electronic component built-in wiring board |
-
1989
- 1989-06-13 JP JP1149972A patent/JPH0671144B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH0314293A (en) | 1991-01-22 |
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Legal Events
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Free format text: PAYMENT UNTIL: 20080907 Year of fee payment: 14 |
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