JP2001028481A - Multi-layer wiring board and manufacture thereof - Google Patents
Multi-layer wiring board and manufacture thereofInfo
- Publication number
- JP2001028481A JP2001028481A JP19955499A JP19955499A JP2001028481A JP 2001028481 A JP2001028481 A JP 2001028481A JP 19955499 A JP19955499 A JP 19955499A JP 19955499 A JP19955499 A JP 19955499A JP 2001028481 A JP2001028481 A JP 2001028481A
- Authority
- JP
- Japan
- Prior art keywords
- double
- sided circuit
- circuit boards
- wiring
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、多層配線基板およ
びその製造方法に関するものである。The present invention relates to a multilayer wiring board and a method for manufacturing the same.
【0002】[0002]
【従来の技術】近年の電子機器の小型化,高性能化に伴
い、電子機器を構成する半導体装置およびこれを実装す
る多層配線基板には、小型薄型化,高性能化,高信頼性
が要求されている。これらの要求を受けて、実装方法は
ピン挿入型パッケージから表面実装型パッケージへと移
行してきており、最近では半導体素子を直接プリント基
板に実装するベアチップ実装と呼ばれる実装方法が研究
されている。また、半導体素子の多ピン化に伴い、これ
を搭載する基板の多層化の必要性が増している。この多
層化の方法として、基体の片面もしくは両面に、感光性
樹脂を用いた絶縁層と、めっきや蒸着により形成した導
体層を交互に積み重ねたビルトアップ方式の多層配線基
板が提案されている。ところが、このものでは、製造工
程が複雑で工程数が多いこと、しかも歩留りが低いこと
や納期がかかること等の問題があった。また、ガラスエ
ポキシ片面銅張り積層板の片面(銅張り面)に電導性ペ
ーストをディスペンサー等により突起として形成し、接
着シートと銅箔を重ねて加圧し、それを繰り返すことに
より多層化する方法も提案されている(特開平8−28
8649号公報)。しかしながら、このものでは、接続
の信頼性,接続抵抗等の面に問題があるうえ、ファイン
回路への応用が困難であり、しかも多層化するために層
数の分だけプレスを繰り返す必要があり、製造に時間が
かかる等の種々の問題があった。2. Description of the Related Art With the recent trend toward miniaturization and high performance of electronic devices, semiconductor devices constituting the electronic devices and multilayer wiring boards on which the electronic devices are mounted are required to be small, thin, high performance, and high reliability. Have been. In response to these demands, the mounting method has shifted from a pin insertion type package to a surface mount type package. Recently, a mounting method called bare chip mounting, in which a semiconductor element is directly mounted on a printed circuit board, has been studied. Further, with the increase in the number of pins of the semiconductor element, the necessity of increasing the number of layers of the substrate on which the semiconductor element is mounted is increasing. As a method of multi-layering, a built-up type multilayer wiring board has been proposed in which an insulating layer using a photosensitive resin and a conductor layer formed by plating or vapor deposition are alternately stacked on one or both sides of a base. However, in this case, there are problems that the manufacturing process is complicated and the number of processes is large, and that the yield is low and the delivery time is long. Alternatively, a method of forming a conductive paste on one surface (copper-coated surface) of a glass epoxy single-sided copper-clad laminate as a projection using a dispenser or the like, stacking an adhesive sheet and a copper foil, applying pressure, and repeating the process to form a multilayer structure. It has been proposed (Japanese Patent Laid-Open No. 8-28
No. 8649). However, this method has problems in connection reliability, connection resistance, and the like, and is difficult to apply to fine circuits. Further, in order to increase the number of layers, it is necessary to repeat pressing for the number of layers. There were various problems such as a long time for manufacturing.
【0003】一方、ベアチップ実装では、熱膨張係数:
3〜4ppm/℃のシリコンチップを熱膨張係数:10
〜20ppm/℃のプリント基板上に直接接着剤を介し
て接着するため、両者の熱膨張の差により応力がかか
り、接続信頼性が低下するという問題が生じている。ま
た、上記応力は接着剤にクラックを生じさせて耐湿性を
低下させる等の問題をも引き起こしている。このような
応力を緩和するために、接着剤の弾性率を下げて応力の
拡散効果を図る方法等も実施されているが、これらの方
法によっても、接続信頼性を充分に確保することができ
ず、さらに高い接続信頼性を確保するには、基体自体の
熱膨張係数を下げることが必要不可欠となっている。On the other hand, in the bare chip mounting, the thermal expansion coefficient:
A silicon chip of 3 to 4 ppm / ° C. has a coefficient of thermal expansion of 10
Since the printed circuit board is directly bonded to the printed board at 2020 ppm / ° C. via an adhesive, a stress is applied due to a difference in thermal expansion between the two, causing a problem that connection reliability is reduced. In addition, the above-mentioned stress also causes problems such as causing cracks in the adhesive and reducing moisture resistance. In order to alleviate such stress, a method of lowering the elastic modulus of the adhesive to achieve the effect of diffusing the stress has been carried out. However, even with these methods, sufficient connection reliability can be ensured. In order to ensure even higher connection reliability, it is essential to lower the thermal expansion coefficient of the base itself.
【0004】このような背景の中、本発明らは、メタル
コアを基体とした有機高分子樹脂からなる絶縁層の両面
に配線導体を設け、これら表裏両面の配線導体をスルー
ホールにより電気的に接続してなる低熱膨張両面回路基
板を複数枚用意し、これら両面回路基板を接着剤層を介
して積層一体化した多層配線基板およびその製造方法を
提案している(特願平9−260201号公報)。Against this background, the present invention provides wiring conductors on both surfaces of an insulating layer made of an organic polymer resin having a metal core as a base, and electrically connects these wiring conductors on both front and back surfaces with through holes. A multilayer wiring board in which a plurality of low-thermal-expansion double-sided circuit boards are prepared, and these double-sided circuit boards are laminated and integrated via an adhesive layer, and a method for manufacturing the same are proposed (Japanese Patent Application No. 9-260201). ).
【0005】[0005]
【発明が解決しようとする課題】しかしながら、上記多
層配線基板を構成する複数の両面回路基板において、そ
の表裏両面の配線導体を電気的に接続するスルーホール
は、温度サイクル試験等の環境加速試験においてスルー
ホール内部もしくはスルーホールコーナー部に亀裂が生
じる等信頼性に問題がある。このため、上記スルーホー
ルのめっき厚みを厚くすることにより信頼性を向上させ
ることが考えられるが、この場合には、エッチングによ
る回路形成工程において微細配線を設けることができな
い。一方、微細配線を形成するためには、表裏両面の導
体層の厚みを小さくする必要があるが、スルーホールの
信頼性は低下する。しかも、上記複数の両面回路基板を
接着剤層を介して積層一体化する工程において、積み重
なる(上下に隣り合う)2つの両面回路基板の配線導体
を半田製導電体により電気的に接続することを行ってい
るが、上記両面回路基板のスルーホール上に半田製導電
体を設けることができないため、配線の自由度が大きく
阻害されている。However, in a plurality of double-sided circuit boards constituting the above-mentioned multilayer wiring board, through holes for electrically connecting the wiring conductors on the front and back surfaces of the circuit board are not used in an environmental acceleration test such as a temperature cycle test. There is a problem in reliability such as cracks generated in the inside of the through hole or the corner of the through hole. Therefore, it is conceivable to improve the reliability by increasing the plating thickness of the through hole, but in this case, fine wiring cannot be provided in a circuit forming process by etching. On the other hand, in order to form fine wiring, it is necessary to reduce the thickness of the conductor layers on both the front and back surfaces, but the reliability of the through holes is reduced. Further, in the step of laminating and integrating the plurality of double-sided circuit boards via the adhesive layer, it is necessary to electrically connect the wiring conductors of the two (both vertically adjacent) stacked two-sided circuit boards with a conductor made of solder. However, since a conductor made of solder cannot be provided on the through hole of the double-sided circuit board, the degree of freedom of wiring is greatly impaired.
【0006】本発明は、このような事情に鑑みなされた
もので、熱膨張率が極めて小さく、しかも、接続信頼性
が高く、配線の自由度が大きい多層配線基板およびその
製造方法の提供をその目的とする。The present invention has been made in view of such circumstances, and an object of the present invention is to provide a multilayer wiring board having a very low coefficient of thermal expansion, high connection reliability, and a high degree of freedom in wiring, and a method of manufacturing the same. Aim.
【0007】[0007]
【課題を解決するための手段】上記の目的を達成するた
め、本発明は、メタルコアを基体とした有機高分子樹脂
からなる絶縁層の両面に配線導体が設けられこれら両配
線導体が硬化型導電性樹脂が充填されたビアホールによ
り電気的に接続された複数の両面回路基板が、接着剤層
を介して積層一体化され、上記接着剤層には、これを挟
む2つの両面回路基板の配線導体に当接する部分の所定
位置に孔が穿設され、上記穿孔部に半田製導電体が設け
られ、上記半田製導電体により上記2つの両面回路基板
の配線導体が電気的に接続されている多層配線基板を第
1の要旨とし、この多層配線基板を製造する方法であっ
て、メタルコアを基体とした有機高分子樹脂からなる絶
縁層の両面に配線導体が設けられこれら両配線導体が硬
化型導電性樹脂が充填されたビアホールにより電気的に
接続された複数の両面回路基板と、上記両面回路基板の
配線導体の所定部分に対応する位置に開孔した接着シー
トとを準備する工程と、上記両面回路基板に設けた配線
導体の所定部分に上記接着シートの開孔部を位置合わせ
した状態で上記両面回路基板に接着シートを仮接着する
工程と、接着シート仮接着後に各接着シートの開孔部に
印刷により半田ペーストを充填し加熱溶融させて半田バ
ンプを形成する工程と、半田バンプ形成後に上記各両面
回路基板の配線導体が所定の電気的接続を行えるよう位
置合わせして上記各両面回路基板を積み重ね加熱加圧し
て全体を一体化させる工程を備えている多層配線基板の
製造方法を第2の要旨とする。In order to achieve the above-mentioned object, the present invention provides an insulating layer made of an organic polymer resin having a metal core as a base, and wiring conductors are provided on both surfaces of the insulating layer. A plurality of double-sided circuit boards electrically connected by via holes filled with a conductive resin are laminated and integrated via an adhesive layer, and the adhesive layer has wiring conductors of two double-sided circuit boards sandwiching the same. A hole is formed at a predetermined position of a portion in contact with the substrate, a conductor made of solder is provided in the hole, and a wiring conductor of the two double-sided circuit boards is electrically connected by the conductor made of solder. A method of manufacturing a multilayer wiring board having a wiring board according to a first aspect, wherein wiring conductors are provided on both surfaces of an insulating layer made of an organic polymer resin having a metal core as a base, and both of the wiring conductors are hardened conductive layers. Resin A step of preparing a plurality of double-sided circuit boards electrically connected by the filled via holes and an adhesive sheet opened at a position corresponding to a predetermined portion of the wiring conductor of the double-sided circuit board; Temporarily bonding the adhesive sheet to the double-sided circuit board in a state where the opening of the adhesive sheet is aligned with a predetermined portion of the provided wiring conductor, and printing the opening of each adhesive sheet after the adhesive sheet is temporarily bonded. Filling the solder paste and heating and melting to form solder bumps, and stacking and heating each of the double-sided circuit boards by aligning the wiring conductors of each of the double-sided circuit boards after the formation of the solder bumps so that predetermined electrical connections can be made. A second feature of the present invention is a method for manufacturing a multilayer wiring board including a step of integrating the whole by pressing.
【0008】すなわち、本発明者らは、熱膨張率が極め
て小さく、しかも、接続信頼性が高く、配線の自由度が
大きい多層配線基板を得るため、一連の研究を行った結
果、メタルコアを基体とし、かつ、表裏両面の配線導体
を硬化型導電性樹脂を充填したビアホールで電気的に接
続すると、熱膨張率が極めて小さく、しかも、接続信頼
性が高く、配線の自由度が大きい多層配線基板を得るこ
とができることを見出し、本発明に到達した。本発明の
多層配線基板のように、メタルコアを基体とすることに
より、低熱膨張両面回路基板を得ることができ、これら
を多層に積層一体化することにより、低熱膨張多層配線
基板を得ることができる。また、本発明の多層配線基板
のように、スルーホールを設ける代りに、硬化型導電性
樹脂を充填したビアホールを設けると、温度サイクル試
験等の環境加速試験においても内部やコーナー部に亀裂
が生じず、接続信頼性が高い。また、硬化型導電性樹脂
を充填したビアホール上に半田製導電体を設けて、積み
重なる(上下に隣り合う)2つの両面回路基板の配線導
体を電気的に接続することができるため、配線の自由度
が大きい。また、各両面回路基板に基体として配設した
メタルコアは、XY方向のみならず、Z方向にも極めて
熱膨張率が低いため、温度サイクル試験等の環境加速試
験において、ビアホールの寸法変化を抑制する効果があ
り、接続信頼性を向上させることができる。That is, the present inventors have conducted a series of studies to obtain a multilayer wiring board having a very low coefficient of thermal expansion, high connection reliability, and high wiring flexibility. And when the wiring conductors on both sides are electrically connected by via holes filled with curable conductive resin, the coefficient of thermal expansion is extremely small, and the connection reliability is high and the wiring flexibility is large. Have been found, and the present invention has been achieved. As in the multilayer wiring board of the present invention, a low thermal expansion double-sided circuit board can be obtained by using a metal core as a base, and a low thermal expansion multilayer wiring board can be obtained by laminating and integrating these in multiple layers. . Also, when a via hole filled with a curable conductive resin is provided instead of providing a through hole as in the multilayer wiring board of the present invention, cracks occur inside and at corners even in an environmental acceleration test such as a temperature cycle test. And high connection reliability. Further, by providing a conductor made of solder on the via hole filled with the curable conductive resin, it is possible to electrically connect the wiring conductors of the two double-sided circuit boards that are stacked (adjacent vertically), so that the wiring is free. Great degree. Further, since the metal core disposed as a base on each double-sided circuit board has a very low coefficient of thermal expansion not only in the XY directions but also in the Z direction, it suppresses dimensional changes of via holes in an environmental acceleration test such as a temperature cycle test. There is an effect, and connection reliability can be improved.
【0009】一方、本発明の製造方法では、両面回路基
板に接着シートを位置合わせして仮接着し、この接着シ
ートに開けた開孔部に半田バンプを形成したのち、各両
面回路基板を位置合わせして積重し加熱加圧して全体を
一体化させているため、一回の加熱加圧により複数の両
面回路基板を一体化することができる。と同時に、配線
導体の層数が何層であっても、上記一回の加熱加圧によ
り各配線導体間の電気的接続が行える。本発明におい
て、「両面回路基板の配線導体の所定部分に対応する位
置に開孔した接着シートを準備する」とは、接着シート
を両面回路基板上に載せたのち開孔する場合を含む意味
である。On the other hand, in the manufacturing method of the present invention, the adhesive sheet is aligned and temporarily bonded to the double-sided circuit board, and solder bumps are formed in the openings formed in the adhesive sheet. Since the whole is integrated and stacked and heated and pressed, a plurality of double-sided circuit boards can be integrated by one heating and pressing. At the same time, regardless of the number of layers of the wiring conductor, electrical connection between the wiring conductors can be performed by the single heating and pressing. In the present invention, "preparing an adhesive sheet that is opened at a position corresponding to a predetermined portion of a wiring conductor of a double-sided circuit board" means that the adhesive sheet is placed on a double-sided circuit board and then opened. is there.
【0010】つぎに、本発明を詳しく説明する。Next, the present invention will be described in detail.
【0011】本発明の多層配線基板を構成する両面回路
基板において、絶縁層として用いられる有機高分子材料
としては、ポリイミド系接着剤が好適に用いられるが、
これに限定するものではなく、ポリエーテルイミド,ポ
リエーテルサルフォン,エポキシ系等が用いられる。ま
た、上記絶縁層の表裏両面の配線導体を構成する金属材
料としては、銅が好適に用いられるが、これに限定する
ものではなく、金,銀等が用いられる。In the double-sided circuit board constituting the multilayer wiring board of the present invention, a polyimide adhesive is preferably used as the organic polymer material used as the insulating layer.
The present invention is not limited to this, and polyetherimide, polyethersulfone, epoxy, and the like are used. Further, as a metal material forming the wiring conductors on both the front and back surfaces of the insulating layer, copper is preferably used, but not limited thereto, and gold, silver or the like is used.
【0012】また、絶縁層にビアホール(貫通孔)を開
ける手段としては、孔の大きさにより適切な方法を選択
すればよいが、ドリル,パンチ,レーザー等が挙げられ
る。また、貫通孔に充填する硬化型導電性樹脂として
は、Ag,Cu,Au,Ni,Pb,Sn,C等の導電
性材料と、エポキシ樹脂,フェノール樹脂,ポリイミド
樹脂等を必要により有機剤とともに混合してペースト状
とした公知の硬化型導電性樹脂を使用することができ
る。As a means for forming a via hole (through hole) in the insulating layer, an appropriate method may be selected according to the size of the hole, and examples thereof include a drill, a punch, and a laser. As the curable conductive resin to be filled in the through hole, a conductive material such as Ag, Cu, Au, Ni, Pb, Sn, C, and an epoxy resin, a phenol resin, a polyimide resin, and the like, together with an organic agent as necessary. A well-known curable conductive resin mixed into a paste can be used.
【0013】上記貫通孔内への硬化型導電性樹脂の充填
においては、この硬化型導電性樹脂が上記貫通孔の全空
間を満たすように充填すればよい。上記硬化型導電性樹
脂の代表的な充填法としては、例えば、印刷法により1
回あるいは複数回の塗布を行う方法、上記両面基板の表
裏両面側から表裏一対のスキージにより圧入する方法、
ロールコーターあるいはカーテンコーターにより充填
し、過度量をスキージで掻き取る方法等が好適に用いら
れる。また、貫通孔に充填された硬化型導電性樹脂の硬
化は、熱風炉,赤外線炉,遠赤外線炉,紫外線硬化炉,
電子線硬化炉等公知の硬化方法により硬化型導電性樹脂
の硬化に適するものを選択すればよい。In filling the through-hole with the curable conductive resin, the curable conductive resin may be filled so as to fill the entire space of the through-hole. As a typical filling method of the curable conductive resin, for example, a printing method is used.
A method of applying once or a plurality of times, a method of press-fitting with a pair of front and back squeegees from both front and back sides of the double-sided board,
A method of filling with a roll coater or a curtain coater and scraping an excessive amount with a squeegee is suitably used. The curing of the curable conductive resin filled in the through holes is performed by a hot air oven, infrared oven, far-infrared oven, ultraviolet curing oven,
What is necessary is just to select what is suitable for hardening of a hardening type conductive resin by well-known hardening methods, such as an electron beam hardening furnace.
【0014】上記貫通孔内に硬化型導電性樹脂が充填さ
れた両面基板における回路形成は、予め接着剤層に貫通
孔を設け、この貫通孔に硬化型導電性樹脂を充填し、こ
の接着剤層の表裏両面に銅箔を貼り合わせたのちパター
ニングを行うことにより得られる。回路層の厚みは、3
6μm以下に設定され、好ましくは18μm以下がよ
い。この範囲以上では、回路配線の微細化が難しい。To form a circuit on a double-sided board in which the through-hole is filled with a curable conductive resin, a through-hole is provided in advance in an adhesive layer, and the through-hole is filled with the curable conductive resin. It is obtained by laminating copper foil on both sides of the layer and then performing patterning. The thickness of the circuit layer is 3
It is set to 6 μm or less, preferably 18 μm or less. Above this range, it is difficult to miniaturize circuit wiring.
【0015】基板の低熱膨張化を実現するために用いら
れる芯材としては、Fe,Ni,Cr,Al,Ti,C
u,Coあるいはこれらを含む合金箔、もしくはセラミ
ック材料が用いられる。上記金属箔もしくはセラミック
材料は、導体層および絶縁層の膨張を抑制する働きをす
るため、それ自体の熱膨張率は充分に小さい必要があ
る。芯材がNi−Fe系合金箔の場合、その比率により
熱膨張率が変化するため、Ni含有率(重量%)は31
〜50重量%、好ましくは31〜45重量%の範囲が好
適に用いられる。この範囲以上もしくは以下であると、
熱膨張係数が大きく、チップと同等の熱膨張係数を得ら
れない。また、上記金属箔の厚みは、10〜300μ
m、好ましくは、10〜200μm、さらに好ましく
は、10〜100μmの範囲がよい。この厚みより小さ
いと、回路基板とシリコンチップの熱膨張差を抑えるこ
とができない。また、上記金属箔と絶縁層の合計厚みに
対する上記金属箔の厚みの割合は、10〜95%、好ま
しくは、30〜95%である。この割合より小さいと、
温度サイクル試験時、ビアホールの寸法変化を充分に抑
制できないという問題があり、大きいと、マイグレーシ
ョン試験において回路層とメタルコア間における絶縁抵
抗値が上昇するという問題がある。Core materials used for realizing low thermal expansion of the substrate include Fe, Ni, Cr, Al, Ti, and C.
u, Co or an alloy foil containing them, or a ceramic material is used. Since the metal foil or the ceramic material functions to suppress the expansion of the conductor layer and the insulating layer, the coefficient of thermal expansion of the metal foil or the ceramic material itself needs to be sufficiently small. When the core material is a Ni—Fe alloy foil, since the coefficient of thermal expansion changes depending on the ratio, the Ni content (% by weight) is 31%.
The range of 50 to 50% by weight, preferably 31 to 45% by weight is suitably used. If it is above or below this range,
The coefficient of thermal expansion is large, and the same coefficient of thermal expansion as the chip cannot be obtained. The thickness of the metal foil is 10 to 300 μm.
m, preferably 10 to 200 μm, more preferably 10 to 100 μm. If the thickness is smaller than this, the difference in thermal expansion between the circuit board and the silicon chip cannot be suppressed. The ratio of the thickness of the metal foil to the total thickness of the metal foil and the insulating layer is 10 to 95%, preferably 30 to 95%. If less than this percentage,
During the temperature cycle test, there is a problem that the dimensional change of the via hole cannot be sufficiently suppressed. If the size is large, there is a problem that the insulation resistance value between the circuit layer and the metal core increases in the migration test.
【0016】上記両面回路基板を多層化するには、上記
両面回路基板の必要な場所に対応する位置に開孔した接
着シートを、上記両面回路基板の両面もしくは片面に位
置合わせして仮接着し、上記開孔部に印刷で半田ペース
トを入れ、加熱溶融させて半田バンプを形成した上記半
田バンプ付き両面回路基板を位置合わせして複数枚重
ね、加熱加圧し一体化させることにより実現できる。こ
こで、上記開孔部は、両面回路基材の表裏両面の配線導
体を電気的に接続しているビア上回路においても適用す
ることができる。In order to make the double-sided circuit board multi-layered, an adhesive sheet perforated at a position corresponding to a required position of the double-sided circuit board is aligned and temporarily bonded to both sides or one side of the double-sided circuit board. It can be realized by putting a solder paste into the opening by printing, heating and melting the double-sided circuit board with solder bumps on which solder bumps are formed, aligning a plurality of the double-sided circuit boards, and applying heat and pressure to integrate them. Here, the opening may be applied to a circuit on a via that electrically connects wiring conductors on both front and back surfaces of a double-sided circuit substrate.
【0017】上記接着シートは積層一体化後に絶縁層と
なるため、これを構成する接着剤としては、耐熱性,電
気的特性等からポリイミド系,エポキシ系またはその混
合系等が好ましい。上記接着シートの厚みとしては、
0.01mmから1.0mm程度とするのがよい。この
範囲より小さいと作業性が悪い。この範囲以上であると
半田ペーストがうまく上記開孔部に充填されず信頼性を
低下させる原因となる。上記接着シートに孔を開ける手
段としては、孔の大きさにより適切な方法を選択すれば
よいが、例えば、ドリル,パンチ,レーザー等が挙げら
れる。Since the above-mentioned adhesive sheet becomes an insulating layer after lamination and integration, the adhesive constituting the adhesive sheet is preferably a polyimide type, an epoxy type or a mixture type thereof from the viewpoint of heat resistance, electric characteristics and the like. As the thickness of the adhesive sheet,
It is preferable that the thickness be about 0.01 mm to 1.0 mm. If it is smaller than this range, workability is poor. If the amount is more than this range, the solder paste is not filled into the opening portion well, which causes a decrease in reliability. As a means for forming a hole in the adhesive sheet, an appropriate method may be selected according to the size of the hole, and examples thereof include a drill, a punch, and a laser.
【0018】上記接着シートを仮固定する工程におい
て、上記低熱膨張両面回路基板の両面もしくは片面の任
意の位置に、開孔した接着シートを熱プレスを用いて仮
接着すればよい。また、予め接着シートを上記両面回路
基板の両面もしくは片面に仮接着したのち、レーザーを
用いて開孔してもよい。レーザーとしては、炭酸ガス,
エキシマ,YAG等が好適に用いられる。In the step of temporarily fixing the adhesive sheet, the opened adhesive sheet may be temporarily bonded to an arbitrary position on both sides or one side of the low thermal expansion double-sided circuit board by using a hot press. Alternatively, the adhesive sheet may be preliminarily bonded to both sides or one side of the double-sided circuit board, and then the holes may be opened using a laser. As a laser, carbon dioxide,
Excimer, YAG and the like are preferably used.
【0019】上記半田バンプを形成するにあたり、半田
ペーストは一般に市販されているものが用いられるが、
半田粒子の大きさは100μm以下、好ましくは50μ
m以下、さらに好ましくは10μm以下に設定される。
また、半田組成は特に限定されず、基板に求められる耐
熱性に応じて選択すればよい。積層後の半田バンプは対
局電極に接触して導通されるが、必要であれば、半田の
融点以上に基板を加熱して金属接合させてもよい。この
金属接合させる方法は、加熱加圧による基板の一体化と
同時に行うか、もしくは一体化したのちに再度加熱して
も良い。In forming the solder bumps, a commercially available solder paste is used.
The size of the solder particles is 100 μm or less, preferably 50 μm.
m or less, more preferably 10 μm or less.
The solder composition is not particularly limited, and may be selected according to the heat resistance required for the substrate. The solder bumps after the lamination are brought into contact with the opposite electrodes and become conductive, but if necessary, the substrate may be heated to a temperature higher than the melting point of the solder for metal bonding. This metal bonding method may be performed simultaneously with the integration of the substrates by heating and pressing, or may be performed again after the integration.
【0020】[0020]
【発明の実施の形態】つぎに、本発明の実施の形態を図
面にもとづいて説明する。Next, embodiments of the present invention will be described with reference to the drawings.
【0021】図1は本発明の多層配線基板の一実施の形
態を示している。図において、1はNi−Fe系合金箔
2を基体としたポリイミド樹脂からなる絶縁層3の表裏
両面に銅箔からなる回路(配線導体)4が形成された両
面回路基板である。この実施の形態では、3枚の両面回
路基板1が用いられており、これにより、多層配線基板
として6層配線基板が作製されている。5は上記各両面
回路基板1に穿設された貫通孔(ビアホール)1aに導
電性ペースト5aを充填してなるビアであり、表裏両面
の回路4を電気的に接続している。上記導電性ペースト
5aとしては、導電性のフィラーとして平均粒径5μm
の球状銅粉末を、樹脂として熱硬化エポキシ樹脂を、硬
化剤として酸無水物系の硬化剤をそれぞれ混合したもの
を使用した。6は上記各両面回路基板1同士を接着する
ポリイミド系接着剤層である。7は積み重なる(上下に
隣り合う)2つの両面回路基板1の回路4を電気的に接
続する半田製導電体である。FIG. 1 shows an embodiment of the multilayer wiring board of the present invention. In FIG. 1, reference numeral 1 denotes a double-sided circuit board in which a circuit (wiring conductor) 4 made of a copper foil is formed on both front and back surfaces of an insulating layer 3 made of a polyimide resin having a Ni-Fe alloy foil 2 as a base. In this embodiment, three double-sided circuit boards 1 are used, whereby a six-layer wiring board is manufactured as a multilayer wiring board. Reference numeral 5 denotes a via formed by filling a through-hole (via hole) 1a formed in each of the double-sided circuit boards 1 with a conductive paste 5a, and electrically connects the circuits 4 on both front and back sides. The conductive paste 5a has a mean particle size of 5 μm as a conductive filler.
The spherical copper powder was mixed with a thermosetting epoxy resin as a resin and an acid anhydride-based curing agent as a curing agent. Reference numeral 6 denotes a polyimide adhesive layer for bonding the two-sided circuit boards 1 to each other. Reference numeral 7 denotes a conductor made of solder for electrically connecting the circuits 4 of the two double-sided circuit boards 1 stacked (adjacent to each other).
【0022】上記両面回路基板1を、つぎのようにして
製造することができる。すなわち、まず、図2に示すよ
うに、Ni−Fe系合金箔2の所定位置(半田製導電体
5aを充填するビア5を設ける位置)に孔2aを開け、
ついで、Ni−Fe系合金箔2の表裏両面からポリイミ
ド系接着シート11(後述する基材8の絶縁層3とな
る)を張り合わせ、図3に示すような基材8を作製す
る。つぎに、図4に示すように、上記基材8のNi−F
e系合金箔2の開孔部2aに対応する部分に、この開孔
部2aより小さい貫通孔1aを開ける。つぎに、図5に
示すように、この貫通孔1aに導電性ペースト5aを充
填したのち、表裏両面から、銅箔からなる導体層4aを
貼り合わせることにより、表裏両面の導体層4aを電気
的に接続する(図6参照)。このようにして得られた基
材9の熱膨張率は芯材の材料であるNi−Fe系合金に
支配されているため、Ni−Feの比率や箔の厚みを変
えることにより上記熱膨張率を調節することができる。
つぎに、図6に示す基材9の表裏両面の導体層4aに回
路4を形成して両面回路基板1(図7参照)を作製す
る。The double-sided circuit board 1 can be manufactured as follows. That is, first, as shown in FIG. 2, a hole 2 a is opened at a predetermined position of the Ni—Fe alloy foil 2 (a position where a via 5 filling the conductor 5 a made of solder) is provided.
Then, a polyimide-based adhesive sheet 11 (which will be an insulating layer 3 of the base material 8 described later) is attached to the front and back surfaces of the Ni-Fe-based alloy foil 2 to produce the base material 8 as shown in FIG. Next, as shown in FIG.
In the portion corresponding to the opening 2a of the e-based alloy foil 2, a through hole 1a smaller than the opening 2a is opened. Next, as shown in FIG. 5, after filling the through-hole 1a with the conductive paste 5a, the conductor layers 4a made of copper foil are bonded from both the front and back surfaces to electrically connect the conductor layers 4a on both front and back surfaces. (See FIG. 6). Since the coefficient of thermal expansion of the base material 9 thus obtained is governed by the Ni—Fe-based alloy as the material of the core material, the coefficient of thermal expansion can be changed by changing the ratio of Ni—Fe and the thickness of the foil. Can be adjusted.
Next, the circuit 4 is formed on the conductor layers 4a on both the front and back surfaces of the base material 9 shown in FIG. 6 to produce the double-sided circuit board 1 (see FIG. 7).
【0023】上記多層配線基板を、つぎのようにして製
造することができる。すなわち、まず、ポリイミド樹脂
からなる絶縁層3の表裏両面に銅箔よりなる回路4が形
成された3枚の両面回路基板1(図7参照)と、ポリイ
ミド系接着剤からなる2枚の接着シート(図8参照)1
3とを準備する。ついで、図9に示すように、上記各接
着シート13を(3枚のうちの)2枚の両面回路基板1
の上面に、各接着シート13の開孔部13aを各両面回
路基板1の回路4の所定位置(図1の半田製導電体7を
設ける位置)に位置合わせして仮接着する。つぎに、図
10に示すように、上記各接着シート13の開孔部13
aにスクリーン印刷により半田ペーストを入れ、加熱溶
融させて各両面回路基板1の回路4上に半田バンプ14
を形成する。つぎに、半田バンプ14を設けた2枚の両
面回路基板1と、回路4を形成しただけの1枚の両面回
路基板1をそれぞれ位置合わせして複数枚重ねたのち
(図11参照)、加熱加圧し一体化させる。この状態で
は、各接着シート13は接着剤層6となり、各半田バン
プ14は半田製導電体7となる。これにより、3枚の両
面回路基板1が積層一体化された6層配線基板を得るこ
とができる。The above multilayer wiring board can be manufactured as follows. That is, first, three double-sided circuit boards 1 (see FIG. 7) in which a circuit 4 made of copper foil is formed on both sides of an insulating layer 3 made of a polyimide resin, and two adhesive sheets made of a polyimide-based adhesive (See FIG. 8)
Prepare 3 and 3. Next, as shown in FIG. 9, each of the adhesive sheets 13 is attached to two (of three) double-sided circuit boards 1.
The opening 13a of each adhesive sheet 13 is aligned with a predetermined position of the circuit 4 of each double-sided circuit board 1 (the position where the solder conductor 7 in FIG. 1 is provided) and temporarily bonded. Next, as shown in FIG.
a, solder paste is applied to the circuit 4 of each double-sided circuit board 1 by heating and melting.
To form Next, two double-sided circuit boards 1 on which the solder bumps 14 are provided and one double-sided circuit board 1 on which only the circuit 4 is formed are aligned with each other, and a plurality of the double-sided circuit boards 1 are stacked (see FIG. 11). Press and integrate. In this state, each adhesive sheet 13 becomes the adhesive layer 6, and each solder bump 14 becomes the conductor 7 made of solder. As a result, a six-layer wiring board in which three double-sided circuit boards 1 are laminated and integrated can be obtained.
【0024】上記のように、この実施の形態では、一回
の加熱加圧により3枚の両面回路基板1の一体化が行え
ると同時に、6層間の電気的接続が行える。しかも、2
層の回路4に対して、1層の割合でNi−Fe系合金箔
2が配設されているため、銅箔で回路4を構成する場合
にも、6層配線基板全体の熱膨張率を低くすることがで
き、極めて高い接続信頼性を得ることができる。また、
6層の電気的接続(6層間の電気的接続)には、いずれ
も導電体5a,7を用いているため、接続抵抗が低く、
信頼性の高い接続が行える。さらに、各半田製導電体7
の接合部の位置は、ビア5の導電性ペースト5aの影響
を受けず、任意の位置に配置できるため、設計の自由度
が上がり、高密度配線が実現できる。As described above, in this embodiment, the three double-sided circuit boards 1 can be integrated by one heating and pressurization, and at the same time, the electrical connection between the six layers can be performed. Moreover, 2
Since the Ni—Fe-based alloy foil 2 is disposed at a ratio of one layer to the circuit 4 of the layer, even when the circuit 4 is formed of copper foil, the thermal expansion coefficient of the entire six-layer wiring board is reduced. The connection reliability can be reduced, and extremely high connection reliability can be obtained. Also,
In the electrical connection of the six layers (electrical connection between the six layers), the conductors 5a and 7 are used, so that the connection resistance is low,
A highly reliable connection can be made. Furthermore, each conductor 7 made of solder
Can be arranged at any position without being affected by the conductive paste 5a of the via 5, so that the degree of freedom in design is increased and high-density wiring can be realized.
【0025】以下、実施例により、本発明の効果を示
す。Hereinafter, the effects of the present invention will be described with reference to examples.
【0026】[0026]
【実施例】所定位置に直径150μmのパンチで300
μmピッチにて孔2aを開けた厚み50μmの36アロ
イ箔2(Ni:36重量%,Fe:64重量%、熱膨張
係数1.5ppm/℃)の表裏両面に、厚み35μmの
ポリイミド系接着シート11(新日鐡化学社製:SPB
−035A)を用いて、加圧加熱接着(40kg/cm
2 、200℃、60min)を行い(図2参照)、低熱
膨張基板8を作製した(図3参照)。つぎに、36アロ
イ箔2の孔2aと同じ位置に直径100μmのパンチを
用いて貫通孔1aを開けた(図4参照)。上記貫通孔1
a上部に導電性ペーストをスクリーン印刷により充填し
たのち、硬化(175℃、60min)を行い、導電性
ビア5を設けた(図5参照)。このとき、導電性ペース
トは、導電性のフィラーとして平均粒径5μmの球状銅
粉末を、樹脂として熱硬化エポキシ樹脂を、硬化剤とし
て酸無水物系の硬化剤をそれぞれ85重量%、12.5
重量%、2.5重量%の割合で混合したものを使用し
た。つぎに、上記低熱膨張基板8の表裏両面に、厚み1
8μmの銅箔4aを加圧加熱接着(40kg/cm 2 、
200℃、60min)を行ったのち(図6参照)、従
来のエッチング法により表裏両面の銅箔4aに回路4を
形成して両面回路基板1を作製した(図7参照)。Example: 300 mm at a predetermined position with a punch having a diameter of 150 μm.
36 holes of 50μm thickness with holes 2a opened at μm pitch
A foil 2 (Ni: 36% by weight, Fe: 64% by weight, thermal expansion
(Coefficient of 1.5 ppm / ° C)
Polyimide adhesive sheet 11 (manufactured by Nippon Steel Chemical: SPB
-035A) using pressure and heat bonding (40 kg / cm
Two(200 ° C, 60 min) (see Fig. 2)
An expansion substrate 8 was produced (see FIG. 3). Next, 36 alo
A punch having a diameter of 100 μm is placed at the same position as the hole 2 a of the foil 2.
Using this, a through-hole 1a was opened (see FIG. 4). The through hole 1
a Fill the top with conductive paste by screen printing
After curing (175 ° C, 60min)
A via 5 was provided (see FIG. 5). At this time, the conductive pace
Is spherical copper with an average particle size of 5 μm as a conductive filler
Powder, thermosetting epoxy resin as resin, curing agent
85% by weight of acid anhydride-based curing agent
% And 2.5% by weight.
Was. Next, a thickness of 1 on both surfaces of the low thermal expansion substrate 8.
8μm copper foil 4a is bonded under pressure and heat (40kg / cm Two,
(200 ° C., 60 min) (see FIG. 6).
The circuit 4 is applied to the copper foil 4a on both sides by the conventional etching method.
Thus, a double-sided circuit board 1 was manufactured (see FIG. 7).
【0027】上記方法により製造した低熱膨張両面回路
基板1に対して、直径150μmのパンチで孔13aを
開けたポリイミド系接着シート13(新日鐡化学社製:
SPB−035A)(図8参照)を所定の位置に合わせ
て載せ、その状態で加熱加圧接着(20kg/cm2 、
175℃、30min)した(図9参照)。つぎに、接
着シート13の開孔部13aに半田ペースト(タムラ化
研社製:SQ10−11)をスクリーン印刷で充填し、
220℃でリフローしたのち、フラックスを洗浄除去し
半田バンプ14を形成した(図10参照)。同様の方法
により、もう一枚の半田バンプ14付き両面回路基板1
と、回路4形成まで行った両面回路基板1を製造し、こ
れら3枚を位置合わせして重ね、加熱加圧(50kg/
cm2 、175℃、60min)により一体化し(図1
1参照)、6層配線基板を作製した(図1参照)。A polyimide adhesive sheet 13 (manufactured by Nippon Steel Chemical Co., Ltd.) in which holes 13a are opened with a punch having a diameter of 150 μm on the low-thermal-expansion double-sided circuit board 1 manufactured by the above method.
SPB-035A) (see FIG. 8) was placed at a predetermined position, and in that state, heat and pressure bonding (20 kg / cm 2 ,
(175 ° C., 30 min) (see FIG. 9). Next, the opening 13a of the adhesive sheet 13 was filled with a solder paste (manufactured by Tamura Kaken Corp .: SQ10-11) by screen printing.
After reflow at 220 ° C., the flux was washed away to form solder bumps 14 (see FIG. 10). In the same manner, another double-sided circuit board 1 with solder bumps 14
To manufacture a double-sided circuit board 1 which has been performed up to the formation of the circuit 4, these three substrates are aligned and stacked, and heated and pressed (50 kg /
cm 2 at 175 ° C. for 60 minutes (FIG. 1)
1), and a six-layer wiring board was produced (see FIG. 1).
【0028】[0028]
【比較例1】所定位置に直径150μmのパンチで30
0μmピッチにて孔2aを開けた厚み50μmの36ア
ロイ箔2(Ni:36重量%,Fe:64重量%,熱膨
張係数1.5ppm/℃)の表裏両面に、厚み18μm
の銅箔4aを厚み35μmのポリイミド系接着シート
(新日鐡化学社製:SPB−035A)(後述する基板
8の絶縁層3になる)を用いて加圧加熱接着(40kg
/cm2 、200℃、60min)し、低熱膨張基板8
を作製した(図12参照)。さらに、36アロイ箔2の
孔2aと同じ位置に直径100μmのパンチを用いて貫
通孔1aを開けた(図13参照)。つぎに、図14に示
すように、めっきの厚み10μmの銅のスルーホールめ
っきを行い(スルーホールめっき部16を形成し)、従
来のエッチング法により表裏両面の銅箔4aに回路4を
形成して両面回路基板1を作製した(図15参照)。Comparative Example 1 A punch having a diameter of 150 μm was placed at a predetermined position by 30
A 50 μm thick 36-alloy foil 2 (Ni: 36% by weight, Fe: 64% by weight, thermal expansion coefficient: 1.5 ppm / ° C.) having holes 2a formed at a pitch of 0 μm is formed on both the front and back surfaces by a thickness of 18 μm.
Pressure bonding by using a 35 μm-thick polyimide-based adhesive sheet (SPB-035A, manufactured by Nippon Steel Chemical Co., Ltd.) (which becomes the insulating layer 3 of the substrate 8 described below) under pressure and heat (40 kg)
/ Cm 2 , 200 ° C., 60 min) and a low thermal expansion substrate 8
(See FIG. 12). Further, a through-hole 1a was opened at the same position as the hole 2a of the 36 alloy foil 2 using a punch having a diameter of 100 μm (see FIG. 13). Next, as shown in FIG. 14, through-hole plating of copper having a plating thickness of 10 μm is performed (through-hole plating portions 16 are formed), and a circuit 4 is formed on the copper foil 4a on both front and back surfaces by a conventional etching method. Thus, a double-sided circuit board 1 was produced (see FIG. 15).
【0029】そののち、上記実施例と同様にして、接着
シート13を仮接着し、半田バンプ14を形成し、加熱
加圧して全体を一体化し、層間の電気的接続を行い、6
層構造の低熱膨張多層配線基板を作製した。After that, in the same manner as in the above embodiment, the adhesive sheet 13 is temporarily bonded, the solder bumps 14 are formed, the whole is integrated by heating and pressing, and the electrical connection between the layers is performed.
A low thermal expansion multilayer wiring board having a layer structure was manufactured.
【0030】[0030]
【比較例2】ポリイミド樹脂からなる絶縁層21(厚み
50μm)の表裏両面に厚み35μmのポリイミド系接
着シート22(新日鐡化学社製:SPB−035A)を
加圧加熱接着(40kg/cm2 、200℃、5mi
n)したポリイミド基材の所定の位置に直径100μm
のパンチで貫通孔23aを開けた(図16参照)。つぎ
に、上記貫通孔23a上部に導電性ペーストをスクリー
ン印刷により充填したのち、硬化(175℃、60mi
n)を行い、導電性ビア24を設けた(図17参照)。
このとき、導電性ペーストは、導電性のフィラーとして
平均粒径5μmの球状銅粉末を、樹脂として熱硬化エポ
キシ樹脂を、硬化剤として酸無水物系の硬化剤をそれぞ
れ85重量%、12.5重量%、2.5重量%の割合で
混合したものを使用した。つぎに、上記実施例と同様に
して、厚み18μmの銅箔を加圧加熱接着したのち、回
路25形成を行い、両面回路基板26を作製したのち
(図18参照)、接着シート13を仮接着し、半田バン
プ14を形成し、加熱加圧して全体を一体化し、層間の
電気的接続を行い、6層構造の低熱膨張多層配線基板を
作製した。Comparative Example 2 A 35-μm-thick polyimide-based adhesive sheet 22 (SPB-035A, manufactured by Nippon Steel Chemical Co., Ltd.) was applied to both the front and back surfaces of an insulating layer 21 (thickness: 50 μm) made of polyimide resin under pressure and heat (40 kg / cm 2) , 200 ° C, 5mi
n) A diameter of 100 μm at a predetermined position on the polyimide substrate
(See FIG. 16). Next, a conductive paste is filled in the upper portion of the through hole 23a by screen printing, and then cured (175 ° C., 60 mi).
n) was performed to provide conductive vias 24 (see FIG. 17).
At this time, the conductive paste was composed of spherical copper powder having an average particle size of 5 μm as a conductive filler, a thermosetting epoxy resin as a resin, and an acid anhydride-based curing agent as a curing agent at 85% by weight. What was mixed at the ratio of 2.5% by weight was used. Next, in the same manner as in the above example, a copper foil having a thickness of 18 μm was bonded by heating under pressure, a circuit 25 was formed, a double-sided circuit board 26 was produced (see FIG. 18), and an adhesive sheet 13 was temporarily bonded. Then, the solder bumps 14 were formed, and the whole was integrated by heating and pressurizing, and electrical connection between layers was performed, thereby producing a low thermal expansion multilayer wiring board having a six-layer structure.
【0031】上記のようにして作製した実施例、比較例
1,2に記載した6層配線基板における各ビア5,24
の電気的接続信頼性を熱衝撃試験(液層:−65℃⇔1
50℃、各5min)を用いて評価した。下記の表1に
は、各ビア5,24において導通不良が発生したサイク
ル数を示した。ここでは、抵抗値変化で±10%以上の
場合を導通不良と見なした。Each of the vias 5, 24 in the six-layer wiring board described in the embodiment and the comparative examples 1 and 2 manufactured as described above.
Thermal shock test (liquid layer: -65 ° C : 1)
(50 ° C., 5 min each). Table 1 below shows the number of cycles in which conduction failure occurred in each of the vias 5 and 24. Here, the case where the resistance value change is ± 10% or more is regarded as a conduction failure.
【0032】[0032]
【表1】 [Table 1]
【0033】上記の表1から明らかなように、比較例1
(従来のスルーホール構造を有した6層配線基板)にお
いては、100サイクル以下で導通不良が生じる。これ
に対して、実施例に示した6層配線基板は800サイク
ルまで、各ビア5の抵抗値変化は±10%以内を維持し
ており、各回路4間の電気的接続が導体性ペースト5a
が充填されたビア5,24により行われている6層配線
基板の接続信頼性が高いことが明白である。また、各回
路4間の電気的接続が導電性ビア5により行われている
実施例と比較例2を比較したところ、芯材として、Ni
−Fe系合金箔2を使用することにより信頼性が大幅に
向上している。Ni−Fe系合金箔2により、ビア5周
辺のZ軸方向の変形量が抑制されたために実施例の信頼
性が向上したと考えられる。As apparent from Table 1 above, Comparative Example 1
In a (six-layer wiring board having a conventional through-hole structure), conduction failure occurs in 100 cycles or less. On the other hand, in the six-layer wiring board shown in the example, the change in the resistance value of each via 5 is maintained within ± 10% up to 800 cycles, and the electrical connection between the circuits 4 is made of the conductive paste 5a.
It is clear that the connection reliability of the six-layered wiring board performed by the vias 5 and 24 filled with is high. Further, a comparison between the example in which the electrical connection between the respective circuits 4 is made by the conductive vias 5 and the comparative example 2 shows that Ni was used as the core material.
The reliability is greatly improved by using the Fe-based alloy foil 2. It is considered that the Ni-Fe-based alloy foil 2 suppressed the amount of deformation in the Z-axis direction around the via 5 and thus improved the reliability of the embodiment.
【0034】また、実施例,比較例2に関しては、任意
の層間を微細なビア5,24で自由に接続できるため、
設計の自由度が上がり、高密度配線を容易に実現できる
ことは明白である。In the embodiment and the comparative example 2, since arbitrary layers can be freely connected by fine vias 5 and 24,
It is obvious that the degree of freedom in design is increased and high-density wiring can be easily realized.
【0035】さらに、上記両面回路基板1の絶縁層に
は、導体層4aに対して1層の割合でNi−Fe系合金
箔2からなる低熱膨張の芯材が含まれている。実施例お
よび比較例1,2に記載した6層配線基板の熱膨張率を
室温(25℃)から200℃の範囲で測定したところ、
下記の表2のようになった。Further, the insulating layer of the double-sided circuit board 1 contains a low thermal expansion core material made of a Ni--Fe alloy foil 2 in a ratio of one layer to the conductor layer 4a. When the coefficient of thermal expansion of the six-layer wiring boards described in Examples and Comparative Examples 1 and 2 was measured in a range from room temperature (25 ° C.) to 200 ° C.,
The results are shown in Table 2 below.
【0036】[0036]
【表2】 [Table 2]
【0037】上記の表2に示すように、芯材として、N
i−Fe系合金箔2を使用した実施例および比較例1の
6層配線基板の熱膨張率は極めて小さく、ベアチップ実
装に適した基板であることが明白である。このように、
実施例の低熱膨張多層配線基板は、ベアチップ実装に適
した極めて電気的接続信頼性の高い基板であることは言
うまでもない。As shown in Table 2 above, N was used as the core material.
The thermal expansion coefficients of the six-layer wiring boards of the example and the comparative example 1 using the i-Fe-based alloy foil 2 are extremely small, and it is clear that the boards are suitable for bare chip mounting. in this way,
Needless to say, the low thermal expansion multilayer wiring board of the embodiment is a board having extremely high electrical connection reliability suitable for bare chip mounting.
【0038】[0038]
【発明の効果】以上のように、本発明の多層配線基板に
よれば、スルーホールを設ける代りに、硬化型導電性樹
脂を充填したビアホールを設けると、温度サイクル試験
等の環境加速試験においても内部やコーナー部に亀裂が
生じず、接続信頼性が高い。また、硬化型導電性樹脂を
充填したビアホール上に半田製導電体を設けて、隣り合
う(積み重なる)2つの両面回路基板の配線導体を電気
的に接続することができるため、配線の自由度が大き
い。また、各両面回路基板に基体として配設したメタル
コアは、XY方向のみならず、Z方向にも極めて熱膨張
率が低いため、温度サイクル試験等の環境加速試験にお
いて、ビアホールの寸法変化を抑制する効果があり、接
続信頼性を向上させる。As described above, according to the multilayer wiring board of the present invention, when a via hole filled with a curable conductive resin is provided instead of providing a through hole, an environmental acceleration test such as a temperature cycle test can be performed. No cracks are formed inside or at the corners, and the connection reliability is high. In addition, since a conductor made of solder is provided on the via hole filled with the curable conductive resin and the wiring conductors of two adjacent (stacked) double-sided circuit boards can be electrically connected, the degree of freedom of wiring is increased. large. Further, since the metal core disposed as a base on each double-sided circuit board has a very low coefficient of thermal expansion not only in the XY directions but also in the Z direction, it suppresses dimensional changes of via holes in an environmental acceleration test such as a temperature cycle test. It is effective and improves connection reliability.
【0039】一方、本発明の製造方法では、両面回路基
板に接着シートを位置合わせして仮接着し、この接着シ
ートに開けた開口に半田バンプを形成したのち、各両面
回路基板を位置合わせして積重し加熱加圧して全体を一
体化させているため、一回の加熱加圧により複数の両面
回路基板を一体化することができる。と同時に、配線導
体の層数が何層であっても、上記一回の加熱加圧により
各配線導体間の電気的接続が行える。本発明において、
「両面回路基板の配線導体の所定部分に対応する位置に
開孔した接着シートを準備する」とは、接着シートを両
面回路基板上に載せたのち開孔する場合を含む意味であ
る。On the other hand, in the manufacturing method of the present invention, the adhesive sheet is aligned and temporarily bonded to the double-sided circuit board, solder bumps are formed in the openings formed in the adhesive sheet, and the double-sided circuit boards are aligned. Since the whole is integrated by heating and pressing, a plurality of double-sided circuit boards can be integrated by one heating and pressing. At the same time, regardless of the number of layers of the wiring conductor, electrical connection between the wiring conductors can be performed by the single heating and pressing. In the present invention,
“Preparing an adhesive sheet that is opened at a position corresponding to a predetermined portion of the wiring conductor of the double-sided circuit board” means that the adhesive sheet is placed on the double-sided circuit board and then opened.
【図1】本発明の多層配線基板の一実施の形態を示す断
面図である。FIG. 1 is a sectional view showing an embodiment of a multilayer wiring board of the present invention.
【図2】両面回路基板の製造工程を示す断面図である。FIG. 2 is a cross-sectional view illustrating a manufacturing process of the double-sided circuit board.
【図3】上記両面回路基板の製造工程を示す断面図であ
る。FIG. 3 is a sectional view showing a manufacturing process of the double-sided circuit board.
【図4】上記両面回路基板の製造工程を示す断面図であ
る。FIG. 4 is a cross-sectional view showing a manufacturing process of the double-sided circuit board.
【図5】上記両面回路基板の製造工程を示す断面図であ
る。FIG. 5 is a sectional view showing a manufacturing process of the double-sided circuit board.
【図6】上記両面回路基板の製造工程を示す断面図であ
る。FIG. 6 is a cross-sectional view showing a manufacturing process of the double-sided circuit board.
【図7】上記両面回路基板の断面図である。FIG. 7 is a sectional view of the double-sided circuit board.
【図8】接着シートを示す断面図である。FIG. 8 is a sectional view showing an adhesive sheet.
【図9】両面回路基板に接着シートを仮接着した状態を
示す断面図である。FIG. 9 is a cross-sectional view showing a state where an adhesive sheet is temporarily bonded to a double-sided circuit board.
【図10】接着シートに半田バンプを形成した状態を示
す断面図である。FIG. 10 is a sectional view showing a state in which solder bumps are formed on an adhesive sheet.
【図11】各両面回路基板を積層する状態を示す断面図
である。FIG. 11 is a cross-sectional view showing a state in which respective double-sided circuit boards are stacked.
【図12】比較例1の製造工程を示す断面図である。FIG. 12 is a cross-sectional view illustrating a manufacturing process of Comparative Example 1.
【図13】比較例1の製造工程を示す断面図である。FIG. 13 is a cross-sectional view illustrating a manufacturing process of Comparative Example 1.
【図14】比較例1の製造工程を示す断面図である。FIG. 14 is a cross-sectional view illustrating a manufacturing process of Comparative Example 1.
【図15】比較例1の製造工程を示す断面図である。FIG. 15 is a cross-sectional view illustrating a manufacturing process of Comparative Example 1.
【図16】比較例2の製造工程を示す断面図である。FIG. 16 is a cross-sectional view showing a manufacturing process of Comparative Example 2.
【図17】比較例2の製造工程を示す断面図である。FIG. 17 is a cross-sectional view illustrating a manufacturing process of Comparative Example 2.
【図18】比較例2の製造工程を示す断面図である。FIG. 18 is a cross-sectional view showing a manufacturing step of Comparative Example 2.
1 両面回路基板 2 合金箔 3 絶縁層 4 回路 5a 導電性ペースト 6 接着剤層 7 半田製導電体 DESCRIPTION OF SYMBOLS 1 Double-sided circuit board 2 Alloy foil 3 Insulating layer 4 Circuit 5a Conductive paste 6 Adhesive layer 7 Solder conductor
───────────────────────────────────────────────────── フロントページの続き (72)発明者 井上 泰史 大阪府茨木市下穂積1丁目1番2号 日東 電工株式会社内 (72)発明者 長沢 徳 大阪府茨木市下穂積1丁目1番2号 日東 電工株式会社内 (72)発明者 桶結 卓司 大阪府茨木市下穂積1丁目1番2号 日東 電工株式会社内 Fターム(参考) 5E346 AA03 AA43 CC08 CC09 CC10 CC32 CC37 CC38 CC39 CC40 DD02 EE05 EE08 EE13 FF18 FF19 FF24 GG08 GG09 GG15 GG28 HH31 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Yasushi Inoue 1-1-2 Shimohozumi, Ibaraki-shi, Osaka Nitto Denko Corporation (72) Inventor Toku Nagasawa 1-2-1, Shimohozumi, Ibaraki-shi, Osaka Nitto Denko Corporation (72) Inventor Takuji Okei 1-1-2 Shimohozumi, Ibaraki-shi, Osaka Nitto Denko Corporation F-term (reference) 5E346 AA03 AA43 CC08 CC09 CC10 CC32 CC37 CC38 CC39 CC40 DD02 EE05 EE08 EE13 FF18 FF19 FF24 GG08 GG09 GG15 GG28 HH31
Claims (6)
からなる絶縁層の両面に配線導体が設けられこれら両配
線導体が硬化型導電性樹脂が充填されたビアホールによ
り電気的に接続された複数の両面回路基板が、接着剤層
を介して積層一体化され、上記接着剤層には、これを挟
む2つの両面回路基板の配線導体に当接する部分の所定
位置に孔が穿設され、上記穿孔部に半田製導電体が設け
られ、上記半田製導電体により上記2つの両面回路基板
の配線導体が電気的に接続されていること特徴とする多
層配線基板。A plurality of wiring conductors are provided on both surfaces of an insulating layer made of an organic polymer resin having a metal core as a base, and both wiring conductors are electrically connected by via holes filled with a curable conductive resin. The double-sided circuit board is laminated and integrated via an adhesive layer, and a hole is formed in the adhesive layer at a predetermined position of a portion of the two double-sided circuit boards that abuts the wiring conductor and sandwiches the hole. A multi-layer wiring board, wherein a conductor made of solder is provided in a portion, and the wiring conductors of the two double-sided circuit boards are electrically connected by the conductor made of solder.
Au,Ni,Pb,Sn,Cから選ばれた少なくとも1
種類からなる導電性物質を含んでいる請求項1記載の多
層配線基板。2. The method according to claim 1, wherein the curable conductive resin is Ag, Cu,
At least one selected from Au, Ni, Pb, Sn, C
The multilayer wiring board according to claim 1, wherein the multilayer wiring board includes a conductive material of a kind.
Ti,Cu,Coあるいはこれらを含む合金からなる金
属箔である請求項1記載の多層配線基板。3. The method according to claim 2, wherein the metal core is Fe, Ni, Al,
2. The multilayer wiring board according to claim 1, which is a metal foil made of Ti, Cu, Co, or an alloy containing these.
であり、Ni含有量が31〜50重量%で、かつ、その
厚みが10μm〜100μmの範囲である請求項1記載
の多層配線基板。4. The multilayer wiring board according to claim 1, wherein the metal core is a Ni—Fe alloy foil, the Ni content is 31 to 50% by weight, and the thickness is in a range of 10 μm to 100 μm.
する上記メタルコアの厚みの割合が30〜95%である
請求項1記載の多層配線基板。5. The multilayer wiring board according to claim 1, wherein the ratio of the thickness of the metal core to the total thickness of the metal core and the insulating layer is 30 to 95%.
方法であって、メタルコアを基体とした有機高分子樹脂
からなる絶縁層の両面に配線導体が設けられこれら両配
線導体が硬化型導電性樹脂が充填されたビアホールによ
り電気的に接続された複数の両面回路基板と、上記両面
回路基板の配線導体の所定部分に対応する位置に開孔し
た接着シートとを準備する工程と、上記両面回路基板に
設けた配線導体の所定部分に上記接着シートの開孔部を
位置合わせした状態で上記両面回路基板に接着シートを
仮接着する工程と、接着シート仮接着後に各接着シート
の開孔部に印刷により半田ペーストを充填し加熱溶融さ
せて半田バンプを形成する工程と、半田バンプ形成後に
上記各両面回路基板の配線導体が所定の電気的接続を行
えるよう位置合わせして上記各両面回路基板を積み重ね
加熱加圧して全体を一体化させる工程を備えていること
特徴とする多層配線基板の製造方法。6. A method for manufacturing a multilayer wiring board according to claim 1, wherein wiring conductors are provided on both surfaces of an insulating layer made of an organic polymer resin having a metal core as a base, and both of the wiring conductors are hardened conductive layers. Preparing a plurality of double-sided circuit boards electrically connected by via holes filled with a conductive resin, and an adhesive sheet opened at a position corresponding to a predetermined portion of a wiring conductor of the double-sided circuit board; Temporarily bonding the adhesive sheet to the double-sided circuit board in a state where the opening of the adhesive sheet is aligned with a predetermined portion of the wiring conductor provided on the circuit board; Filling the solder paste by printing and heating and melting to form solder bumps, and aligning the wiring conductors on each of the double-sided circuit boards after the formation of the solder bumps so that predetermined electrical connections can be made. And a step of stacking the double-sided circuit boards, heating and pressurizing them to integrate them as a whole.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19955499A JP2001028481A (en) | 1999-07-13 | 1999-07-13 | Multi-layer wiring board and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19955499A JP2001028481A (en) | 1999-07-13 | 1999-07-13 | Multi-layer wiring board and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2001028481A true JP2001028481A (en) | 2001-01-30 |
Family
ID=16409767
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19955499A Pending JP2001028481A (en) | 1999-07-13 | 1999-07-13 | Multi-layer wiring board and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2001028481A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6328201B1 (en) * | 1997-09-25 | 2001-12-11 | Nitto Denko Corporation | Multilayer wiring substrate and method for producing the same |
JP2002231342A (en) * | 2001-02-02 | 2002-08-16 | Citizen Electronics Co Ltd | Electrical connector |
JP2017191874A (en) * | 2016-04-14 | 2017-10-19 | 新光電気工業株式会社 | Wiring board and method for manufacturing the same |
-
1999
- 1999-07-13 JP JP19955499A patent/JP2001028481A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6328201B1 (en) * | 1997-09-25 | 2001-12-11 | Nitto Denko Corporation | Multilayer wiring substrate and method for producing the same |
JP2002231342A (en) * | 2001-02-02 | 2002-08-16 | Citizen Electronics Co Ltd | Electrical connector |
JP2017191874A (en) * | 2016-04-14 | 2017-10-19 | 新光電気工業株式会社 | Wiring board and method for manufacturing the same |
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