JPH1145955A - Device built-in multilayered printed circuit board and its manufacture - Google Patents
Device built-in multilayered printed circuit board and its manufactureInfo
- Publication number
- JPH1145955A JPH1145955A JP9201653A JP20165397A JPH1145955A JP H1145955 A JPH1145955 A JP H1145955A JP 9201653 A JP9201653 A JP 9201653A JP 20165397 A JP20165397 A JP 20165397A JP H1145955 A JPH1145955 A JP H1145955A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- circuit layer
- wiring circuit
- insulating
- electric element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、例えば、多層配線
基板及び半導体素子収納用パッケージなどに適し、特に
絶縁基板内部に電気素子が内蔵されてなる多層配線基板
とその製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board suitable for, for example, a multilayer wiring board and a package for accommodating a semiconductor element, and more particularly to a multilayer wiring board having an electric element built in an insulating substrate and a method of manufacturing the same.
【０００２】[0002]
【従来技術】従来より、電子機器は小型化が進んでいる
が、近年携帯情報端末の発達や、コンピューターを持ち
運んで操作する、いわゆるモバイルコンピューティング
の普及によってさらに小型、薄型且つ高精細の多層配線
基板が求められる傾向にある。2. Description of the Related Art Conventionally, electronic devices have been reduced in size. However, in recent years, with the development of portable information terminals and the spread of so-called mobile computing that carries and operates a computer, so-called mobile computing has become smaller, thinner and higher definition multilayer wiring. Substrates tend to be required.
【０００３】従来のプリント配線基板では、プリプレグ
と呼ばれる有機樹脂を含む平板の表面に銅箔を接着した
後、これをエッチングして微細な回路を形成し、これを
積層した後、所望位置にマイクロドリルでスルーホール
の穴明けを行い、そのホール内壁にメッキ法により金属
を付着させてスルーホール導体を形成して各層間の電気
的な接続を行っている。In a conventional printed wiring board, a copper foil is adhered to the surface of a flat plate containing an organic resin called a prepreg, and then etched to form a fine circuit. Through holes are drilled with a drill, metal is adhered to the inner walls of the holes by plating to form through-hole conductors, and electrical connection between the layers is performed.
【０００４】ところが、この方法では、スルーホール導
体は配線基板全体にわたり貫通したものであるために、
積層数が増加するに伴い、スルーホール数が増加する
と、配線に必要なスペースが確保できなくなるという問
題が生じ、電子機器の軽量、小型化に伴うプリント基板
の薄層化、小型化、軽量化に対しては、対応できないの
が現状である。However, in this method, since the through-hole conductor penetrates the entire wiring board,
As the number of stacked layers increases, the number of through-holes increases, making it impossible to secure the space required for wiring, and the thinning, miniaturization, and weight reduction of printed circuit boards accompanying the lightness and miniaturization of electronic devices. Can not respond to the current situation.
【０００５】そこで、最近では、絶縁層に対して形成し
たビアホール内に金属粉末を充填してビアホール導体を
形成した後、他の絶縁層を積層して多層化した配線基板
が提案されている。Therefore, recently, a wiring board has been proposed in which a via hole formed in an insulating layer is filled with metal powder to form a via-hole conductor, and then another insulating layer is laminated to form a multilayer.
【０００６】また、従来のプリント配線基板に対して、
半導体素子やコンデンサ素子、抵抗素子などを実装する
場合には、配線基板の表面に形成された配線回路層に対
してこれらの電気素子を半田等により実装し、実装した
素子を樹脂によってモールドする方法、絶縁基板の表面
に凹部を形成して、その凹部内に素子を収納して樹脂モ
ールドしたり、蓋体によって凹部を気密に封止する方法
がある。[0006] Further, with respect to a conventional printed wiring board,
When mounting semiconductor elements, capacitor elements, resistance elements, etc., these electric elements are mounted on the wiring circuit layer formed on the surface of the wiring board by soldering, etc., and the mounted elements are molded with resin. There is a method of forming a concave portion on the surface of an insulating substrate, housing the element in the concave portion and performing resin molding, or sealing the concave portion hermetically with a lid.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、ビアホ
ール導体を金属粉末の充填によって形成する方法は、ビ
アホール導体の小径化が可能であるとともに、任意の位
置に配設できる点で配線基板の小型化に対しては有効で
あるが、配線基板をより多層化したとしても、その配線
基板に搭載する素子は、配線基板の表面にしか実装する
ことができないために、配線基板の小型化には自ずと限
界があった。However, the method of forming the via-hole conductor by filling the metal powder can reduce the diameter of the via-hole conductor and reduce the size of the wiring board in that the via-hole conductor can be arranged at an arbitrary position. Although it is effective for wiring boards, even if the wiring board is multi-layered, the elements mounted on the wiring board can only be mounted on the surface of the wiring board, which naturally limits the miniaturization of the wiring board was there.
【０００８】従って、本発明は、半導体素子や電子部品
（コンデンサ素子、抵抗素子、フィルター素子、発振素
子など）の電気素子を搭載する多層配線基板において、
基板の小型化と、素子の実装密度を高めることのできる
多層配線基板を提供することを目的とするものである。
さらに、本発明は、基板の内部に素子を内蔵することの
できる多層配線基板を容易に作製することのできる多層
配線基板の製造方法を提供することを目的とするもので
ある。Accordingly, the present invention provides a multilayer wiring board on which electric elements such as semiconductor elements and electronic parts (capacitor elements, resistance elements, filter elements, oscillation elements, etc.) are mounted.
It is an object of the present invention to provide a multilayer wiring board capable of reducing the size of a board and increasing the mounting density of elements.
Still another object of the present invention is to provide a method of manufacturing a multilayer wiring board that can easily manufacture a multilayer wiring board in which elements can be built in a substrate.
【０００９】[0009]
【課題を解決するための手段】本発明者は、電気素子を
搭載した配線基板の小型化について検討を重ねた結果、
配線基板内に、電気素子を実装収納するための空隙部を
形成することにより、配線基板のより多くの電気素子を
搭載した小型の配線基板を提供できること、さらには，
配線基板を作製するにあたり、金属箔からなる配線回路
層を転写シートからの転写によって形成する際に、転写
シート上のする銅箔に予め電気素子を半田などで接続し
た後に、空隙部を形成した絶縁層に転写することで、絶
縁層に何ら影響を及ぼすことなく、素子を内蔵した配線
基板を作製できることを見いだし、本発明に至った。The inventor of the present invention has studied the miniaturization of a wiring board on which electric elements are mounted, and as a result,
By forming a gap portion for mounting and housing the electric element in the wiring board, it is possible to provide a small-sized wiring board on which more electric elements of the wiring board are mounted.
In manufacturing the wiring board, when forming a wiring circuit layer made of a metal foil by transfer from a transfer sheet, a gap portion was formed after an electric element was previously connected to a copper foil to be formed on the transfer sheet by soldering or the like. The present inventors have found that a transfer board having a built-in element can be manufactured without any influence on the insulating layer by transferring to the insulating layer.
【００１０】即ち、本発明の多層配線基板は、電気素子
を内蔵したものであり、少なくとも熱硬化性樹脂を含む
複数の絶縁層を積層してなる絶縁基板と、該絶縁基板の
表面および内部に形成された配線回路層と、前記配線回
路層間を電気的に接続するためのビアホール導体を具備
する多層配線基板において、前記絶縁基板内部に、空隙
部を形成するとともに、該空隙部内に電気素子を実装収
納してなることを特徴とするものである。That is, the multilayer wiring board of the present invention has a built-in electric element, and has at least a plurality of insulating layers containing a thermosetting resin laminated on each other; In the formed wiring circuit layer, in a multilayer wiring board including a via hole conductor for electrically connecting the wiring circuit layers, a void portion is formed inside the insulating substrate, and an electric element is formed in the void portion. It is characterized by being mounted and stored.
【００１１】また、前記空隙部内にて、前記電気素子を
金属箔からなる配線回路層に半田実装してなること、前
記電気素子が、半導体素子または電子部品であること、
前記配線回路層を金属箔により形成し、前記ビアホール
導体を金属粉末の充填によって形成したこと、さらに
は、前記空隙部を、配線基板の積層方向に複数設けたこ
とを特徴とするものである。The electric element is solder-mounted in a wiring circuit layer made of a metal foil in the gap, and the electric element is a semiconductor element or an electronic component.
The wiring circuit layer is formed of a metal foil, the via-hole conductor is formed by filling a metal powder, and a plurality of the voids are provided in a stacking direction of a wiring board.
【００１２】また、かかる配線基板の製造方法として
は、転写シートの表面に形成された配線回路層に電気素
子を実装する実装工程と、少なくとも熱硬化性樹脂から
なる第１の絶縁層にキャビティを形成するキャビティ形
成工程と、前記第１の絶縁層の前記キャビティ内に前記
電気素子が収納されるように、前記転写シートから前記
配線回路層と前記電気素子を前記第１の絶縁層に転写す
る転写工程と、転写工程後の前記第１の絶縁層の上下面
に、少なくとも熱硬化性樹脂を含む第２および第３の絶
縁層を積層圧着する積層工程、とを具備することを特徴
とするものである。Further, as a method of manufacturing such a wiring board, a mounting step of mounting an electric element on a wiring circuit layer formed on a surface of a transfer sheet, and forming a cavity in at least a first insulating layer made of a thermosetting resin. Forming a cavity, and transferring the wiring circuit layer and the electric element from the transfer sheet to the first insulating layer so that the electric element is accommodated in the cavity of the first insulating layer. A transfer step, and a laminating step of laminating and pressing at least second and third insulating layers containing a thermosetting resin on the upper and lower surfaces of the first insulating layer after the transfer step. Things.
【００１３】[0013]
【発明の実施の形態】以下、本発明を図面をもとに説明
する。図１は、本発明の素子内蔵多層配線基板を製造す
るための第１の製造工程を説明するための図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a view for explaining a first manufacturing process for manufacturing a multilayer wiring board with a built-in element according to the present invention.
【００１４】図１によれば、まず、図１（ａ）に示すよ
うに、熱硬化性樹脂を含む軟質（Ｂステージ状態）の第
１の絶縁シート１を作製する。また、この絶縁シート１
には、所望により厚み方向に貫通するスルーホールを形
成し、そのスルーホール内に金属粉末を含む導体ペース
トをスクリーン印刷や吸引処理しながら充填して、ビア
ホール導体２を形成する。また、この絶縁シート１の所
定箇所に電気素子を収納するための空隙部３を形成す
る。According to FIG. 1, first, as shown in FIG. 1A, a soft (B-stage) first insulating sheet 1 containing a thermosetting resin is prepared. Also, this insulating sheet 1
A via-hole conductor 2 is formed by forming a through-hole penetrating in the thickness direction as desired, filling the through-hole with a conductive paste containing a metal powder while performing screen printing or suction processing. In addition, a gap 3 for accommodating an electric element is formed at a predetermined position of the insulating sheet 1.
【００１５】次に、図１（ｂ）に示すように、絶縁シー
ト１の表面に配線回路層４を形成するとともに、絶縁シ
ート１の空隙部に電気素子５を実装収納する。配線回路
層４は、１）絶縁シート１の表面に金属箔を貼り付けた
後、エッチング処理して回路パターンを形成する方法、
２）絶縁シート１表面にレジストを形成して、メッキに
より形成する方法、３）転写フィルム表面に金属箔を貼
り付け、金属箔をエッチング処理して回路パターンを形
成した後、この金属箔からなる回路パターンを絶縁シー
ト１表面に転写させる方法等が挙げられる。Next, as shown in FIG. 1B, the wiring circuit layer 4 is formed on the surface of the insulating sheet 1, and the electric element 5 is mounted and accommodated in the gap of the insulating sheet 1. The wiring circuit layer 4 includes: 1) a method of forming a circuit pattern by attaching a metal foil to the surface of the insulating sheet 1 and then performing an etching process;
2) A method in which a resist is formed on the surface of the insulating sheet 1 and formed by plating. 3) A metal foil is attached to the surface of the transfer film, and the metal foil is etched to form a circuit pattern. A method of transferring a circuit pattern onto the surface of the insulating sheet 1 is exemplified.
【００１６】本第１の製造方法においては、配線回路層
４と、配線回路層４に電気素子５を実装した構造物を転
写フィルムから絶縁シート１に転写させる。その具体的
な方法を図１（ｂ１）〜（ｂ３）に示す。この方法によ
れば、例えば、樹脂や金属からなる転写フィルム６の表
面に金属箔を接着した後、エッチングして配線回路層４
を形成する（図１（ｂ１））。その後、その配線回路層
４に、電気素子５を半田、ＴＡＢ、ワイヤーボンディン
グにより実装する（図１（ｂ２））。In the first manufacturing method, the wiring circuit layer 4 and the structure in which the electric element 5 is mounted on the wiring circuit layer 4 are transferred from the transfer film to the insulating sheet 1. The specific method is shown in FIGS. 1 (b1) to (b3). According to this method, for example, a metal foil is adhered to the surface of the transfer film 6 made of resin or metal, and then etched to form the wiring circuit layer 4.
Is formed (FIG. 1 (b1)). Thereafter, the electric element 5 is mounted on the wiring circuit layer 4 by soldering, TAB, and wire bonding (FIG. 1 (b2)).
【００１７】その後、電気素子５が実装された転写フィ
ルム６を絶縁シート１に対して、電気素子５が絶縁シー
ト１の空隙部３に収納されるように積層して圧着した
後、転写フィルム６を剥がして（図１（ｂ３））、配線
回路層４と電気素子５とを絶縁シート１に転写させて、
図１（ｂ）に示すような電気素子５が空隙部３に実装収
納された単層の配線層を形成することができる。この
時、絶縁シート１は、未硬化または半硬化状態であり軟
質であることから、配線回路層４を圧着することによ
り、絶縁シート１の表面に埋め込むことができるととも
に、絶縁シート１に形成されたビアホール導体２を緻密
化することができる。Thereafter, the transfer film 6 on which the electric element 5 is mounted is laminated and pressed on the insulating sheet 1 so that the electric element 5 is accommodated in the gap 3 of the insulating sheet 1. Is peeled off (FIG. 1 (b3)), the wiring circuit layer 4 and the electric element 5 are transferred to the insulating sheet 1, and
As shown in FIG. 1B, a single wiring layer in which the electric element 5 is mounted and accommodated in the gap 3 can be formed. At this time, since the insulating sheet 1 is in an uncured or semi-cured state and is soft, it can be embedded in the surface of the insulating sheet 1 by pressing the wiring circuit layer 4 and formed on the insulating sheet 1. Via hole conductor 2 can be made denser.
【００１８】また、上記の例では、基本的には、電気素
子５を実装する配線回路層４は、電気素子５とともに、
同時に転写させるものであるが、電気素子５の実装に関
与しない配線回路層（図示せず）は、電気素子５と配線
回路層４とともに同時するか、または個別に前述した
１）〜３）のいずれの方法で形成してもよい。In the above example, basically, the wiring circuit layer 4 on which the electric element 5 is mounted, together with the electric element 5,
The wiring circuit layer (not shown) which is to be transferred at the same time but is not involved in the mounting of the electric element 5 can be transferred together with the electric element 5 and the wiring circuit layer 4 or separately from the above-mentioned 1) to 3). It may be formed by any method.
【００１９】また、空隙部３内に収納された電気素子５
は、配線回路層４に実装された状態でエポキシ樹脂等に
より封止してもよい。The electric element 5 housed in the gap 3
May be sealed with an epoxy resin or the like while being mounted on the wiring circuit layer 4.
【００２０】次に、上記のように空隙部３内に電気素子
５が実装収納された絶縁シート１の上下面に、軟化状態
（Ｂステージ状態）の第２および第３の絶縁シート７、
８を積層圧着して、絶縁シート１、７、８中の熱硬化性
樹脂が硬化するに十分な温度に加熱して一括して完全硬
化させる。なお、絶縁シート７、８には、配線回路層
９、１０やビアホール導体１１、１２を前述した方法に
より適宜形成してもよい。このようにして、図１（ｃ）
に示すように、絶縁基板１３内に電気素子５を内蔵する
多層配線基板を形成することができる。Next, the second and third insulating sheets 7 in a softened state (B stage state) are provided on the upper and lower surfaces of the insulating sheet 1 in which the electric element 5 is mounted and housed in the gap 3 as described above.
8 are laminated and pressure-bonded, heated to a temperature sufficient to cure the thermosetting resin in the insulating sheets 1, 7, 8 and completely cured at once. Note that the wiring sheets 9 and 10 and the via-hole conductors 11 and 12 may be appropriately formed on the insulating sheets 7 and 8 by the method described above. Thus, FIG. 1 (c)
As shown in (1), a multilayer wiring board in which the electric element 5 is built in the insulating substrate 13 can be formed.
【００２１】次に、本発明の第２の製造方法によれば、
図２（ａ）に示すように、熱硬化性樹脂を含有する絶縁
シート２０に、適宜ビアホールを形成してそのホール内
に金属粉末を含有する導体ペーストを充填してビアホー
ル導体２１を形成し、さらにその表面又は裏面に配線回
路層２２を形成する。配線回路層２２の形成は、前述し
た１）〜３）のいずれの方法でもよい。Next, according to the second manufacturing method of the present invention,
As shown in FIG. 2A, via holes are formed in the insulating sheet 20 containing a thermosetting resin as appropriate, and a conductive paste containing a metal powder is filled in the holes to form via-hole conductors 21. Further, the wiring circuit layer 22 is formed on the front surface or the back surface. The wiring circuit layer 22 may be formed by any of the above-described methods 1) to 3).
【００２２】次に、図２（ｂ）に示すように、配線回路
層２２の表面に、電気素子２３を半田、フリップチッ
プ、ワイヤーボンディングなどの方法で実装する。Next, as shown in FIG. 2B, an electric element 23 is mounted on the surface of the wiring circuit layer 22 by a method such as solder, flip chip, wire bonding, or the like.
【００２３】その後、図２（ｃ）に示すように、電気素
子２３が実装された絶縁シート２０の表面に、空隙部２
４が形成された絶縁シート２５を電気素子２３が空隙部
２４に収納されるように位置合わせして積層する。な
お、絶縁シート２５には、所望により配線回路層２６、
ビアホール導体２７を形成してもよい。Thereafter, as shown in FIG. 2C, the gap 2 is formed on the surface of the insulating sheet 20 on which the electric element 23 is mounted.
The insulating sheet 25 formed with 4 is aligned and laminated so that the electric element 23 is accommodated in the gap 24. The insulating sheet 25 may include a wiring circuit layer 26, if desired.
Via-hole conductor 27 may be formed.
【００２４】そして、図２（ｄ）に示すように、空隙部
２４が形成された絶縁シート２５を積層したその上に、
空隙部２４を密封するように、絶縁シート２８を積層す
る。Then, as shown in FIG. 2D, the insulating sheet 25 having the voids 24 formed thereon is laminated thereon.
An insulating sheet 28 is laminated so as to seal the gap 24.
【００２５】また、この絶縁シート２８には、所望によ
り配線回路層２９、ビアホール導体３０を形成してもよ
い。The insulating sheet 28 may be provided with a wiring circuit layer 29 and a via-hole conductor 30 if desired.
【００２６】そして、最終的にこれらの積層物を絶縁シ
ート２０、２５、２８中の熱硬化性樹脂が硬化するに十
分な温度に加熱して一括して完全硬化させることによ
り、絶縁基板内に電気素子２３を内蔵する多層配線基板
を形成することができる。Finally, these laminates are heated to a temperature sufficient to cure the thermosetting resin in the insulating sheets 20, 25, and 28, and are completely cured at a time, so that the laminated substrate can be placed inside the insulating substrate. A multilayer wiring board incorporating the electric element 23 can be formed.
【００２７】また、本発明によれば、上記第１および第
２の電気素子の空隙部内への実装収納方法を基礎とし
て、あらゆる形態の多層配線基板を作製することができ
る。例えば、図３に示すように、多層配線基板の絶縁基
板３２内において、ＩＣ素子３３やコンデンサ３４等の
などの電気素子を収納する空隙部３５、３６を同一面
内、または異なる層内に空隙部３７を複数箇所形成し
て、これら複数の電気素子を実装収納させることができ
る。また、絶縁基板３２の表面にも、他の電気素子３
８、３９を表面実装することができる。その結果、表面
のみならず、絶縁基板内部にも電気素子を高密度に実装
した多層配線基板を作製することができる。Further, according to the present invention, a multilayer wiring board of any form can be manufactured based on the method of mounting and housing the first and second electric elements in the gap. For example, as shown in FIG. 3, in an insulating substrate 32 of a multilayer wiring board, gaps 35 and 36 for accommodating electric elements such as an IC element 33 and a capacitor 34 are formed in the same plane or in different layers. A plurality of portions 37 can be formed to mount and house the plurality of electric elements. In addition, another electric element 3 is also provided on the surface of the insulating substrate 32.
8, 39 can be surface mounted. As a result, it is possible to manufacture a multilayer wiring board on which electric elements are mounted at high density not only on the surface but also inside the insulating substrate.
【００２８】上記の第１および第２の製造方法におい
て、用いられる熱硬化性樹脂を含有する絶縁シートは、
熱硬化性有機樹脂、または熱硬化性有機樹脂とフィラー
などの組成物を混練機や３本ロールなどの手段によって
十分に混合し、これを圧延法、押し出し法、射出法、ド
クターブレード法などによってシート状に成形する。そ
して、所望により熱処理して熱硬化性樹脂を半硬化させ
る。半硬化には、樹脂が完全硬化するに十分な温度より
もやや低い温度に加熱する。In the first and second manufacturing methods, the insulating sheet containing the thermosetting resin used is
A thermosetting organic resin or a composition of a thermosetting organic resin and a filler is sufficiently mixed by means of a kneader or a three-roll mill, and the mixture is subjected to a rolling method, an extrusion method, an injection method, a doctor blade method, or the like. Form into a sheet. Then, the thermosetting resin is semi-cured by heat treatment if desired. For semi-curing, the resin is heated to a temperature slightly lower than a temperature sufficient to completely cure the resin.
【００２９】そして、この状態の絶縁層に対するスルー
ホール（ビアホール）および空隙部の形成は、ドリル、
パンチング、サンドブラスト、あるいは炭酸ガスレー
ザ、ＹＡＧレーザ、及びエキシマレーザ等の照射による
加工など公知の方法が採用される。The formation of through holes (via holes) and voids in the insulating layer in this state is performed by drilling,
A known method such as punching, sandblasting, or processing by irradiation with a carbon dioxide gas laser, a YAG laser, an excimer laser, or the like is employed.
【００３０】なお、絶縁シートを形成する熱硬化性樹脂
としては、絶縁材料としての電気的特性、耐熱性、およ
び機械的強度を有する熱硬化性樹脂であれば特に限定さ
れるものでなく、例えば、アラミド樹脂、フェノール樹
脂、エポキシ樹脂、イミド樹脂、フッ素樹脂、フェニレ
ンエーテル樹脂、ビスマイレイドトリアジン樹脂、ユリ
ア樹脂、メラミン樹脂、シリコーン樹脂、ウレタン樹
脂、不飽和ポリエステル樹脂、アリル樹脂等が、単独ま
たは組み合わせて使用できる。The thermosetting resin forming the insulating sheet is not particularly limited as long as the thermosetting resin has electrical characteristics, heat resistance, and mechanical strength as an insulating material. , Aramid resin, phenolic resin, epoxy resin, imide resin, fluororesin, phenylene ether resin, bismailide triazine resin, urea resin, melamine resin, silicone resin, urethane resin, unsaturated polyester resin, allyl resin, etc., alone or Can be used in combination.
【００３１】また、上記の絶縁シート１中には、絶縁基
板あるいは配線基板全体の強度を高めるために、有機樹
脂に対してフィラーを複合化させることもできる。有機
樹脂と複合化されるフィラーとしては、ＳｉＯ2 、Ａｌ
2 Ｏ3 、ＺｒＯ2 、ＴｉＯ2、ＡｌＮ、ＳｉＣ、ＢａＴ
ｉＯ3 、ＳｒＴｉＯ3 、ゼオライト、ＣａＴｉＯ3 、ほ
う酸アルミニウム等の無機質フィラーが好適に用いられ
る。また、ガラスやアラミド樹脂からなる不織布、織布
などに上記樹脂を含浸させて用いてもよい。なお、有機
樹脂とフィラーとは、体積比率で１５：８５〜５０：５
０の比率で複合化されるのが適当である。In the insulating sheet 1, a filler can be compounded with an organic resin in order to increase the strength of the entire insulating substrate or wiring substrate. SiO 2 , Al
2 O 3 , ZrO 2 , TiO 2 , AlN, SiC, BaT
Inorganic fillers such as iO 3 , SrTiO 3 , zeolite, CaTiO 3 and aluminum borate are preferably used. Further, a nonwoven fabric or a woven fabric made of glass or aramid resin may be used by impregnating the above resin. The organic resin and the filler are in a volume ratio of 15:85 to 50: 5.
Suitably, the compound is formed in a ratio of 0.
【００３２】これらの電気素子を収納するための空隙部
を形成する絶縁シートは、上記の種々の材質の中でも空
隙部をパンチング又はレーザーで容易に加工できる点か
ら、エポキシ樹脂、イミド樹脂、フェニレンエーテル樹
脂と、シリカまたはアラミド不織布との混合物であるこ
とが最も望ましい。The insulating sheet forming the gap for accommodating these electric elements is made of an epoxy resin, an imide resin, a phenylene ether, since the gap can be easily processed by punching or laser among the various materials described above. Most preferably, it is a mixture of a resin and a silica or aramid nonwoven fabric.
【００３３】一方、ビアホール導体２に充填される金属
ペーストは、銅粉末、銀粉末、銀被覆銅粉末、銅銀合金
などの、平均粒径が０．５〜５０μｍの金属粉末を含
む。金属粉末の平均粒径が０．５μｍよりも小さいと、
金属粉末同士の接触抵抗が増加してスルーホール導体の
抵抗が高くなる傾向にあり、５０μｍを越えるとスルー
ホール導体の低抵抗化が難しくなる傾向にある。On the other hand, the metal paste filled in the via-hole conductor 2 includes metal powder having an average particle size of 0.5 to 50 μm, such as copper powder, silver powder, silver-coated copper powder, and copper-silver alloy. When the average particle size of the metal powder is smaller than 0.5 μm,
The contact resistance between the metal powders tends to increase and the resistance of the through-hole conductor tends to increase. If it exceeds 50 μm, it tends to be difficult to reduce the resistance of the through-hole conductor.
【００３４】また、導体ペーストは、前述したような金
属粉末に対して、前述したような結合用有機樹脂や溶剤
を添加混合して調製される。ペースト中に添加される溶
剤としては、用いる結合用有機樹脂が溶解可能な溶剤で
あればよく、例えば、イソプロピルアルコール、テルピ
ネオール、２−オクタノール、ブチルカルビトールアセ
テート等が用いられる。The conductive paste is prepared by adding and mixing the above-mentioned organic resin for binding and the solvent to the above-mentioned metal powder. The solvent to be added to the paste may be any solvent that can dissolve the binding organic resin to be used. For example, isopropyl alcohol, terpineol, 2-octanol, butyl carbitol acetate and the like are used.
【００３５】上記の導体ペースト中の結合用有機樹脂と
しては、前述した種々の絶縁シートを構成する有機樹脂
の他、セルロースなども使用される。この有機樹脂は、
前記金属粉末同士を互いに接触させた状態で結合すると
ともに、金属粉末を絶縁シートに接着させる作用をなし
ている。この有機樹脂は、金属ペースト中において、
０．１乃至４０体積％、特に０．３乃至３０体積％の割
合で含有されることが望ましい。これは、樹脂量が０．
１体積％よりも少ないと、金属粉末同士を強固に結合す
ることが難しく、低抵抗金属を絶縁層に強固に接着させ
ることが困難となり、逆に４０体積％を越えると、金属
粉末間に樹脂が介在することになり粉末同士を十分に接
触させることが難しくなり、スルーホール導体の抵抗が
大きくなるためである。As the organic resin for bonding in the above-mentioned conductor paste, cellulose and the like are used in addition to the above-mentioned organic resins constituting the various insulating sheets. This organic resin is
The metal powders are bonded in a state where they are in contact with each other, and the metal powders are bonded to the insulating sheet. This organic resin, in the metal paste,
It is desirable that the content is 0.1 to 40% by volume, particularly 0.3 to 30% by volume. This means that the amount of resin is 0.1.
If the amount is less than 1% by volume, it is difficult to firmly bond the metal powders to each other, and it is difficult to firmly bond the low-resistance metal to the insulating layer. This makes it difficult to bring the powders into sufficient contact with each other and increases the resistance of the through-hole conductor.
【００３６】配線回路層としては、銅、アルミニウム、
金、銀の群から選ばれる少なくとも１種、または２種以
上の合金からなることが望ましく、特に、銅、または銅
を含む合金が最も望ましい。また、場合によっては、導
体組成物として回路の抵抗調整のためにＮｉ−Ｃｒ合金
などの高抵抗の金属を混合、または合金化してもよい。
さらには、配線層の低抵抗化のために、前記低抵抗金属
よりも低融点の金属、例えば、半田、錫などの低融点金
属を導体組成物中の金属成分中に２〜２０重量％の割合
で含んでもよい。As the wiring circuit layer, copper, aluminum,
It is desirable to be made of at least one or two or more alloys selected from the group consisting of gold and silver, and particularly desirable is copper or an alloy containing copper. In some cases, a high-resistance metal such as a Ni—Cr alloy may be mixed or alloyed as the conductor composition for adjusting the resistance of the circuit.
Further, in order to lower the resistance of the wiring layer, a metal having a lower melting point than the low-resistance metal, for example, a low-melting metal such as solder or tin is used in an amount of 2 to 20% by weight in the metal component in the conductor composition. It may be included in proportion.
【００３７】配線回路層４と絶縁シート１との密着強度
を高める上では、絶縁シート１の配線回路層４の形成箇
所および／または転写フィルム表面の配線回路層４表面
の表面を０．１μｍ以上、特に０．３μｍ〜３μｍ、最
適には０．３〜１．５μｍに粗面加工することが望まし
い。また、ビアホール導体の両端を金属箔からなる配線
回路層によって封止する上では、配線回路層４の厚み
は、５〜４０μｍが適当である。In order to increase the adhesion strength between the wiring circuit layer 4 and the insulating sheet 1, the area of the insulating sheet 1 where the wiring circuit layer 4 is formed and / or the surface of the wiring circuit layer 4 on the surface of the transfer film is 0.1 μm or more. In particular, it is desirable to roughen the surface to 0.3 μm to 3 μm, optimally to 0.3 to 1.5 μm. In order to seal both ends of the via-hole conductor with a wiring circuit layer made of a metal foil, the thickness of the wiring circuit layer 4 is appropriately 5 to 40 μm.
【００３８】このようにして、本発明によれば、従来の
積層方法を用いて、複数の絶縁層が積層されてなる絶縁
基板内部に電気素子を実装収納することができ、これに
より多層配線基板の電気素子を高密度に実装することが
でき、多層配線基板の小型化を図ることができる。As described above, according to the present invention, an electric element can be mounted and housed inside an insulating substrate having a plurality of insulating layers laminated by using a conventional laminating method. Can be mounted at high density, and the size of the multilayer wiring board can be reduced.
【００３９】[0039]
実施例１ （１） アラミド樹脂の不織布に対してイミド樹脂を５
０体積％の割合で含浸した厚さ１００μｍのプリプレグ
に、炭酸ガスレーザーで直径０．１ｍｍのビアホールを
形成し、そのホール内に銀をメッキした銅粉末を含む銅
ペーストを充填してビアホール導体を形成した。また、
このプリプレグにレーザーを用いて半導体素子や電子部
品を設置するための１２ｍｍ×１２ｍｍの大きさの空隙
部を形成した。Example 1 (1) An imide resin was added to an aramid resin nonwoven fabric in an amount of 5%.
A via hole having a diameter of 0.1 mm is formed in a prepreg having a thickness of 100 μm impregnated at a ratio of 0% by volume with a carbon dioxide gas laser, and the hole is filled with a copper paste containing copper powder plated with silver to form a via hole conductor. Formed. Also,
A void having a size of 12 mm × 12 mm for mounting a semiconductor element or an electronic component was formed in the prepreg using a laser.
【００４０】（２） 一方、イミド樹脂５０体積％、シ
リカ粉末５０体積％の割合となるように、ワニス状態の
樹脂と粉末を混合しドクターブレード法により、厚さ７
５ｍｍの絶縁シートを作製し、その絶縁シートにパンチ
ングで直径０．１ｍｍのビアホールを形成し、そのホー
ル内に銀をメッキした銅粉末を含む銅ペーストを充填し
てビアホール導体を形成した。(2) On the other hand, a resin and powder in a varnish state were mixed so as to have a ratio of 50% by volume of the imide resin and 50% by volume of the silica powder, and the thickness was adjusted to 7% by a doctor blade method.
A 5 mm insulating sheet was prepared, a via hole having a diameter of 0.1 mm was formed in the insulating sheet by punching, and the hole was filled with a copper paste containing copper powder plated with silver to form a via hole conductor.
【００４１】（３） また、一方、ポリエチレンテレフ
タレート（ＰＥＴ）樹脂からなる転写シートの表面に接
着剤を塗布し、厚さ１２μｍ、表面粗さ０．８μｍの銅
箔を一面に接着した。そして、フォトレジスト（ドライ
フィルム）を塗布し露光現像を行った後、これを塩化第
二鉄溶液中に浸漬して非パターン部をエッチング除去し
て配線回路層を形成した。なお、作製した配線回路層
は、線幅が２０μｍ、配線と配線との間隔が２０μｍの
微細なパターンである。その後、この配線回路層にＩＣ
素子をフリップチップ接続し、ポリイミド樹脂で封止し
た。(3) On the other hand, an adhesive was applied to the surface of a transfer sheet made of polyethylene terephthalate (PET) resin, and a copper foil having a thickness of 12 μm and a surface roughness of 0.8 μm was adhered to one surface. Then, after applying a photoresist (dry film) and performing exposure and development, it was immersed in a ferric chloride solution to remove non-pattern portions by etching to form a wiring circuit layer. Note that the manufactured wiring circuit layer is a fine pattern having a line width of 20 μm and an interval between wirings of 20 μm. After that, the IC
The device was flip-chip connected and sealed with a polyimide resin.
【００４２】（４）そして、（１）で作製したプリプレ
グに対して、（２）で電気素子を実装した転写シート
を、プリプレグの空隙部に電気素子が収納されるように
位置決めして５０ｋｇ／ｃｍ2 の圧力を加えて圧着した
後、転写フィルムを剥離して、配線回路層とＩＣ素子を
プリプレグに転写した。(4) Then, with respect to the prepreg prepared in (1), the transfer sheet on which the electric element is mounted in (2) is positioned so that the electric element is housed in the gap of the prepreg, and the transfer sheet is 50 kg / After applying a pressure of 2 cm 2 and pressure bonding, the transfer film was peeled off, and the wiring circuit layer and the IC element were transferred to a prepreg.
【００４３】（５）（２）で作製した絶縁シートの表面
に、（３）と同様にして金属箔からなる配線回路層を形
成したＰＥＴ樹脂フィルムから、配線回路層を転写させ
た。(5) The wiring circuit layer was transferred from the PET resin film on which the wiring circuit layer made of metal foil was formed on the surface of the insulating sheet prepared in (2) in the same manner as in (3).
【００４４】（６）空隙部にＩＣ素子が収納されたプリ
プレグを中心に、その上下面に（５）のようにして配線
回路層が転写された絶縁シートを上下各２層づつ積層し
５０ｋｇ／ｃｍ2 の圧力で圧着し、２００℃で１時間加
熱して完全硬化させて多層配線基板を作製した。(6) With the prepreg containing the IC element in the gap as the center, two upper and lower insulating sheets on which the wiring circuit layer has been transferred as shown in (5) are laminated on the upper and lower surfaces, and 50 kg / Crimping was performed under a pressure of 2 cm 2 , and heating was performed at 200 ° C. for 1 hour to completely cure, thereby producing a multilayer wiring board.
【００４５】得られた多層配線基板に対して、断面にお
ける配線回路層やビアホール導体の形成付近を観察した
結果、ＩＣ素子と配線回路層、ビアホール導体と配線回
路層とは良好な接続状態であり、各配線間の導通テスト
を行った結果、配線の断線も認められなかった。また、
ＩＣ素子の動作においても何ら問題はなかった。得られ
た多層配線基板を湿度８５％、温度８５℃の高温多湿雰
囲気に１００時間放置したが、目視で判別できる程度の
変化は生じていなかった。As a result of observing the vicinity of the formation of the wiring circuit layer and the via-hole conductor in the cross section of the obtained multilayer wiring board, the IC element and the wiring circuit layer and the via-hole conductor and the wiring circuit layer were in a good connection state. As a result of conducting a continuity test between the wirings, no disconnection of the wiring was observed. Also,
There was no problem in the operation of the IC element. The obtained multilayer wiring board was left in a high-temperature and high-humidity atmosphere at a humidity of 85% and a temperature of 85 ° C. for 100 hours, but no change that could be visually discriminated occurred.
【００４６】実施例２ （１）アラミド不織布にエポキシ樹脂を含浸させた厚さ
６０μｍの半硬化状態の絶縁シートＡに、炭酸ガスレー
ザーで直径０．１ｍｍのビアホールを形成し、そのホー
ル内に銀をメッキした銅粉末を含む銅ペーストを充填し
てビアホール導体を形成した。そして、転写フイルムの
表面に銅箔を接着した後、フォトレジスト（ドライフィ
ルム）を塗布し露光現像を行った後、これを塩化第二鉄
溶液中に浸漬して非パターン部をエッチング除去して配
線回路層を形成し、この配線回路層を絶縁シートＡに位
置合わせして積層し、１００ｋｇ／ｃｍ2 の圧力で圧着
してフィルムを剥がし、配線回路層を転写させた。Example 2 (1) A via hole having a diameter of 0.1 mm was formed with a carbon dioxide laser on a semi-cured insulating sheet A having a thickness of 60 μm in which an aramid nonwoven fabric was impregnated with an epoxy resin, and silver was formed in the hole. Was filled with a copper paste containing copper powder to form a via-hole conductor. Then, after adhering a copper foil to the surface of the transfer film, applying a photoresist (dry film) and performing exposure and development, this is immersed in a ferric chloride solution to remove non-pattern portions by etching. A wiring circuit layer was formed, this wiring circuit layer was positioned and laminated on the insulating sheet A, and the film was peeled off by pressing under a pressure of 100 kg / cm 2 to transfer the wiring circuit layer.
【００４７】（２） 次に、この配線回路層の表面にセ
ラミックコンデンサ素子を半田を用いて実装した。(2) Next, a ceramic capacitor element was mounted on the surface of the wiring circuit layer using solder.
【００４８】（３） その後、コンデンサ素子を実装し
た絶縁シートＡの表面に、（１）と同様にしてビアホー
ル導体および配線回路層を形成するとともに、前記セラ
ミックコンデンサ素子を収納するための空隙部をレーザ
ー加工によって形成した絶縁シートＢを３０ｋｇ／ｃｍ
2 の圧力で積層圧着した。(3) Thereafter, on the surface of the insulating sheet A on which the capacitor element is mounted, the via hole conductor and the wiring circuit layer are formed in the same manner as in (1), and a gap for accommodating the ceramic capacitor element is formed. 30 kg / cm of insulating sheet B formed by laser processing
The laminate was pressure-bonded at a pressure of 2 .
【００４９】（４）さらに、その絶縁シートＢの表面
に、（１）と同様にしてビアホール導体および配線回路
層を形成した絶縁シートＣを３０ｋｇ／ｃｍ2 の圧力で
積層圧着した。(4) Further, on the surface of the insulating sheet B, an insulating sheet C having a via-hole conductor and a wiring circuit layer formed thereon was laminated and pressed at a pressure of 30 kg / cm 2 in the same manner as in (1).
【００５０】（５）そして、絶縁シートＡ、Ｂ、Ｃの積
層物を３５ｋｇ／ｃｍ2 の圧力を印加しながら１９５℃
に加熱して完全硬化させて多層配線基板を作製した。(5) Then, the laminate of the insulating sheets A, B and C was heated at 195 ° C. while applying a pressure of 35 kg / cm 2.
To complete curing to produce a multilayer wiring board.
【００５１】得られた基板に対して、得られた多層配線
基板に対して、断面における配線回路層やビアホール導
体の形成付近を観察した結果、コンデンサ素子と配線回
路層、ビアホール導体と配線回路層とは良好な接続状態
であり、各配線間の導通テストを行った結果、配線の断
線も認められなかった。また、コンデンサ素子において
も何ら問題なく、所定の容量を得ることができた。得ら
れた多層配線基板を湿度８５％、温度８５℃の高温多湿
雰囲気に１００時間放置したが、目視で判別できる程度
の変化は生じていなかった。As a result of observing the vicinity of the formation of the wiring circuit layer and the via hole conductor in the cross section of the obtained substrate and the obtained multilayer wiring board, the capacitor element and the wiring circuit layer, and the via hole conductor and the wiring circuit layer were observed. Indicates a good connection state, and as a result of conducting a continuity test between the wirings, no disconnection of the wiring was observed. Also, a predetermined capacitance could be obtained without any problem in the capacitor element. The obtained multilayer wiring board was left in a high-temperature and high-humidity atmosphere at a humidity of 85% and a temperature of 85 ° C. for 100 hours, but no change that could be visually discriminated occurred.
【００５２】[0052]
【発明の効果】以上詳述したとおり、本発明によれば、
電気素子を絶縁基板の内部に形成した空隙部に実装収納
することにより、転写フィルム上の銅箔から形成した配
線回路層に対して半導体素子や各種電子部品等の電気素
子を実装した後、空隙部を形成した絶縁層の表面に転写
して、電気素子を空隙部に収納することにより、電気素
子を絶縁基板内に内蔵させることができ、これにより多
層配線基板に積層一体化することにより高密度、高精
細、且つ多機能の配線基板を容易に形成できる。As described in detail above, according to the present invention,
By mounting and housing the electric element in the gap formed inside the insulating substrate, the electric element such as a semiconductor element or various electronic components is mounted on the wiring circuit layer formed from the copper foil on the transfer film, and then the gap is formed. The electric element can be embedded in the insulating substrate by transferring the electric element to the surface of the insulating layer in which the portion has been formed, and housing the electric element in the gap portion. A high-density, high-definition, multifunctional wiring board can be easily formed.
【図１】本発明の素子内蔵多層配線基板の製造方法の一
実施例を説明するための工程図である。FIG. 1 is a process chart for explaining one embodiment of a method of manufacturing a multilayer wiring board with a built-in element according to the present invention.
【図２】本発明の素子内蔵多層配線基板の製造方法の他
の実施例を説明するための工程図である。FIG. 2 is a process chart for explaining another embodiment of the method for manufacturing a multi-layer wiring board with a built-in element according to the present invention.
【図３】本発明の素子内蔵多層配線基板において、電気
素子を内蔵した空隙部を複数形成した多層配線基板を説
明するための概略断面図である。FIG. 3 is a schematic cross-sectional view for explaining a multilayer wiring board in which a plurality of voids containing electric elements are formed in the multilayer wiring board with a built-in element of the present invention.
１，７，８，２０，２５，２８ 絶縁シート ２，１１，１２，２１，２７，３０ ビアホール導体 ３，２４，３５，３６，３７ 空隙部 ４，９，１０，２２，２６，２９ 配線回路層 ５，２３，３３，３４，３７、３８ 電気素子 ６ 転写フィルム １３，３１，３２ 絶縁基板 1,7,8,20,25,28 Insulating sheet 2,11,12,21,27,30 Via hole conductor 3,24,35,36,37 Void 4,9,10,22,26,29 Wiring circuit Layers 5, 23, 33, 34, 37, 38 Electrical elements 6 Transfer film 13, 31, 32 Insulating substrate
Claims (6)
層を積層してなる絶縁基板と、該絶縁基板の表面および
内部に形成された配線回路層と、前記配線回路層間を電
気的に接続するためのビアホール導体を具備する多層配
線基板において、前記絶縁基板内部に、空隙部を形成す
るとともに、該空隙部内に電気素子を実装収納してなる
ことを特徴とする素子内蔵多層配線基板。An electrical connection is made between an insulating substrate formed by laminating a plurality of insulating layers containing at least a thermosetting resin, a wiring circuit layer formed on the surface and inside of the insulating substrate, and the wiring circuit layer. A multilayer wiring board provided with a via-hole conductor for forming an electric element, wherein a void is formed inside the insulating substrate, and an electric element is mounted and housed in the void.
からなる配線回路層に半田実装してなることを特徴とす
る請求項１記載の素子内蔵多層配線基板。2. The multi-layer wiring board with a built-in element according to claim 1, wherein the electric element is solder-mounted in a wiring circuit layer made of metal foil in the gap.
品であることを特徴とする請求項１記載の素子内蔵多層
配線基板。3. The multilayer wiring board with a built-in element according to claim 1, wherein said electric element is a semiconductor element or an electronic component.
って形成したことを特徴とする請求項１記載の素子内蔵
多層配線基板。4. The multilayer wiring board with a built-in element according to claim 1, wherein said via hole conductor is formed by filling a metal powder.
設けたことを特徴とする素子内蔵多層配線基板。5. A multi-layer wiring board with a built-in element, wherein a plurality of the voids are provided in a laminating direction of the wiring board.
に電気素子を実装する実装工程と、少なくとも熱硬化性
樹脂からなる第１の絶縁層にキャビティを形成するキャ
ビティ形成工程と、前記第１の絶縁層の前記キャビティ
内に前記電気素子が収納されるように、前記転写シート
から前記配線回路層と前記電気素子を前記第１の絶縁層
に転写する転写工程と、転写工程後の前記第１の絶縁層
の上下面に、少なくとも熱硬化性樹脂を含み、少なくと
も配線回路層が形成された第２および第３の絶縁層を積
層圧着する積層工程、とを具備することを特徴とする素
子内蔵多層配線基板の製造方法。6. A mounting step of mounting an electric element on a wiring circuit layer formed on a surface of a transfer sheet; a cavity forming step of forming a cavity in at least a first insulating layer made of a thermosetting resin; Transferring the wiring circuit layer and the electric element from the transfer sheet to the first insulating layer so that the electric element is housed in the cavity of the first insulating layer; and A laminating step of laminating and pressing at least the second and third insulating layers including at least a thermosetting resin on at least the upper and lower surfaces of the first insulating layer and having at least the wiring circuit layer formed thereon. A method for manufacturing a multilayer wiring board with a built-in element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9201653A JP3051700B2 (en) | 1997-07-28 | 1997-07-28 | Method of manufacturing multilayer wiring board with built-in element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9201653A JP3051700B2 (en) | 1997-07-28 | 1997-07-28 | Method of manufacturing multilayer wiring board with built-in element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1145955A true JPH1145955A (en) | 1999-02-16 |
| JP3051700B2 JP3051700B2 (en) | 2000-06-12 |
Family
ID=16444669
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9201653A Expired - Fee Related JP3051700B2 (en) | 1997-07-28 | 1997-07-28 | Method of manufacturing multilayer wiring board with built-in element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3051700B2 (en) |
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