JP2002076637A - Chip component built-in substrate and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] A component configuration in which a mounting area is small and a component built-in layer thickness can be reduced when a chip component is embedded in a substrate, and a connection with a wiring pattern while forming a fine wiring pattern on a circuit board. The present invention provides a manufacturing method for accurately mounting and incorporating chip passive components such as LCRs while forming a chip. An electrode is formed on at least one of upper and lower surfaces, and one or more chip components are built in. A thickness t of the chip passive element 204 is smaller than a length L and a width W, and the chip component is At least one of the surfaces corresponding to the upper and lower surfaces in the thickness direction has an external connection electrode 205, and the external connection electrode 205 and the wiring pattern 203 formed on the electrically insulating multilayer wiring board 201 are electrically connected. I have.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board incorporating a passive component comprising a chip component having a component wiring pattern formed thereon by using a component wiring pattern forming material for transfer, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, with the demand for higher performance, smaller size, and higher frequency of electronic equipment, higher density and higher function of semiconductors have been demanded. For this reason, in addition to the semiconductor, passive components themselves such as a capacitor (C), an inductor (L), and a resistor (R) are also miniaturized, and a circuit board for mounting a chip passive component whose characteristics are guaranteed. However, there is a need for smaller and higher-density devices.

In response to these requirements, for example, an inner via hole (IVH), which is an electrical connection method between substrate layers, which enables electrical wiring between LSIs and mounted components to be connected in the shortest distance.
Since the connection method enables the highest-density wiring of the circuit, development is being promoted in various fields. In general, examples of the wiring board having such an IVH structure include a multilayer ceramic wiring board, a multilayer printed wiring board by a build-up method, and a multilayer composite wiring board made of a mixture of a resin and an inorganic filler.

The multilayer ceramic wiring board is, for example,
It can be manufactured as shown below. First, a plurality of green sheets made of ceramic powder such as alumina, an organic binder, and a plasticizer are prepared. Via holes are provided in each of the green sheets, and the via holes are filled with a conductive paste. And stack the green sheets. Then, the multilayer ceramic wiring board can be manufactured by removing the binder and firing the laminate. Since such a multilayer ceramic wiring board has an IVH structure, an extremely high-density wiring pattern can be formed, and is most suitable for miniaturization of electronic devices and the like.

[0005] Further, printed wiring boards which simulate the structure of the multilayer ceramic wiring board by the build-up method have been developed in various fields. For example, Japanese Patent Application Laid-Open No. Hei 9-116
No. 267, Japanese Unexamined Patent Publication No. Hei 9-51168, and the like disclose, as a general build-up method, a method in which a conventionally used glass-epoxy substrate is used as a core, and a photosensitive insulating layer is formed on the surface of the substrate. A method is disclosed in which a via hole is provided by photolithography, copper plating is further performed on the entire surface, and the copper plating is chemically etched to form a wiring pattern.

Japanese Patent Application Laid-Open No. 9-326562 discloses a method for filling a via hole processed by the photolithography method with a conductive paste in the same manner as the build-up method. Japanese Patent Laid-Open Publication No. Hei 10-51139 discloses that a conductive circuit is formed on one surface of an insulative hard base material and an adhesive layer is formed on the other surface, a through-hole is formed in the conductive circuit, and a conductive paste is filled. After that, a multi-layering method is disclosed in which a plurality of base materials are overlapped and laminated.

Further, Japanese Patent No. 26001128 and Patent No. 2
No. 603053 and Japanese Patent No. 2587596 disclose that aramid-epoxy prepreg is provided with a through-hole by laser processing, filled with a conductive paste, laminated with a copper foil and patterned, and using this substrate as a core to form a conductive layer. This is a method of further sandwiching between prepregs filled with paste to form a multilayer.

As described above, for example, if the resin-based printed wiring board is connected by IVH, the electrical connection between only the necessary layers is possible as in the case of the multilayer ceramic wiring board. Since there is no through hole in the top layer,
Excellent mountability.

However, as described above, even in a multilayer wiring board having a high-density wiring, the proportion of electronic components mounted on the surface of the wiring board, such as capacitors and resistors, is still high. This is a major issue. As a solution to such a problem, a proposal has been disclosed for embedding electronic components in a wiring board to achieve high-density mounting.

For example, Japanese Patent Laid-Open Publication No. Sho 54-38561 in which leadless components are embedded in through holes provided in a printed circuit board, and Japanese Patent Publication No. Sho 60-1985 in which passive elements such as ceramic capacitors are embedded in through holes provided in an insulating substrate. Japanese Patent Application Laid-Open No. 41480/1991, Japanese Patent Application Laid-Open No. 4-79992 and Japanese Patent Application Laid-Open No. 5-218615, in which a bypass capacitor of a semiconductor element is buried in a hole of a printed wiring board, are disclosed.

Japanese Patent Laid-Open Publication No. Hei 8-222656, in which a conductive material and a dielectric material are filled in via holes provided in a ceramic wiring substrate and fired simultaneously, a through-hole provided in an organic insulating substrate has an electronic component forming material. Embedded therein, and then solidified to form a capacitor or a resistor.
No. 51 is disclosed.

The above-mentioned conventional techniques can be roughly classified into two types. That is, one of them is to bury a completed leadless component such as a chip resistor or a chip capacitor in a through-hole provided in the wiring board, and then to electrically connect the electrode of the leadless component to the wiring pattern on the wiring board. The connection is made by paint or soldering.
On the other hand, in the case of an organic wiring board, an electronic component forming material such as a capacitor is embedded in a through hole provided in the wiring board, and solidified to obtain a desired capacitor. To form an electrode to form an electronic component built-in wiring board, and, in the case of an inorganic wiring board, after filling a dielectric paste or a conductive paste into a via hole provided in a ceramic green sheet,
By firing at a high temperature, a wiring board incorporating a desired capacitor is formed.

However, it is difficult to obtain a large capacity by firing or solidifying a capacitor using these through holes. On the other hand, when burying and mounting a chip capacitor or the like having a large capacity in advance by using a through hole, a layer thickness of 0.6 mm always accompanies even when the current smallest size 0603 chip is used. It is difficult to realize a thin multilayer substrate.

[0014] Further, when viewed as a single chip component, a chip component having electrodes formed on its side surface, such as 1005 and 0603, is typical in the market. -220262 (US Patent 6,038,1
No. 33) has already been proposed, but a structure in which the structure and the shape are taken into consideration in consideration of characteristics and shapes for a built-in structure and a form in which the structure is built in a substrate have not yet been proposed. Furthermore, when viewed as a single chip component, elements having electrodes on the upper and lower surfaces include a single-layer chip capacitor and a thin-film multilayer capacitor, all of which are only supposed to be surface-mounted, and a wire is connected between the electrodes. Connecting with a bond or connecting with a ribbon lead is generally used. Therefore, there has not yet been proposed an effective manufacturing method for incorporating these chip components into a substrate and for accurately connecting the chip components to a wiring pattern when incorporated.

On the other hand, a high-density resin-based printed wiring board having an IVH structure generally has low thermal conductivity, and as the mounting density of components increases, it is particularly important to radiate heat generated from the components. It becomes difficult to mount or incorporate active components such as semiconductor elements.

In the year 2000, the clock frequency of the CPU became about 1 GHz, and as the function became more sophisticated, the power consumption of the CPU became 100 to 15 per chip.
It is estimated to reach 0W. Therefore, high thermal conductivity is being demanded of a substrate in which components are built.

From this viewpoint, when viewed from the viewpoint of the substrate, the multilayer composite wiring substrate is provided for the purpose of complementing the fact that the ceramic wiring substrate is relatively expensive and the resin-based printed wiring substrate has a problem in thermal conductivity. JP-A-9-2705
No. 84, JP-A-8-125291, JP-A-8-125291
Japanese Patent Application Laid-Open No. 288596/1998, Japanese Patent Application Laid-Open No. 10-173097 and the like. This multilayer composite wiring board is a board obtained by mixing a thermosetting resin such as an epoxy resin and an inorganic filler having excellent thermal conductivity (for example, ceramic powder) to form a composite. , The thermal conductivity of the substrate can be improved. Further, by selecting the type of the inorganic filler, for example, it is possible to arbitrarily control the dielectric constant, the coefficient of thermal expansion, and the like.

On the other hand, in order to promote the high-density mounting of the substrate, formation of a fine wiring pattern and formation and mounting of an LCR connected to the wiring pattern are important. In the multilayer ceramic wiring board, formation of the wiring pattern includes:
For example, a method of screen-printing a thick-film conductive paste on a ceramic substrate and baking it by baking is generally used. However, in this screen printing method, 10
It is said that it is difficult to mass-produce a wiring pattern having a line width of 0 μm or less. In addition, passive components such as LCR are limited to surface mounting, and it is difficult to incorporate them in a substrate. Further, since a firing process is involved in a ceramic substrate, it has been impossible to incorporate inexpensively available chip components whose characteristics are guaranteed. In this sense, there is a limit to high-density mounting.

In a normal printed wiring board, for example, a method of forming a wiring pattern by a subtractive method is general. In this subtractive method, a wiring pattern is formed on a substrate by chemically etching a copper foil having a thickness of about 18 to 35 μm.
It is said that even with this method, it is difficult to mass-produce a wiring pattern having a line width of 75 μm or less, and it is necessary to make the copper foil thinner in order to further miniaturize the wiring pattern.

According to the subtractive method,
Since the wiring pattern has a structure protruding from the substrate surface, it is difficult to place solder or conductive adhesive for electrical connection on the bump formed on the semiconductor, and the bump moves between the wiring patterns, There is a risk of short circuit. Also,
Due to the protruding wiring pattern, for example, there is a possibility that it may become an obstacle when sealing with a sealing resin in a later step.

Further, in the printed wiring board by the build-up method, in addition to the subtractive method,
For example, the additive method tends to be adopted. The additive method is, for example, a method of selectively plating a wiring pattern on a substrate surface on which a resist is formed,
A wiring pattern having a line width of about 30 μm can be formed. However, this method has a problem that the adhesion strength of the wiring pattern to the substrate is weaker than the subtractive method.

Therefore, a method has been devised in which a fine wiring pattern is formed in advance, a pattern inspection is performed, and then only a good wiring pattern is transferred to a desired substrate. For example, U.S. Pat. No. 5,407,511 discloses a method in which a fine pattern is previously formed on a surface of a carbon plate by printing and baking, and this is transferred to a ceramic substrate.

Japanese Patent Application Laid-Open Nos. 10-84186 and 10-41611 disclose a method of transferring a wiring pattern made of a copper foil formed on a release support plate to a prepreg. And JP-A-11-261219.
Japanese Patent Application Laid-Open No. 8-330709 discloses a method of transferring a wiring pattern made of copper foil onto a release support plate made of copper foil via a nickel-phosphorus alloy release layer. A method of transferring a copper foil to a substrate by utilizing the fact that the degree of adhesion between a roughened surface and a glossy surface of a copper foil is different is disclosed.

The wiring pattern transferred by such a transfer method is embedded in the surface of the substrate, and the surface of the obtained wiring substrate has a flat structure. Therefore, the problem caused by the protrusion of the wiring pattern as described above is avoided. . Further, Japanese Patent Application Laid-Open
JP-A-190191 also discloses an effect of compressing the conductive via paste filled in the through hole by the thickness of the wiring pattern when the wiring pattern is embedded in the substrate surface.

[0025]

However, in these methods, the pattern formed on the transfer material is only a wiring portion such as a copper foil. For higher density mounting, it is also possible to propose that LCRs and the like be mounted on the transfer forming material in the form of a chip. However, with current chips, electrodes are formed on the side surfaces. Therefore, a considerably large mounting connection area is required as compared with the component area. In order to prevent this, the chip is mounted in a state where the electrode is vertical on the transfer material and transferred to the board and embedded in the board. There are various problems such as securing a large layer thickness, and the number of limitations is increased in designing a multilayer substrate.
In the case where a transfer bonding material is mounted on the transfer forming material and embedded in the transfer, the area is preliminarily sealed with a resin, protected, and then embedded. However, it has been reported that when connected by wire bonding, the wiring between components becomes longer, so that characteristics are degraded in high frequency applications.

Therefore, the present invention provides a component structure in which a mounting area is small and a component built-in layer thickness can be reduced when a chip component is built into a substrate, and a connection with a wiring pattern while forming a fine wiring pattern on a circuit board. While forming L
An object of the present invention is to provide a manufacturing method for accurately mounting and incorporating a chip passive component such as a CR.

[0027]

Means for Solving the Problems In order to achieve the above object, the present inventors have proposed a chip passive element in which electrodes are formed on one of upper and lower surfaces having a small thickness, and use them by using a transfer forming material. In this way, a wiring board with a built-in thin chip component and a shortest wiring suitable for high-frequency applications can be provided because it can be accurately mounted and embedded.

That is, in the wiring board with a built-in chip component of the present invention, electrodes are formed on at least one of the upper and lower surfaces, and
An electrically insulating wiring board containing at least one chip component, wherein the thickness t of the chip passive element is equal to or less than a length L and a width W, and the chip component corresponds to upper and lower surfaces in the thickness direction. At least one of the surfaces has an external connection electrode, and the external connection electrode is electrically connected to a wiring pattern formed on the electrically insulating multilayer wiring board.

Next, in a first method of the present invention, a metal layer is directly adhered to a carrier layer via a release layer, processed into a wiring pattern shape, a transfer wiring pattern is formed, and the transfer wiring pattern is formed. Using a transfer component wiring pattern forming material on which a chip passive element is mounted while being aligned with the shape, the side on which the component wiring pattern is formed is in contact with at least one surface of a sheet-like base material constituting an electrically insulating substrate. And glue and embed them,
A method for manufacturing a wiring board with a built-in chip component, comprising peeling off the metal layer of the wiring pattern for transfer from a carrier layer and transferring the component wiring pattern including at least the metal layer and the chip component to the sheet-like substrate.

Next, the second method of the present invention is as follows: (a) a carrier layer is composed of a first metal layer, and a second metal layer is directly adhered on the first metal layer to form a wiring pattern; Processing, forming a transfer wiring pattern, and (b) mounting and forming a chip component pattern while aligning with the wiring pattern shape. Arranged such that the side on which the component wiring pattern is formed is in contact with at least one surface of the sheet-like base material constituting the electrically insulating substrate,
These are bonded and embedded, and (c) the transfer wiring pattern metal layer including the second metal layer is peeled off from the first metal layer, and at least the second metal layer and the component pattern are formed on the sheet-like base material. A method of manufacturing a wiring board with a built-in chip component, including transferring the component wiring pattern.

Next, in a third method of the present invention, a metal layer is directly adhered to a carrier layer via a release layer, processed into a wiring pattern shape, a transfer wiring pattern is formed, and the transfer wiring pattern is formed. Using a transfer component wiring pattern forming material on which a semiconductor element is mounted while aligning with the shape, the metal layer side on which the element wiring pattern is formed is at least one surface of a sheet-like base material constituting an electrically insulating substrate. Arranging them so as to be in contact with each other, adhering them, peeling the transfer wiring pattern metal layer from the carrier layer, and transferring the component wiring pattern including at least the metal layer and the semiconductor element to the sheet-like substrate. The wiring board with built-in semiconductor and the wiring board with built-in chip component are connected via vias or bumps to obtain decoupled chip components. It is a chip component built-in wiring board manufacturing method characterized by.

Next, in a fourth method of the present invention, a metal layer is directly adhered to a carrier layer via a release layer, processed into a wiring pattern shape, a transfer wiring pattern is formed, and the transfer wiring pattern is formed. A transfer component wiring pattern forming material on which the semiconductor element is mounted while being aligned with the shape, and a metal layer is directly adhered to the carrier layer via a release layer and processed into a wiring pattern shape to form a transfer wiring pattern, Using a transfer component wiring pattern forming material on which a chip component is mounted while being aligned with the transfer wiring pattern shape,
The side on which these element wiring patterns are formed is arranged so as to be in contact with the front and back surfaces of the sheet-like base material constituting the electrically insulating substrate, and these are adhered and embedded to form the transfer wiring pattern metal layer. Is separated from the carrier layer, and the wiring board with a built-in semiconductor, in which the component wiring pattern including at least the metal layer and the semiconductor element is transferred to the sheet-like base material, and the wiring board with a built-in chip component are connected via a via or a bump. And a method of manufacturing a wiring board with a built-in chip component, wherein each chip component is decoupled.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to an electrically insulating multilayer wiring board having a built-in chip passive element having electrodes formed on at least one of the upper and lower surfaces, wherein the thickness t of the chip passive element is a length L. And at least one of the planes corresponding to the upper and lower surfaces with respect to the thickness direction thereof, having an external connection electrode that fits within the plane, and the external connection electrode and the electrically insulating multilayer wiring board This is a multilayer wiring board with a built-in chip component to which the wiring pattern formed in the above is connected.

This is different from a substrate in which a normal chip component is built in. Since electrodes are formed on the upper and lower surfaces, no new area is required for mounting, and a thin chip component is adopted. Therefore, a small and thin chip component built-in substrate having extremely high volume efficiency can be formed.

In the above, it is preferable that an active element including a semiconductor element is further incorporated in the electrically insulating substrate.

If the chip passive element is a single-layer chip capacitor in which electrodes are formed on both upper and lower surfaces, the chip passive element can be made extremely thin and small in area. Further, the capacitance specification of the single-layer chip capacitor can realize a value that is more than 10 times more accurate than that of a normal multilayer chip capacitor, and can be effective in high-frequency applications where design is severe.

Further, the electrode structure formed on the upper and lower surfaces of the single-layer capacitor is constituted by two or more pluralities,
As a result, a plurality of capacitances can be obtained.

The chip passive element is a chip component constituted by a multilayer substrate having a passive element formed of a conductor pattern therein, and corresponds to, for example, a multilayer chip inductor and a multilayer chip capacitor. And a chip component built-in substrate having a large inductance and a large capacity guaranteed.

Further, the multilayer chip capacitor is configured such that a plurality of dielectric layers made of ceramics, an internal electrode formed inside the dielectric layer, and an internal electrode are electrically connected to external terminal electrodes formed on the upper or lower surface. It is preferable to provide a via-hole connection portion penetrating the dielectric layer so as to make the connection. Therefore, the connection terminal can be taken out only by the lower surface electrode, and the distance between the terminal electrode and the internal laminated electrode is shorter than that of the conventional side electrode, so that the stray capacitance can be reduced. Another advantage is that an accurate capacity can be easily derived.

The multilayer chip capacitor further includes a plurality of internal electrodes arranged so as to overlap with the lower surface of the ceramic sintered body via a ceramic layer in a direction perpendicular to the lower surface of the ceramic sintered body. In order to take out the capacitance, a part of the end circle is exposed on the upper surface and the lower surface of the ceramic sintered body, and the first external electrode formed on the upper surface of the ceramic sintered body, At least one second external electrode formed on the lower surface is further provided, and the capacitance can be taken out. Therefore, since the terminal electrodes can be formed on the upper and lower surfaces without using the via hole connection portion, the chip capacitor can be easily manufactured. In addition, since a multilayer structure is employed, a large-capacity capacitor can be obtained, and a chip capacitor built-in substrate having no thickness can be obtained.

Further, the electrode structure formed on the upper and lower surfaces of the multilayer capacitor is composed of a plurality of two or more,
As a result, a plurality of capacitances can be obtained.

The thickness of the chip passive element is 0.1 mm.
If it is above, it can be handled so as not to cause cracks and the like. On the other hand, if it is within the range of 0.5 mm or less, the thickness of the layer containing the chip component can be suppressed.

Further, when the electrically insulating substrate contains an inorganic filler and a thermosetting resin composition and has at least one through hole, and the conductive paste is filled in the through hole, the substrate becomes hard. Excellent, chip components can be easily embedded.

Further, when the inorganic filler is Al ₂ O ₃ , Mg
At least one inorganic filler selected from the group consisting of O, BN, AlN and SiO ₂ , wherein the proportion of the inorganic filler is 70 to 95% by weight and the proportion of the thermosetting resin composition is 5 to 30% by weight %. According to this example, since the inorganic filler is extremely densely packed, if Al ₂ O ₃ is selected for the inorganic filler, for example, a substrate having higher thermal conductivity than a general organic resin substrate can be obtained,
The properties of the inorganic filler can be utilized.

The insulating substrate is made of a woven glass fiber fabric,
At least one reinforcing material selected from the group consisting of a nonwoven fabric of glass fiber, a woven fabric of heat-resistant organic fiber and a nonwoven fabric of heat-resistant organic fiber, and a material obtained by impregnating the reinforcing material with a thermosetting resin composition, and at least one It may have a through hole, and the through hole may be filled with a conductive paste.

Further, when the chip passive element is mounted with a conductive adhesive and a chip component made of a lead-free material is employed, a completely lead-free chip component built-in substrate can be manufactured.

Further, if the chip capacitor built-in wiring layer and the semiconductor element are decoupled and connected via vias or bumps, the shortest distance mounting between the semiconductor element and the chip capacitor is realized. In addition, a device having excellent characteristics such as low noise can be realized.
Here, decoupling refers to confining high-frequency noise generated during the operation of the IC to a high-speed circuit around the IC as much as possible so as not to flow to an external printed circuit board or cable.

Further, if the wiring layer with a built-in chip capacitor and the wiring layer with the built-in semiconductor element are decoupled and connected via vias or bumps, the shortest distance between the semiconductor element and the chip capacitor can be reduced. Mounting and maximum volume efficiency can be realized, and the overall thickness of the laminated built-in substrate can be reduced.

It is preferable that the chip capacitor and the semiconductor element are incorporated in the same layer, and the respective elements are connected by performing decoupling via vias or bumps. According to this example, realization of the shortest distance mounting of the semiconductor element and the chip capacitor and maximal volumetric efficiency were realized, the overall thickness of the built-in substrate was reduced, and the chip capacitor and the built-in process of the semiconductor element were simultaneously performed. Can be performed, and the process can be simplified.

In the present invention, the thickness t of the chip passive element is preferably 5 to 100% of the length L, and more preferably 5 to 100%.
It is preferably from 90% to 90%, particularly preferably from 20% to 70%. The thickness t of the chip passive element is 5 to 10 of the width W.
It is preferably 0%, more preferably 5 to 90%, particularly preferably 20 to 70%. More specifically, the length L of the chip passive element is preferably in the range of 0.2 mm to 2.3 mm, and the width W is preferably in the range of 0.2 mm to 2.5 mm.

Next, according to the first method of the present invention, chip components can be easily mounted on a substrate.

According to the second method of the present invention, for example, a chip component connected to a silver wiring pattern can be easily mounted in a substrate.

In the above-mentioned method, according to an example in which the method of directly attaching the second metal layer and processing it into a wiring pattern shape is a plating method, a fine pattern can be easily realized.

Further, according to the example in which the chip component is mounted on the transfer wiring pattern using a conductive adhesive, it is possible to realize a lead-free component built-in wiring board.

If two or more layers are further laminated by batch lamination, the component built-in substrate can be easily laminated.

Next, according to the third method of the present invention, the substrate with a built-in semiconductor and the substrate with a built-in chip component can be easily laminated while being electrically connected to each other.

Next, according to the fourth method of the present invention, since the semiconductor element and the chip component can be incorporated at the same time, the manufacturing process can be simplified.

In the above method, the wiring board with a built-in semiconductor and the board with a built-in chip component are prepared in a state where they are cured in advance on a C stage, and the respective substrate layers are laminated with a wiring layer of a B stage via a via. Thereby, the components built in the subsequent lamination process can be more firmly protected.

In the present invention, the term “substrate” refers to a sheet-like base material or the like before a wiring pattern is formed, the term “wiring board” refers to a substrate on which a wiring pattern is formed, and the term “circuit board” refers to the above-described circuit board. The figure shows an example in which not only a wiring pattern but also an active component such as a semiconductor chip or a passive component such as LCR is mounted on a substrate.

[0060]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) FIG. 2 is a schematic diagram showing an example of a configuration of an example of a substrate with a built-in chip component according to a first embodiment of the present invention.
Shown in

As shown in FIG. 1A, a conventional chip component built-in substrate has an embedded chip component 104, a via connection portion 102 formed on a substrate 101, and a wiring portion 103.
Are connected by wire bonds 105 or, as shown in FIG. 1B, the embedded chip component 104 and the via connection portion 10 formed on the substrate 101.
2. A structure in which the wiring portion 103 is connected with the solder 106. In the wire bond connection structure shown in FIG. 1A, since the wiring length is long, there is a problem in characteristics particularly in a high frequency range.
On the other hand, in the solder connection structure shown in FIG. 1B, although the problem of the wiring length can be somewhat avoided, the mounting area required for the solder reflow is larger than the chip component, which is an adverse effect on the high-density mounting.

On the other hand, as shown in FIG. 2, in the chip component built-in substrate according to the first embodiment, the built-in chip component 204 has electrodes formed on at least one of the upper and lower surfaces, and The thickness t of the passive element 204 is set smaller than the length L and the width W, and at least one of the surfaces corresponding to the upper and lower surfaces with respect to the thickness direction has the external connection electrode 205 that fits in the surface. The external connection electrode 205 is connected to the wiring pattern 203 formed on the electrically insulating multilayer wiring board 201.

The chip passive element 204 may be, for example, a single-layer chip capacitor. The external dimensions of the single-layer chip capacitor are from 0.25 mm square to 2.5 mm square order, and the thickness is covered according to the capacity from 80 μm to 300 μm, which is extremely thin and accurate compared to ordinary multilayer chip capacitors. A capacitance value can be derived.
Accordingly, it is not necessary to particularly increase the layer thickness of the substrate with embedding, and it is most suitable for a multi-layer substrate with built-in high-density chip components.

As the dielectric material constituting the single-layer chip capacitor, a material mainly composed of barium titanate and a material mainly composed of Pb-based perovskite oxide are considered, but other dielectric materials may be used. Absent.

When high frequency characteristics and high reliability are emphasized, an Au electrode is used as the electrode. However, the present invention is not limited to this, and any of an Ag metallized electrode, a Ni electrode and the like may be used depending on the application. . When an Au electrode is used, TiW is preferably used as a base electrode as a protective film.

On the other hand, the method of forming the through-holes for realizing the interlayer via connection is appropriately determined depending on the type of the sheet-like base material and the like. For example, carbon dioxide laser processing, processing by a punching machine, and a mold Batch processing.

The conductive paste is not particularly limited as long as it has conductivity, but usually a resin containing particles of a conductive metal material can be used. As the conductive metal material, for example, copper, silver, gold, silver palladium or the like can be used, and as the resin, an epoxy binder, a phenolic resin, a cellulose resin, an organic binder such as an acrylic resin can be used. .

In this embodiment, the interlayer connection by filling the conductive paste is assumed, but a connection structure using a through-hole plated via may be used.

(Embodiment 2) Next, FIG. 3 shows a multilayer board with built-in chip parts according to a second embodiment of the present invention. A chip component 304 built in the substrate 301 is a single-layer chip capacitor, and a monopolar electrode 305 is provided on the upper surface.
A large number of electrodes 306 are formed on the lower surface, and an external connection electrode 305, which is a monopolar electrode that fits within these surfaces, and a wiring pattern 303 formed on the electrically insulating multilayer wiring board 301 are connected. External connection terminal 3 which is an electrode
06 and an interlayer connection via 302 formed in the electrically insulating multilayer wiring board 301 are connected via a land wiring layer 307. Multiple electrodes 30 formed on the lower surface
6 may have a multi-terminal structure in the form of a grid as shown in FIG.

According to such a structure, a plurality of different chip capacitors can be prepared for a capacitor which does not exhibit a capacitance as designed according to the mounting form. Can be easily provided. This functions effectively especially when a capacitance change occurs due to the internal structure.

(Embodiment 3) Next, a schematic configuration of a multilayer board with built-in chip parts according to a third embodiment of the present invention is shown in FIG.
Shown in In FIG. 4, a chip component 404 is formed by electrically connecting a plurality of dielectric layers 406 made of ceramics, an internal electrode 404 formed inside the dielectric layer, and an internal electrode and an external terminal electrode formed on the upper or lower surface. A chip multilayer capacitor 404 having a via hole connection portion 402 penetrating the dielectric layer so as to be connected is embedded in a substrate 401. The connection between the layers is performed at the via-hole connection portion 407. Therefore, compared with the case of the multilayer chip capacitor in which the connection terminal can be taken out only by the lower surface electrode (the upper surface electrode after embedding) and the conventional external terminal electrode is constituted by the side surface electrode, the present embodiment The chip capacitor described above has a structure in which the distance between the external terminal electrode and the internal laminated electrode is short, so that the stray capacitance can be reduced and an accurate capacitance can be derived.

(Embodiment 4) Next, a schematic configuration of a multilayer board with built-in chip components according to a fourth embodiment of the present invention is shown in FIG.
Shown in In FIG. 5, a plurality of internal electrodes 506 are provided so as to overlap with the lower surface of the ceramic sintered body 505 via a ceramic layer along a direction perpendicular to the lower surface of the ceramic sintered body 505. A part of the end circle is exposed on the upper surface and the lower surface of the ceramic sintered body, and the first external electrode 507 formed on the upper surface of the ceramic sintered body and the lower electrode formed on the lower surface of the ceramic sintered body. And at least one second external electrode 508 buried in the substrate 501, wherein the interlayer connection via 502 formed in the substrate 501 and the external electrode 508 are connected via the wiring layer 504. Have been. Further, the upper electrode 507 on the chip capacitor and the wiring layer 503 are connected and arranged.

According to this structure, since a laminated structure is employed, a large capacitance can be taken out as a chip capacitor. Further, since the terminal electrodes can be formed on the upper and lower surfaces without using the via hole connection portion, the chip capacitor can be easily manufactured. Therefore,
It is possible to obtain a substrate with a built-in chip capacitor having a large capacity and no thickness.

In the present invention, a chip capacitor is used in each of the embodiments and examples as a representative of chip components. However, it is needless to say that a multilayer ceramic inductor, a chip resistor and the like are also effective. .

The multilayer capacitor is formed by using a rectangular parallelepiped ceramic sintered body, and may use an appropriate dielectric ceramic such as a barium titanate ceramic.

In the ceramic sintered body, a plurality of internal electrodes are arranged so as to overlap with each other via a ceramic layer.

(Embodiment 5) Next, FIG. 6 shows a multilayer board with built-in chip components according to a fifth embodiment of the present invention. The chip component 604 built in the substrate 601 is a multilayer chip capacitor, and a plurality of chip components are arranged so as to overlap with each other via a ceramic layer along a direction perpendicular to the lower surface of the ceramic sintered body 605 as in the fourth embodiment. Of the plurality of internal electrodes, in order to take out the capacitance, a part of the end circle is exposed on the upper surface and the lower surface of the ceramic sintered body, and the upper surface of the ceramic sintered body And a plurality of external electrodes 607 formed on the lower surface of the ceramic sintered body, and are embedded in the substrate 601.
1 or the wiring layer 6
03 is connected to the external multiple electrodes 607 or 608. The plurality of electrodes 607 and 608 may have a multi-terminal structure in a grid shape as shown in FIG.

(Embodiment 6) Next, FIG. 7 shows a multilayer board with built-in chip components according to a sixth embodiment of the present invention. FIG. 7 shows a ceramic sintered body 70 similar to the fourth embodiment.
5 and a plurality of internal electrodes 706 arranged so as to overlap with each other via a ceramic layer along a direction perpendicular to the lower surface of the internal electrode 5. Are exposed on the upper and lower surfaces of the ceramic sintered body 705, and a first external electrode 707 formed on the upper surface of the ceramic sintered body and at least one second electrode formed on the lower surface of the ceramic sintered body. External electrode 708
And a structure embedded in the substrate 701,
A wiring forming layer 703 formed in a substrate 701 and an external electrode 708 are connected and mounted with a conductive adhesive. Therefore, since this is a solder-free mounting mode, if a chip component made of a lead-free material is used for the ceramic sintered body 705, a chip component built-in board made entirely of a lead-free material can be manufactured. .

The built-in chip parts are not limited to the chip capacitors having the multilayer structure shown in FIG. 7, but may be single-layer chip capacitors, chip inductors or chip resistors.

(Embodiment 7) Next, FIG. 8 shows a multilayer board with built-in chip components according to a seventh embodiment of the present invention. FIG. 8 shows that a chip capacitor 804 having a laminated structure of vertical electrodes is embedded in a substrate 801 as in the sixth embodiment.
01 is connected to the external connection electrode 806 of the chip capacitor 804, and the built-in chip capacitor 804 and the semiconductor element 808 mounted on the surface layer of the substrate are decoupled. Therefore, the shortest distance mounting of the semiconductor element 808 and the chip capacitor 804 is realized, and a device having excellent characteristics such as low noise can be realized.

The built-in chip components are not limited to the chip capacitors having the multilayer structure shown in FIG. 8, but may be single-layer chip capacitors.

(Embodiment 8) Next, FIG. 9 shows a multilayer board with built-in chip components according to an eighth embodiment of the present invention. FIG. 9 shows a chip capacitor 904 having a laminated structure of vertical electrodes embedded in a substrate 901, similarly to the seventh embodiment.
01 (a) and a structure in which a connection via 902 formed in the chip capacitor 904 is connected to an external connection electrode 906 and a structure in which a semiconductor element 908 is built in a substrate 901 (b). The chip capacitor built-in wiring layer 904 and the wiring layer 9 in which the semiconductor element is built in
05 is connected via an interlayer via 902 and the chip capacitor 904 and the semiconductor element 908 are decoupled. Therefore, the shortest distance mounting between the semiconductor element and the chip capacitor and the maximum volume efficiency can be achieved. It is possible to reduce the thickness of the entire laminated built-in substrate.

The built-in chip parts are not limited to the chip capacitors having the multilayer structure shown in FIG. 9 but may be single-layer chip capacitors.

(Embodiment 9) Similarly, FIG. 10 shows a multilayer board with built-in chip components according to a ninth embodiment of the present invention. FIG. 10 shows a chip capacitor 1004 having a laminated structure of vertical electrodes embedded in a substrate 1001 and an interlayer connection via 1002 formed in the substrate 1001 in the same manner as in the eighth embodiment.
And the external connection electrode 100 of the chip capacitor 1004
6 is the same, but the same substrate 100
1, a semiconductor element 1008 is also built in, and a wiring layer 1005 formed on the substrate 1001 is flip-chip connected. Further, a chip capacitor 1004 and a semiconductor element 1008 are connected via an interlayer via 1002 and the wiring layer 1005. Is a structure for performing decoupling.
According to this structure, the step of incorporating the chip capacitor 1004 and the step of incorporating the semiconductor element 1008 can be performed at the same time, so that the steps can be simplified, and the shortest distance mounting between the semiconductor element and the chip capacitor can be achieved. The minimum volume efficiency can be realized.

The built-in chip components are not limited to the chip capacitors having the multilayer structure shown in FIG. 10, but may be single-layer chip capacitors, multilayer chip inductors, or chip resistors.

On the other hand, as the substrate in which the chip components and the semiconductor elements are embedded, the following sheet-like base materials are desirable. For example, it is preferable that the sheet-like substrate includes an inorganic filler and a thermosetting resin composition, has at least one through hole, and the through hole is filled with a conductive paste. This makes it possible to easily obtain a high-density mounting wiring board having excellent heat conductivity and having an IVH structure in which the wiring patterns are electrically connected by the conductive paste.

When this sheet-shaped substrate is used, a high-temperature treatment is not required in the production of a wiring board. For example, a low-temperature treatment of about 200 ° C., which is the curing temperature of a thermosetting resin, is sufficient. .

It is preferable that the proportion of the inorganic filler is 70 to 95% by weight and the proportion of the thermosetting resin composition is 5 to 30% by weight, particularly preferably, to the entire sheet-like substrate. The ratio of the inorganic filler is 85 to 85;
90% by weight, and the ratio of the thermosetting resin composition is 1
0 to 15% by weight. Since the sheet-like base material can contain the inorganic filler at a high concentration, it is possible to arbitrarily set a coefficient of thermal expansion, a thermal conductivity, a dielectric constant, and the like in the wiring board according to the content.

The inorganic filler is Al ₂ O ₃ , MgO,
Preferably, at least one inorganic filler selected from the group consisting of BN, AlN and SiO ₂ .
By appropriately determining the type of the inorganic filler, for example, thermal conductivity, thermal expansion property, it is possible to set the dielectric constant to desired conditions, for example, thermal expansion in the planar direction in the sheet-like substrate It is also possible to set the coefficient to be substantially the same as the coefficient of thermal expansion of the semiconductor to be mounted, and to impart high thermal conductivity.

Among the inorganic fillers, for example, Al
_TwoO_ThreeBN, AlN and other sheet-like substrates
The sheet-like substrate made of MgO has excellent heat conductivity.
It is excellent and can increase the coefficient of thermal expansion. Also
SiO_Two, Especially amorphous SiO 2 _TwoIf used, thermal expansion
Coefficient, low weight, low dielectric constant sheet-like substrate
Can be The inorganic filler is one kind.
Or two or more of them may be used in combination.

The sheet-like substrate containing the inorganic filler and the thermosetting resin composition can be produced, for example, as follows. First, a viscosity adjusting solvent is added to a mixture containing the inorganic filler and the thermosetting resin composition to prepare a slurry having an arbitrary slurry viscosity. As the viscosity adjusting solvent, for example, methyl ethyl ketone, toluene and the like can be used.

Then, on the release film prepared in advance, a film is formed using the slurry by, for example, a doctor blade method or the like, and is processed at a temperature lower than the curing temperature of the thermosetting resin to obtain the viscosity. After the solvent for adjustment is volatilized, the release film is removed to obtain a sheet-like substrate.

The film thickness at the time of forming the film is appropriately determined depending on the composition of the mixture and the amount of the viscosity adjusting solvent to be added, and is usually in the range of 80 to 200 μm.
The conditions for volatilizing the viscosity adjusting solvent are appropriately determined depending on, for example, the type of the viscosity adjusting solvent and the type of the thermosetting resin.
C. for 5-15 minutes.

As the release film, generally, an organic film can be used. For example, at least one selected from the group consisting of polyethylene, polyethylene phthalate, polyethylene naphthalate, polyphenylene sulfide (PPS), polyphenylene phthalate, polyimide and polyamide An organic film containing one resin is preferable, and PPS is particularly preferable.

Another sheet-like base material is a sheet-like reinforcing material impregnated with a thermosetting resin composition,
There is a sheet-like base material having at least one through hole, and the through hole is filled with a conductive paste.

The sheet-like reinforcing material is not particularly limited as long as it can hold the thermosetting resin. However, the woven fabric of glass fiber, the nonwoven fabric of glass fiber, the woven fabric of heat-resistant organic fiber, and the heat-resistant organic fiber can be used. Preferably, it is at least one sheet-like reinforcing material selected from the group consisting of nonwoven fabrics. Examples of the heat-resistant organic fiber include wholly aromatic polyamide (aramid resin), wholly aromatic polyester, polybutylene oxide and the like, and among them, aramid resin is preferable.

The thermosetting resin is not particularly limited as long as it has heat resistance. However, since it is particularly excellent in heat resistance, a group consisting of an epoxy resin, a phenol resin, a cyanate resin, a polyphenylene phthalate resin, and a polyphenylene ether resin. It is preferable to include at least one resin selected from the group consisting of: Further, the thermosetting resin may be any one type, or two or more types may be used in combination.

Such a sheet-like substrate can be produced, for example, by immersing the sheet-like reinforcing material in the above-mentioned thermosetting resin composition, followed by drying to obtain a semi-cured state.

It is preferable that the impregnation is performed such that the ratio of the thermosetting resin in the entire sheet-like substrate is 30 to 60% by weight.

In these manufacturing methods, when a sheet-like substrate containing a thermosetting resin as described above is used, the lamination of the wiring substrates is performed by curing the thermosetting resin by heating and pressing. It is preferred to do so. According to this, in the laminating step of the wiring substrate, for example, a low-temperature treatment of about 200 ° C. which is a curing temperature of the thermosetting resin is sufficient.

The sheet-like reinforcing material is made of polyimide, LC
A sheet obtained by coating a thermosetting resin on a film sheet such as P or aramid may be used.

(Embodiment 10) Next, the tenth embodiment of the present invention will be described.
FIG. 12 shows a method for manufacturing a multilayer board with built-in chip components according to the embodiment, in comparison with the manufacturing method according to the conventional embodiment, FIG.

As shown in FIGS. 11 (a) and 11 (b), the transfer component wiring pattern forming material according to the embodiment which has already been proposed includes a release carrier metal foil 1106 which is a first metal layer.
And a solder paste 1105 for connecting a chip component on a transfer wiring pattern forming material formed in a two-layer structure of a wiring metal layer 1103 as a second metal layer formed thereon.
Is printed. The transfer wiring pattern and the chip component may be connected by using a conductive adhesive.

Next, as shown in FIG.
After setting 104 at a predetermined position, the chip component was mounted on a transfer forming material by passing through a reflow furnace.

Thereafter, as shown in FIGS. 11 (d) to 11 (e), pressure is applied to the sheet-like base material 1101 constituting the substrate, on which the interlayer connection vias 1102 are formed, while performing positioning, and the chip is formed. The transfer forming material on which the components were mounted was pressed, and the sheet-like base material was simultaneously cured.

Thereafter, as shown in FIG. 11F, only the portion of the metal foil 1106 for the release carrier is removed by etching to obtain a substrate in which the chip component 1104 is built.

In this case, the chip component is solder-mounted on the transfer forming material in a lying state. However, it has been reported as a conventional example that the chip component is mounted in a standing state and is embedded in a substrate. However, in such a case, the length direction of the chip component is often buried corresponding to the layer thickness as it is, and the layer thickness of the substrate is increased, and it is practically difficult to form a multilayer structure.

In any case, a certain fixed or more mounting area is required in order to stably connect the wiring pattern of the transfer forming material and the side surface electrode of the chip component by soldering. Therefore,
It has become difficult to arrange wiring very close to the chip components, which has hindered high-density mounting.

On the other hand, in the manufacturing method according to the tenth embodiment of the present invention, the single-layer chip capacitor 1204 having electrodes on both the upper and lower surfaces is formed by using the wiring pattern 1 having the transfer forming material.
Since the mounting is performed on the mounting surface 203, even when the mounting is performed by soldering or a conductive adhesive as shown in FIG. Can be.

According to these manufacturing methods, after forming a reverse pattern using a dry film resist (DFR),
Since the wiring pattern metal layer is formed by a direct drawing method such as electroless plating or pattern plating including electrolytic plating, sputtering, and vapor deposition, a fine wiring pattern can be formed. In addition, the metal foil constituting the wiring pattern, in the case of the plating method, the metal foil constituting the carrier may be the same as, for example, copper foil,
Further, it may be constituted by a silver plating film which is a different metal. Further, for the same reason as described above, the metal foil for a carrier as the first metal layer can be reused, so that the cost can be reduced and the industrial use is excellent.

When a single-layer chip capacitor is embedded using a transfer forming agent, as shown in FIG.
The wiring pattern for connecting the chip capacitor may be transferred to the sheet-like device 1201 in advance,
Depending on the wiring pattern, the chip component 1204 and the interlayer connection via 1202 may be directly buried so as to be connected.

In the present embodiment, the release carrier copper foil 1206 constituting the transfer forming material can be transferred by peeling off only the release carrier 1206 without etching. Have confirmed.

According to this manufacturing method, since the area required for mounting the chip component is small and the thickness is small, the thickness of the component built-in layer can be suppressed to about 100 to 200 μm, and it is sufficient to increase the number of layers. It becomes possible.

(Embodiment 11) Next, the first embodiment of the present invention will be described.
FIG. 13 shows a method for manufacturing a multilayer board with built-in chip components according to one embodiment.

As shown in FIGS. 13 (a) to 13 (c), in this embodiment, first, an adhesive film layer 1302 is formed on a release resin film 1301, and then a wiring pattern layer 1303 is formed.
To form Thereafter, as in the tenth embodiment, the single-layer chip capacitor 1304 is mounted on the transfer forming material. However, the single-layer chip capacitor 13 used in this embodiment
Reference numeral 04 denotes a single electrode on one side only, and the other side includes a large number of electrodes. In the present embodiment, FIG.
As shown in (i) to (i), after mounting and connecting the chip component and the transfer wiring pattern on the side of the plurality of electrodes, a crimping and embedding process is performed on the sheet-like device 1306 while performing alignment. In embedding, as shown in FIG. 13 (f), the wiring pattern on the other side was previously transferred. Thereafter, the release carrier resin film was manually peeled off. When a resin is used for the release film of the transfer forming material as in the present embodiment, the continuity and the like of the chip components mounted on the transfer forming material can be checked before embedding.

When a plurality of external terminal electrodes are provided for a single-layer chip capacitor as in the present embodiment, a predetermined capacitance can be easily obtained. In particular, the adjustment is easy when the capacitance changes due to the built-in substrate, which is particularly effective.

In the manufacturing method of this embodiment, a single-layer chip capacitor is used. However, a vertical chip multilayer chip capacitor, a chip inductor, and a chip resistor as shown in FIGS. I do not care.

(Embodiment 12) Next, the first embodiment of the present invention will be described.
FIG. 14 shows a method of manufacturing a multilayer board with built-in chip components according to the second embodiment. As shown in FIG. 14, the transfer forming material used in the present embodiment includes a release carrier metal foil 1406 as a first metal layer and a release layer 1 formed thereon.
407 and a wiring metal 1403 which is a second metal layer formed thereon.

In these transfer component wiring pattern forming materials, it is preferable that the adhesive strength between the first metal layer and the second metal layer forming the wiring layer is weak, for example, 50 gf / cm or less. In the first transfer component wiring pattern forming material, a plating method, a vapor deposition method, or the like is used, so that a process such as etching, plating, and washing with water is performed.
It has been recognized that only the second metal layer can be easily peeled when peeling, although the metal layers of the layers do not peel. Further, the chip component pattern formed of solder or a conductive adhesive can be easily separated from the first metal layer as a carrier.

On the other hand, in the transfer component wiring pattern forming material, an organic layer having an adhesive force of less than 1 μm having an adhesive force, for example, a thermosetting resin such as a urethane resin, an epoxy resin, or a phenol resin can be used. However, the present invention is not limited to this, and another thermoplastic resin or the like may be used. However, when the thickness is more than 1 μm, the peeling performance deteriorates,
1 μm or less is preferable because transfer may become difficult.

On the other hand, a plating layer may be interposed as the release layer 1407 for the purpose of intentionally reducing the adhesive strength. For example, a metal plating layer, a nickel plating layer, a nickel phosphorus alloy layer, an aluminum plating layer, or the like, which is thinner than 1 μm, may be interposed between the copper foils so as to have releasability.

Thus, with respect to the wiring portion made of the second metal layer, the second metal layer is easily separated from the first metal layer when transferred to the substrate, and the second metal layer is easily transferred. And it becomes easy to transfer the component pattern to the substrate. In the case of a metal plating layer, a thickness of the release layer of 100 nm to 1 μm is sufficient, and as the thickness increases, the cost increases in the process. Therefore, it is desirable that the thickness be at least less than 1 μm.

In the transfer component wiring pattern forming material, the first metal layer preferably contains at least one metal selected from the group consisting of copper, aluminum, silver and nickel, and particularly contains copper. Is preferred.
Like the first metal layer, the second metal layer preferably contains at least one metal selected from the group consisting of copper, aluminum, silver and nickel. In the case of the forming material, silver is used. In the case of the second or third transfer component wiring pattern forming material, silver is used.
Preferably, it contains copper. This is because when copper is used for the first metal layer, it is inexpensive, that is, there are many commercially available foils having a predetermined thickness. In addition, when copper is used for the second metal layer, it is easy to generate by plating. Also, the third
In the case of the transfer forming material according to the embodiment, the first metal layer and the second
If the metal layer is the same, there is an effect that processing can be controlled with the same etchant, but when the metal layer is copper, there is an advantage that fine processing conditions by etching have already been well developed. The metal may be one kind, or two or more kinds may be used in combination.

In the first, second and third transfer component wiring pattern forming materials, the thickness of the second metal layer is preferably in the range of 1 to 18 μm, particularly preferably 3 to 12 μm. Range. The thickness is 3
When the thickness is smaller than μm, good conductivity may not be exhibited when the second metal layer is transferred to a substrate. When the thickness is greater than 18 μm, it is difficult to form a fine wiring pattern. There is a risk.

In the transfer component wiring pattern forming material, the thickness of the first metal layer is preferably in the range of 4 to 100 μm, particularly preferably 20 to 70 μm.
m. The first metal layer functions as a carrier, and in some cases, as shown in the present embodiment, the surface layer is etched to have an uneven structure like the wiring layer. Preferably, it is a layer. In addition, since the carrier layer used for transfer is a metal layer, sufficient mechanical strength and heat resistance against thermal strain generated during transfer and stress strain in a planar direction are exhibited.

The chemical etching for forming the wiring pattern can be specifically performed as follows. When a basic cupric chloride aqueous solution containing ammonium ions is used as an etchant, only the second metal layer can be etched when the release layer is made of, for example, a nickel-phosphorus alloy layer. Thereafter, if a mixed solution of nitric acid and hydrogen peroxide is used as an etching solution, only the peeling layer can be removed. It is used when it is intended that the wiring portion does not become a concave portion after the transfer but becomes flat.

Further, by making the metal foil forming the wiring pattern the same as the metal foil forming the carrier, the wiring to the first metal layer forming the carrier can be performed by one etching process as in the present embodiment. The same concavo-convex shape as the pattern can be formed.

Further, after the transfer, the constituent materials of the transfer wiring pattern forming material other than the second metal layer may be reused, and in particular, in the latter case, the transfer wiring pattern forming material may be processed into a wiring pattern shape. It is also possible to use it for letterpress printing to form patterns in different ways. For this reason, cost reduction is possible and it is excellent in industrial use.

In the configuration of the transfer component wiring pattern, the metal layer may be formed on the second metal layer by electrolytic plating on the second wiring pattern. If the third metal layer or the metal layer for forming the wiring pattern is formed by the electrolytic plating method, an appropriate adhesive property can be obtained on the bonding surface between the second metal layer and the third metal layer. In addition, since there is no gap between the metal layers, a favorable wiring pattern can be formed even if etching is performed, for example. On the other hand, after the third metal layer is formed on the second metal layer by panel plating, the pattern may be formed by masking the wiring pattern. In this case, it is effective in preventing surface oxidation of the second metal layer after transfer and improving solder wettability.

In this method of manufacturing a transfer wiring pattern, before forming the third metal layer on the second metal layer, it is preferable to roughen the surface of the second metal layer. . Before forming the metal layer, before forming a metal layer for a wiring pattern on the second metal layer, or on the second metal layer masked in the wiring pattern, the wiring pattern Before the formation of the second metal layer. As described above, when the second metal layer is subjected to a surface roughening treatment, the adhesion between the second metal layer and the third metal layer is improved.

Further, in the method for manufacturing a transfer wiring pattern, a different metal layer may be formed on the third metal layer by an electrolytic plating method. By selecting a metal component that is chemically stable with respect to an etchant that corrodes the metal layer that is different from the electrolytic plating method, that is, the first to third metal layers, By chemical etching method,
Without reducing the thickness of the third and fourth metal layers, the first
This is preferable because it can be processed into a wiring pattern including the surface portion of the metal layer.

The layers composed of the different metals include:
For example, a chemically stable and low-resistance Ag or Au plating layer is desirable. Since these are metals that are not easily oxidized, the connectivity between the wiring layers plated with these and, for example, vias or bare chip bumps or conductive adhesive formed in advance on the substrate can be further stabilized.

On the other hand, when the chip parts and the wiring patterns are transferred to the surface layer, especially when the distance between terminals of inductors, capacitors, semiconductor chips, etc. is short,
From the viewpoint of increasing the creepage distance, a transfer forming material partially processed up to the carrier layer 1406 as in this embodiment is preferable.

When the wiring portion has such a concave shape, excellent mountability is exhibited when, for example, flip-chip mounting of a semiconductor is performed.

(Thirteenth Embodiment) Similarly, FIG. 15 shows a method of manufacturing a multilayer board with built-in chip components according to a thirteenth embodiment of the present invention. The present embodiment is characterized in that the component built-in layers are stacked in two or more layers.

As shown in FIG. 15A, a semiconductor bare chip 1510 is flip-chip mounted on a transfer forming material on which a wiring pattern 1503 similar to the above embodiment is formed.
Reference numeral 1509 denotes an underfill for reinforcing the mounting. In the present embodiment, a resistor 1511 formed by printing at the same time is also added.

The circuit board can transfer and form component patterns and wiring patterns at a low temperature of 100 ° C. or less.
Even in a sheet using a thermosetting resin, an uncured state can be maintained, and as shown in FIG. 15D, thermosetting shrinkage by batch lamination can be realized.

Therefore, in a circuit board having four or more layers, it is not necessary to correct the curing shrinkage for each layer.
Thereby, a circuit board having a multilayer structure having fine wiring patterns and component patterns can be manufactured. However, the wiring portion and the component portion forming the inner layer need not be concave as described above, and may be flat.

As shown in FIGS. 15D and 15E,
In the case of manufacturing a multilayer circuit board as in the present embodiment, the semiconductor elements manufactured as described above, or the respective single-layer circuit boards in which chip components and the like are embedded, are stacked,
It can be produced by bonding between layers. Naturally, as in the present embodiment, the wiring layers 1512 and 1513 in which the B-stage wiring pattern and the interlayer via are formed are added.
It can be laminated on a five-layer plate at a time.

Further, according to this structure, since the semiconductor element and the chip capacitor functioning as a decap can be mounted so as to be located very close to each other, excellent characteristics can be found.

As described in the present embodiment, the components to be incorporated are not limited to chip components, but may be semiconductor devices, or film-like LCRs formed by printing or the like.
Various components can also be incorporated.

For example, when a circuit board containing a sheet-shaped base material containing a thermosetting resin is laminated, first, as shown in FIGS. ,
Only the component wiring pattern is transferred to the sheet-like base material in a low-temperature range where the thermosetting is not performed, and the obtained single-layer circuit board is laminated. Then, the laminate is heat-pressed at the curing temperature of the thermosetting resin, and the thermosetting resin is cured, whereby the circuit boards are bonded and fixed. When the circuit layer is transferred by intentionally setting the temperature of the heating and pressing conditions to 100 ° C. or less, the sheet-like base material can be treated almost like a prepreg even after the transfer, so that multilayering by batch stacking instead of sequential stacking is possible. Become.

Although the number of layers in the multilayer circuit board is not particularly limited, it is usually 4 to 8 layers, and may be as many as 12 layers. Further, the overall thickness of the multilayer circuit board is usually 500 to 1000 μm.

Note that the circuit board constituting the intermediate layer other than the outermost layer of the multilayer circuit board is not a recess in which a wiring pattern or the like is embedded in the surface but is flat in consideration of an electrical connection structure by inner vias. You may. In order to intentionally obtain this structure, it is preferable to use the first or second transfer component wiring pattern of the present invention. The outermost layer of the multilayer structure may be a circuit board having a flat surface, but a circuit board having a concave portion on the surface and a second metal layer or the like formed on the bottom thereof may be a semiconductor chip or the like. Is easier and more preferable.

(Embodiment 14) Similarly, FIG. 16 shows a method of manufacturing a multilayer board with built-in chip components according to a fourteenth embodiment of the present invention. This embodiment corresponds to the first embodiment.
As in the case of No. 3, the component built-in layers are stacked in two or more layers.

According to the manufacturing method of this embodiment, the step of incorporating individual semiconductor elements and chip components is the same as that of the thirteenth embodiment.
This is similar to the above, except that the sheet-shaped base material as the circuit board is completely cured at the same time as the built-in process. According to this manufacturing method, since the component built-in layers 1601 and 1602 are completely cured, the B-stage wiring layer 1603 that serves as an adhesive when connecting the layers in the stack.
Will be done through.

Accordingly, in the laminating step, the components such as the semiconductor element 1610 and the chip component 1611 are already protected by the cured substrates 1601 and 1602, so that the possibility of damage is reduced. .

(Embodiment 15) Next, the first embodiment of the present invention will be described.
FIG. 17 shows a method of manufacturing a multilayer board with built-in chip components according to the fifth embodiment. The present embodiment is characterized by a structure in which a chip component and a semiconductor element are built in the same component built-in layer, and the chip component and the semiconductor element are located very close to each other and connected.

According to the manufacturing method of the present embodiment, the point that the transfer forming material is used in the step of incorporating individual semiconductor elements and chip components is the same as that of the above embodiment, but the transfer forming material including each chip component is used. 1710 and semiconductor element 170
This is characterized in that the transfer-forming material 1706 containing No. 5 is simultaneously buried from both upper and lower surfaces of a sheet-like base material as a circuit board and is built therein. According to this manufacturing method, it is possible to realize a structure in which the semiconductor element 1703 is connected to the chip component 1704 through the interlayer connection via 1708 by a short wiring while each component built-in layer is a single layer.

In this case, if the chip component 1704 is a decoupling device, decoupling with a semiconductor element such as an MPU can be performed, and excellent functions can be exhibited.

[0151]

Next, the present invention will be described more specifically with reference to the drawings by using embodiments.

(Example 1) FIG. 12 is a cross-sectional view showing an example of a schematic process of manufacturing the transfer wiring pattern forming material. As shown in FIG. 12A, the first metal layer 1206
, An electrolytic copper foil having a thickness of 35 μm was prepared. First, a copper salt raw material is dissolved in an alkaline bath, and this is electrodeposited on a rotating drum so as to have a high current density to form a metal layer (copper layer). A copper foil was produced.

Next, as shown in FIG. 12B, a wiring reverse pattern was formed using a dry film resist 1209. Thereafter, as shown in FIG.
On the surface of the first metal layer 1206, a metal layer 1203 for forming a wiring pattern made of silver is laminated by electrolytic plating so as to have a thickness of 9 μm, and FIG.
As shown in (1), a transfer wiring pattern forming material having a two-layer structure was produced. Center line average roughness of this surface (Ra)
However, a surface roughening treatment was performed so as to be about 4 μm.

Next, after printing using a solder paste on the mounting position of the single-layer chip capacitor, the capacitor was mounted and the connection was secured in a reflow furnace.

First, the substrate 120 for transferring the wiring pattern
1 was prepared. The substrate 1201 was manufactured by preparing a sheet-shaped base material made of a composite material, providing a via hole in the base material, and filling the via hole with a conductive paste 1207. Hereinafter, the sheet-like substrate 12
01 shows the component composition.

(Component Composition of Sheet-like Substrate 1201) (1) Al ₂ O ₃ (AS-40, manufactured by Showa Denko KK; particle size: 12 μm)
m): 90% by weight (2) Liquid epoxy resin (manufactured by Nippon Lec, EF-45)
0): 9.5% by weight (3) Carbon black (manufactured by Toyo Carbon): 0.2% by weight (4) Coupling agent (manufactured by Ajinomoto Co., titanate: 46)
B): 0.3% by weight Each of the above components was weighed so as to have the above composition, and a methyl ethyl ketone solvent was added to the mixture as a viscosity adjusting solvent until the slurry viscosity of the mixture became about 20 Pa · s. Was added. Then, a cobblestone of alumina was added thereto, and the mixture was rotated and mixed in a pot for 48 hours at a speed of 500 rpm to prepare a slurry.

Next, a release film having a thickness of 75 μm was prepared.
A polyethylene terephthalate (PET) film having a gap of about 0.1 m was prepared on the PET film by the doctor blade method using the slurry.
A film was formed to a thickness of 7 mm to form a film-formed sheet. Then, the film-forming sheet was left at a temperature of 100 ° C. for 1 hour to volatilize the methyl ethyl ketone solvent in the sheet, remove the PET film, and produce a sheet-like substrate 1201 having a thickness of 200 μm. Removing the solvent,
Since the test was performed at a temperature of 100 ° C., the epoxy resin remained in an uncured state, and the sheet-shaped substrate had flexibility.

This sheet-like substrate is cut into a predetermined size by utilizing its flexibility, and a carbon dioxide laser is used to cut a sheet having a diameter of 0 mm at a position having a pitch of 0.2 mm to 2 mm at equal intervals. A through hole (via hole) of .15 mm was provided. Then, the through-hole was filled with a conductive paste 1207 for filling a via hole by a screen printing method, and the substrate was manufactured. As the conductive paste 1207, the following materials were prepared so as to have the following composition, and kneaded with three rolls.

(Conductive paste 1202) (1) Spherical copper particles (Mitsui Metal Mining Co., Ltd .: particle size 2 μm)
m): 85% by weight (2) Bisphenol A type epoxy resin (Eicoat 828, manufactured by Yuka Shell Epoxy): 3% by weight (3) Glucidyl ester epoxy resin (YD-171, manufactured by Toto Kasei): 9 % By weight (4) Amine adduct hardener (manufactured by Ajinomoto Co., MY-2
4): 3% by weight Next, as shown in FIG.
Were placed so that the chip component pattern side of the transfer component wiring pattern forming material was in contact with both sides of the transfer member, and heated and pressed at a pressing temperature of 120 ° C. and a pressure of 10 kg / cm ² for 5 minutes using a hot press. Note that regarding the capacitor 1204,
When a structure sandwiching the upper and lower electrode surfaces is employed, the electrode pattern 1207 may be transferred and formed on the substrate 1201 in advance.

By this heating and pressurizing treatment, the substrate 120
1 (the epoxy resin in the sheet-like base material and the conductive paste 1202) melts and softens, and as shown in FIG.
04 and the wiring pattern 1203 were buried in the substrate 1201. Then, the heating temperature was further increased, and the epoxy resin was cured by treating at a temperature of 175 ° C. for 60 minutes.

As a result, the sheet-like base material and all the component patterns are firmly adhered to each other.
202 and each component pattern were electrically connected (inner via connection) and adhered firmly.

By removing the first metal layer 1206 as the carrier layer from the lamination step shown in FIG. 12G, a substrate with a built-in chip capacitor as shown in FIG. Was done.

The mounting position of the chip component was also accurate, and a circuit board having a strict design could be easily formed. According to the manufacturing method using the transfer forming material including the chip capacitor of the present embodiment, the chip component and the interlayer connection via 1
The bonding of the wiring between the wiring pattern 202 and the wiring pattern 1203 was good and functioned well. In addition, even when a capacitor high-temperature load reliability test (125 ° C., 50 V, 1000 hours) was performed, the insulation resistance of the dielectric layer of the capacitor 1204 did not deteriorate, and an insulation resistance of 10 ⁶ Ω or more could be secured.

After the transfer and heating freezing steps, a flat mounting surface was formed on this wiring board. In this embodiment, a gold plating layer may be formed on the wiring layer 1203 of the circuit board.

In this circuit board, the built-in chip components were realized in a form in which the thickness of the component built-in substrate layer was relatively small, 200 μm, and no warping, cracking, or distortion of the board occurred.

In this embodiment, alumina powder is used as the inorganic filler of the substrate, but silicon oxide powder may be used. In this case, similarly, high thermal conductivity was maintained as compared with a normal resin substrate such as FR-4, and a characteristic having a low dielectric constant of 3.5 was found.

In this embodiment, the carrier copper foil is used as the transfer forming material. However, a transfer forming material using a resin film as a carrier may be used.

(Example 2) FIGS. 17A to 17D are cross-sectional views schematically showing an example of a manufacturing process of the transfer wiring pattern forming material for mounting a chip component.

As shown in FIG. 17A, an electrolytic copper foil having a thickness of 35 μm was prepared as the first metal layer 1701.
Specifically, a copper salt raw material is dissolved in an alkaline bath, and this is electrodeposited on a rotating drum so as to have a high current density to form a metal layer (copper layer), and the copper layer is continuously wound. Thus, an electrolytic copper foil was produced.

Next, as shown in FIG. 17B, a thin plating layer made of a nickel-phosphorus alloy is formed on the surface of the first metal layer 1701, and a peeling layer 1702 is formed. As the metal layer 1703 for forming a wiring pattern, the same electrolytic copper foil as that of the first metal layer 1701 was used.
To obtain a laminate having a three-layer structure.

The center line average roughness (Ra) of this surface is 4
The surface was roughened to a thickness of about μm. The surface roughening treatment was performed by depositing fine copper particles on the electrolytic copper foil.

Next, the second metal layer 1703 and the first metal layer 170 having arbitrary wiring patterns are etched by a chemical etching method (immersion in an aqueous ferric chloride solution).
Patterning was performed on the surface layer portion of No. 1.

Thereafter, the mask portion was removed with a release agent to obtain a transfer wiring pattern forming material shown in FIG. Since the first metal layer and the second metal layer are made of the same copper, a wiring layer having a convex portion is formed not only on the second metal layer but also on the first metal layer by one chemical etching. Can be formed. There is a structural feature in that the first metal layer which is a carrier layer is partially processed. In this embodiment, a nickel plating layer is used as the release layer. However, for example, a transfer forming material having a similar structure can be obtained even if an organic layer or the like is formed.

In the pattern forming material formed only at the transfer wirings manufactured at this stage, the first metal layer 170 is used.
1 and the metal layer 1703 for forming a wiring pattern through a release layer have excellent adhesiveness even though the adhesive force itself is weak,
Even when the entire metal layer having the three-layer structure was etched, the wiring pattern could be formed without any problem without peeling. On the other hand, the first metal layer 1701 and the second metal layer 1
The adhesive strength with 703 was 40 g / cm, and the peelability was excellent.

Next, a multilayer ceramic chip capacitor 1704 having a plurality of vertical electrodes inside was connected using a conductive adhesive. Chip laminated capacitor 1704 having this structure
Since there were external connection terminals on the upper and lower surfaces, they could be easily mounted on the transfer forming material.

Similarly, the semiconductor device 1705 is also flip-chip mounted on the transfer forming material, and as shown in FIG. 17D, while aligning with the interlayer connection via 1708 formed in the substrate, While heating at 150 ° C. The sheet base material used in this example is the same as in Example 1, and the pressing conditions for embedding are also the same.

The point that the transfer forming material is used in the step of incorporating the chip component is the same as that of the above embodiment, but the transfer forming material including the respective chip components and the transfer forming material 1706 including the semiconductor element 1705 are simultaneously formed on the circuit board. It is characterized in that it is embedded and built in from both upper and lower surfaces of a sheet-like substrate.

According to this manufacturing method, each component-containing layer has one layer.
Although the semiconductor element 1705 is a layer,
Through 708, a structure connected to the chip component 1704 by short wiring could be realized.

As a result, the chip component 17 which is a decap
04 decoupled with the MPU semiconductor element 1703, and was able to exhibit excellent functions at high frequencies.

Also, the sheet-like base material 1 constituting the circuit board
As a result of the transfer of the second metal layer 1703 to the second metal layer 1707, the bonding surface of the first metal layer 1701 and the second metal layer 1703 via the separation layer was easily peeled off, and the second metal layer 1703 was peeled off. Only 1703 could be transferred to the substrate.

In this wiring board 1707, a recess corresponding to the depth at which the first metal layer 1701 was etched was formed, and a component pattern including all the wirings was formed at the bottom of the recess. Accordingly, when another semiconductor bare chip was flip-chip mounted on the surface layer on which the wiring layer of the concave portion was formed, excellent mountability and reliability could be obtained.

The mounting position of each chip component was also accurate, and a circuit board of exactly the same design could be formed by batch transfer. According to the transfer forming material of this example, the bonding between the bumps and the wiring of the semiconductor chip was good, and the capacitor mounted to function as the bypass capacitor of the semiconductor chip also functioned well. Capacitor high temperature load reliability test (125 ° C, 50V, 1000 hours)
Even after the above, the insulation resistance of the dielectric layer of the capacitor did not deteriorate, and an insulation resistance of 10 ⁶ Ω or more could be secured.

[0183]

As described above, in addition to the formation of a fine wiring pattern, the chip component built-in substrate of the present invention mounts and forms chip components such as LCR with solder or conductive adhesive, and collectively forms them. Transfer and built-in, it can be easily and accurately mounted on a substrate. In addition, by configuring chip components suitable for embedding, chip characteristics with strict characteristic specifications can be utilized even after embedding, and since the chip thickness is small even with embedding, the layer thickness is not bulky Since the electrodes are provided on the upper and lower surfaces, mounting is easy and the mounting area is not required.

[Brief description of the drawings]

FIGS. 1 (a) and 1 (b) are cross-sectional views schematically showing a configuration of a chip component built-in substrate according to a conventional embodiment.

FIG. 2 is a cross-sectional view schematically illustrating a configuration of a component-embedded substrate according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a schematic configuration of a component-embedded substrate according to a second embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a schematic configuration of a component-embedded substrate according to a third embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating a schematic configuration of a component-embedded substrate according to a fourth embodiment of the present invention.

FIG. 6 is a cross-sectional view schematically illustrating a configuration of a component-embedded substrate according to a fifth embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating a schematic configuration of a component-embedded substrate according to a sixth embodiment of the present invention.

FIG. 8 is a sectional view showing a schematic configuration of a component-embedded substrate according to a seventh embodiment of the present invention.

FIG. 9 is a cross-sectional view illustrating a schematic configuration of a component-embedded substrate according to an eighth embodiment of the present invention.

FIG. 10 is a sectional view showing a schematic configuration of a component-embedded substrate according to a ninth embodiment of the present invention.

11 (a) to 11 (f) are cross-sectional views schematically showing manufacturing steps of each layer of a multilayer circuit board formed using a conventional transfer component wiring pattern forming material.

FIGS. 12 (a) to (i) show a process for manufacturing a chip component wiring pattern forming material for transfer and a chip component built-in substrate formed using the same in the tenth embodiment and Example 1 of the present invention. Sectional view showing the outline of

FIGS. 13A to 13I are cross-sectional views schematically showing a process for manufacturing a transfer component wiring pattern forming material and a chip component built-in substrate formed using the same according to an eleventh embodiment of the present invention. Figure

FIGS. 14A to 14I are cross-sectional views schematically showing a process for manufacturing a transfer component wiring pattern forming material and a chip component built-in substrate formed using the same according to a twelfth embodiment of the present invention. Figure

FIGS. 15A to 15E are cross-sectional views schematically illustrating a manufacturing process of each layer of a substrate with built-in chip components and a laminating method according to a thirteenth embodiment of the present invention;

FIGS. 16A and 16B are cross-sectional views illustrating a method of laminating each layer of a substrate with built-in chip components according to a fourteenth embodiment of the present invention;

FIGS. 17 (a) to (h) show transfer component wiring pattern forming materials according to a fifteenth embodiment of the present invention and Example 2 of the present invention, and a chip component built-in substrate formed using the same. Sectional view showing the outline of the manufacturing process

[Explanation of symbols]

1106,1206,1301,1406,1504,1701 First metal layer constituting carrier 1208,1302,1407 Release layer 103,203,303,403,503,603,703,803,903,1003,1103,120
3,1303,1403,1503,1612,1703 Second metal layer 101,201,301,401,501,601,701,801,901,1001,1101,120 for forming wiring pattern
1,1306,1401,1501,1605,1706 Sheet base material 102,202,302,402,502,602,702,802,902,1002,1102,120
2,1307,1402,1502,1708 Conductive paste 104,1104 Normal chip component 204,304,1204,1304,1505,1617 Single-layer chip capacitor 1404 Multilayer capacitor with interlayer connection via 407 Interlayer connection via 404 Inner layer multilayer electrode (plane Direction) 403 External connection terminal 1704 Multilayer capacitor with vertical laminated internal electrode 506 Inner layer laminated electrode (vertical direction) 305,306,403,507,508,605,608,707,1205 External connection terminal electrode 206,504,608,707,906,1006,1207 Wiring layer 1510,1610, connecting internal chip parts and interlayer connection via 1705 Semiconductor chip 1509,1609 Underfill

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Shingo Komatsu 1006 Kazuma Kadoma, Osaka Pref. Matsushita Electric Industrial Co., Ltd. (72) Inventor Seiichi Nakatani 1006 Kadoma Kadoma Kadoma, Osaka Pref. Matsushita Electric Industrial Co., Ltd. F term (reference) 5E336 AA08 BB03 CC32 CC42 CC49 EE03 EE08 GG14 GG30 5E343 AA07 AA17 AA24 BB24 BB25 BB54 BB72 DD32 DD56 GG20 5E346 CC09 CC16 CC32 CC39 CC40 DD03 DD24 FF18 FF45 GG15 HH06

Claims (28)

[Claims] 1. An electrically insulated wiring board having electrodes formed on at least one of upper and lower surfaces and having at least one chip component built therein, wherein the thickness t of the chip passive element is not more than a length L and a width W. And the chip component has an external connection electrode on at least one of surfaces corresponding to upper and lower surfaces with respect to a thickness direction of the chip component, and wiring formed on the external connection electrode and the electrically insulating multilayer wiring board. A wiring board with a built-in chip component, wherein the patterns are electrically connected. 2. The wiring board with a built-in chip component according to claim 1, wherein an active element including a semiconductor element is further incorporated in the electrically insulating substrate. 3. The wiring board with a built-in chip component according to claim 1, wherein said chip component is a single-layer chip capacitor having electrodes formed on both upper and lower surfaces. 4. The wiring board with a built-in chip component according to claim 3, wherein the single-layer capacitor has a plurality of electrodes formed on both upper and lower surfaces thereof and can extract a plurality of capacitances. 5. The multilayer wiring board with a built-in chip component according to claim 1, wherein said chip component is a chip passive element having a multilayer structure having a passive element formed of a conductor pattern therein. 6. The wiring board with a built-in chip component according to claim 1, wherein said chip component is a multilayer chip capacitor. 7. A multilayer chip capacitor comprising: a plurality of dielectric layers made of ceramics; an internal electrode formed inside the dielectric layer; an internal electrode; and an external terminal electrode formed on an upper surface or a lower surface. The wiring board with a built-in chip component according to claim 6, further comprising a via-hole connecting portion penetrating the dielectric layer so as to be connected. 8. The multilayer chip capacitor according to claim 1, further comprising: a plurality of internal electrodes arranged so as to overlap with a lower surface of the ceramic sintered body via a ceramic layer along a direction perpendicular to the lower surface of the ceramic sintered body. In order to take out the capacitance, a part of the end circle is exposed on the upper surface and the lower surface of the ceramic sintered body, and a first external electrode formed on the upper surface of the ceramic sintered body, and a ceramic sintered body. 6. The wiring board with a built-in chip component according to claim 5, further comprising at least one second external electrode formed on the lower surface of the chip and capable of extracting capacitance. 9. The built-in chip component according to claim 8, wherein the multilayer chip capacitor has a plurality of first external electrodes and a plurality of second external electrodes, and a plurality of capacitances can be taken out. Wiring board. 10. The chip passive element has a thickness of 0.1 mm.
2. The multilayer wiring board with a built-in chip component according to claim 1, wherein the thickness is not less than 0.5 mm. 11. The method according to claim 1, wherein the electrically insulating substrate contains an inorganic filler and a thermosetting resin composition, has at least one through hole, and the through hole is filled with a conductive paste. The wiring board with a built-in chip component as described. 12. The method according to claim 12, wherein the inorganic filler is Al ₂ O ₃ , Mg.
At least one filler selected from O, BN, AlN and SiO ₂ , wherein the proportion of the inorganic filler is 70 to 95% by weight and the proportion of the thermosetting resin composition is 5 to 30% by weight. A multilayer wiring board with a built-in chip component according to claim 11. 13. The reinforcing material selected from the group consisting of a woven fabric of glass fiber, a non-woven fabric of glass fiber, a woven fabric of heat-resistant organic fiber, and a non-woven fabric of heat-resistant organic fiber, wherein the electrically insulating substrate is a reinforcing material. Made of a material impregnated with a thermosetting resin composition, having at least one through hole,
2. A conductive paste is filled in the through hole.
The wiring board with a built-in chip component according to 1. 14. The wiring board with a built-in chip component according to claim 1, wherein said chip passive element is mounted with a conductive adhesive. 15. The multilayer wiring board with a built-in chip component including the semiconductor element, wherein the wiring layer with a built-in chip capacitor and the semiconductor element are decoupled and connected via vias or bumps. 7. The wiring board with a built-in chip component according to 6. 16. A multilayer wiring board with a built-in chip component including a semiconductor element, wherein the wiring layer with a built-in chip capacitor and the wiring layer with the semiconductor element built therein are decoupled and connected via vias or bumps. The wiring board with a built-in chip component according to claim 15 having a structure. 17. A wiring board containing a semiconductor element and a chip component, wherein the chip capacitor and the semiconductor element are built in the same layer, and the respective elements are connected by performing decoupling via or bumps. The wiring board with a built-in chip component according to claim 15. 18. A thickness t of the chip passive element is equal to a length L.
And the thickness t of the chip passive element.
Is 5 to 90% of the width W. 19. A chip passive element is formed by directly attaching a metal layer to a carrier layer via a release layer and processing it into a wiring pattern shape to form a transfer wiring pattern, and aligning the transfer wiring pattern shape with the carrier layer. Using the mounted component wiring pattern forming material for transfer, disposing the component wiring pattern so that the side on which the component wiring pattern is formed is in contact with at least one surface of the sheet-like base material constituting the electrically insulating substrate, and these are adhered. A method of manufacturing a wiring board with a built-in chip component, comprising: transferring the wiring pattern metal layer for transfer from a carrier layer, and transferring the component wiring pattern including at least the metal layer and the chip component to the sheet-like base material. . 20. The transfer wiring pattern, wherein (a) the carrier layer is composed of a first metal layer, and the same component as the first metal layer is formed on the first metal layer via a release layer. Forming a second metal layer containing a metal of a three-layer structure,
20. The method according to claim 19, further comprising: (b) processing only the second metal layer into a wiring pattern shape. 21. The transfer wiring pattern, wherein (a) the carrier layer is formed of a first metal layer, and the same component as the first metal layer is formed on the first metal layer via a release layer. Forming a second metal layer containing a metal of a three-layer structure,
(B) processing the second metal layer, the release layer, and the surface layer of the first metal layer up to an arbitrary depth into a wiring pattern shape to form an uneven portion on the surface layer of the first metal layer; 20. The method for manufacturing a wiring board with built-in chip components according to claim 19, comprising: 22. (a) The carrier layer is composed of a first metal layer, and a second metal layer is directly adhered on the first metal layer and processed into a wiring pattern shape to form a transfer wiring pattern. And (b) mounting and forming the chip component pattern while aligning with the wiring pattern shape, using the component wiring pattern forming material for transfer, the component wiring pattern is formed. Side is placed so as to be in contact with at least one surface of the sheet-shaped base material constituting the electrically insulating substrate, these are bonded and embedded,
(C) separating the transfer wiring pattern metal layer including the second metal layer from the first metal layer, and transferring the component wiring pattern including at least the second metal layer and the component pattern to the sheet-like base material; A method for manufacturing a wiring board with a built-in chip component, the method including: 23. A method for forming a wiring pattern by directly adhering the second metal layer by a plating method.
3. The method for manufacturing a wiring board with a built-in chip component according to item 2. 24. The method according to claim 19, wherein the chip component is mounted on the transfer wiring pattern using a conductive adhesive.
24. The method of manufacturing a wiring board with a built-in chip component according to any one of 23. 25. A wiring board with a built-in chip component formed by the method according to claim 19.
A method for manufacturing a wiring board with a built-in chip component, which is further laminated into two or more layers by batch lamination. 26. A metal layer is directly attached to a carrier layer via a release layer, processed into a wiring pattern shape, a transfer wiring pattern is formed, and a semiconductor element is mounted while being aligned with the transfer wiring pattern shape. Using the transfer component wiring pattern forming material obtained, arranged such that the metal layer side on which the element wiring pattern is formed is in contact with at least one surface of the sheet-like base material constituting the electrically insulating substrate, and Adhering, separating the transfer wiring pattern metal layer from the carrier layer, and transferring the component wiring pattern including at least the metal layer and the semiconductor element to the sheet-like base material; and the chip component. A chip part connected to a built-in wiring board via a via or a bump to obtain a decoupled chip part. Method of manufacturing a built-in wiring board. 27. A wiring board of a B-stage (semi-cured) via vias, wherein the wiring board with a built-in semiconductor and the substrate with a built-in chip component are prepared in a state of being previously cured to a C-stage (completely cured). 27. The method of manufacturing a wiring board with a built-in chip component according to claim 26, wherein the semiconductor device and the chip component are connected with each other by stacking. 28. A metal layer is directly attached to a carrier layer via a release layer, processed into a wiring pattern shape, a transfer wiring pattern is formed, and a semiconductor element is mounted while being aligned with the transfer wiring pattern shape. The transferred component wiring pattern forming material, and a metal layer is directly adhered to the carrier layer via a release layer, processed into a wiring pattern shape, a transfer wiring pattern is formed, and the transfer wiring pattern shape is aligned. Using a transfer component wiring pattern forming material on which chip components are mounted, make sure that the side on which these element wiring patterns are formed is in contact with the front and back surfaces of the sheet-like base material constituting the electrically insulating substrate. Arrange them, bond and embed them, peel off the transfer wiring pattern metal layer from the carrier layer, and attach at least the metal layer and A wiring board with a built-in semiconductor on which the component wiring pattern including a conductive element is transferred and the wiring board with a built-in chip component are connected via vias or bumps to obtain a decoupled chip component. Manufacturing method of wiring board with built-in chip components.