WO2023095402A1 - Electronic component-embedded substrate - Google Patents

Electronic component-embedded substrate Download PDF

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Publication number
WO2023095402A1
WO2023095402A1 PCT/JP2022/031835 JP2022031835W WO2023095402A1 WO 2023095402 A1 WO2023095402 A1 WO 2023095402A1 JP 2022031835 W JP2022031835 W JP 2022031835W WO 2023095402 A1 WO2023095402 A1 WO 2023095402A1
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Prior art keywords
electronic component
insulating layer
thermal expansion
expansion coefficient
embedded
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PCT/JP2022/031835
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French (fr)
Japanese (ja)
Inventor
玲央 花田
和俊 露谷
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Tdk株式会社
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Publication of WO2023095402A1 publication Critical patent/WO2023095402A1/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits

Definitions

  • the present invention relates to an electronic component embedded substrate, and more particularly to an electronic component embedded substrate having a structure in which electronic components are embedded in a plurality of insulating layers.
  • Patent documents 1 and 2 disclose electronic component built-in substrates having a structure in which electronic components such as semiconductor ICs are embedded in a plurality of insulating layers.
  • an object of the present invention is to suppress the occurrence of warpage in an electronic component built-in substrate having a structure in which electronic components are embedded in a plurality of insulating layers.
  • An electronic component-embedded substrate is an electronic component-embedded substrate having a structure in which a plurality of conductor layers and a plurality of insulating layers are alternately laminated, wherein the plurality of insulating layers comprises one or more first electrons.
  • a thermal expansion coefficient adjusting member smaller than the total volume and having a thermal expansion coefficient different from that of the insulating material forming the first insulating layer is further embedded in the first insulating layer.
  • the thermal expansion coefficient adjusting member embedded in the first insulating layer can suppress warping caused by the difference between the total volume of the first electronic component and the total volume of the second electronic component. becomes.
  • the first electronic component has a smaller thermal expansion coefficient than the insulating material forming the first insulating layer
  • the second electronic component has a thermal expansion coefficient smaller than that of the insulating material forming the second insulating layer.
  • the thermal expansion coefficient adjustment member may have a smaller thermal expansion coefficient than the insulating material forming the first insulating layer. According to this, since the thermal expansion coefficient of the entire first insulating layer including the first electronic component and the thermal expansion coefficient adjusting member is reduced, the thermal expansion of the entire second insulating layer including the second electronic component is reduced. It is possible to approximate the coefficient.
  • the first electronic component and the second electronic component may overlap in the stacking direction. According to this, it is possible to reduce the planar size of the electronic component built-in board.
  • the thermal expansion coefficient adjusting member may be a core material containing glass cloth. According to this, it is possible to increase the mechanical strength while suppressing the warp of the electronic component built-in board.
  • the electronic component built-in substrate may further include via conductors penetrating through the first insulating layer and the core material, or may further comprise via conductors penetrating through the first insulating layer, the core material being the via conductor. may be arranged to avoid the position where is provided.
  • the former makes it possible to improve the connection reliability of via conductors, and the latter makes it easier to form vias for embedding via conductors.
  • the thickness of the thermal expansion coefficient adjusting member may be thinner than the thickness of the first electronic component. According to this, the thermal expansion coefficient adjusting member does not increase the overall thickness.
  • the coefficient of thermal expansion of the first insulating layer and the coefficient of thermal expansion of the second insulating layer may differ from each other. According to this, it is possible to suppress the warp caused by the difference between the total volume of the first electronic component and the total volume of the second electronic component due to the difference in thermal expansion coefficient between the first and second insulating layers. Become.
  • the plurality of insulating layers include a third insulating layer that covers the first insulating layer from the side opposite to the second insulating layer, and a second insulating layer that covers the second insulating layer from the side opposite to the first insulating layer.
  • a covering fourth insulating layer may be further included, and the coefficient of thermal expansion of the third insulating layer and the coefficient of thermal expansion of the fourth insulating layer may be different from each other. According to this, the difference in thermal expansion coefficient between the third and fourth insulating layers makes it possible to suppress the warpage caused by the difference between the total volume of the first electronic component and the total volume of the second electronic component. Become.
  • FIG. 1 is a schematic cross-sectional view for explaining the structure of an electronic component built-in board 1 according to a first embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional view for explaining the structure of the electronic component built-in substrate 2 according to the second embodiment of the present invention.
  • FIG. 3 is a schematic cross-sectional view for explaining the structure of an electronic component built-in substrate 3 according to a third embodiment of the present invention.
  • FIG. 4 is a schematic cross-sectional view for explaining the structure of an electronic component built-in board 4 according to a fourth embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional view for explaining the structure of an electronic component built-in substrate 5 according to a fifth embodiment of the present invention.
  • FIG. 1 is a schematic cross-sectional view for explaining the structure of an electronic component built-in board 1 according to a first embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional view for explaining the structure of the electronic component built-in substrate 2 according to
  • FIG. 6 is a schematic cross-sectional view for explaining the structure of an electronic component built-in board 6 according to a sixth embodiment of the present invention.
  • FIG. 7 is a schematic cross-sectional view for explaining the structure of an electronic component built-in board 7 according to a seventh embodiment of the present invention.
  • FIG. 8 is a schematic cross-sectional view for explaining the structure of an electronic component built-in substrate 8 according to an eighth embodiment of the present invention.
  • FIG. 9 is a schematic cross-sectional view for explaining the structure of an electronic component built-in substrate 9 according to a ninth embodiment of the present invention.
  • FIG. 1 is a schematic cross-sectional view for explaining the structure of an electronic component built-in board 1 according to a first embodiment of the present invention.
  • the electronic component built-in substrate 1 has a structure in which five conductor layers L1 to L5 and four insulating layers 11 to 14 are alternately laminated in the lamination direction. are doing.
  • the insulating layer 11 is positioned between the conductor layers L1 and L2
  • the insulating layer 12 is positioned between the conductive layers L2 and L3
  • the insulating layer 13 is positioned between the conductive layers L3 and L4
  • the insulating layer 14 is positioned between the conductor layers L3 and L4.
  • the insulating layers 11 to 14 are all interlayer films having conductor layers on the front and back sides, and in that sense the solder resists 21 and 22 do not correspond to insulating layers.
  • the conductor layer L1 is located on the uppermost layer, and part of it is covered with a solder resist 21.
  • the exposed portion of the conductor layer L1 that is not covered with the solder resist 21 constitutes the terminal electrode E1 positioned on one surface 1a of the substrate 1 with a built-in electronic component.
  • the conductor layer L5 is located at the bottom layer and partly covered with the solder resist 22 .
  • the exposed portion of the conductor layer L5 not covered with the solder resist 22 constitutes the terminal electrode E2 located on the other surface 1b side of the electronic component built-in substrate 1. As shown in FIG.
  • Electronic components such as a semiconductor IC and passive components may be mounted on the surface 1a of the electronic component built-in substrate 1, or may be used as a mounting surface for another circuit board (not shown).
  • the surface 1b of the electronic component built-in board 1 may be used as a mounting surface for another circuit board (not shown), or electronic components such as semiconductor ICs and passive components (not shown) may be mounted thereon.
  • two conductor layers adjacent in the stacking direction are connected to each other by via conductors.
  • the conductor pattern 31 located on the conductor layer L1 and the conductor pattern 32 located on the conductor layer L2 are connected through the via conductors 41 provided through the insulating layer 11 .
  • the conductor pattern 32 located on the conductor layer L2 and the conductor pattern 33 located on the conductor layer L3 are connected through the via conductors 42 provided through the insulating layer 12 .
  • the conductor pattern 33 located on the conductor layer L3 and the conductor pattern 34 located on the conductor layer L4 are connected through via conductors 43 that penetrate through the insulating layer 13 .
  • the conductor pattern 34 located on the conductor layer L4 and the conductor pattern 35 located on the conductor layer L5 are connected through via conductors 44 that penetrate the insulating layer 14 .
  • the insulating layer 12 is composed of two insulating layers 12a and 12b, and an electronic component 51 is embedded so as to be sandwiched between the two layers.
  • the insulating layer 13 is composed of two insulating layers 13a and 13b, and an electronic component 52 is embedded so as to be sandwiched between the two layers.
  • Terminal electrodes provided on electronic component 51 are connected to conductor pattern 32 located on conductor layer L2 through via conductors 45 .
  • Terminal electrodes provided on electronic component 52 are connected to conductor pattern 33 located on conductor layer L3 through via conductors 46 .
  • the insulating layers 12a and 13a function as adhesive layers when the electronic components 51 and 52 are mounted face-up in the manufacturing process of the electronic component built-in substrate 1 .
  • the insulating layers 12b and 13b function as embedding layers for embedding the electronic components 51 and 52 in the manufacturing process of the electronic component built-in substrate 1 .
  • the electronic components 51 and 52 overlap in the stacking direction, thereby reducing the planar size of the electronic component built-in board 1 .
  • the types of the electronic components 51 and 52 are not particularly limited, and they may be semiconductor ICs or passive components such as capacitors, inductors, and filters.
  • the thickness of the chip may be reduced to 200 ⁇ m or less, for example, about 50 to 100 ⁇ m. Since the electronic components 51 and 52 are mainly made of an inorganic material such as silicon, they have a smaller coefficient of thermal expansion than the insulating layers 11 to 14 whose main component is a resin material.
  • the volume of the electronic component 52 embedded in the insulating layer 13 is smaller than the volume of the electronic component 51 embedded in the insulating layer 12 .
  • a core material 60 containing glass cloth is embedded in the insulating layer 13 .
  • the core material 60 Since the core material 60 has a smaller thermal expansion coefficient than the insulating material forming the insulating layer 13 , it functions as a thermal expansion coefficient adjusting member that reduces the thermal expansion coefficient of the entire insulating layer 13 including the electronic component 52 and the core material 60 .
  • the insulating layer 12 does not have a core material with a low coefficient of thermal expansion embedded therein. As a result, the difference between the thermal expansion coefficient of the entire insulating layer 12 including the electronic component 51 and the thermal expansion coefficient of the entire insulating layer 13 including the electronic component 52 and the core material 60 is reduced. Warping that occurs can be suppressed.
  • the core material 60 does not exist at the position overlapping the electronic component 52 and its surroundings, the electronic component 52 and the core material 60 do not interfere with each other. Furthermore, if the thickness of the core material 60 is thinner than the thickness of the electronic component 52, the thickness of the whole is not increased by the core material 60. FIG.
  • the core material 60 with a small thermal expansion coefficient is embedded in the insulating layer 13, heat It is possible to suppress the warping of the electronic component built-in substrate 1 due to the difference in expansion coefficient.
  • the core material 60 is provided on almost the entire surface of the insulating layer 13, the mechanical strength of the electronic component built-in substrate 1 is also enhanced.
  • the via conductor 43 is provided through the core material 60, the inner wall of the via is roughened by the glass cloth. As a result, the adhesion between the via conductors 43 and the insulating layer 13 is improved, and the connection reliability of the via conductors 43 is also improved.
  • the insulating material forming the insulating layer 12 has a higher thermal conductivity than the insulating material forming the insulating layer 13 .
  • a material having a large coefficient of expansion may be used.
  • the content of the inorganic filler in the insulating layer 12 should be less than the content of the inorganic filler in the insulating layer 13 .
  • a material having a larger thermal expansion coefficient than the insulating material forming the insulating layer 14 may be used as the insulating material forming the insulating layer 11. Even in this case, since the thermal expansion coefficient on the surface 1a side increases, it is possible to ensure a balance between the thermal expansion coefficient on the surface 1a side and the thermal expansion coefficient on the surface 1b side.
  • FIG. 2 is a schematic cross-sectional view for explaining the structure of the electronic component built-in substrate 2 according to the second embodiment of the present invention.
  • the volume of the electronic component 51 embedded in the insulating layer 12 is larger than the volume of the electronic component 52 embedded in the insulating layer 13. It differs from the electronic component built-in substrate 1 according to the first embodiment in that it is small and a core material 60 containing glass cloth is embedded in the insulating layer 12 . Since other basic configurations are the same as those of the electronic component built-in board 1 according to the first embodiment, the same elements are denoted by the same reference numerals, and overlapping descriptions are omitted.
  • the core material 60 is not embedded in the insulating layer 13, and the insulation By embedding the core material 60 in the layer 12, it is possible to suppress the warping of the electronic component built-in substrate 2 due to the difference in thermal expansion coefficient.
  • FIG. 3 is a schematic cross-sectional view for explaining the structure of an electronic component built-in substrate 3 according to a third embodiment of the present invention.
  • the electronic component embedded substrate 3 according to the third embodiment differs from the electronic component embedded substrate 1 according to the first embodiment in that a plurality of electronic components 51 are embedded in the insulating layer 12. do. Since other basic configurations are the same as those of the electronic component built-in board 1 according to the first embodiment, the same elements are denoted by the same reference numerals, and overlapping descriptions are omitted.
  • FIG. 4 is a schematic cross-sectional view for explaining the structure of an electronic component built-in board 4 according to a fourth embodiment of the present invention.
  • the electronic component embedded substrate 4 according to the fourth embodiment differs from the electronic component embedded substrate 3 according to the third embodiment in that dummy electronic components 53 are embedded in the insulating layer 13. do. Since other basic configurations are the same as those of the electronic component built-in board 3 according to the third embodiment, the same elements are denoted by the same reference numerals, and overlapping descriptions are omitted.
  • the electronic component 53 is a dummy electronic component that does not function as a circuit, and plays the role of reducing the thermal expansion coefficient of the insulating layer 13 exclusively. Therefore, the electronic component 53 may not be electrically connected to any conductor pattern, and the conductor pattern may be connected for the purpose of dissipating heat to the electronic component 53 .
  • two electronic components 51 are embedded in the insulating layer 12, and one electronic component 52 and one dummy electronic component 53 are embedded in the insulating layer 13. If the individual volumes of 51 to 53 are substantially the same, it is possible to suppress warpage of electronic component built-in substrate 4 due to differences in thermal expansion coefficients.
  • the thermal expansion coefficient adjusting member is the core material 60 made of glass cloth or the like. Also, if a defective product that should be discarded is used as the dummy electronic component 53, it is possible to reduce the manufacturing cost.
  • FIG. 5 is a schematic cross-sectional view for explaining the structure of an electronic component built-in substrate 5 according to a fifth embodiment of the present invention.
  • the electronic component according to the first embodiment is different in that the core material 60 is arranged to avoid the positions where the via conductors 43 are provided. It is different from the built-in substrate 1. Since other basic configurations are the same as those of the electronic component built-in board 1 according to the first embodiment, the same elements are denoted by the same reference numerals, and overlapping descriptions are omitted.
  • the core material 60 is arranged to avoid the position where the via conductor 43 is provided, processing becomes easy when the via for embedding the via conductor 43 is formed by laser processing or the like. .
  • FIG. 6 is a schematic cross-sectional view for explaining the structure of an electronic component built-in board 6 according to a sixth embodiment of the present invention.
  • the electronic component built-in board 6 according to the sixth embodiment differs from the electronic component built-in board 1 according to the first embodiment in that the core member 60 is arranged only around the electronic component 52. differ. Since other basic configurations are the same as those of the electronic component built-in board 1 according to the first embodiment, the same elements are denoted by the same reference numerals, and overlapping descriptions are omitted.
  • the core material 60 it is not necessary to arrange the core material 60 on almost the entire surface, and the core material 60 may be arranged only around the electronic component 52 as long as the warping of the whole is suppressed.
  • core material 60 is preferably arranged so as to overlap electronic component 51 . According to this, it is possible to substantially match the planar position where the thermal expansion coefficient of the insulating layer 13 is reduced with the electronic component 51 .
  • a thermal expansion coefficient adjusting member made of an inorganic material such as silicon may be used instead of the core material 60.
  • FIG. 7 is a schematic cross-sectional view for explaining the structure of an electronic component built-in board 7 according to a seventh embodiment of the present invention.
  • the electronic component built-in board 7 according to the seventh embodiment differs from the electronic component built-in board 1 according to the first embodiment in that a plurality of dummy chips 61 are arranged on the insulating layer 13. do. Since other basic configurations are the same as those of the electronic component built-in substrate 1 according to the first embodiment, the same elements are denoted by the same reference numerals, and overlapping descriptions are omitted.
  • the dummy chips 61 are thermal expansion coefficient adjusting members made of an inorganic material such as silicon, and the number of dummy chips 61 is determined so that the thermal expansion coefficient of the insulating layer 13 has a target value. As illustrated in this embodiment, it is also possible to reduce the thermal expansion coefficient of the insulating layer 13 by embedding a plurality of dummy chips 61 in the insulating layer 13 . According to this, the thermal expansion coefficient of the insulating layer 13 can be finely adjusted by the number of dummy chips 61 .
  • FIG. 8 is a schematic cross-sectional view for explaining the structure of an electronic component built-in substrate 8 according to an eighth embodiment of the present invention.
  • the electronic component built-in substrate 8 according to the eighth embodiment differs from the electronic component built-in substrate according to the first embodiment in that the insulating layer 12 is also embedded with a core material 62 containing glass cloth. different from 1. Since other basic configurations are the same as those of the electronic component built-in board 1 according to the first embodiment, the same elements are denoted by the same reference numerals, and overlapping descriptions are omitted.
  • the area of the core material 62 embedded in the insulating layer 12 is smaller than the area of the core material 60 embedded in the insulating layer 13 . Therefore, the degree to which the coefficient of thermal expansion of the insulating layer 12 is lowered by the core member 62 is smaller than the degree to which the coefficient of thermal expansion of the insulating layer 13 is lowered by the core member 60 .
  • a core material may be embedded in both the insulating layers 12 and 13 as illustrated in this embodiment. In the example shown in FIG. 8, the core material 62 is locally embedded in the insulating layer 12, but the core material 62 thinner than the core material 60 may be embedded almost entirely.
  • FIG. 9 is a schematic cross-sectional view for explaining the structure of an electronic component built-in substrate 9 according to a ninth embodiment of the present invention.
  • a core material 60 is provided with a locally thin concave portion 60a, and an electronic component 52 is placed in the concave portion 60a. It is different from the electronic component built-in board 1 according to the first embodiment in this respect. Since other basic configurations are the same as those of the electronic component built-in board 1 according to the first embodiment, the same elements are denoted by the same reference numerals, and overlapping descriptions are omitted.
  • the core material 60 and the electronic component 52 may overlap.
  • the concave portion 60a is provided in the portion that overlaps with the electronic component 52, it is possible to suppress an increase in the overall thickness.
  • the coefficient of thermal expansion of the electronic components 51 and 52 is smaller than the coefficient of thermal expansion of the insulating material forming the insulating layers 12 and 13 has been described.
  • the coefficient may be larger than the thermal expansion coefficient of the insulating material forming the insulating layers 12 and 13 .
  • a material having a larger thermal expansion coefficient than the insulating material forming the insulating layer 12 may be used as the thermal expansion coefficient adjusting member.

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  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

[Problem] To suppress the occurrence of warpage in an electronic component-embedded substrate having a structure in which electronic components are embedded in a plurality of insulating layers. [Solution] This electronic component-embedded substrate 1 has a structure in which conductive layers L1-L5 and insulating layers 11-14 are alternately stacked. The insulating layers 11-14 include: an insulating layer 13 in which an electronic component 52 is embedded; and an insulating layer 12 in which an electronic component 51 is embedded. The total volume of the electronic component 52 is smaller than the total volume of the electronic component 51. In the insulating layer 13, a core material 60 is further embedded which has a thermal expansion coefficient different from that of the insulating material constituting the insulating layer 13 and functions as a thermal expansion coefficient adjustment member. Accordingly, the core material 60 makes it possible to suppress warpage caused by the difference between the total volume of the electronic component 51 and the total volume of the electronic component 52.

Description

電子部品内蔵基板Substrate with built-in electronic components
　本発明は電子部品内蔵基板に関し、特に、複数の絶縁層に電子部品が埋め込まれた構造を有する電子部品内蔵基板に関する。 The present invention relates to an electronic component embedded substrate, and more particularly to an electronic component embedded substrate having a structure in which electronic components are embedded in a plurality of insulating layers.
　特許文献１及び２には、複数の絶縁層に半導体ＩＣなどの電子部品が埋め込まれた構造を有する電子部品内蔵基板が開示されている。 Patent documents 1 and 2 disclose electronic component built-in substrates having a structure in which electronic components such as semiconductor ICs are embedded in a plurality of insulating layers.
特開２０１７－１９１８３１号公報JP 2017-191831 A 特開２０１６－２０８３６７号公報JP 2016-208367 A
　半導体ＩＣなどの電子部品は、絶縁層を構成する樹脂などの絶縁材料に対して熱膨張係数が大きく異なっていることから、複数の絶縁層に埋め込まれた電子部品のボリュームが異なると、表裏における熱膨張係数の差に起因して電子部品内蔵基板に反りが生じるという問題があった。 Since electronic parts such as semiconductor ICs have greatly different coefficients of thermal expansion from insulating materials such as resins that make up the insulating layers, if the volumes of the electronic parts embedded in the insulating layers differ, There is a problem that the electronic component built-in board warps due to the difference in thermal expansion coefficient.
　したがって、本発明は、複数の絶縁層に電子部品が埋め込まれた構造を有する電子部品内蔵基板において、反りの発生を抑えることを目的とする。 Therefore, an object of the present invention is to suppress the occurrence of warpage in an electronic component built-in substrate having a structure in which electronic components are embedded in a plurality of insulating layers.
　本発明による電子部品内蔵基板は、複数の導体層と複数の絶縁層が交互に積層された構造を有する電子部品内蔵基板であって、複数の絶縁層は、１又は２以上の第１の電子部品が埋め込まれた第１の絶縁層と、１又は２以上の第２の電子部品が埋め込まれた第２の絶縁層とを含み、第１の電子部品の合計体積は第２の電子部品の合計体積よりも小さく、第１の絶縁層には、第１の絶縁層を構成する絶縁材料とは熱膨張係数の異なる熱膨張係数調整部材がさらに埋め込まれていることを特徴とする。 An electronic component-embedded substrate according to the present invention is an electronic component-embedded substrate having a structure in which a plurality of conductor layers and a plurality of insulating layers are alternately laminated, wherein the plurality of insulating layers comprises one or more first electrons. a first insulating layer embedded with a component and a second insulating layer embedded with one or more second electronic components, wherein the total volume of the first electronic component is that of the second electronic component A thermal expansion coefficient adjusting member smaller than the total volume and having a thermal expansion coefficient different from that of the insulating material forming the first insulating layer is further embedded in the first insulating layer.
　本発明によれば、第１の絶縁層に埋め込まれた熱膨張係数調整部材によって、第１の電子部品の合計体積と第２の電子部品の合計体積の差に起因する反りを抑えることが可能となる。 According to the present invention, the thermal expansion coefficient adjusting member embedded in the first insulating layer can suppress warping caused by the difference between the total volume of the first electronic component and the total volume of the second electronic component. becomes.
　本発明において、第１の電子部品は第１の絶縁層を構成する絶縁材料よりも熱膨張係数が小さく、第２の電子部品は第２の絶縁層を構成する絶縁材料よりも熱膨張係数が小さく、熱膨張係数調整部材は第１の絶縁層を構成する絶縁材料よりも熱膨張係数が小さくても構わない。これによれば、第１の電子部品及び熱膨張係数調整部材を含む第１の絶縁層全体の熱膨張係数が低下することから、第２の電子部品を含む第２の絶縁層全体の熱膨張係数に近づけることが可能となる。 In the present invention, the first electronic component has a smaller thermal expansion coefficient than the insulating material forming the first insulating layer, and the second electronic component has a thermal expansion coefficient smaller than that of the insulating material forming the second insulating layer. The thermal expansion coefficient adjustment member may have a smaller thermal expansion coefficient than the insulating material forming the first insulating layer. According to this, since the thermal expansion coefficient of the entire first insulating layer including the first electronic component and the thermal expansion coefficient adjusting member is reduced, the thermal expansion of the entire second insulating layer including the second electronic component is reduced. It is possible to approximate the coefficient.
　本発明において、第１の電子部品と第２の電子部品が積層方向に重なりを有していても構わない。これによれば、電子部品内蔵基板の平面サイズを小型化することが可能となる。 In the present invention, the first electronic component and the second electronic component may overlap in the stacking direction. According to this, it is possible to reduce the planar size of the electronic component built-in board.
　本発明において、熱膨張係数調整部材はガラスクロスを含む芯材であっても構わない。これによれば、電子部品内蔵基板の反りを抑えつつ、機械的強度を高めることが可能となる。この場合、電子部品内蔵基板は、第１の絶縁層及び芯材を貫通するビア導体をさらに備えていても構わないし、第１の絶縁層を貫通するビア導体をさらに備え、芯材はビア導体が設けられた位置を避けて配置されていても構わない。前者によればビア導体の接続信頼性を高めることができ、後者によればビア導体を埋め込むためのビアの形成が容易となる。 In the present invention, the thermal expansion coefficient adjusting member may be a core material containing glass cloth. According to this, it is possible to increase the mechanical strength while suppressing the warp of the electronic component built-in board. In this case, the electronic component built-in substrate may further include via conductors penetrating through the first insulating layer and the core material, or may further comprise via conductors penetrating through the first insulating layer, the core material being the via conductor. may be arranged to avoid the position where is provided. The former makes it possible to improve the connection reliability of via conductors, and the latter makes it easier to form vias for embedding via conductors.
　本発明において、熱膨張係数調整部材の厚さは、第１の電子部品の厚さよりも薄くても構わない。これによれば、熱膨張係数調整部材によって全体の厚さが増加することがない。 In the present invention, the thickness of the thermal expansion coefficient adjusting member may be thinner than the thickness of the first electronic component. According to this, the thermal expansion coefficient adjusting member does not increase the overall thickness.
　本発明において、第１の絶縁層の熱膨張係数と第２の絶縁層の熱膨張係数が互いに異なっていても構わない。これによれば、第１及び第２の絶縁層の熱膨張係数の差によって、第１の電子部品の合計体積と第２の電子部品の合計体積の差に起因する反りを抑えることが可能となる。 In the present invention, the coefficient of thermal expansion of the first insulating layer and the coefficient of thermal expansion of the second insulating layer may differ from each other. According to this, it is possible to suppress the warp caused by the difference between the total volume of the first electronic component and the total volume of the second electronic component due to the difference in thermal expansion coefficient between the first and second insulating layers. Become.
　本発明において、複数の絶縁層は、第１の絶縁層を第２の絶縁層とは反対側から覆う第３の絶縁層と、第２の絶縁層を第１の絶縁層とは反対側から覆う第４の絶縁層とをさらに含み、第３の絶縁層の熱膨張係数と第４の絶縁層の熱膨張係数が互いに異なっていても構わない。これによれば、第３及び第４の絶縁層の熱膨張係数の差によって、第１の電子部品の合計体積と第２の電子部品の合計体積の差に起因する反りを抑えることが可能となる。 In the present invention, the plurality of insulating layers include a third insulating layer that covers the first insulating layer from the side opposite to the second insulating layer, and a second insulating layer that covers the second insulating layer from the side opposite to the first insulating layer. A covering fourth insulating layer may be further included, and the coefficient of thermal expansion of the third insulating layer and the coefficient of thermal expansion of the fourth insulating layer may be different from each other. According to this, the difference in thermal expansion coefficient between the third and fourth insulating layers makes it possible to suppress the warpage caused by the difference between the total volume of the first electronic component and the total volume of the second electronic component. Become.
　このように、本発明によれば、複数の絶縁層に電子部品が埋め込まれた構造を有する電子部品内蔵基板において、反りの発生を抑えることが可能となる。 Thus, according to the present invention, it is possible to suppress the occurrence of warpage in an electronic component built-in substrate having a structure in which electronic components are embedded in a plurality of insulating layers.
図１は、本発明の第１の実施形態による電子部品内蔵基板１の構造を説明するための模式的な断面図である。FIG. 1 is a schematic cross-sectional view for explaining the structure of an electronic component built-in board 1 according to a first embodiment of the present invention. 図２は、本発明の第２の実施形態による電子部品内蔵基板２の構造を説明するための模式的な断面図である。FIG. 2 is a schematic cross-sectional view for explaining the structure of the electronic component built-in substrate 2 according to the second embodiment of the present invention. 図３は、本発明の第３の実施形態による電子部品内蔵基板３の構造を説明するための模式的な断面図である。FIG. 3 is a schematic cross-sectional view for explaining the structure of an electronic component built-in substrate 3 according to a third embodiment of the present invention. 図４は、本発明の第４の実施形態による電子部品内蔵基板４の構造を説明するための模式的な断面図である。FIG. 4 is a schematic cross-sectional view for explaining the structure of an electronic component built-in board 4 according to a fourth embodiment of the present invention. 図５は、本発明の第５の実施形態による電子部品内蔵基板５の構造を説明するための模式的な断面図である。FIG. 5 is a schematic cross-sectional view for explaining the structure of an electronic component built-in substrate 5 according to a fifth embodiment of the present invention. 図６は、本発明の第６の実施形態による電子部品内蔵基板６の構造を説明するための模式的な断面図である。FIG. 6 is a schematic cross-sectional view for explaining the structure of an electronic component built-in board 6 according to a sixth embodiment of the present invention. 図７は、本発明の第７の実施形態による電子部品内蔵基板７の構造を説明するための模式的な断面図である。FIG. 7 is a schematic cross-sectional view for explaining the structure of an electronic component built-in board 7 according to a seventh embodiment of the present invention. 図８は、本発明の第８の実施形態による電子部品内蔵基板８の構造を説明するための模式的な断面図である。FIG. 8 is a schematic cross-sectional view for explaining the structure of an electronic component built-in substrate 8 according to an eighth embodiment of the present invention. 図９は、本発明の第９の実施形態による電子部品内蔵基板９の構造を説明するための模式的な断面図である。FIG. 9 is a schematic cross-sectional view for explaining the structure of an electronic component built-in substrate 9 according to a ninth embodiment of the present invention.
　以下、添付図面を参照しながら、本発明の好ましい実施形態について詳細に説明する。 Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
＜第１の実施形態＞
　図１は、本発明の第１の実施形態による電子部品内蔵基板１の構造を説明するための模式的な断面図である。 <First embodiment>
FIG. 1 is a schematic cross-sectional view for explaining the structure of an electronic component built-in board 1 according to a first embodiment of the present invention.
　図１に示すように、第１の実施形態による電子部品内蔵基板１は、５層の導体層Ｌ１～Ｌ５と、４層の絶縁層１１～１４が積層方向に交互に積層された構造を有している。ここで、絶縁層１１は導体層Ｌ１，Ｌ２間に位置し、絶縁層１２は導体層Ｌ２，Ｌ３間に位置し、絶縁層１３は導体層Ｌ３，Ｌ４間に位置し、絶縁層１４は導体層Ｌ４，Ｌ５間に位置する。絶縁層１１～１４はいずれも表裏に導体層が存在する層間膜であり、その意味においてソルダーレジスト２１，２２は絶縁層に該当しない。 As shown in FIG. 1, the electronic component built-in substrate 1 according to the first embodiment has a structure in which five conductor layers L1 to L5 and four insulating layers 11 to 14 are alternately laminated in the lamination direction. are doing. Here, the insulating layer 11 is positioned between the conductor layers L1 and L2, the insulating layer 12 is positioned between the conductive layers L2 and L3, the insulating layer 13 is positioned between the conductive layers L3 and L4, and the insulating layer 14 is positioned between the conductor layers L3 and L4. Located between layers L4 and L5. The insulating layers 11 to 14 are all interlayer films having conductor layers on the front and back sides, and in that sense the solder resists 21 and 22 do not correspond to insulating layers.
　導体層Ｌ１は最上層に位置し、その一部はソルダーレジスト２１で覆われている。ソルダーレジスト２１で覆われていない導体層Ｌ１の露出部分は、電子部品内蔵基板１の一方の表面１ａ側に位置する端子電極Ｅ１を構成する。導体層Ｌ５は最下層に位置し、その一部はソルダーレジスト２２で覆われている。ソルダーレジスト２２で覆われていない導体層Ｌ５の露出部分は、電子部品内蔵基板１の他方の表面１ｂ側に位置する端子電極Ｅ２を構成する。電子部品内蔵基板１の表面１ａには、図示しない半導体ＩＣや受動部品などの電子部品を搭載しても構わないし、図示しない別の回路基板に対する実装面として用いても構わない。電子部品内蔵基板１の表面１ｂは、図示しない別の回路基板に対する実装面として用いても構わないし、図示しない半導体ＩＣや受動部品などの電子部品を搭載しても構わない。 The conductor layer L1 is located on the uppermost layer, and part of it is covered with a solder resist 21. The exposed portion of the conductor layer L1 that is not covered with the solder resist 21 constitutes the terminal electrode E1 positioned on one surface 1a of the substrate 1 with a built-in electronic component. The conductor layer L5 is located at the bottom layer and partly covered with the solder resist 22 . The exposed portion of the conductor layer L5 not covered with the solder resist 22 constitutes the terminal electrode E2 located on the other surface 1b side of the electronic component built-in substrate 1. As shown in FIG. Electronic components such as a semiconductor IC and passive components (not shown) may be mounted on the surface 1a of the electronic component built-in substrate 1, or may be used as a mounting surface for another circuit board (not shown). The surface 1b of the electronic component built-in board 1 may be used as a mounting surface for another circuit board (not shown), or electronic components such as semiconductor ICs and passive components (not shown) may be mounted thereon.
　図１に示すように、積層方向に隣接する２つの導体層は、ビア導体によって相互に接続される。例えば、導体層Ｌ１に位置する導体パターン３１と導体層Ｌ２に位置する導体パターン３２は、絶縁層１１を貫通して設けられたビア導体４１を介して接続される。導体層Ｌ２に位置する導体パターン３２と導体層Ｌ３に位置する導体パターン３３は、絶縁層１２を貫通して設けられたビア導体４２を介して接続される。導体層Ｌ３に位置する導体パターン３３と導体層Ｌ４に位置する導体パターン３４は、絶縁層１３を貫通して設けられたビア導体４３を介して接続される。導体層Ｌ４に位置する導体パターン３４と導体層Ｌ５に位置する導体パターン３５は、絶縁層１４を貫通して設けられたビア導体４４を介して接続される。 As shown in FIG. 1, two conductor layers adjacent in the stacking direction are connected to each other by via conductors. For example, the conductor pattern 31 located on the conductor layer L1 and the conductor pattern 32 located on the conductor layer L2 are connected through the via conductors 41 provided through the insulating layer 11 . The conductor pattern 32 located on the conductor layer L2 and the conductor pattern 33 located on the conductor layer L3 are connected through the via conductors 42 provided through the insulating layer 12 . The conductor pattern 33 located on the conductor layer L3 and the conductor pattern 34 located on the conductor layer L4 are connected through via conductors 43 that penetrate through the insulating layer 13 . The conductor pattern 34 located on the conductor layer L4 and the conductor pattern 35 located on the conductor layer L5 are connected through via conductors 44 that penetrate the insulating layer 14 .
　絶縁層１２は２層の絶縁層１２ａ，１２ｂからなり、両者に挟まれるよう電子部品５１が埋め込まれている。同様に、絶縁層１３は２層の絶縁層１３ａ，１３ｂからなり、両者に挟まれるよう電子部品５２が埋め込まれている。電子部品５１に設けられた端子電極は、ビア導体４５を介して導体層Ｌ２に位置する導体パターン３２に接続される。電子部品５２に設けられた端子電極は、ビア導体４６を介して導体層Ｌ３に位置する導体パターン３３に接続される。絶縁層１２ａ，１３ａは、電子部品内蔵基板１の製造プロセスにおいて、電子部品５１，５２をフェイスアップ方式で載置する際の接着層として機能する。一方、絶縁層１２ｂ，１３ｂは、電子部品内蔵基板１の製造プロセスにおいて、電子部品５１，５２を埋め込む埋込層として機能する。本実施形態においては電子部品５１，５２が積層方向に重なりを有しており、これにより電子部品内蔵基板１の平面サイズが小型化されている。 The insulating layer 12 is composed of two insulating layers 12a and 12b, and an electronic component 51 is embedded so as to be sandwiched between the two layers. Similarly, the insulating layer 13 is composed of two insulating layers 13a and 13b, and an electronic component 52 is embedded so as to be sandwiched between the two layers. Terminal electrodes provided on electronic component 51 are connected to conductor pattern 32 located on conductor layer L2 through via conductors 45 . Terminal electrodes provided on electronic component 52 are connected to conductor pattern 33 located on conductor layer L3 through via conductors 46 . The insulating layers 12a and 13a function as adhesive layers when the electronic components 51 and 52 are mounted face-up in the manufacturing process of the electronic component built-in substrate 1 . On the other hand, the insulating layers 12b and 13b function as embedding layers for embedding the electronic components 51 and 52 in the manufacturing process of the electronic component built-in substrate 1 . In this embodiment, the electronic components 51 and 52 overlap in the stacking direction, thereby reducing the planar size of the electronic component built-in board 1 .
　電子部品５１，５２の種類については特に限定されず、半導体ＩＣであっても構わないし、キャパシタ、インダクタ、フィルタなどの受動部品であっても構わない。電子部品５１，５２が半導体ＩＣである場合、チップの厚みは２００μｍ以下、例えば５０～１００μｍ程度に薄型化されていても構わない。電子部品５１，５２は、主にシリコンなどの無機材料からなるため、樹脂材料を主成分とする絶縁層１１～１４よりも熱膨張係数が小さい。 The types of the electronic components 51 and 52 are not particularly limited, and they may be semiconductor ICs or passive components such as capacitors, inductors, and filters. When the electronic components 51 and 52 are semiconductor ICs, the thickness of the chip may be reduced to 200 μm or less, for example, about 50 to 100 μm. Since the electronic components 51 and 52 are mainly made of an inorganic material such as silicon, they have a smaller coefficient of thermal expansion than the insulating layers 11 to 14 whose main component is a resin material.
　本実施形態においては、絶縁層１２に埋め込まれた電子部品５１の体積よりも、絶縁層１３に埋め込まれた電子部品５２の体積の方が小さい。その結果、電子部品内蔵基板１の表面１ａ側における熱膨張係数と表面１ｂにおける熱膨張係数に差が生じ、これに起因して電子部品内蔵基板１に反りが生じるおそれがある。これを抑制すべく、本実施形態による電子部品内蔵基板１においては、絶縁層１３にガラスクロスを含む芯材６０を埋め込んでいる。芯材６０は絶縁層１３を構成する絶縁材料よりも熱膨張係数が小さいため、電子部品５２及び芯材６０を含む絶縁層１３全体の熱膨張係数を低下させる熱膨張係数調整部材として機能する。これに対し、絶縁層１２には熱膨張係数の低い芯材が埋め込まれていない。これにより、電子部品５１を含む絶縁層１２全体の熱膨張係数と、電子部品５２及び芯材６０を含む絶縁層１３全体の熱膨張係数の差が緩和されることから、電子部品内蔵基板１に生じる反りを抑制することができる。また、電子部品５２と重なる位置及びその周囲には芯材６０が存在しないことから、電子部品５２と芯材６０が干渉することもない。さらに、芯材６０の厚さを電子部品５２の厚さよりも薄くすれば、芯材６０によって全体の厚さが増加することもない。 In this embodiment, the volume of the electronic component 52 embedded in the insulating layer 13 is smaller than the volume of the electronic component 51 embedded in the insulating layer 12 . As a result, there is a difference between the coefficient of thermal expansion of the surface 1a and the coefficient of thermal expansion of the surface 1b of the electronic component-embedded substrate 1, which may cause the electronic component-embedded substrate 1 to warp. In order to suppress this, in the electronic component built-in substrate 1 according to the present embodiment, a core material 60 containing glass cloth is embedded in the insulating layer 13 . Since the core material 60 has a smaller thermal expansion coefficient than the insulating material forming the insulating layer 13 , it functions as a thermal expansion coefficient adjusting member that reduces the thermal expansion coefficient of the entire insulating layer 13 including the electronic component 52 and the core material 60 . On the other hand, the insulating layer 12 does not have a core material with a low coefficient of thermal expansion embedded therein. As a result, the difference between the thermal expansion coefficient of the entire insulating layer 12 including the electronic component 51 and the thermal expansion coefficient of the entire insulating layer 13 including the electronic component 52 and the core material 60 is reduced. Warping that occurs can be suppressed. In addition, since the core material 60 does not exist at the position overlapping the electronic component 52 and its surroundings, the electronic component 52 and the core material 60 do not interfere with each other. Furthermore, if the thickness of the core material 60 is thinner than the thickness of the electronic component 52, the thickness of the whole is not increased by the core material 60. FIG.
　このように、本実施形態による電子部品内蔵基板１は、電子部品５１，５２の体積に差が存在するものの、絶縁層１３に熱膨張係数の小さい芯材６０が埋め込まれていることから、熱膨張係数の差に起因する電子部品内蔵基板１の反りを抑制することが可能となる。しかも、絶縁層１３のほぼ全面に芯材６０が設けられていることから、電子部品内蔵基板１の機械的強度も高められる。また、ビア導体４３は、芯材６０を貫通して設けられているため、ガラスクロスによってビアの内壁が粗面化される。その結果、ビア導体４３と絶縁層１３の密着性が向上することから、ビア導体４３の接続信頼性も高められる。 As described above, in the electronic component built-in substrate 1 according to the present embodiment, although there is a difference in volume between the electronic components 51 and 52, since the core material 60 with a small thermal expansion coefficient is embedded in the insulating layer 13, heat It is possible to suppress the warping of the electronic component built-in substrate 1 due to the difference in expansion coefficient. Moreover, since the core material 60 is provided on almost the entire surface of the insulating layer 13, the mechanical strength of the electronic component built-in substrate 1 is also enhanced. In addition, since the via conductor 43 is provided through the core material 60, the inner wall of the via is roughened by the glass cloth. As a result, the adhesion between the via conductors 43 and the insulating layer 13 is improved, and the connection reliability of the via conductors 43 is also improved.
　また、芯材６０のみでは熱膨張係数の差に起因する電子部品内蔵基板１の反りを解消できない場合には、絶縁層１２を構成する絶縁材料として、絶縁層１３を構成する絶縁材料よりも熱膨張係数の大きい材料を用いればよい。一例として、絶縁層１２，１３に熱膨張係数の小さい無機フィラーが添加されている場合、絶縁層１３における無機フィラーの含有率よりも絶縁層１２における無機フィラーの含有率を少なくすれば良い。同様に、絶縁層１１を構成する絶縁材料として、絶縁層１４を構成する絶縁材料よりも熱膨張係数の大きい材料を用いても構わない。この場合であっても、表面１ａ側における熱膨張係数が増加することから、表面１ａ側における熱膨張係数と表面１ｂ側における熱膨張係数のバランスを確保することが可能となる。 In addition, when the warpage of the electronic component built-in substrate 1 caused by the difference in the thermal expansion coefficient cannot be eliminated by the core material 60 alone, the insulating material forming the insulating layer 12 has a higher thermal conductivity than the insulating material forming the insulating layer 13 . A material having a large coefficient of expansion may be used. As an example, when an inorganic filler having a small thermal expansion coefficient is added to the insulating layers 12 and 13 , the content of the inorganic filler in the insulating layer 12 should be less than the content of the inorganic filler in the insulating layer 13 . Similarly, as the insulating material forming the insulating layer 11, a material having a larger thermal expansion coefficient than the insulating material forming the insulating layer 14 may be used. Even in this case, since the thermal expansion coefficient on the surface 1a side increases, it is possible to ensure a balance between the thermal expansion coefficient on the surface 1a side and the thermal expansion coefficient on the surface 1b side.
＜第２の実施形態＞
　図２は、本発明の第２の実施形態による電子部品内蔵基板２の構造を説明するための模式的な断面図である。 <Second embodiment>
FIG. 2 is a schematic cross-sectional view for explaining the structure of the electronic component built-in substrate 2 according to the second embodiment of the present invention.
　図２に示すように、第２の実施形態による電子部品内蔵基板２は、絶縁層１３に埋め込まれた電子部品５２の体積よりも、絶縁層１２に埋め込まれた電子部品５１の体積の方が小さく、絶縁層１２にガラスクロスを含む芯材６０が埋め込まれている点において、第１の実施形態による電子部品内蔵基板１と相違する。その他の基本的な構成については、第１の実施形態による電子部品内蔵基板１と同一であることから、同一の要素には同一の符号を付し、重複する説明は省略する。 As shown in FIG. 2, in the electronic component embedded substrate 2 according to the second embodiment, the volume of the electronic component 51 embedded in the insulating layer 12 is larger than the volume of the electronic component 52 embedded in the insulating layer 13. It differs from the electronic component built-in substrate 1 according to the first embodiment in that it is small and a core material 60 containing glass cloth is embedded in the insulating layer 12 . Since other basic configurations are the same as those of the electronic component built-in board 1 according to the first embodiment, the same elements are denoted by the same reference numerals, and overlapping descriptions are omitted.
　第２の実施形態による電子部品内蔵基板２が例示するように、電子部品５２の体積よりも電子部品５１の体積の方が小さい場合には、絶縁層１３に芯材６０を埋め込むことなく、絶縁層１２に芯材６０を埋め込めば、熱膨張係数の差に起因する電子部品内蔵基板２の反りを抑制することが可能となる。 As illustrated in the electronic component built-in board 2 according to the second embodiment, when the volume of the electronic component 51 is smaller than the volume of the electronic component 52, the core material 60 is not embedded in the insulating layer 13, and the insulation By embedding the core material 60 in the layer 12, it is possible to suppress the warping of the electronic component built-in substrate 2 due to the difference in thermal expansion coefficient.
＜第３の実施形態＞
　図３は、本発明の第３の実施形態による電子部品内蔵基板３の構造を説明するための模式的な断面図である。 <Third Embodiment>
FIG. 3 is a schematic cross-sectional view for explaining the structure of an electronic component built-in substrate 3 according to a third embodiment of the present invention.
　図３に示すように、第３の実施形態による電子部品内蔵基板３は、絶縁層１２に複数の電子部品５１が埋め込まれている点において、第１の実施形態による電子部品内蔵基板１と相違する。その他の基本的な構成については、第１の実施形態による電子部品内蔵基板１と同一であることから、同一の要素には同一の符号を付し、重複する説明は省略する。 As shown in FIG. 3, the electronic component embedded substrate 3 according to the third embodiment differs from the electronic component embedded substrate 1 according to the first embodiment in that a plurality of electronic components 51 are embedded in the insulating layer 12. do. Since other basic configurations are the same as those of the electronic component built-in board 1 according to the first embodiment, the same elements are denoted by the same reference numerals, and overlapping descriptions are omitted.
　本実施形態において、個々の電子部品５１の体積と電子部品５２の体積については大きな差はない。しかしながら、絶縁層１３には１個の電子部品５２が埋め込まれているのに対し、絶縁層１２には２個の電子部品５１が埋め込まれていることから、電子部品５２の合計体積は電子部品５１の合計体積よりも小さくなっている。このような場合であっても、絶縁層１２に芯材６０を埋め込むことなく、絶縁層１３に芯材６０を埋め込めば、熱膨張係数の差に起因する電子部品内蔵基板３の反りを抑制することが可能となる。本実施形態が例示するように、絶縁層１２や絶縁層１３に複数の電子部品が埋め込まれている場合、埋め込まれた電子部品の合計体積が小さい方の絶縁層に熱膨張係数調整部材である芯材６０を設ければよい。 In this embodiment, there is no big difference between the volume of each electronic component 51 and the volume of each electronic component 52 . However, since one electronic component 52 is embedded in the insulating layer 13 and two electronic components 51 are embedded in the insulating layer 12, the total volume of the electronic components 52 is 51 total volume. Even in such a case, by embedding the core material 60 in the insulating layer 13 instead of embedding the core material 60 in the insulating layer 12, the warping of the electronic component built-in substrate 3 due to the difference in thermal expansion coefficient can be suppressed. becomes possible. As illustrated in this embodiment, when a plurality of electronic components are embedded in the insulating layer 12 or the insulating layer 13, the thermal expansion coefficient adjustment member is placed in the insulating layer having the smaller total volume of the embedded electronic components. A core material 60 may be provided.
＜第４の実施形態＞
　図４は、本発明の第４の実施形態による電子部品内蔵基板４の構造を説明するための模式的な断面図である。 <Fourth Embodiment>
FIG. 4 is a schematic cross-sectional view for explaining the structure of an electronic component built-in board 4 according to a fourth embodiment of the present invention.
　図４に示すように、第４の実施形態による電子部品内蔵基板４は、絶縁層１３にダミーの電子部品５３が埋め込まれている点において、第３の実施形態による電子部品内蔵基板３と相違する。その他の基本的な構成については、第３の実施形態による電子部品内蔵基板３と同一であることから、同一の要素には同一の符号を付し、重複する説明は省略する。 As shown in FIG. 4, the electronic component embedded substrate 4 according to the fourth embodiment differs from the electronic component embedded substrate 3 according to the third embodiment in that dummy electronic components 53 are embedded in the insulating layer 13. do. Since other basic configurations are the same as those of the electronic component built-in board 3 according to the third embodiment, the same elements are denoted by the same reference numerals, and overlapping descriptions are omitted.
　電子部品５３は、回路として機能しないダミーの電子部品であり、もっぱら絶縁層１３の熱膨張係数を低下させる役割を果たす。したがって、電子部品５３は、どの導体パターンにも電気的に接続されていなくても構わないし、電子部品５３への放熱を目的として導体パターンを接続していても構わない。図４に示す例では、絶縁層１２に２個の電子部品５１が埋め込まれ、絶縁層１３に１個の電子部品５２と１個のダミーの電子部品５３が埋め込まれていることから、電子部品５１～５３の個々の体積がほぼ同じであれば、熱膨張係数の差に起因する電子部品内蔵基板４の反りを抑制することが可能となる。本実施形態が例示するように、熱膨張係数調整部材がガラスクロスなどからなる芯材６０であることは必須でない。また、ダミーの電子部品５３として廃棄されるべき不良品を用いれば、製造コストを削減することも可能となる。 The electronic component 53 is a dummy electronic component that does not function as a circuit, and plays the role of reducing the thermal expansion coefficient of the insulating layer 13 exclusively. Therefore, the electronic component 53 may not be electrically connected to any conductor pattern, and the conductor pattern may be connected for the purpose of dissipating heat to the electronic component 53 . In the example shown in FIG. 4, two electronic components 51 are embedded in the insulating layer 12, and one electronic component 52 and one dummy electronic component 53 are embedded in the insulating layer 13. If the individual volumes of 51 to 53 are substantially the same, it is possible to suppress warpage of electronic component built-in substrate 4 due to differences in thermal expansion coefficients. As illustrated in this embodiment, it is not essential that the thermal expansion coefficient adjusting member is the core material 60 made of glass cloth or the like. Also, if a defective product that should be discarded is used as the dummy electronic component 53, it is possible to reduce the manufacturing cost.
＜第５の実施形態＞
　図５は、本発明の第５の実施形態による電子部品内蔵基板５の構造を説明するための模式的な断面図である。 <Fifth Embodiment>
FIG. 5 is a schematic cross-sectional view for explaining the structure of an electronic component built-in substrate 5 according to a fifth embodiment of the present invention.
　図５に示すように、第５の実施形態による電子部品内蔵基板５は、ビア導体４３が設けられた位置を避けて芯材６０が配置されている点において、第１の実施形態による電子部品内蔵基板１と相違する。その他の基本的な構成については、第１の実施形態による電子部品内蔵基板１と同一であることから、同一の要素には同一の符号を付し、重複する説明は省略する。 As shown in FIG. 5, in the electronic component built-in substrate 5 according to the fifth embodiment, the electronic component according to the first embodiment is different in that the core material 60 is arranged to avoid the positions where the via conductors 43 are provided. It is different from the built-in substrate 1. Since other basic configurations are the same as those of the electronic component built-in board 1 according to the first embodiment, the same elements are denoted by the same reference numerals, and overlapping descriptions are omitted.
　本実施形態が例示するように、ビア導体４３が設けられた位置を避けて芯材６０を配置すれば、ビア導体４３を埋め込むためのビアをレーザー加工などによって形成する場合、加工が容易となる。 As illustrated in the present embodiment, if the core material 60 is arranged to avoid the position where the via conductor 43 is provided, processing becomes easy when the via for embedding the via conductor 43 is formed by laser processing or the like. .
＜第６の実施形態＞
　図６は、本発明の第６の実施形態による電子部品内蔵基板６の構造を説明するための模式的な断面図である。 <Sixth embodiment>
FIG. 6 is a schematic cross-sectional view for explaining the structure of an electronic component built-in board 6 according to a sixth embodiment of the present invention.
　図６に示すように、第６の実施形態による電子部品内蔵基板６は、電子部品５２の周囲にだけ芯材６０が配置されている点において、第１の実施形態による電子部品内蔵基板１と相違する。その他の基本的な構成については、第１の実施形態による電子部品内蔵基板１と同一であることから、同一の要素には同一の符号を付し、重複する説明は省略する。 As shown in FIG. 6, the electronic component built-in board 6 according to the sixth embodiment differs from the electronic component built-in board 1 according to the first embodiment in that the core member 60 is arranged only around the electronic component 52. differ. Since other basic configurations are the same as those of the electronic component built-in board 1 according to the first embodiment, the same elements are denoted by the same reference numerals, and overlapping descriptions are omitted.
　本実施形態が例示するように、芯材６０をほぼ全面に配置する必要はなく、全体の反りが抑制される限り、電子部品５２の周囲にのみ芯材６０を配置しても構わない。この場合、芯材６０は電子部品５１と重なるように配置することが好ましい。これによれば、絶縁層１３において熱膨張係数が低減される平面位置を電子部品５１とほぼ一致させることが可能となる。また、芯材６０の代わりに、シリコンなどの無機材料からなる熱膨張係数調整部材を用いても構わない。 As exemplified in this embodiment, it is not necessary to arrange the core material 60 on almost the entire surface, and the core material 60 may be arranged only around the electronic component 52 as long as the warping of the whole is suppressed. In this case, core material 60 is preferably arranged so as to overlap electronic component 51 . According to this, it is possible to substantially match the planar position where the thermal expansion coefficient of the insulating layer 13 is reduced with the electronic component 51 . Also, instead of the core material 60, a thermal expansion coefficient adjusting member made of an inorganic material such as silicon may be used.
＜第７の実施形態＞
　図７は、本発明の第７の実施形態による電子部品内蔵基板７の構造を説明するための模式的な断面図である。 <Seventh embodiment>
FIG. 7 is a schematic cross-sectional view for explaining the structure of an electronic component built-in board 7 according to a seventh embodiment of the present invention.
　図７に示すように、第７の実施形態による電子部品内蔵基板７は、絶縁層１３に複数のダミーチップ６１が配置されている点において、第１の実施形態による電子部品内蔵基板１と相違する。その他の基本的な構成については、第１の実施形態による電子部品内蔵基板１と同一であることから、同一の要素には同一の符号を付し、重複する説明は省略する。 As shown in FIG. 7, the electronic component built-in board 7 according to the seventh embodiment differs from the electronic component built-in board 1 according to the first embodiment in that a plurality of dummy chips 61 are arranged on the insulating layer 13. do. Since other basic configurations are the same as those of the electronic component built-in substrate 1 according to the first embodiment, the same elements are denoted by the same reference numerals, and overlapping descriptions are omitted.
　ダミーチップ６１は、シリコンなどの無機材料からなる熱膨張係数調整部材であり、絶縁層１３の熱膨張係数が目的とする値となるよう、その個数が定められる。本実施形態が例示するように、絶縁層１３に複数のダミーチップ６１を埋め込むことによって絶縁層１３の熱膨張係数を低減させることも可能である。これによれば、ダミーチップ６１の個数によって、絶縁層１３の熱膨張係数を細かく調整することが可能となる。 The dummy chips 61 are thermal expansion coefficient adjusting members made of an inorganic material such as silicon, and the number of dummy chips 61 is determined so that the thermal expansion coefficient of the insulating layer 13 has a target value. As illustrated in this embodiment, it is also possible to reduce the thermal expansion coefficient of the insulating layer 13 by embedding a plurality of dummy chips 61 in the insulating layer 13 . According to this, the thermal expansion coefficient of the insulating layer 13 can be finely adjusted by the number of dummy chips 61 .
＜第８の実施形態＞
　図８は、本発明の第８の実施形態による電子部品内蔵基板８の構造を説明するための模式的な断面図である。 <Eighth embodiment>
FIG. 8 is a schematic cross-sectional view for explaining the structure of an electronic component built-in substrate 8 according to an eighth embodiment of the present invention.
　図８に示すように、第８の実施形態による電子部品内蔵基板８は、絶縁層１２にもガラスクロスを含む芯材６２が埋め込まれている点において、第１の実施形態による電子部品内蔵基板１と相違する。その他の基本的な構成については、第１の実施形態による電子部品内蔵基板１と同一であることから、同一の要素には同一の符号を付し、重複する説明は省略する。 As shown in FIG. 8, the electronic component built-in substrate 8 according to the eighth embodiment differs from the electronic component built-in substrate according to the first embodiment in that the insulating layer 12 is also embedded with a core material 62 containing glass cloth. different from 1. Since other basic configurations are the same as those of the electronic component built-in board 1 according to the first embodiment, the same elements are denoted by the same reference numerals, and overlapping descriptions are omitted.
　絶縁層１２に埋め込まれた芯材６２の面積は、絶縁層１３に埋め込まれた芯材６０の面積よりも小さい。このため、芯材６２によって絶縁層１２の熱膨張係数を低下させる度合いは、芯材６０によって絶縁層１３の熱膨張係数を低下させる度合いよりも小さい。本実施形態が例示するように、絶縁層１２，１３の両方に芯材を埋め込んでも構わない。図８に示す例では、絶縁層１２に芯材６２を局所的に埋め込んでいるが、芯材６０よりも厚みの薄い芯材６２をほぼ全面に埋め込んでも構わない。 The area of the core material 62 embedded in the insulating layer 12 is smaller than the area of the core material 60 embedded in the insulating layer 13 . Therefore, the degree to which the coefficient of thermal expansion of the insulating layer 12 is lowered by the core member 62 is smaller than the degree to which the coefficient of thermal expansion of the insulating layer 13 is lowered by the core member 60 . A core material may be embedded in both the insulating layers 12 and 13 as illustrated in this embodiment. In the example shown in FIG. 8, the core material 62 is locally embedded in the insulating layer 12, but the core material 62 thinner than the core material 60 may be embedded almost entirely.
＜第９の実施形態＞
　図９は、本発明の第９の実施形態による電子部品内蔵基板９の構造を説明するための模式的な断面図である。 <Ninth Embodiment>
FIG. 9 is a schematic cross-sectional view for explaining the structure of an electronic component built-in substrate 9 according to a ninth embodiment of the present invention.
　図９に示すように、第９の実施形態による電子部品内蔵基板９は、芯材６０に局所的に厚みの薄い凹部６０ａが設けられており、凹部６０ａに電子部品５２が載置されている点において、第１の実施形態による電子部品内蔵基板１と相違する。その他の基本的な構成については、第１の実施形態による電子部品内蔵基板１と同一であることから、同一の要素には同一の符号を付し、重複する説明は省略する。 As shown in FIG. 9, in the electronic component built-in substrate 9 according to the ninth embodiment, a core material 60 is provided with a locally thin concave portion 60a, and an electronic component 52 is placed in the concave portion 60a. It is different from the electronic component built-in board 1 according to the first embodiment in this respect. Since other basic configurations are the same as those of the electronic component built-in board 1 according to the first embodiment, the same elements are denoted by the same reference numerals, and overlapping descriptions are omitted.
　本実施形態が例示するように、芯材６０と電子部品５２は重なりを有していても構わない。この場合、電子部品５２と重なる部分に凹部６０ａを設ければ、全体の厚みの増大を抑制することが可能となる。 As illustrated in this embodiment, the core material 60 and the electronic component 52 may overlap. In this case, if the concave portion 60a is provided in the portion that overlaps with the electronic component 52, it is possible to suppress an increase in the overall thickness.
　以上、本発明の好ましい実施形態について説明したが、本発明は、上記の実施形態に限定されることなく、本発明の主旨を逸脱しない範囲で種々の変更が可能であり、それらも本発明の範囲内に包含されるものであることはいうまでもない。 Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention. Needless to say, it is included within the scope.
　例えば、上記各実施形態においては、電子部品５１，５２の熱膨張係数が絶縁層１２，１３を構成する絶縁材料の熱膨張係数よりも小さいケースを説明したが、電子部品５１，５２の熱膨張係数が絶縁層１２，１３を構成する絶縁材料の熱膨張係数よりも大きくても構わない。この場合には、熱膨張係数調整部材として、絶縁層１２を構成する絶縁材料よりも熱膨張係数の大きな材料を用いればよい。 For example, in each of the above embodiments, the case where the coefficient of thermal expansion of the electronic components 51 and 52 is smaller than the coefficient of thermal expansion of the insulating material forming the insulating layers 12 and 13 has been described. The coefficient may be larger than the thermal expansion coefficient of the insulating material forming the insulating layers 12 and 13 . In this case, a material having a larger thermal expansion coefficient than the insulating material forming the insulating layer 12 may be used as the thermal expansion coefficient adjusting member.
１～９　　電子部品内蔵基板
１ａ　　一方の表面
１ｂ　　他方の表面
１１～１４，１２ａ，１２ｂ，１３ａ，１３ｂ　　絶縁層
２１，２２　　ソルダーレジスト
３１～３５　　導体パターン
４１～４６　　ビア導体
５１～５３　　電子部品
６０，６２　　芯材
６０ａ　　凹部
６１　　ダミーチップ
Ｅ１，Ｅ２　　端子電極
Ｌ１～Ｌ５　　導体層 1 to 9 electronic component built-in board 1a one surface 1b the other surface 11 to 14, 12a, 12b, 13a, 13b insulating layers 21, 22 solder resists 31 to 35 conductor patterns 41 to 46 via conductors 51 to 53 electronic components 60, 62 core material 60a recess 61 dummy chips E1, E2 terminal electrodes L1 to L5 conductor layer

Claims (9)

  1. 　複数の導体層と複数の絶縁層が交互に積層された構造を有する電子部品内蔵基板であって、
    　前記複数の絶縁層は、１又は２以上の第１の電子部品が埋め込まれた第１の絶縁層と、１又は２以上の第２の電子部品が埋め込まれた第２の絶縁層とを含み、
    　前記第１の電子部品の合計体積は、前記第２の電子部品の合計体積よりも小さく、
    　前記第１の絶縁層には、前記第１の絶縁層を構成する絶縁材料とは熱膨張係数の異なる熱膨張係数調整部材がさらに埋め込まれていることを特徴とする電子部品内蔵基板。     An electronic component built-in board having a structure in which a plurality of conductor layers and a plurality of insulating layers are alternately laminated,
    The plurality of insulating layers include a first insulating layer embedded with one or more first electronic components and a second insulating layer embedded with one or more second electronic components. ,
    the total volume of the first electronic component is smaller than the total volume of the second electronic component;
    An electronic component-embedded substrate, wherein a thermal expansion coefficient adjusting member having a thermal expansion coefficient different from that of an insulating material forming said first insulating layer is further embedded in said first insulating layer.
  2. 　前記第１の電子部品は、前記第１の絶縁層を構成する絶縁材料よりも熱膨張係数が小さく、
    　前記第２の電子部品は、前記第２の絶縁層を構成する絶縁材料よりも熱膨張係数が小さく、
    　前記熱膨張係数調整部材は、前記第１の絶縁層を構成する絶縁材料よりも熱膨張係数が小さいことを特徴とする請求項１に記載の電子部品内蔵基板。     The first electronic component has a smaller thermal expansion coefficient than the insulating material forming the first insulating layer,
    the second electronic component has a smaller thermal expansion coefficient than the insulating material forming the second insulating layer;
    2. The electronic component built-in board according to claim 1, wherein the thermal expansion coefficient adjusting member has a smaller thermal expansion coefficient than the insulating material forming the first insulating layer.
  3. 　前記第１の電子部品と前記第２の電子部品が積層方向に重なりを有していることを特徴とする請求項１又は２に記載の電子部品内蔵基板。 The electronic component built-in board according to claim 1 or 2, wherein the first electronic component and the second electronic component overlap in the stacking direction.
  4. 　前記熱膨張係数調整部材は、ガラスクロスを含む芯材であることを特徴とする請求項１乃至３のいずれか一項に記載の電子部品内蔵基板。 The substrate with built-in electronic components according to any one of claims 1 to 3, wherein the thermal expansion coefficient adjusting member is a core material containing glass cloth.
  5. 　前記第１の絶縁層及び前記芯材を貫通するビア導体をさらに備えることを特徴とする請求項４に記載の電子部品内蔵基板。 5. The electronic component built-in substrate according to claim 4, further comprising via conductors penetrating through the first insulating layer and the core material.
  6. 　前記第１の絶縁層を貫通するビア導体をさらに備え、
    　前記芯材は、前記ビア導体が設けられた位置を避けて配置されていることを特徴とする請求項４に記載の電子部品内蔵基板。     further comprising a via conductor penetrating through the first insulating layer;
    5. The electronic component-embedded substrate according to claim 4, wherein the core material is arranged to avoid a position where the via conductor is provided.
  7. 　前記熱膨張係数調整部材の厚さは、前記第１の電子部品の厚さよりも薄いことを特徴とする請求項１乃至６のいずれか一項に記載の電子部品内蔵基板。 The electronic component built-in board according to any one of claims 1 to 6, wherein the thickness of the thermal expansion coefficient adjusting member is thinner than the thickness of the first electronic component.
  8. 　前記第１の絶縁層の熱膨張係数と前記第２の絶縁層の熱膨張係数が互いに異なることを特徴とする請求項１乃至７のいずれか一項に記載の電子部品内蔵基板。 The electronic component built-in board according to any one of claims 1 to 7, wherein the coefficient of thermal expansion of the first insulating layer and the coefficient of thermal expansion of the second insulating layer are different from each other.
  9. 　前記複数の絶縁層は、前記第１の絶縁層を前記第２の絶縁層とは反対側から覆う第３の絶縁層と、前記第２の絶縁層を前記第１の絶縁層とは反対側から覆う第４の絶縁層とをさらに含み、
    　前記第３の絶縁層の熱膨張係数と前記第４の絶縁層の熱膨張係数が互いに異なることを特徴とする請求項１乃至８のいずれか一項に記載の電子部品内蔵基板。     The plurality of insulating layers include: a third insulating layer covering the first insulating layer from the side opposite to the second insulating layer; and a side covering the second insulating layer from the side opposite to the first insulating layer. a fourth insulating layer covering from
    9. The electronic component built-in board according to claim 1, wherein the thermal expansion coefficient of the third insulating layer and the thermal expansion coefficient of the fourth insulating layer are different from each other.
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JP2006049424A (en) * 2004-08-02 2006-02-16 Shinko Electric Ind Co Ltd Electronic component-incorporating substrate and manufacturing method therefor
JP2015018979A (en) * 2013-07-12 2015-01-29 イビデン株式会社 Printed wiring board
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