JP4592177B2 - Package substrate - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention also relates to a package substrate on which an electronic component such as an IC chip is placed, and particularly to a package substrate in which a capacitor is built.
[0002]
[Prior art]
Currently, in a package substrate, a chip capacitor is sometimes surface-mounted in order to reduce loop inductance from a power source to a power source / ground of an IC chip. That is, the loop inductance that causes transmission loss is the wiring length from the power supply terminal 272P of the IC chip 270 shown in FIG. 15A to the power supply via the power supply line in the package substrate 300, and the power supply to the package substrate 300. It is proportional to the wiring length to the ground terminal 272E of the IC chip 270 via the ground wire. For this reason, as shown in FIG. 15B, a chip capacitor 298 is surface-mounted on the package substrate 300, and the loop inductance is determined by interposing the chip capacitor 298 between the power source and the power source / ground of the IC chip. As shown by the solid line in the figure, the wiring length between the chip capacitors 298 is shortened.
[0003]
[Problems to be solved by the invention]
However, the reactance component XL of the loop inductance depends on the frequency as shown in the following equation.
XL = 2πfL f: frequency L: inductance
For this reason, as the frequency of the IC chip increases, it becomes impossible to reduce the reactance XL of the loop inductance by mounting the chip capacitor as described above with reference to FIG. 15B.
[0004]
In order to cope with such a problem, the present inventor has devised that a resin insulating layer and a wiring layer are laminated on a ceramic plate incorporating a capacitor. In the package substrate having such a configuration, the loop length can be shortened by disposing a capacitor immediately below the IC chip. However, since the signal line is arranged through the low dielectric constant resin and the high dielectric constant dielectric layer that forms the capacitor, the signal is reflected due to impedance discontinuity and when passing through the high dielectric It was expected to cause a delay in signal propagation.
[0005]
The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a package substrate in which a large-capacity capacitor can be disposed in the vicinity of an IC chip.
[0008]
[Means for Solving the Problems]
In order to solve the problems described above, claim 1A package substrate having a build-up layer formed by laminating a resin insulating layer and a conductor circuit on both surfaces of a core substrate,
  Technical features of being provided below the IC chip mounting portion, including plate capacitors in the core substrate, and connecting the build-up layers on both sides of the core substrate through through holes formed in the core substrate And
[0009]
  Claim1Then, the build-up layers (wiring) on both sides of the core substrate are connected through the through holes formed in the core substrate, and the signal line does not pass through the capacitor. Propagation delay due to passing through the high dielectric does not occur. Further, since the plate capacitor is accommodated in the core substrate, it is difficult for the package substrate to be warped.
[0010]
  Claim2Is a package substrate in which a build-up layer formed by laminating a resin insulating layer and a conductor circuit on both surfaces of a core substrate,
  Technology in which a plate capacitor is provided in the core substrate below the IC chip mounting portion, and build-up layers on both sides of the core substrate are connected via electrodes of the plate capacitor in the core substrate. Characteristic.
[0011]
  Claim2Then, since the build-up layers (wirings) on both sides of the core substrate are connected via the electrode of the plate capacitor in the core substrate, the IC chip and the capacitor, the capacitor and the external connection substrate, and the IC chip and the external connection are connected at a short distance. A substrate can be connected.
[0014]
  Claim3Is a package substrate in which a build-up layer formed by laminating a resin insulating layer and a conductor circuit on both surfaces of a core substrate,
  Below the IC chip mounting portion, provided with a plate capacitor on the lower surface of the core substrate,
  The technical feature is that the through hole formed in the core substrate and the external substrate connection terminal of the package substrate are connected via vias formed in a buildup layer formed on the lower surface of the core substrate.
[0015]
  Claim3Then, the through hole formed in the core substrate and the external substrate connection terminal of the package substrate are connected via the via formed in the buildup layer formed on the lower surface of the core substrate, and the signal line does not pass through the capacitor. Therefore, reflection due to impedance discontinuity due to the high dielectric material and propagation delay due to passage through the high dielectric material do not occur. Further, since the plate-like capacitor is disposed on the lower surface of the core substrate, it is difficult for the core substrate to be warped.
[0016]
  Claim4Then, since the plate capacitor is made of a ceramic plate, a dielectric layer having a high dielectric constant can be easily formed by simultaneous firing.
[0017]
  Claim5Then, since the metal substrate of the plate capacitor is disposed directly under the IC chip, electromagnetic wave interference from the IC chip to the mother board can be shielded.
[0018]
  Claim6Then, since the power supply capacitor is arranged directly under the IC chip, the distance between the IC chip and the power supply capacitor is shortened, and it is possible to instantaneously supply large power to the IC chip side.
[0019]
  Claim7Then, the dielectric layer is made of titanium oxide salt orTheSince it is formed of a skite-based material, a capacitor can be formed with a large capacity. In addition, by forming the dielectric layer by firing, the layer itself can be thinned. The titanate that can be used in the above-mentioned dielectric layer means a compound of titanate and metal composed of barium titanate, lead titanate, strontium titanate, calcium titanate, bismuth titanate, and magnesium titanate. PeroTheThe term “skite-based material” means all compounds that are at least MgxNbyOz. Among these, it is particularly preferable to use barium titanate. This is because the dielectric constant is easily set to 1000 or more, and the adhesion between the metal layer and the dielectric layer is excellent.
[0020]
  Claim8In the package substrate, the surface layer (the outermost dielectric layer) of the built-in plate capacitor is mainly formed of copper. As a result, the via hole in the interlayer resin insulation layer is also formed mainly from a metal made of copper, so that peeling due to a difference in expansion coefficient due to a different metal can be prevented and reliability is improved.
[0021]
  Claim9In the package substrate, a roughened layer is formed on the surface layer (outermost dielectric layer) of the built-in plate capacitor. This improves the adhesion between the interlayer resin insulation layer and the via hole formed in the interlayer resin insulation layer, and can prevent failures caused by electrical connection such as peeling or disconnection.
  The roughening layer can be formed by electrolytic plating film, oxidation-reduction treatment, or roughening treatment by etching. The roughened layer is desirably formed with an average roughness of 0.5 to 5 μm. If it is less than 0.5 μm, improvement in adhesion cannot be expected. On the other hand, if the thickness exceeds 5 μm, a resin residue is caused on the bottom surface when forming the via hole, and there is a concern that reliability may be lowered.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[First embodiment]
First, the configuration of the package substrate according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 6 shows a cross section of the package substrate 10, and FIG. 7 shows a state where the IC chip 70 is mounted on the package substrate 10 shown in FIG. 6 and attached to the daughter board 80 side.
[0023]
As shown in FIG. 6, the package substrate 10 includes a plate capacitor 30, a core substrate 20 that houses the plate capacitor 30, and interlayer resin insulating layers 40, 140, and 240 that form buildup layers 90 </ b> A and 90 </ b> B. . A via hole 46 and a conductor circuit 48 are formed in the interlayer resin insulation layer 40, and a via hole 146 and a conductor circuit 148 are formed in the interlayer resin dielectric layer 140. A via hole 246 and a conductor circuit 248 are formed in the interlayer resin insulation layer 240.
[0024]
As shown in FIG. 7, bumps 66 for connecting to pads 72S, 72P1, 72P2 of the IC chip 70 are formed in the via holes 246 of the upper buildup layer 90A. On the other hand, bumps 66 for connection to the pads 82S, 82P1, and 82P2 of the daughter board 80 are disposed on the conductor circuit 248 of the lower buildup layer 90B. A through hole 26 is formed in the core substrate 20.
[0025]
The plate capacitor 30 is formed by disposing the dielectric layer 14 and the conductor layer 16 on the surface of the metal substrate 12. That is, a power supply capacitor is formed by disposing the dielectric layer 14 on the surface of the metal substrate 12 and the conductor layer 16 on the surface of the dielectric layer 14.
[0026]
The signal pads 82S of the daughter board 80 shown in FIG. 7 are bump 66-conductor circuit 248-via hole 246-conductor circuit 148-via hole 146-conductor circuit 48-via hole 46-through hole 26-via hole 46-. Conductor circuit 48 -via hole 146 -conductor circuit 148 -via hole 246 -conductor circuit 248 -via hole 246 is connected to signal pad 72S of IC chip 70. Further, although not shown, the pad 82S is connected to the signal pad 72S of the IC chip 70 through the through hole 26-via hole 46-conductor circuit 48-via hole 146-conductor circuit 148-via hole 246. .
[0027]
The pad 82P1 for power supply of the daughter board 80 is connected to the electrode of the plate capacitor 30 via the bump 66-conductor circuit 248-via hole 246-conductor circuit 148-via hole 146-conductor circuit 48-via hole 46-power supply terminal 17. It is connected to the metal substrate 12 which comprises. Similarly, the other power supply pad 82P2 of the daughter board 80 is connected to the other side of the plate capacitor 30 via the bump 66-conductor circuit 248-via hole 246-conductor circuit 148-via hole 146-conductor circuit 48-via hole 46. It is connected to the conductor layer 16 constituting the electrode.
[0028]
On the other hand, the power supply pad 72P1 of the IC chip constitutes the electrode of the plate capacitor 30 via the bump 66-via hole 246-conductor circuit 148-via hole 146-conductor circuit 48-via hole 46-power supply terminal 17. Connected to the metal substrate 12. The other pad 72P2 for power supply of the IC chip constitutes the other electrode of the power supply capacitor described above via the bump 66-via hole 246-conductor circuit 148-via hole 146-conductor circuit 48-via hole 46. It is connected to the conductor layer 16. That is, the electric power supplied from the daughter board 80 is supplied to the IC chip side via the plate capacitor 30 directly under the IC chip.
[0029]
In the package substrate 10 of the present embodiment, the plate capacitor 30 is disposed immediately below the IC chip 70, so the distance between the IC chip and the capacitor is shortened, and large power can be instantaneously supplied to the IC chip side. become. That is, the loop length that determines the loop inductance can be shortened.
[0030]
In the present embodiment, the wiring (via hole 46, conductor circuit 48, via hole 146, conductor circuit 148, via hole 246, conductor circuit 248) of the build-up layers 90A and 90B on both surfaces of the core substrate 20 is provided inside the core substrate 20. The IC chip 70 and the capacitor 30, the capacitor 30 and the daughter board (external connection board) 80, and the IC chip 70 and the daughter board 80 are connected to each other through the electrode (conductor layer) 16 of the plate capacitor 30. can do.
[0031]
  In the package substrate of this embodiment, the dielectric layer 14 is made of titanium barium oxide having a high dielectric constant as an inorganic material, and the capacitor is formed with a large capacity by reducing the thickness of the dielectric layer. it can. Furthermore, since the inorganic material is sintered on the metal substrate 12 which is a single metal, there is only one kind of sintered material, and the atmosphere control and the sintering control are easy, and a dielectric layer having a stable dielectric constant is formed. be able to. Here, the dielectric layer may be a titanium oxide salt or a perovsk with a high dielectric constant.TheCapacitors can be formed with a large capacity by using a skite material. Further, if the dielectric layer is formed by firing, the layer itself can be thinned. The titanate that can be used in the above-mentioned dielectric layer means a compound of titanate and metal composed of barium titanate, lead titanate, strontium titanate, calcium titanate, bismuth titanate, and magnesium titanate. PeroTheThe term “skite-based material” means all compounds that are at least MgxNbyOz.
[0032]
Further, a through hole 26 for connection to the daughter board 80 is provided on the core substrate 20 side that accommodates the plate capacitor 30, and the signal line does not pass through the dielectric layer 14 of the plate capacitor 30. There is no reflection due to continuation and no propagation delay due to passage through a high dielectric.
[0033]
Further, since the metal substrate 12 is disposed directly under the IC chip 70, it is possible to shield electromagnetic wave interference from the IC chip to the motherboard side. Further, since the metal substrate 12 side having high thermal conductivity and heat resistance is used, the IC chip can be efficiently cooled. Further, since the metal substrate 12 is used, sufficient substrate rigidity can be obtained even if the metal substrate 12 is formed thin, and the package substrate is not warped.
[0034]
Furthermore, since the interlayer resin insulation layers 40, 140, and 240 are formed on the flat metal substrate 12, the film thickness can be controlled with high accuracy, the characteristic impedance of the conductor circuits 48, 148, and 248 can be easily controlled, and high-speed propagation can be achieved. The design suitable for can be made.
[0035]
Next, a method for manufacturing the package substrate described above with reference to FIG. 6 will be described with reference to FIGS.
A metal substrate 12 made of copper, aluminum, or the like having a thickness of 200 to 1000 μm is used as a starting material (FIG. 1A). Titanium barium oxide is formed into a green sheet 14α by a well-known method and is attached to the metal substrate 12, and an opening 14a is punched or drilled in the green sheet 14α by a laser (FIG. 1B). Subsequently, an Ag paste 16α serving as a plain layer is printed on the green sheet 14α, and an Ag paste 17α serving as an electrode terminal is printed in the opening 14a (FIG. 1C). Here, Ag is used, but Cu paste can also be used.
[0036]
After these laminated bodies are thermocompression bonded, they are baked in air at 950 ° C. for 30 minutes to form a plate capacitor 30 including the metal substrate 12, the dielectric layer 14, and the conductor layer 16 (FIG. 1D). In the present embodiment, since the dielectric layer 14 is formed by firing, an inorganic high dielectric constant material such as titanium barium oxide can be used, and a large-capacity capacitor can be formed.
[0037]
On the other hand, the core substrate 20 is prepared (FIG. 2A). As the core substrate 20, a laminated plate formed by laminating prepregs impregnated with an epoxy resin can be used. In addition to epoxies, those generally used in printed wiring boards such as those containing reinforcing materials such as BT, phenolic resin or glass cloth can be used. Next, the through hole 20a is punched by punching, and a through hole 22 having a diameter of 300 to 500 μm is formed with a drill (FIG. 2B). Thereafter, electroless plating and electrolytic plating are performed to form a metal film 24 on the surface of the core substrate 20 (FIG. 2C). Then, the metal film 24 is pattern-etched to form a through hole 26 (FIG. 2D). Finally, the copper paste 28 is filled into the through hole 26 (FIG. 2E). The substrate serving as the core is a resin and has a melting point of 300 ° C. or lower. Therefore, when a temperature of 350 ° C. or higher is applied, it is dissolved, softened, or carbonized.
[0038]
Subsequently, the plate capacitor 30 completed in the process described with reference to FIG. 1 is inserted into the through hole 20a of the core substrate 20 completed in the process described with reference to FIG. 2 (FIG. 3A). . Then, an insulating resin 40α is applied on the conductor layer 16 and the core substrate 20 (FIG. 3B). As the insulating resin, a thermosetting resin such as epoxy, BT, polyimide, or olefin, or a mixture of a thermosetting resin and a thermoplastic resin can be used. Moreover, a resin film can also be stuck instead of apply | coating resin.
[0039]
After the insulating resin 40α is heated and cured to form the interlayer resin insulating layer 40, the opening diameter reaching the through-hole 26 or the conductor layer 16 in the interlayer resin insulating layer 40 by a CO2 laser, YAG laser, excimer laser or UV laser. A 20 to 250 μm non-through hole 40a is formed (FIG. 3C). Thereafter, desmear processing is performed.
[0040]
A palladium catalyst is applied to the core substrate 20 and immersed in an electroless plating solution to deposit an electroless plating film 42 having a thickness of 0.2 to 5 μm uniformly on the surface of the interlayer resin insulating layer 40 (FIG. 4A). )). Here, electroless plating is used, but a metal film such as copper or nickel can be formed by sputtering. Sputtering is disadvantageous in terms of cost, but has an advantage of improving adhesion with the resin. Alternatively, the plating film may be formed after providing a roughened layer on the interlayer resin insulating layer.
[0041]
Subsequently, a photosensitive dry film is attached to the surface of the electroless plating film 42, a mask is placed, and exposure and development are performed to form a plating resist resist 43 having a thickness of 25 μm (FIG. 4B). Then, it is immersed in an electroless plating solution, and a current is passed through the electroless plating film 42 to form the electrolytic plating 44 on the non-formed portion of the resist 43 (FIG. 4C).
[0042]
Then, after the resist 43 and the mask 45 are peeled and removed with 5% KOH, etching is performed with a mixed solution of sulfuric acid and hydrogen peroxide to dissolve and remove the electroless plating film 42 under the plating resist, and the electroless plating 42 and the electrolytic copper plating. A conductor circuit 48 and a via hole 46 having a thickness of 18 μm (10 to 30 μm) made of 44 are obtained (FIG. 5A).
[0043]
Furthermore, it is immersed in chromic acid, permanganic acid, etc. for 1 minute, and the surface of the interlayer resin insulation layer 40 between the conductor circuits 48 is etched by 1 μm to remove the palladium catalyst on the surface. Further, a roughened surface (not shown) may be formed on the surfaces of the conductor circuit 48 and the via hole 46 with an etching solution containing a cupric complex and an organic acid, and Sn substitution may be performed on the surface. .
[0044]
3B to 5A are repeated to form interlayer resin dielectric layer 140, via hole 146, conductor circuit 148, interlayer resin insulating layer 240, and via hole 246 (FIG. 5). (B)).
[0045]
Solder bumps are formed on the package substrate described above. A solder resist composition is applied to both sides of the substrate to a thickness of 30 μm, dried, and then a 5 mm thick photomask film (not shown) on which a circular pattern (mask pattern) is drawn is adhered. And exposed to ultraviolet light for development. Further, heat treatment is performed to form a solder resist layer (thickness 20 μm) 60 having openings 60a in solder pad portions (including via holes and land portions thereof) (FIG. 5C).
[0046]
Then, a solder paste is filled in the opening 60a of the solder resist layer 60 (not shown). Thereafter, the solder filled in the opening 60a is reflowed at 200 ° C. to form solder bumps (solder bodies) 66 (see FIG. 6). In order to improve the corrosion resistance, a metal layer such as Ni, Au, Ag, or Pd can be formed on the opening 60a by plating or sputtering.
[0047]
Next, placement of the IC chip on the package substrate and attachment to the daughter board will be described with reference to FIG. The IC chip 70 is mounted by placing the IC chip 70 so that the solder pads 72S, 72P1, and 72P2 of the IC chip 70 correspond to the solder bumps 66 of the completed package substrate 10 and performing reflow. Similarly, the package substrate 10 is attached to the daughter board 80 by reflowing the pads 82S, 82P1, and 82P2 of the daughter board 80 to the solder bumps 66 of the package substrate 10.
[0048]
Subsequently, a package substrate according to a modification of the first embodiment of the present invention will be described with reference to FIGS. The modified package substrate 10 is substantially the same as that of the first embodiment described above. However, in the package substrate of this modified example, the conductive pins 84 are disposed and formed so as to be connected to the daughter board via the conductive pins 84.
[0049]
In the first embodiment described above, the plate capacitor 30 is formed of a single metal plate. However, in the modified example, the plate capacitor 130 is formed by stacking three ceramic plates 118. Yes. FIG. 9 shows an enlarged cross section of the plate capacitor 130. A conductive layer 112 serving as a capacitor electrode is disposed on the surface of each ceramic plate 118, and a dielectric layer 114 having the same configuration as that of the first embodiment is disposed on the surface of the conductive layer 112. On the surface of the dielectric layer 114, a dielectric layer 116 that is to be the other electrode of the capacitor is further formed. The plate capacitor 130 is manufactured by simultaneous firing in a state where three layers of ceramic green sheets to be the ceramic plate 118 are laminated.
[0050]
In the modified example, since the plate capacitor 130 is made of the ceramic plate 118, the high dielectric constant dielectric layer 114 can be easily formed by simultaneous firing.
[0051]
[Second Embodiment]
The configuration of the package substrate according to the second embodiment of the present invention will be described with reference to FIG.
In the first embodiment described above, the plate capacitor 30 is accommodated in the through hole 20 a formed in the center of the core substrate 20. On the other hand, in the second embodiment, the plate capacitor 30 is disposed on the upper side of the core substrate 20.
[0052]
Here, the power supply pad 72P1 of the IC chip 70 is connected to the metal substrate 12 constituting the electrode of the plate capacitor 30 via the bump 66 and the power supply terminal 17. The other pad 72P2 for power supply of the IC chip is connected to the conductor layer 16 constituting the other electrode of the plate capacitor 30 via the bump 66.
[0053]
On the other hand, the power supply pad 82P1 of the daughter board 80 is formed of the bump 66-interlayer resin insulating layers 240, 140, 40 of the buildup layer 90B, the conductor circuits 248, 148, 48 and the via holes 246, 146, 46-through holes 26-. The power supply terminal 17 is connected to the metal substrate 12 constituting the electrode of the plate capacitor 30. Similarly, the other power supply pad 82P2 of the daughter board 80 is connected to the conductor circuit 248, 148, 48 of the interlayer resin insulation layers 240, 140, 40 of the bump 66-buildup layer 90B and the via holes 246, 146, 46-through. The hole 26 is connected to the conductor layer 16 constituting the other electrode of the plate capacitor 30.
[0054]
On the other hand, the signal pad 72S of the IC chip 72 is formed of the bump 66—the conductive circuits 248, 148, 48 of the interlayer resin insulation layers 240, 140, 40 of the buildup layer 90A and the via holes 246, 146, 46—through holes 26—. The buildup layer 90B is connected to the signal pad 82S of the daughter board 80 via the conductor circuits 248, 148, 48 of the interlayer resin insulation layers 240, 140, 40 and via holes 246, 146, 46-bumps 66.
[0055]
In the second embodiment, the signal pads 72S of the IC chip 70 and the through holes 26 formed in the core substrate 20 are connected to vias 246 formed in the buildup layer 90A formed on the upper surface of the core substrate 20. Since the signal lines do not pass through the plate-like capacitor 30 connected through 146, 46, reflection due to impedance discontinuity due to the high dielectric and propagation delay due to passage through the high dielectric do not occur. Further, since the plate capacitor 30 is disposed on the upper surface of the core substrate 20, the core substrate is unlikely to warp.
[0056]
In the package substrate 110 of the second embodiment, since the plate capacitor 30 is disposed immediately below the IC chip 70, the distance between the IC chip and the capacitor is shortened, and a large amount of power can be instantaneously supplied to the IC chip side. It becomes possible. That is, the loop length that determines the loop inductance can be minimized.
[0057]
Next, a package substrate according to a modification of the second embodiment of the present invention will be described with reference to FIG. The modified package substrate 110 is substantially the same as that of the second embodiment described above. However, in the package substrate of this modified example, the conductive pins 84 are disposed and formed so as to be connected to the daughter board via the conductive pins 84.
[0058]
In the second embodiment described above, the plate capacitor 30 is formed of a single metal plate. However, in the modified example, the plate capacitor 130 is formed by stacking three ceramic plates 118. (See FIG. 9).
[0059]
[Third embodiment]
Next, the configuration of the package substrate according to the third embodiment of the present invention will be described with reference to FIG.
In the first embodiment described above, the plate capacitor 30 is accommodated in the through hole 20 a formed in the center of the core substrate 20. On the other hand, in the third embodiment, the plate capacitor 30 is disposed below the core substrate 20.
[0060]
Here, the power supply pads 72P1 of the IC chip 70 are the bumps 66-interlayer resin insulation layers 240, 140, 40 of the buildup layer 90B, conductive circuits 248, 148, 48 and via holes 246, 146, 46-through holes. 26-connected to the metal substrate 12 constituting the electrode of the plate capacitor 30 via the power supply terminal 17. Similarly, the other pad 72P2 for the power supply of the IC chip is the bump 66-the conductive resin 248,148,48 of the interlayer resin insulation layers 240,140,40 of the buildup layer 90B and the via holes 246,146,46-through. The hole 26 is connected to the conductor layer 16 constituting the other electrode of the plate capacitor 30.
[0061]
On the other hand, the power supply pad 82 </ b> P <b> 1 of the daughter board 80 is connected to the metal substrate 12 constituting the electrode of the plate capacitor 30 via the bump 66 -power supply terminal 17. Similarly, the power supply pad 82 </ b> P <b> 2 of the daughter board 80 is connected to the conductive layer 16 constituting the other electrode of the plate capacitor 30 via the bump 66.
[0062]
On the other hand, the signal pad 72S of the IC chip 72 is formed of the bump 66—the conductive circuits 248, 148, 48 of the interlayer resin insulation layers 240, 140, 40 of the buildup layer 90A and the via holes 246, 146, 46—through holes 26—. The buildup layer 90B is connected to the signal pad 82S of the daughter board 80 via the conductor circuits 248, 148, 48 of the interlayer resin insulation layers 240, 140, 40 and via holes 246, 146, 46-bumps 66.
[0063]
In the third embodiment, the through holes 26 formed in the core substrate 20 and the daughter board connecting bumps 66 are connected to vias 246, 146, 46 formed in the buildup layer 90 </ b> B formed on the lower surface of the core substrate 20. Since the signal line does not pass through the plate capacitor 30, reflection due to impedance discontinuity due to the high dielectric and propagation delay due to passage through the high dielectric do not occur. Further, since the plate capacitor 30 is disposed on the lower surface of the core substrate 20, the core substrate is less likely to warp.
[0064]
In the package substrate 110 of the third embodiment, since the plate capacitor 30 is disposed directly under the IC chip 70, the distance between the IC chip and the capacitor is shortened, and large power can be instantaneously supplied to the IC chip side. It becomes possible. That is, the loop length that determines the loop inductance can be shortened.
[0065]
Next, a package substrate according to a modification of the third embodiment of the present invention will be described with reference to FIG. The modified package substrate 110 is substantially the same as that of the third embodiment described above. However, in the package substrate of this modified example, the conductive pins 84 are disposed and formed so as to be connected to the daughter board via the conductive pins 84.
[0066]
In the third embodiment described above, the plate capacitor 30 is formed of a single metal plate. However, in a modified example, the plate capacitor 130 is formed by stacking three ceramic plates 118. (See FIG. 9). In the modified examples of the first, second, and third embodiments, the plate capacitor 130 made of a plurality of ceramic plates is shown. However, it may be configured as a single plate type, or a conductor layer and a dielectric layer. Can be folded to form a capacitor.
[0067]
[Fourth embodiment]
FIG. 14A shows a plate capacitor built in the package substrate according to the fourth embodiment. In the fourth embodiment, the plate-like capacitor 30 is formed by disposing the dielectric layer 14 and the conductor layer 16 on the surface of the metal substrate 12. The dielectric layer 16 is formed by firing silver or copper paste, and an electroless copper plating film 18 b and an electrolytic copper plating film 18 b are formed on the surface of the dielectric layer 16.
[0068]
In the fourth embodiment, copper plating films 18 a and 18 b are disposed on the surface layer (outermost dielectric layer 16) of the plate capacitor 30. As a result, the via hole in the interlayer resin insulation layer is also formed mainly from a metal made of copper, so that peeling due to a difference in expansion coefficient due to a different metal can be prevented and reliability is improved.
[0069]
[Fifth Embodiment]
FIG. 14B shows a plate capacitor built in the package substrate according to the fifth embodiment. In the fifth embodiment, the plate capacitor 30 includes a dielectric layer 14 and a conductor layer 16 disposed on the surface of the metal substrate 12. On the surface of the dielectric layer 16, a roughened layer 21 having an average roughness of 3 μm is formed by an electroless plating film made of a Cu—Ni—P alloy. Instead of the electroless plating film, the roughening layer is made of an etching solution composed of a cupric complex and organic hydrochloric acid, and NaOH (10 g / l), NaClO2 (40 g / l), Na3 PO4 (6 g / l). A blackening treatment using an aqueous solution containing the blackening bath (oxidation bath) and a reduction treatment using an aqueous solution containing NaOH (10 g / l) and NaBH4 (6 g / l) as a reducing bath can also be formed.
[0070]
In the package substrate of the fifth embodiment, the roughened layer 21 is formed on the surface layer (outermost dielectric layer) of the built-in plate capacitor. This improves the adhesion between the interlayer resin insulation layer and the via hole formed in the interlayer resin insulation layer, and can prevent failures caused by electrical connection such as peeling or disconnection.
[0071]
【The invention's effect】
According to the configuration of the present invention, large power can be supplied to the IC chip, the loop inductance can be reduced, and the capacitor is built in, so that peeling due to warpage or contraction of the substrate can be prevented. Further, since the capacitor and the via hole in the interlayer resin insulation layer are connected, the electrical connectivity and reliability are improved.
Furthermore, by forming copper on the surface layer of the capacitor, the connection reliability with via holes made of copper is improved.
On the other hand, by forming a roughened layer on the surface layer of the capacitor, the connection reliability with the interlayer resin insulating layer and the via hole is further improved.
[Brief description of the drawings]
FIG. 1 is a manufacturing process diagram of a package substrate according to a first embodiment of the present invention.
FIG. 2 is a manufacturing process diagram of the package substrate according to the first embodiment of the present invention.
FIG. 3 is a manufacturing process diagram of the package substrate according to the first embodiment of the present invention.
FIG. 4 is a manufacturing process diagram of the package substrate according to the first embodiment of the present invention.
FIG. 5 is a manufacturing process diagram of the package substrate according to the first embodiment of the present invention.
FIG. 6 is a cross-sectional view of the package substrate according to the first embodiment.
FIG. 7 is a cross-sectional view of the package substrate according to the first embodiment.
FIG. 8 is a cross-sectional view of a package substrate according to a modification of the first embodiment.
9 is a cross-sectional view of a plate capacitor of the package substrate shown in FIG.
FIG. 10 is a cross-sectional view of a package substrate according to a second embodiment of the present invention.
FIG. 11 is a cross-sectional view of a package substrate according to a modification of the second embodiment of the present invention.
FIG. 12 is a cross-sectional view of a package substrate according to a third embodiment of the present invention.
FIG. 13 is a cross-sectional view of a package substrate according to a modification of the third embodiment of the present invention.
14A is a cross-sectional view of a plate capacitor according to a fourth embodiment of the present invention, and FIG. 14B is a cross-sectional view of a plate capacitor according to a fifth embodiment.
FIGS. 15A and 15B are explanatory diagrams of loop inductance of a package substrate according to the related art.
[Explanation of symbols]
12 Metal substrate
14 Dielectric layer
16 Conductor layer (electrode)
20 Core substrate
20a through hole
30 plate capacitor
40 Interlayer resin insulation layer
40a Non-through hole
42 Electroless plating film
44 Electroplating
46 Bahia Hall
48 conductor circuit
60 Solder resist
66 Solder bump
70 IC chip
80 daughter board
84 Conductive pin
140 Interlayer resin insulation layer
146 Bahia Hall

Claims (9)

A package substrate having a build-up layer formed by laminating a resin insulating layer and a conductor circuit on both surfaces of a core substrate,
It is below the IC chip mounting portion, and includes a plate capacitor in the core substrate, and the build-up layers on both surfaces of the core substrate are connected through through holes formed in the core substrate. Package substrate. A package substrate having a build-up layer formed by laminating a resin insulating layer and a conductor circuit on both surfaces of a core substrate,
It is below the IC chip mounting part, the plate capacitor is provided in the core substrate, and the build-up layers on both surfaces of the core substrate are connected via the electrodes of the plate capacitor in the core substrate. A package substrate. A package substrate having a build-up layer formed by laminating a resin insulating layer and a conductor circuit on both surfaces of a core substrate,
Below the IC chip mounting portion, comprising a plate capacitor on the lower surface of the core substrate,
A package substrate, wherein a through hole formed in the core substrate and an external substrate connection terminal of the package substrate are connected through a via formed in a buildup layer formed on a lower surface of the core substrate. The plate capacitor, the package substrate according to claim 1 to 3 formed by providing a conductor layer and a dielectric layer on a ceramic plate. The plate capacitor, the package substrate according to claim 1 to 3 formed by providing a conductor layer and the dielectric layer to the metal plate. Package substrate according to claim 1 to 3, characterized in that said plate-shaped capacitor and a capacitor for power supply. The dielectric layer is, the package substrate according to claim 4 or 5, characterized by being formed by a titanium oxide salt or Perot Bed Sukaito based material. Package substrate according to claim 1-7, characterized in that it copper is formed on the surface of the plate-shaped capacitor. Package substrate according to claim 1-7, characterized in that the roughened layer is formed on the surface layer of the plate-shaped capacitor.

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