JPH11307687A - Package board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lower the inductance of a wiring to allow a high current to be fed instantaneously to an integrated circuit chip by mounting a chip capacitor directly beneath the integrated circuit chip at the surface of a lower face, to shorten the distance of a wiring from the chip capacitor to the integrated circuit chip. SOLUTION: This package board 10 a power chip capacitor C and a chip resistance for terminating an integrated circuit 90 directly beneath the integrated circuit chip 90 on the surface of the lower face of the package board 10, and vias 60U are connected directly to through-holes 16 for shortening the wiring length, whereby the wiring length from the chip capacitor C to the integrated circuit chip 90 mounted on the package board 10 becomes short, the inductance of the wiring can be lowered, a heavy current can be fed instantaneously to the integrated circuit chip 90 from the chip capacitor, reflections at the wiring can be suppressed and the impedance matching becomes easy.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package substrate having an integrated circuit chip mounted on an upper surface and a lower surface attached to the substrate.

[0002]

2. Description of the Related Art A capacitor is sometimes provided on a package substrate constituting a package on which an integrated circuit chip such as a CPU is mounted. That is, a capacitor is provided on a package substrate, and an electric charge is stored in the capacitor so that a large current can be supplied in order for the CPU to instantaneously require a large current with the increase in speed.

Here, in a ceramic multilayer wire plate, a capacitor is formed by forming conductor layers 252 and 254 on both surfaces of an insulating layer 250 as shown in FIG. On the other hand, in a package substrate using a resin substrate, as shown in FIG. 8B, a chip capacitor C is mounted on the upper surface of the package substrate. This is because the package substrate is made of a resin substrate, and the dielectric constant of the resin is lower than that of ceramic. Therefore, a capacitor is formed inside the package substrate by providing conductor layers on the upper and lower surfaces of the resin substrate. This is because a high capacity cannot be obtained.

[0004]

However, FIG.
When the chip capacitor C is disposed on the upper surface of the package substrate as shown in FIG. 3B, the distance from the chip capacitor C to the integrated circuit chip 90 increases, and the distance between the chip capacitor C and the integrated circuit chip 90 increases.
Therefore, it is difficult to increase the amount of current that can be supplied to the integrated circuit chip 90 instantaneously.

[0005] For this reason, the present inventor has filed Japanese Patent Application No.
No. 232 proposed a technique for disposing a chip capacitor inside a package substrate. According to this technique, although the distance from the integrated circuit chip 90 to the capacitor can be shortened, manufacturing is difficult.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and an object of the present invention is to provide a package substrate capable of instantaneously supplying a large current from a capacitor.

[0007]

According to a first aspect of the present invention, an integrated circuit chip is mounted on an upper surface to achieve the above object.
In the package substrate having the lower surface attached to the substrate side, a technical feature is that a mounting component is attached to a surface on the lower surface side, directly below the integrated circuit chip.

According to a second aspect of the present invention, there is provided a package substrate on which an integrated circuit chip is mounted on an upper surface and a lower surface is mounted on a substrate side, wherein interlayer resin insulating layers and conductive layers are alternately laminated. In a package substrate in which build-up wiring layers connected by via holes are formed on both surfaces of a core substrate, a through-hole formed in the core substrate is filled with a filler and A conductor layer is formed to cover the exposed surface from the through hole, and a via hole is connected to the conductor layer, and a mounting component is mounted on the lower surface of the package substrate and directly below the integrated circuit chip. This is a technical feature.

A third aspect of the present invention is characterized in that, in the first or second aspect, the mounted component is a chip capacitor using ceramic as a dielectric material.

According to the first aspect of the present invention, since the mounting component (chip capacitor) is mounted on the lower surface side and immediately below the integrated circuit chip, the distance of the wiring from the mounting component to the integrated circuit chip becomes shorter. Since the inductance of the wiring can be reduced, a large current can be instantaneously supplied to the integrated circuit chip.

According to the second aspect, the via hole is directly connected to the via hole by making the conductor layer provided immediately above the through hole function as an inner layer pad, and the wiring distance between the through hole and the via hole is shortened. Then, by mounting a mounting component (chip capacitor) directly below the integrated circuit chip, the distance of the wiring from the mounting component to the integrated circuit chip is shortened, the inductance of the wiring is reduced, and the integrated circuit chip is mounted. It is possible to supply a large current instantaneously.

According to the third aspect, since a high dielectric constant ceramic is used as the dielectric material of the chip capacitor, a high capacitance can be obtained.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a package substrate according to an embodiment of the present invention will be described with reference to the drawings. First,
The configuration of the package substrate 10 will be described with reference to FIGS. FIG. 6 shows a cross section of the package substrate 10 before the integrated circuit chip 90 is mounted, and FIG. 7 shows a cross section of the package substrate 10 on which the integrated circuit chip 90 is mounted. As shown in FIG. 7, an integrated circuit chip 90 is mounted on the upper surface side of the package substrate 10, and the lower surface side is connected to the daughter board 94. A power supply chip capacitor C and an integrated circuit chip 9 are provided on the lower surface of the package substrate and directly below the integrated circuit chip 90.
A chip resistor (not shown) for termination of 0 is mounted. As the chip capacitor C, a high-capacity ceramic capacitor is selected.

The structure of the package substrate will be described in detail with reference to FIG. In the package substrate 10, the build-up wiring layers 80 are formed on the front and back surfaces of the multilayer core substrate 30.
A and 80B are formed. The built-up layer 80A
Is composed of an interlayer resin insulation layer 50 having via holes 60U and conductor circuits 58 formed therein, and an interlayer resin insulation layer 150 having via holes 160U and conductor circuits 158 formed therein. The build-up wiring layer 80B is formed of the interlayer resin insulation layer 5 having the via hole 60D and the conductor circuit 58 formed thereon.
0 and the interlayer resin insulating layer 150 in which the via hole 160D and the conductor circuit 158 are formed.

On the upper surface side, solder bumps 76U for connection to lands 92 (see FIG. 7) of the integrated circuit chip 90 are provided. The solder bump 76U is connected to the through hole 16 via the via hole 160U and the via hole 60U. On the other hand, a solder bump 76D for connection to a land 96 (see FIG. 7) of the daughter board (sub-board) 94 is provided on the lower surface side. The solder bump 76D is connected to the through hole 16 via the via hole 160D and the via hole 60D.
The chip capacitor C is connected to a power supply line (not shown) from the daughter board 94, and
0 for via holes 160D, 60D, through hole 1
6. It is configured to supply current through via holes 60U and 160U.

The through hole 16 is filled with a filler 22, and a conductor layer 26a is formed so as to cover the exposed surface of the filler 22 from the through hole 16. The conductor layer 2
6 a is formed in a circular shape, and is formed above and below the filler 22 in the through hole 16. Upper conductor layer 2
The via hole 60U is directly connected to 6a, and the via hole 60D is directly connected to the lower conductor layer 26a. By directly connecting the via hole to the via hole, a pad is added to the land of the through hole and the via hole is connected to the pad as in the prior art. The wiring lengths to 60U and 60D are shortened.

The package substrate 10 of the first embodiment
A power supply chip capacitor C and a chip resistor (not shown) for terminating the integrated circuit chip 90 are mounted on the lower surface side of the package substrate and directly below the integrated circuit chip 90. Further, by directly connecting the via holes 60U and 60D to the through hole 16, the wiring length is shortened. As a result, the wiring length from the chip capacitor C to the integrated circuit chip 90 mounted on the package substrate is reduced, and the inductance of the wiring is reduced. A large current can be supplied. Similarly, since the distance from a chip resistor (termination resistor) (not shown) to the integrated circuit chip 90 is shortened, reflection on the wiring can be suppressed, and impedance matching can be easily performed.

Subsequently, a method for manufacturing the package substrate shown in FIG. 6 will be specifically described by way of an example. The method described below relates to a method for manufacturing a package substrate by a semi-additive method. However, in the method for manufacturing a package substrate according to the present invention, a full additive method, a multi-lamination method, and a pin lamination method can be adopted. . (1) 0.5mm thick glass epoxy resin or BT
Core substrate 3 made of (bismaleimide triazine) resin
A copper-clad laminate 30A in which 18 μm copper foils 12 are laminated on both sides of the substrate is used as a starting material (see FIG. 1A). An etching resist was provided on both surfaces thereof, and etching treatment was performed with a sulfuric acid-hydrogen peroxide aqueous solution to obtain a core substrate 30 having the conductor circuit 14 (FIG. 1B).

(2) Next, a pitch interval of 6
A through hole 16 having a diameter of 300 μm and a diameter of 300 μm is drilled with a drill (see FIG. 1C). Then, a palladium-tin colloid is adhered, and electroless plating is performed with the following composition. An electrolytic plating film 18 was formed (see FIG. 1D). [Electroless plating aqueous solution] EDTA 150 g / l Copper sulfate 20 g / l HCHO 30 ml / l NaOH 40 g / l α, α'-bipyridyl 80 mg / l PEG 0.1 g / l [Electroless plating conditions] 70 30 minutes at liquid temperature of ℃

(3) In the above (2), the electroless copper plating film 18
The substrate 30 on which the conductor (including the through hole 16) formed of is formed is washed with water and dried, and then NaOH (10 g /
l), NaClO ₂ (40 g / l), Na ₃ PO ₄ (6
g / l) in an oxidation bath (blackening bath), NaOH (10 g / l).
1) The substrate was subjected to an oxidation-reduction treatment using NaBH ₄ (6 g / l) as a reducing bath, and a roughened layer 20 was provided on the entire surface of the conductor 18 including the through hole 16 (see FIG. 1E).

(4) Next, a filler 22 containing copper particles having an average particle diameter of 10 μm (non-conductive filled copper paste made by Tatsuta Electric Wire, trade name: DD paste) is filled into the through-hole 16 by screen printing. , Dried and cured (FIG. 2 (F)). Then, the filler 22 protruding from the roughened layer 20 and the through hole 16 on the upper surface of the conductor 18 is removed by # 60.
The surface of the substrate 30 was flattened by removing it by belt sanding using a belt sanding paper (manufactured by Sankyo Rikagaku Co., Ltd.) and further removing the scratches caused by the belt sanding (FIG. 2 (G)). reference). Thus, the substrate 30 in which the inner wall surface of the through hole 16 and the resin filler 22 are firmly adhered to each other via the roughened layer 20 is obtained.

(5) A palladium catalyst (manufactured by Atotech) is applied to the surface of the substrate 30 flattened in the above (4), and electroless copper plating is performed according to the conditions in the above (2) to obtain a thickness of 0.6 μm. Was formed (see FIG. 2H).

(6) Next, electrolytic copper plating is performed under the following conditions to form an electrolytic copper plating film 24 having a thickness of 15 μm.
A portion serving as the conductor circuit 14 was formed, and a portion serving as a conductor layer (a circular through-hole land) 26a covering the filler 22 filled in the through-hole 16 was formed (FIG. 2 (I)). [Electroplating aqueous solution] Sulfuric acid 180 g / l Copper sulfate 80 g / l Additive (manufactured by Atotech Japan, trade name: Capparaside GL) 1 ml / l [Electroplating conditions] Current density 1 A / dm ² hours 30 minutes Temperature Room temperature

(7) A commercially available photosensitive dry film is adhered to both surfaces of the substrate 30 on which the portions to be the conductor circuits 14 and the conductor layers 26a are formed, and a mask is placed on the substrate 30 for 100 m.
Exposure was performed at J / cm ² and development processing was performed using 0.8% sodium carbonate to form an etching resist 25 having a thickness of 15 μm (see FIG. 2 (J)).

(8) Then, portions of the plating films 23 and 24 where the etching resist 25 is not formed are dissolved and removed by etching using a mixed solution of sulfuric acid and hydrogen peroxide. By stripping off with KOH, a conductor layer 26a covering the independent conductor circuit 14a and the filler 22 was formed (see FIG. 3 (K)).

(9) Next, on the surface of the conductor layer 26a covering the conductor circuit 14a and the filler 22, a roughened layer (irregular layer) 27 made of a Cu-Ni-P alloy and having a thickness of 2.5 μm is formed. Furthermore, a 0.3 μm thick S
An n layer was formed (see FIG. 3 (L), but the Sn layer was not shown). The formation method is as follows.
That is, the substrate 30 is acid-degreased and soft-etched, and then treated with a catalyst solution comprising palladium chloride and an organic acid to provide a Pd catalyst. After activating this catalyst, copper sulfate 8 g / l, sulfuric acid Nickel 0.6g / l, citric acid 1
5 g / l, sodium hypophosphite 29 g / l, boric acid 3
Plating is performed in an electroless plating bath consisting of 1 g / l, surfactant 0.1 g / l, and pH = 9, and the surface of the conductor layer 26a covering the conductor circuit 14a and the filler 22 is Cu-Ni-
A roughened layer 27 of a P alloy was provided. Then, tin borofluoride 0.1 mol / l, thiourea 1.0 mol / l, temperature 5
Cu-Sn substitution reaction under the condition of 0 ° C. and pH = 1.2,
An Sn layer having a thickness of 0.3 μm was provided on the surface of the roughened layer 10 (the Sn layer is not shown).

It should be noted that, instead of the step (9), the conductor circuit 14
A so-called blackening-reducing layer is formed on the surface of the conductor layer 26a covering the a and the filler 22, and a resin such as bisphenol F type epoxy resin is filled between the conductor circuits, the surface is polished, and the Cu is plated by (9). A roughened layer of a -Ni-P alloy may be formed. (The package cross-sectional view shown in FIG. 6 is manufactured using this process.)

(10) A resin filler for smoothing the substrate surface is adjusted. Here, bisphenol F type epoxy monomer (manufactured by Yuka Shell, molecular weight 310, YL98
3U) 100 parts by weight and 6 parts by weight of an imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Chemicals Co., Ltd.) were mixed, and the mixture was mixed with SiO ₂ having an average particle diameter of 1.6 μm, the surface of which was coated with a silane coupling agent. Spherical particles (manufactured by Admatech, CRS1101-CE, where the size of the largest particles is not more than the thickness of the conductor circuit 14a described later)
170 parts by weight, defoamer (manufactured by San Nopco, Perenol S
4) 0.5 parts by weight are mixed and kneaded with a three-roll mill, so that the viscosity of the mixture is 450,000 at 23 ± 1 ° C.
Adjust to 0 to 49,000 cps to obtain a resin filler. This resin filler is solventless. If a resin filler containing a solvent is used, the solvent is volatilized from the resin filler layer when the interlayer agent is applied, heated and dried in a later step, so that a gap between the resin filler layer and the interlayer material is generated. This causes peeling.

(11) Resin filler 2 obtained in (10) above
8 is applied to both surfaces of the substrate 30 using a roll coater to fill the space between the conductor layers 26a on the upper surface.
After drying for 20 minutes, the lower surface is filled with the resin filler 30 between the conductor layers 26a or between the conductor circuits 14a in the same manner, and dried at 70 ° C. for 20 minutes (see FIG. 3 (M)).

(12) One surface of the substrate 30 that has been subjected to the treatment of (11) is subjected to belt sander polishing using # 600 belt polishing paper (manufactured by Sankyo Rikagaku) to form a conductor layer 26a.
Is polished so that the resin filler 28 does not remain on the surface of the conductor circuit 14a, and then buffing is performed to remove the scratches caused by the belt sander polishing (see FIG. 3 (N)). Next, at 100 ° C. for 1 hour, at 120 ° C. for 3 hours,
The heat treatment is performed at 150 ° C. for 1 hour and at 180 ° C. for 7 hours to cure the resin filler 28.

In this way, by removing the roughened layer 27 on the surface of the conductor layer 26a and the conductor circuit 14a and smoothing both surfaces of the substrate, the resin filler 28 and the conductor layer 26a and the side surfaces of the conductor circuit 14a are removed. Firmly adhere through the roughened layer 27.

(13) A roughened layer (concavo-convex layer) 29 made of a Cu-Ni-P alloy having a thickness of 2.5 μm is formed on the upper surface of the conductor layer 26a and the conductor circuit 14a exposed by the process (12). Further, the surface of the roughened layer 29 has a thickness of 0.3 μm.
(See FIG. 3 (O); however, the Sn layer is not shown). The formation method is as follows. That is, the substrate 30 is acid-degreased and soft-etched, then treated with a catalyst solution comprising palladium chloride and an organic acid to provide a Pd catalyst, and after activating this catalyst, copper sulfate 8 g / l, sulfuric acid Plating is carried out in an electroless plating bath consisting of nickel 0.6 g / l, citric acid 15 g / l, sodium hypophosphite 29 g / l, boric acid 31 g / l, surfactant 0.1 g / l, pH = 9. Allocation, copper conductor circuit 4
Then, a roughened layer 29 of a Cu—Ni—P alloy is formed on the land upper surface of the through hole 9. Then, tin borofluoride 0.1 mol / l, thiourea 1.0 mol / l, temperature 5
Cu-Sn substitution reaction under the condition of 0 ° C. and pH = 1.2,
An Sn layer having a thickness of 0.3 μm is provided on the surface of the roughened layer 29 (the Sn layer is not shown).

(14) Adhesives A and B for electroless plating for forming an interlayer resin insulating layer were prepared by the following method. A. Preparation of adhesive for electroless plating of upper layer. 35 parts by weight (solid content: 80%) of a 25% acrylate of a cresol novolak type epoxy resin (manufactured by Nippon Kayaku, molecular weight: 2500), 3.15 parts by weight of a photosensitive monomer (manufactured by Toagosei Co., Aronix M315), an antifoaming agent 0.5 part by weight (manufactured by San Nopco, S-65) and 3.6 parts by weight of NMP were stirred and mixed. . 12 parts by weight of polyether sulfone (PES), 7.2 parts by weight of an epoxy resin particle (manufactured by Sanyo Chemical Industries, Polymer Pole) having an average particle size of 1.0 μm, and an average particle size of 0.5 part
μm, 3.09 parts by weight, and then N
30 parts by weight of MP was added and mixed by stirring with a bead mill. . Imidazole curing agent (2E4MZ-C manufactured by Shikoku Chemicals)
N) 2 parts by weight, a photoinitiator (Ciba Geigy, Irgacure I-907) 2 parts by weight, a photosensitizer (Nippon Kayaku, D
0.2 parts by weight of ETX-S) and 1.5 parts by weight of NMP were mixed with stirring. These were mixed to prepare an adhesive composition A for electroless plating.

B. Preparation of adhesive for electroless plating of lower layer. 35 parts by weight (solid content: 80%) of a 25% acrylate of a cresol novolak type epoxy resin (manufactured by Nippon Kayaku, molecular weight: 2500), 4 parts by weight of a photosensitive monomer (Aronix M315, manufactured by Toa Gosei), an antifoaming agent (San Nopco) , S-65), 0.5 parts by weight and 3.6 parts by weight of NMP were stirred and mixed. . After mixing 12 parts by weight of polyether sulfone (PES) and 14.49 parts by weight of an epoxy resin particle (manufactured by Sanyo Chemical Industries, Polymer Pole) having an average particle size of 0.5 μm, 20 parts by weight of NMP were further added, The mixture was stirred and mixed with a bead mill.

[0035] Imidazole curing agent (Shikoku Chemicals, 2
E4MZ-CN) 2 parts by weight, photoinitiator (Circa Geigy, Irgacure I-907) 2 parts by weight, photosensitizer (Nippon Kayaku, DETX-S) 0.2 parts by weight, NMP
1.5 parts by weight were stirred and mixed. These were mixed to prepare a lower layer adhesive B for electroless plating.

(15) First, on both sides of the substrate,
The adhesive for electroless plating of B prepared in 4) (viscosity 1.5
Pa.s) 44 is applied using a roll coater, left in a horizontal state for 20 minutes, dried at 60 ° C. for 30 minutes, and then an adhesive for electroless plating A (viscosity 1.0 P
a.s) 46 was applied using a roll roller, left in a horizontal state for 20 minutes, and then dried at 60 ° C. for 30 minutes to form an adhesive layer 50 having a thickness of 40 μm (FIG. 4).
(P)).

(16) A photomask film on which a black circle of 85 μmφ is printed is brought into close contact with both surfaces of the substrate on which the adhesive layer 50 is formed, and 500 mJ / cm by an ultra-high pressure mercury lamp.
Exposure at ² . This was spray-developed with a DMDG (diethylene glycol dimethyl ether) solution to form an opening serving as a 85 μmφ via hole in the adhesive layer. Further, the substrate is subjected to an ultra-high pressure mercury lamp for 30 minutes.
Exposure at 00 mJ / cm ² and heat treatment at 100 ° C. for 1 hour and then at 150 ° C. for 5 hours have openings with excellent dimensional accuracy equivalent to a photomask film (via hole forming openings 48). An interlayer insulating material layer (adhesive layer) 50 having a thickness of 35 μm was formed (see FIG. 4 (Q)). Note that the tin plating layer was partially exposed in the opening serving as the via hole.

(17) The substrate on which the opening 48 for forming the via hole is formed is immersed in chromic acid for 20 minutes to dissolve and remove the epoxy resin particles present on the surface of the adhesive layer. Rmax is roughened to a depth of about 1 to 5 μm to form a roughened surface 51, which is then immersed in a neutralizing solution (manufactured by Shipley) and then washed with water (FIG. 4).
(R)).

(18) Roughening of the adhesive layer surface (roughening depth 5
By applying a palladium catalyst (manufactured by Atotech) to the substrate 30 subjected to (μm), catalyst nuclei were provided on the surfaces of the adhesive layer 50 and the via hole openings 48.

(19) The substrate was immersed in an electroless copper plating bath having the same composition as in the above (2) to form an electroless copper plating film 52 having a thickness of 0.6 μm on the entire roughened surface 51 (FIG. 4
(S)). At this time, since the electroless copper plating film 52 was thin, irregularities following the roughened surface 51 of the adhesive layer 50 were observed on the surface of the electroless plating film 52.

(20) A commercially available photosensitive dry film is adhered to the electroless copper plating film 52, and a mask is placed thereon.
Exposure was performed at 00 mJ / cm ² , development processing was performed with 0.8% sodium carbonate, and a plating resist 54 having a thickness of 15 μm was provided (see FIG. 4 (T)).

(21) Next, electrolytic copper plating was performed according to the above condition (6) to form an electrolytic copper plating film 56 having a thickness of 15 μm (see FIG. 5 (U)).

(22) The plating resist 56 is made of 5% KOH
Then, the electroless plating film 52 under the plating resist 56 is dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide to form a film comprising the electroless copper plating film 52 and the electrolytic copper plating film 56. A conductor circuit 58 and via holes 60U and 60D each having a thickness of 16 μm are formed (FIG. 5 (V)).
Subsequently, the conductor circuit 58 and the via holes 60U, 6
A roughened layer 62 was formed on the surface of 0D to obtain a three-layer package substrate on one side (see FIG. 5 (W)). The adhesive layer 5
Pd remaining on the roughened surface of chromic acid (800 g /
1) dipped for 1 to 10 minutes to remove.

(23) The steps (15) to (22) are repeated to further laminate one interlayer resin insulating layer 150 having via holes 160U and one interlayer resin insulating layer 150 having via holes 160D (FIG. 5 ( X)).

(24) A commercially available solder resist composition having a thickness of 20 μm was applied to both surfaces of the wiring board obtained in the above (23). Next, after drying at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, the substrate was exposed to ultraviolet light of 1000 mJ / cm ² and subjected to DMTG development. And then 8
1 hour at 0 ° C, 1 hour at 100 ° C, 1 hour at 120 ° C,
The heat treatment was performed at 150 ° C. for 3 hours, and the pad portion 71 was heated.
A solder resist layer (opening diameter: 200 μm) 70 (opening diameter: 200 μm) was formed (see FIG. 6).

(25) Next, the substrate 30 on which the solder resist layer 70 was formed was replaced with nickel chloride 30 g / l, sodium hypophosphite 10 g / l, and sodium citrate 10 g.
/ L of electroless nickel plating solution of pH = 5
By immersing for 5 minutes, a nickel plating layer 72 having a thickness of 5 μm was formed in the opening 71. Further, the substrate 30 was treated with 2 g / l of potassium gold cyanide, 75 g / l of ammonium chloride,
It was immersed in an electroless gold plating solution consisting of 50 g / l of sodium citrate and 10 g / l of sodium hypophosphite at 93 ° C. for 23 seconds to form a film having a thickness of 0.1 g on the nickel plating layer 72.
A gold plating layer 74 of 03 μm was formed.

(26) The solder resist layer 70
The solder paste is printed on the portion of the conductor circuit 158D where the opening 71, the chip capacitor C and the chip resistor (not shown) are mounted. Here, 9: 1 is used as the solder.
Solder is preferred. Thereafter, a chip capacitor C (manufactured by Murata Manufacturing, GRM36, 1 m long) is connected to the conductor circuit 158D.
m, width 0.5 mm, thickness 0.5 mm) and a chip resistor. Then, the solder bumps 76U and 76D are formed by reflow at 200 ° C.
Attach a chip capacitor C and a chip resistor to 58D. Thereafter, the substrate 20 is washed to remove the flux and the like melted from the solder 64 and the solder bumps 76U and 76D below the chip capacitor. As described above, the chip capacitor C is not embedded in the substrate but mounted on the surface, so that it can be easily attached.

Thereafter, as shown in FIG. 7, after the integrated circuit chip 90 is mounted on the package substrate 10, the package substrate 10 is mounted on the daughter board 94.

[0049]

As described above, according to the first aspect, the chip capacitor is mounted on the lower surface and directly below the integrated circuit chip. Therefore, the wiring distance from the chip capacitor to the integrated circuit chip is reduced. Since the length is shortened and the inductance of the wiring is reduced, a large current can be instantaneously supplied to the integrated circuit chip.

According to the second aspect, by connecting the via hole directly to the through hole, the wiring distance between the through hole and the via hole is reduced. Since the mounting component (chip capacitor) is mounted directly below the integrated circuit chip, the distance of the wiring from the chip capacitor to the integrated circuit chip is shortened, and the inductance of the wiring is reduced. A large current can be instantaneously supplied to the circuit chip.

According to the third aspect, since a high dielectric constant ceramic is used as the dielectric material of the chip capacitor, a high capacitance can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a manufacturing process of a package substrate according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a manufacturing process of the package substrate according to the embodiment of the present invention.

FIG. 3 is a diagram illustrating a manufacturing process of the package substrate according to the embodiment of the present invention.

FIG. 4 is a diagram illustrating a manufacturing process of the package substrate according to the embodiment of the present invention.

FIG. 5 is a diagram showing a manufacturing process of the package substrate according to the embodiment of the present invention.

FIG. 6 is a sectional view showing a package substrate according to the embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a state where an integrated circuit chip is mounted on the package substrate according to the embodiment of the present invention.

FIGS. 8A and 8B are cross-sectional views of a package substrate according to the related art.

DESCRIPTION OF SYMBOLS 10 Package substrate 16 Through hole 22 Filler 26a Conductive layer 30 Core substrate 50 Interlayer resin insulating layer 58 Conductive circuit (conductive layer) 60U, 60D Via hole 80A, 80B Build-up wiring layer 90 Integrated circuit chip 94 Daughter board (Substrate) 150 Interlayer resin insulation layer 160U, 160D Via hole C Chip capacitor (Mounted part)

Claims (3)

[Claims] 1. A package substrate in which an integrated circuit chip is mounted on an upper surface and a lower surface is mounted on the substrate side, wherein a mounting component is mounted on a lower surface side and directly below the integrated circuit chip. Package substrate. 2. A package substrate having an integrated circuit chip mounted on an upper surface and a lower surface mounted on the substrate side, wherein interlayer resin insulating layers and conductive layers are alternately laminated, and each conductive layer is formed by a via hole. In a package substrate in which connected build-up wiring layers are formed on both surfaces of a core substrate, a filler is filled into a through hole formed in the core substrate and the filler is exposed from the through hole. A conductive layer is formed to cover the surface, a via hole is connected to the conductive layer, and a mounting component is mounted on the lower surface of the package substrate, directly below the integrated circuit chip. Package substrate. 3. The package substrate according to claim 1, wherein said mounting component is a chip capacitor using ceramic as a dielectric material.