JP2001237510A - Printed-wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a printed-wiring board having a capacitor function in a substrate. SOLUTION: Outer and inner layer through holes 36 and 62 are oppositely arranged via a resin filler 40 for external layer through holes, thus forming a capacitor function. The resin filler 40 for external layer through holes is made of titanate or perovskite-family materials, thus increasing permittivity and achieving large capacitance as a capacitor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board whose front and back are electrically connected via through holes, and more particularly to a multilayer printed wiring formed by alternately building up a resin insulating layer and a conductive circuit layer. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board which is made of a board and can be suitably used for a package substrate on which electronic components such as IC chips are mounted.

[0002]

2. Description of the Related Art As the frequency of a signal becomes higher, the material of a package substrate is required to have a low dielectric constant and a low dielectric loss tangent. Therefore, the mainstream of the package substrate material is shifting from ceramic to resin. Against this background, as a technique relating to a printed wiring board using a resin substrate, for example, Japanese Patent Publication No. 4-55555
No. 5 discloses a method. First, epoxy acrylate is formed as an interlayer resin insulating layer on a glass epoxy substrate on which a circuit is formed. Subsequently, a lateral opening for a via hole is provided by using a photolithography technique. And
There has been proposed a so-called build-up multilayer printed wiring board in which a plating resist is provided after the surface is roughened, and a conductive circuit and a via hole are formed by plating. When such a build-up multilayer printed wiring board is used as a package board, it is connected to another board called a motherboard or a daughter board. Then, electronic components such as a resistor and a capacitor are mounted on a motherboard or the like, and wiring is connected to match electrical characteristics such as characteristic impedance.

[0003]

However, when the IC chip has a high frequency of 1 GHz or more, the wiring length from the IC chip to the capacitor becomes long in the capacitor arranged on the daughter board or the like, and the loss in the inductance increases. Therefore, an electric signal delay, an error, and the like occur. Further, since the wiring distance from the power supply to the power supply / ground of the IC chip is also increased, the loop inductance is increased. As a result, the IC chip did not work properly, and the function originally possessed could not be sufficiently exhibited.

Conventionally, a build-up multilayer printed wiring board having a built-in capacitor in a substrate is disclosed in, for example,
It is manufactured by the method disclosed in Japanese Patent No. 50272. A multilayer printed wiring board in which an organic resin insulating layer and a thin film wiring conductor are alternately laminated and electrically connected via a through-hole conductor, wherein at least one of the organic resin insulating layers has a metal filler and a relative dielectric constant. Contains 20 or more dielectric fillers. Then, the organic resin insulating layer is formed as a capacitor by being sandwiched between the thin film wiring conductors. This makes it possible to incorporate a capacitor function into the multilayer printed wiring board. Therefore, the number of components mounted on the multilayer printed wiring board is reduced, and the size of the hybrid integrated circuit device or the like can be reduced. However, in the capacitor forming area in the area facing the thin film wiring conductor,
It is not possible to form a wiring that penetrates and becomes a conductor. Therefore, it was not possible to increase the wiring density in that region.

In the method disclosed in JP-A-11-74648, a through hole or a non-through hole is formed in an insulating substrate. In addition, electronic components such as a chip capacitor and a chip resistor are stored and supported in the hole, and the electronic components are electrically connected through the inner wall of the hole. This makes it possible to reduce the size, weight, and thickness of the wiring board on which the electronic components are mounted. However, since the electronic component formed in the hole is electrically connected through the inner wall of the hole, it is difficult to provide a wiring serving as a conductor in the electronic component forming region. In addition, it is not possible to form a wiring that becomes a conductor by penetrating the electronic component housed and supported, because it leads to damage of the electronic component. Therefore, it has not been possible to increase the wiring density in the electronic component storage area.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a printed wiring board having a capacitor function in a substrate and capable of providing wiring at a high density. It is to propose.

[0007]

In order to solve the above-mentioned problems, in a printed wiring board according to the present invention, an outer layer through hole formed in a wall surface of a through hole of a substrate, and an outer layer resin filler in the outer layer through hole are provided. Capacitors are formed by the inner through holes formed therebetween.

In the printed wiring board of the present invention, a titanate or perovskite-based material is used as an outer resin filler provided between the outer through hole and the inner through hole. The titanate means an alloy material of a titanic acid and a metal, such as barium titanate, lead titanate, strontium titanate, calcium titanate, bismuth titanate, magnesium titanate, and the like.As a perovskite-based material, It means at least an alloy material that is at least MgxNybOz. Among them, barium titanate is preferably used. The reason is that the dielectric constant is easily adjusted, and separation and separation from the resin component of the resin filler other than the high dielectric substance hardly occur. The dielectric constant of the outer resin filler is increased by the above-mentioned materials, and the capacity as a capacitor is increased. In addition, since the outer layer through hole and the inner layer through hole formed in the through hole of the core substrate have a capacitor function, a printed circuit board having a built-in capacitor function, a high-density wiring, and excellent electrical characteristics can be obtained. .

Next, a process for manufacturing a multilayer printed wiring board in which a resin filler containing a high dielectric substance in a through hole and a plurality of conductor circuits are formed will be described. As a core substrate, a resin insulating substrate such as a glass epoxy substrate, a polyimide substrate, a BT (bismaleimide-triazine) resin substrate,
A ceramic substrate, a metal substrate, or the like can be used. A through hole for a through hole is formed in the core substrate by a laser such as a drill or a carbon dioxide laser. The core substrate preferably has a thickness of 0.4 to 1.2 mm. The reason is that there is strength as a core substrate and through holes are easily processed.

At this time, two types of through holes for through holes are formed, a through hole for conduction through holes and a through hole for outer layer through holes of coaxial through holes. Note that the coaxial through-hole includes an outer-layer through-hole and an inner-layer through-hole. The opening diameter of the through hole for the outer layer through hole is 200
It is preferable that the thickness be formed to be about 400 μm. Particularly desirable is 250 to 350 μm. If the diameter is less than 200 μm, the resin-filled layer cannot be formed of two or more layers, and the insulation between the conductor circuit formed therein and the conductor formed on the inner wall of the inner layer through hole cannot be maintained. 400μ
If it exceeds m, the effect of increasing the density will be offset. The diameter of the through hole for the through hole for conduction is 5
It is formed with a thickness of 0 to 400 μm. If it is less than 50 μm, it becomes difficult to form a conductor layer, and if it exceeds 400 μm, it becomes impractical. In particular, it is desirable that it is 0.6 to 1.0 mm.

Next, a resin filler is filled in the conduction through-hole and the outer layer through-hole. In some cases,
A roughening layer is provided in the conduction through-hole and the outer layer through-hole. The roughening layer is oxidation-reduction treatment, electroless plating,
It is formed by an etching process. Specifically, in the oxidation-reduction treatment, NaOH (10 g) was used as an oxidation bath.
/ L), NaClO ₂ (40 g / L), Na ₃ PO ₄ (6 g / L
L), NaOH (10 g / L), NaBH ₄ (6
g / L). In electroless copper plating, C
It is formed of an alloy made of u-Ni-P. As the etching treatment, an etching solution containing a cupric complex and an organic acid salt is used.

[0012] The resin filler for filling the through hole includes:
At least a resin component, a curing agent component, and a high dielectric substance are contained. Moreover, what mixed the organic resin filler and the inorganic filler with the resin filler may be used. The resin component may be a thermosetting resin, a thermoplastic resin, or a composite thereof. Particularly desirable is a thermosetting resin, which is easily mixed with a high dielectric substance and can be filled by printing. As the resin, epoxy resin,
A phenol resin, a polyimide resin, a fluorine resin, a polyphenylene resin, a polyolefin resin, or the like can be used. The outer layer through hole and the through hole for conduction may be filled with the same resin filler. Or resin,
It may be filled with different resin fillers having different composition ratios, viscosities and the like. It is desirable to charge the resin filler separately. The filling method is performed by printing, press fitting, or the like. It is preferable that the resin filler whose viscosity is adjusted is printed by using a mask having a through-hole portion opened. The resin filler is preferably adjusted to have a viscosity of about 30 to 200 Pa.s.

As described above, a titanate or perovskite-based material is preferably used as the high dielectric substance.

The curing component is an imidazole curing
Agent, phenolic curing agent, amine curing agent, etc.
be able to. In particular, the use of imidazole curing agents
desirable. As the imidazole curing agent, 2-methyli
Midazole (product name: 2MZ), 4-methyl-2-ethyl
Imidazole (product name: 2E4MZ), 2-phenylimid
Dazol (product name: 2PZ) 4-methyl-2-phenyli
Midazole (product name: 2P4MZ), 1-benzyl-2-
Methyl imidazole (product name: 1B2MZ), 2-methyl
Imidazole (product name: 2EZ), 2-isopropylimi
Dazol (product name: 2IZ), 1-cyanoethyl-2-e
Cyl-4-methylimidazole (product name; 2E4MZ-C
N), 1-cyanoethyl-2-undecylimidazole
(Product name; C ₁₁Z-CN). Above all, 25
It is desirable to use an imidazole hardener which is liquid at
For example, 1-benzyl-2-methylimidazole
(Product name: 1B2MZ), 1-cyanoethyl-2-ethyl
-4-Methylimidazole (product name; 2E4MZ-C
N), 4-methyl-2-ethylimidazole (product name; 2
E4MZ). This imidazole curing agent is
1 to 10% by weight in the content of the resin filler
desirable.

In addition, inorganic particles such as silica, alumina, mullite, and zirconia are preferable as the additive component.
The average particle diameter of the inorganic particles is desirably 0.05 to 5.0 μm. The amount of the inorganic particles is preferably about 1.0 to 2.0 times the amount of the bisphenol type epoxy resin. In addition, there is no particular problem in the grade of each chemical even if it is a special grade, a first grade, or an industrial reagent. By blending the additive component, the filling property in the through-hole is improved, and the coefficient of thermal expansion of the resin filler in the through-hole is matched, so that cracking and peeling are prevented.

After that, it is cured or semi-cured. In some cases, in order to improve the smoothness of the core substrate, buffs, belt sanders, physical polishing such as jet scrub, or acid or oxidizing agent, etc., even if the portion protruding from the through hole is removed by chemical etching Good. As a result, a core substrate composed of through holes and lands having conductivity with the resin filler containing a high dielectric substance is obtained.

The above-mentioned core substrate is provided with a resin insulating layer. A roughened layer may be formed on the conductor circuit. The resin insulating layer may be a thermosetting resin, a thermoplastic resin, a composite of a thermosetting resin and a thermoplastic resin, or a resin in which a photosensitive group is substituted. Specific examples include resins used for printed wiring boards, such as epoxy resins, phenol resins, polyimide resins, and phenoxy resins. Further, a resin having a low dielectric constant in a high frequency region may be used. In particular, it is preferable to use a polyolefin-based resin, a polyphenylene-based resin, a fluororesin, or the like, which is a resin having a dielectric constant at 1 GHz of 3.0 or less. For the formation of the resin insulating layer, it is preferable to apply or apply a B-stage film by heating, pressing, or heating and pressing.

Next, an opening serving as a via hole is formed in the resin insulating layer by photo and laser. Then, a through hole for an inner layer through hole is provided in the resin filler in the outer layer through hole via a resin insulating layer using a drill and a laser. When the opening serving as the via hole and the through hole for the inner layer through hole are formed by a laser, a carbon dioxide gas laser, an excimer laser, a UV laser, a YAG laser, or the like can be used. The diameter of the through hole for the inner layer through hole is 75 to
It is formed at 200 μm. Particularly desirable is 100-
150 μm. After that, a chemical etching process such as desmear and a dry etching process such as plasma and corona treatment are performed to remove the smear of the resin on the inner wall of the through hole for the inner layer through hole, and remove the resin residue to form the metal layer. Encourage.

Next, on the resin insulating layer, Cu and Cu are formed on the inner wall of the opening serving as the via hole and the inner wall of the through hole for the inner layer through hole.
Ni, P, Pd, Co, W, Au, Ag at least 1
At least one kind of metal layer is provided. The metal layer forms a capacitor as an electrode together with the conductive metal on the inner wall of the outer layer through hole. Thereby, the capacitor function can be built in the coaxial through hole. Its thickness is 0.1
Preferably, it is formed to a thickness of about 2 μm. The metal layer may be formed by plating, sputtering, or a two-layer structure in which plating is formed on a sputtered layer. The surface of the resin insulating layer may be provided with a roughened surface. The surface of the resin insulating layer is roughened by chemical etching with an acid or an oxidizing agent. As the acid, sulfuric acid, nitric acid, hydrochloric acid, phosphoric acid and the like, and as the oxidizing agent, chromic acid, chromate, permanganate and the like are suitable for forming a roughened surface. in addition,
The aforementioned metal layer is formed. Then, electroless plating is performed to form an electroless plating film on the metal layer.

A photosensitive resin film (dry film) is laminated on a substrate on which an electroless plating is applied to the inside of the opening serving as the via hole and the through hole for the outer layer through hole on the resin insulating layer. And, on this photosensitive resin film,
A photomask (preferably a glass substrate) on which a plating resist pattern is drawn is placed in close contact, exposed, and developed. Thus, a non-conductive portion on which the plating resist pattern is provided can be formed.

Electrolytic plating is applied to portions other than the non-conductive portion on the electroless plated film, and the conductive portion of the electroless plated film is
An electrolytic plating film is provided in an opening serving as a hole and a through hole for an inner layer through hole. As the electrolytic plating, it is desirable to use electrolytic copper plating, and its thickness is preferably 5 to 20 μm.

Next, the plating resist in the non-conductor circuit portion is removed with an alkaline aqueous solution or the like. Thereafter, the metal layer and the electroless plating film of the nonconductor circuit portion are further removed with an etching solution such as a mixed solution of sulfuric acid and hydrogen peroxide or sodium persulfate, ammonium persulfate, ferric chloride, or cupric chloride. . As a result, a conductive circuit and a via hole having two layers of an electroless plating film and an electrolytic plating film are obtained on the resin insulating layer. Further, in the through hole for the inner layer through hole, an inner layer through hole including a metal layer, an electroless plating film, and an electrolytic plating film is obtained. The via hole may form a flat field via.

Next, the gap in the inner through hole is filled. The filling may be performed by the above-described method, but when the insulating resin layer formed of a film is further formed on the upper layer, the insulating layer and the resin filler may be simultaneously formed. At least one of a resin filler, a resin filler containing a metal filler, copper, solder, nickel and the like is filled in the inner layer through hole. Further, an organic resin filler and an inorganic filler are added to a conventional resin filler in an amount of 0.1 to 20.
What mixed vol% may be used. The resin filler is preferably adjusted to have a viscosity of about 30 to 50 Pa.s.

As another method, an electrolytic plating film, an electroless plating film, or a composite plating film thereof is further laminated on the substrate obtained by electroless plating on the resin insulating layer. The substrate on which the plating film is laminated is filled with a resin filler. At that time, the plating film layer and the resin filler layer may be flattened by polishing after hardening or semi-hardening. After forming an etching resist, placing a mask on which wiring is drawn, exposing, developing, and forming a wiring layer of the resist, sulfuric acid-hydrogen peroxide solution, ferric chloride or cupric chloride, It may be performed by removing the plating film layer and removing the resist using an etching solution composed of an organic hydrochloric acid-cupric complex. As the etchant, all those used in the manufacture of printed wiring boards other than those described above can be used.

Further, it is also possible to divide the wiring to be formed by dividing the corresponding through hole. As a result, more wiring can be passed through the core substrate, and higher density can be achieved.

Further, by applying a resin insulating layer on the upper layer to form a conductor circuit and a via hole, a multilayer printed wiring board can be obtained. Then, a solder resist layer is formed on the surface layer. For the formation of the solder resist layer, it is preferable to apply the coating or the film by heating, pressurizing, or applying heat and pressure. The solder resist layer is provided with a solder pad by a photo and a laser, and Ni / Au, Ni / Pd / Au are provided on a portion exposed from the solder pad.
And the like to form a corrosion-resistant metal layer. When forming a solder pad with a laser, a carbon dioxide gas laser, an excimer laser,
A V laser, a YAG laser, or the like can be used. IC
The solder pads formed by the solder bumps for chip connection are opened with an opening diameter of 100 to 200 μm, and the solder pad portions where BGA / PGA are arranged for connecting external terminals are opened with an opening diameter of 300 to 650 μm.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. First, a configuration of a printed wiring board used as a package substrate according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 7 shows a package substrate 10 according to the first embodiment of the present invention.
FIG. FIG. 8 is an explanatory diagram illustrating a configuration of a through hole according to the first embodiment of the present invention.

The package substrate 10 has build-up wiring layers 80A and 80B formed on the front and back surfaces of the core substrate 30. The build-up wiring layers 80A and 80B are composed of the interlayer resin insulation layer 44 in which the conductor circuits 58 and the via holes 60 are formed, and the conductor circuits 158 and the via holes 160.
And an interlayer resin insulation layer 144 formed with the same. The build-up wiring layer 80A and the build-up wiring layer 80B
It is connected to the coaxial through hole 66 formed in the core substrate 30 via the through hole 34 for conduction. A solder resist layer 70 is formed on interlayer resin insulation layer 144, and solder bumps 76 </ b> U and 76 </ b> D are formed in conductive circuit 158 and via hole 160 via opening 71 of solder resist 70. 76U solder bump
Are connected to the pads 92 of the IC chip 90. On the other hand, the solder bump 76D is connected to the pad 9 of the daughter board 94.
6 is connected.

As shown in FIG.
Is composed of an outer layer through hole 36 and an inner layer through hole 62. The outer layer through-hole 36 and the inner layer through-hole 62 respectively connect the build-up wiring layer 80A and the build-up wiring layer 80B. The outer layer through hole 36 is formed on the wall surface of the through hole 33 of the core substrate 30 by the metal film 38.
Is formed. In the outer layer through hole 36, a resin filler 40 for the outer layer through hole containing a high dielectric substance is disposed. An inner through hole 62 is formed inside the outer layer through hole resin filler 40.

Next, the configuration of the inner layer through hole 62 will be described. As shown in FIG.
Are the metal layer 50, the electroless plating film 52, and the electrolytic plating film 5
6, three layers. Alternatively, it may be formed of two layers. The inside of the inner layer through hole 62 is filled with a resin filler 64 for the inner layer through hole. The inner-layer through-hole 62 becomes an electrode together with the outer-layer through-hole 36 via the resin filler 40 for the outer-layer through-hole containing a high dielectric substance, and forms a capacitor.

In the printed wiring board of the first embodiment, a titanate or perovskite-based material is used as the resin filler 40 for the outer layer through-hole. The titanate means an alloy material of a titanic acid and a metal, such as barium titanate, lead titanate, strontium titanate, calcium titanate, bismuth titanate, magnesium titanate, and the like.As a perovskite-based material, It means at least an alloy material that is at least MgxNybOz. Among them, barium titanate is preferably used. The reason is that the dielectric constant is easily adjusted, and separation and separation from the resin component of the resin filler other than the high dielectric substance hardly occur. The above materials increase the dielectric constant of the resin filler 40 for the outer layer through-hole, thereby increasing the capacitance as a capacitor.

Further, it is possible to form more through holes in the substrate than in a conventional substrate having a built-in capacitor. Therefore, it is possible to obtain a printed wiring board which has a capacitor function, has a high density of wirings, and has excellent electrical characteristics.

Subsequently, according to the first embodiment of the present invention,
A method for manufacturing the package substrate 10 will be described.
Here, first, A.I. used in the method of manufacturing the package substrate is described. B. Resin filler for through hole for conduction, B. Resin filler for outer layer through hole, C.I. The composition of the resin filler for the inner layer through hole will be described.

A. Resin filler for through-hole for conduction [Resin composition] 100 parts by weight of bisphenol F type epoxy monomer (manufactured by Yuka Shell, molecular weight 310, YL983U), SiO with average particle diameter 1.6 μm coated on the surface with a silane coupling agent ₂ spherical particles (Admatech, CRS
1101-CE, where the maximum particle size is 170 parts by weight of the inner layer copper pattern described below (15 μm or less) and 1.5 parts by weight of a leveling agent (manufactured by San Nopco, Perenol S4) by stirring and mixing. The viscosity of the mixture is 23 ±
It was obtained by adjusting to 45,000 to 49,000 cps at 1 ° C. [Curing agent composition] Imidazole curing agent (Shikoku Chemicals,
2E4MZ-CN) 6.5 parts by weight.

B. It is almost the same as the resin filler A for the outer layer through hole, but contains barium titanate (10 parts by weight in which a particle size of 5 μm and 10 μm is mixed) in the [resin composition].

C. Resin filler for inner layer through hole A. The same thing as the resin filler for the through hole for conduction was used.

Next, a method of manufacturing the package substrate 10 according to the first embodiment of the present invention will be described with reference to FIGS.

Manufacturing of package substrate (1) Glass epoxy resin or BT having a thickness of 0.8 mm
Substrate 30 made of (bismaleimide-triazine) resin
The starting material is a copper-clad laminate 30A in which copper foils 31 of 12 μm are laminated on both sides of the substrate (FIG. 1 (A)). First, the copper-clad laminate 30A is drilled with a drill to have a diameter of 35 mm.
0 μm through hole 32 for conduction and a diameter of 350 μm
m through-holes 33 for outer layer through holes (FIG. 1)
(B)). The opening diameter of the through hole 33 for the outer layer through hole is
The thickness is preferably 200 to 400 μm. Particularly desirable is 250 to 350 μm. Further, the opening diameter of the through hole 32 for the through hole for conduction is preferably formed in the range of 50 to 400 μm.

(2) Subsequently, the substrate 30 is subjected to an electroless copper plating process to form a through hole 34 for conduction and an outer layer through hole 36 (FIG. 1C). Furthermore, copper foil 31
By etching on the pattern according to the usual method,
An inner copper pattern (metal film) 38 is formed on both surfaces of the substrate 30 (FIG. 1D).

(3) The substrate 30 on which the inner layer copper pattern (metal film) 38, the conduction through hole 34, and the outer layer through hole 36 are formed is washed with water and dried. Then, NaOH (10 g / l), NaClO ₂ (4
0 g / l), Na ₃ PO ₄ (6 g / l), NaO as a reducing bath
Oxidation using H (10 g / l) and NaBH ₄ (6 g / l)
By the reduction treatment, roughened layers 34α, 36α, and 38α are provided on the surfaces of the inner layer copper pattern (metal film) 38, the conduction through hole 34, and the outer layer through hole 36. Although the roughened layer is provided in the embodiment, it is not necessary to provide the roughened layer if the adhesion of the resin can be ensured (FIG. 1E).

(4) The through hole 34 for conduction and the outer layer through hole 36 are filled with a resin filler. First, the outer layer through hole 36 is filled with the resin filler 40 for the outer layer through hole adjusted by the above B by printing (FIG. 2A). B
It is preferable to use a titanate or a perovskite-based material as the high dielectric substance contained in. As titanates,
It means an alloy material of titanic acid and a metal, such as barium titanate, lead titanate, strontium titanate, calcium titanate, bismuth titanate, magnesium titanate, and the like.
It means all alloy materials that are gxNybOz. Among them, barium titanate is preferably used. The reason is that the dielectric constant is easily adjusted, and separation and separation from the resin component of the resin filler other than the high dielectric substance hardly occur. Further, it is preferable to adjust the viscosity of the resin filler so as to be about 30 to 50 Pa.s. Next, the conductive through-hole 34 is filled with the conductive through-hole resin filler 42 adjusted in the above A (FIG. 2B).

(5) The substrate 30 after the processing of the above (4)
The outer layer is formed on the surface of the lower conductive circuit (inner copper pattern) 38, the through holes 34 for conduction, and the lands 34a, 36a of the outer layer through holes 36 by belt sanding using belt polishing paper (manufactured by Sankyo Rikagaku Co., Ltd.). Polishing is performed so that the resin filler for through-holes 40 and the resin filler for conductive through-holes do not remain, and then buffing is performed to remove scratches due to the belt sander polishing.
Such a series of steps is similarly performed on the other surface of the substrate, and the filled outer layer through-hole resin filler 40 and conductive through-hole resin filler 42 are cured by heating (FIG. 2C). ).

(6) Next, on both surfaces of the substrate 30 after the processing of (5), the surface of the lower conductive circuit 38 once flattened in the same manner as in (3), the conduction through hole 34 and the outer layer The surfaces of the lands 34a, 36a of the through hole 36 are subjected to oxidation-reduction treatment, whereby the surfaces of the lower conductor circuit 38 and the surfaces of the lands 34a, 36a are roughened surfaces 34β, 3
6β and 38β are formed (FIG. 2D).

(7) A thermosetting polyolefin resin sheet having a thickness of 50 μm is applied to both surfaces of the substrate 30 after the step (6), while heating the temperature to a temperature of 50 to 150 ° C. and a pressure of 5 k.
g / cm ² and vacuum lamination to provide an interlayer resin insulation layer 44 made of a polyolefin resin.
(E)). As the resin insulating layer, a resin made of a thermosetting resin or a thermoplastic resin, or a resin obtained by substituting a photosensitive group into them may be used. Specific examples include resins used for printed wiring boards, such as epoxy resins, polyphenol resins, and polyimide resins. Further, a resin having a low dielectric constant in a high frequency region may be used. The degree of vacuum at the time of vacuum compression bonding of the resin is 10 mmHg.

(8) Next, an opening 46 to be a via hole is formed in the interlayer resin insulating layer 44 (FIG. 3A). The carbon dioxide (CO ₂ ) gas laser was used for the formation, and the beam diameter was 5 mm
Under the conditions of a pulse width of 15 μs, a mask hole diameter of 0.8 mm, and one shot, a via hole opening having a diameter of 80 μm is provided in the interlayer resin insulating layer 44 made of a polyolefin resin or an epoxy resin.

Thereafter, a through hole 48 for an inner layer through hole is formed in the outer layer through hole 36 by a drill, a laser, or the like (FIG. 3B). In the case of laser, carbonic acid (C
O ₂ ) A gas laser with a beam diameter of 5 mm, a single mode, a pulse width of 60 μs, a through hole 48 penetrating through the resin filler 40 for the outer layer through hole containing a high dielectric substance and the interlayer resin insulating layer 44 of the core substrate. Form. If necessary, the smear in the through hole 48 for the inner layer through hole is removed by a wet process such as permanganic acid or a dry etching process such as a plasma or corona treatment. Also,
The diameter of the through hole 48 for the inner layer through hole is 50 to 200 μm.
m.

(9) A plasma treatment is performed on the substrate 30 in which the opening 46 to be a via hole is formed in the interlayer resin insulating layer 44 to roughen the surface layer of the interlayer resin insulating layer 44 and to make the roughened layer 44α
Is formed (FIG. 3C). At this time, argon gas was used as an inert gas, electric power 200 W, gas pressure 0.6 P
a, Plasma processing is performed for 2 minutes at a temperature of 70 ° C. (plasma apparatus SV-4540 manufactured by Nippon Vacuum Engineering Co., Ltd.).

(10) Cu is sputtered into the surface layer of the interlayer resin insulating layer 44 and the through hole 48 for the inner layer through hole by sputtering.
A metal layer 50 targeting an alloy of (Ni, P, Pd, Co, W) is formed (FIG. 3D). As the forming conditions, the pressure is 0.6 Pa, the temperature is 80 ° C., the power is 200 W, and the time is 5 minutes (plasma apparatus SV-4 manufactured by Nihon Vacuum Engineering Co., Ltd.).
540). Thereby, the interlayer resin insulation layer 44
An alloy layer can be formed on the surface layer and the through-hole 48 for the inner layer through-hole. The metal layer 50 constitutes a capacitor together with the outer through hole 36 as an electrode. At this time, the thickness of the metal layer 50 is 0.2 μm. Metal layer 50
Is preferably 0.1 to 2 μm. In addition to sputtering, it is also possible to perform the deposition or to form a plating layer without performing the sputtering.

(11) The substrate 30 is conditioned, and a catalyst is applied in an alkaline catalyst solution for 5 minutes. Substrate 3
0 is activated, and an electroless plating film 52 having a thickness of 0.5 μm is formed in a Rochelle salt type chemical copper plating bath (FIG. 4A). Plating conditions for chemical copper plating: CuSO ₄ .5H ₂ O 10 g / l HCHO 8 g / l NaOH 5 g / l Rochelle salt 45 g / l Additive 30 ml / l Temperature 30 ° C. Plating time 18 minutes

(12) On the electroless plating film 52, the thickness 2
Attach a 0 μm photosensitive film (dry film), mount a mask, and expose at 100 mJ / cm ² , 0.8%
Developing with sodium carbonate, a plating resist 54 having a thickness of 20 μm is provided (FIG. 4B).

(13) Electroplating is performed on the non-formed portion of the plating resist 54 on the electroless plating film 52 to form an electroplating film 56 (FIG. 4C). The thickness of the electrolytic plating film 56 is preferably 5 to 20 μm. _{CuSO 4 · 5H 2 O 140g /} l H 2 SO 4 120g / l Cl - 50mg / l additive 300 mg / l acid amine 100 mg / l Temperature 25 ° C. Current density 0,8A / dm ² plating time 30 minutes the film thickness 18μm

(14) Then, at 50 ° C., 40 g / l of N
The plating resist 54 is peeled off in an aOH aqueous solution.
Thereafter, the metal layer 50 and the electroless plating film 52 under the resist 54 are removed by etching using a sulfuric acid-hydrogen peroxide aqueous solution, and the conductive circuit 58 is formed on the interlayer resin insulating layer 44.
(Including the via hole 60), and the inner layer through hole 62 is formed in the outer layer through hole 36 (FIG. 4).
(D)). The inner-layer through-hole 62 becomes an electrode together with the outer-layer through-hole 36 via the resin filler 40 for the outer-layer through-hole containing a high dielectric substance, and forms a capacitor.

(15) Next, similarly to the steps (3) to (5), the inner layer through hole 62 is also filled with the resin filler 64 for the inner layer through hole C described above. It is preferable that the viscosity of the resin filler 64 for the inner layer through hole is adjusted so as to be about 30 to 50 Pa.s. Further, it is preferable to lower the viscosity of the resin filler 64 for the inner layer through-hole than the resin filler 40 for the outer layer through-hole to improve the filling property. Thus, a coaxial through hole 66 including the outer layer through hole 36 and the inner layer through hole 62 can be formed (FIG. 5A).

(16) Thereafter, the interlayer resin insulating layer 1
44, and the conductor circuit 158 (including the through hole 160) is formed through the steps (8) to (15) described above.
A package substrate consisting of six layers is obtained (FIG. 5B).

(17) On the other hand, 46.67 g of a photosensitizing oligomer (molecular weight 4000) in which 60% by weight of a cresol novolac type epoxy resin (manufactured by Nippon Kayaku) dissolved in DMDG was acrylated with 50% of epoxy groups, 15.0 g of 80% by weight bisphenol A type epoxy resin (manufactured by Yuka Shell, Epicoat 1001) dissolved in methyl ethyl ketone, imidazole curing agent (manufactured by Shikoku Chemicals, trade name: 2E4MZ-C)
N) 16 g, 3 g of a polyacrylic monomer (R604, manufactured by Nippon Kayaku), which is a photosensitive monomer, and 1.5 g of a polyvalent acrylic monomer (DPE6A, manufactured by Kyoeisha Chemical Co., Ltd.). -65) was mixed with 0.71 g, and 2 g of benzophenone (manufactured by Kanto Kagaku) as a photoinitiator and 0.2 g of Michler's ketone (manufactured by Kanto Kagaku) as a photosensitizer were added to the mixture to give a viscosity of 25. 2.0Pa at ℃
s is obtained. The viscosity was measured at 60 rpm using a B-type viscometer (Tokyo Keiki, DVL-B type).
For rotor No.4, for 6 rpm, rotor No.3.

(18) The solder resist composition is applied to both sides of the package substrate obtained in the above (17) by 20 μm.
Apply with a thickness of Next, after performing a drying process at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, a 5 mm-thick photomask film on which a circular pattern (mask pattern) is drawn is placed in close contact with the substrate, and 1000 mJ / cm ^2. Exposure with UV light, DM
Perform TG development. And then at 80 ° C for 1 hour at 100 ° C
For 1 hour, at 120 ° C. for 1 hour, and at 150 ° C. for 3 hours, to form a solder resist layer 70 (thickness: 20 μm) having openings 71U and 71D in solder pad portions (including via holes and their land portions). (FIG. 5)
(C)). The solder pads for forming the solder bumps for connecting the IC chip are preferably opened with an opening diameter of 100 to 170 μm. Further, it is preferable that the solder pads for disposing BGA / PGA for connecting external terminals are opened with an opening diameter of 300 to 650 μm.

(19) Then, nickel chloride 2.3 × 10
^-1 mol / l, sodium hypophosphite 2.8 × 10 ^-1 m
ol / l, sodium citrate 1.6 × 10 ⁻¹ mol /
immersed in an electroless nickel plating solution having a pH of 4.5 for 20 minutes and a thickness of 5 μm was applied to the openings 71U and 71D.
The nickel plating layer 72 of m is formed. Then, on the surface layer, potassium cyanide 7.6 × 10 ⁻³ mol / l, ammonium chloride 1.9 × 10 ⁻¹ mol / l, sodium citrate 1.2 × 10 ⁻¹ mol / l, sodium hypophosphite 1.
80 ° C for electroless gold plating solution consisting of 7 × 10 ^-1 mol / l
The gold plating layer 74 having a thickness of 0.03 μm is formed on the nickel plating layer 72 by immersion for 7.5 minutes under the condition of FIG.
(D)).

(20) The solder resist layer 70
Solder paste is printed as a low-melting metal in openings 71U and 71D, and reflowed at 200 ° C. to form solder bumps (solder bodies) 76U and 76D, thereby completing package substrate 10 (see FIG. 6). .

The IC chip 90 is mounted on the solder bumps 76U of the completed package substrate 10 so that the pads 92 of the IC chip 90 correspond to the solder bumps 76U.
The package substrate 10 on which the IC chip 90 is mounted is
It is placed so as to correspond to the bump 96 on the daughter board 94 side, reflowed, and attached to the daughter board 94 (see FIG. 7). Thereby, the BGA is provided,
It is possible to obtain a package substrate which has a capacitor function, has a high density of wirings, and has excellent electrical characteristics.

In the method of manufacturing the package substrate 10 according to the first embodiment of the present invention, the case where the BGA is provided is illustrated, but PGA may be provided. The steps (1) to (19) are the same when the PGA is provided. The subsequent steps will be described. First, the opening 7 on the lower surface side of the substrate (connection surface with the daughter board and the motherboard)
A solder paste is printed as a conductive adhesive 78 in 1D. Next, the conductive connection pin 90 is attached to and supported by an appropriate pin holding device, and the fixing portion 92 of the conductive connection pin 90 is brought into contact with the conductive adhesive 78 in the opening 71D. Then, reflow is performed to fix the conductive connection pins 90 to the conductive adhesive 78. In addition, as a method of attaching the conductive connecting pin 90, a conductive adhesive 78 formed in a ball shape or the like is put into the opening 71D, or the fixing portion 9 is attached.
2 with a conductive adhesive 78 to form conductive connecting pins 90.
May be attached and then reflowed. A solder bump 76 is provided in the opening 71U on the upper surface, the solder bump 76 is placed so as to correspond to the pad 92 of the IC chip 90, and reflow is performed to mount the IC chip 90.
(See FIG. 9). This makes it possible to obtain a package substrate having a capacitor function in which the PGA is provided, having a higher density, and having excellent electrical characteristics.

(Second Embodiment) FIG. 11 shows the structure of a printed wiring board according to a second embodiment, and FIG. 12 shows an enlarged view of the through hole in FIG. The printed wiring board of the second embodiment is almost the same as the first embodiment. However, in the second embodiment, the lid plated portion 94 is formed directly above the inner layer through hole 62, and the inner layer through hole 62 and the upper conductive circuit 158 are connected via the lid plated portion 94. By interposing the cover plating portion 94, the connectivity between the inner layer through hole 62 and the upper conductive circuit 158 is improved. In addition, also when the cover plating part 94 is provided, (1)-
The manufacturing steps up to (15) are the same as in the first embodiment.
The subsequent manufacturing steps will be described with reference to FIG.

(16) The substrate is subjected to electroless plating to form an electroless plated film 68 (FIG. 10A).

(17) Next, after a resist 67 having a predetermined pattern is formed on the substrate, electrolytic plating is performed to form an electrolytic plating film 69 (FIG. 10B). Then, after removing the resist 67, the electroless plating film 6 under the resist 67 is removed.
8 is removed by light etching, so that the electroless plating film 68 and the electrolytic plating film 69
Is formed (FIG. 10C).

(18) Thereafter, the interlayer resin insulating layer 1
44, and (8) to (1) described in the first embodiment.
4), the conductor circuit 158 (through hole 16)
0 is formed, and a package substrate composed of six layers is obtained (FIG. 10D). Note that the subsequent manufacturing steps are the same as (17) to (20) of the first embodiment.

(Third Embodiment) FIG. 13 shows a configuration of a printed wiring board according to a third embodiment, and FIG. 14 shows an enlarged view of the through hole in FIG. The printed wiring board of the third embodiment is almost the same as the first embodiment. However, in the first embodiment, the inner layer through hole 62 is filled with the resin filler 64 for the inner layer through hole, but in the third embodiment, the inner layer through hole 62 is filled by plating.

In the structure of the first and second embodiments, by filling the inner layer through hole 62 with the resin filler 64 for the inner layer through hole, the stress generated in the inner layer through hole 62 is reduced by the resin filler for the inner layer through hole. It can escape to the 64 side. On the other hand, in the third embodiment, the inner layer through-holes 62 are filled with copper plating, so that the diameter can be reduced and the manufacturing cost can be reduced.

(Fourth Embodiment) A manufacturing process of a printed wiring board according to a fourth embodiment will be described with reference to FIGS. (1) 0.8mm thick glass epoxy resin or BT
Substrate 30 made of (bismaleimide-triazine) resin
The starting material is a copper-clad laminate 30A in which 12 μm copper foils 31 are laminated on both sides of the substrate (FIG. 15A). First, the copper-clad laminate 30A is drilled with a drill to have a diameter of 35 mm.
0 μm through hole 32 for conduction and a diameter of 350 μm
m through-holes 33 for outer through-holes are formed (FIG. 15).
(B)).

(2) Subsequently, the substrate 30 is subjected to an electroless copper plating process to form an electroless plated film 37a (FIG. 15).
(C)). (3) An electric current is passed through the electroless plating film 37a to form the electrolytic plating film 37b, whereby the conduction through hole 34 is formed in the conduction through hole through hole 32 and the outer layer is formed in the outer layer through hole 33. A through hole 36 is formed (FIG. 15D).

(4) The through hole 34 for conduction and the through hole 36 in the outer layer are filled with a resin filler. First, the outer layer through hole 36 is filled with the same outer layer through hole resin filler 40 as in the first embodiment by printing (FIG. 15).
(E)).

(5) Next, the through-hole for conduction 34 is filled with the resin filler for through-hole for conduction 42 adjusted in A above (FIG. 16 (A)).

(5) One surface of the substrate 30 is subjected to belt sander polishing using belt polishing paper (manufactured by Sankyo Rikagaku Co., Ltd.), so that the surface of the core substrate 30 has a resin filler 4 for an outer layer through hole.
0, polishing is performed so that the resin filler 42 for through holes for conduction does not remain, and then buffing is performed to remove the scratches caused by the belt sander polishing (FIG. 16B).

(6) An etching resist is applied, a mask (not shown) on which wiring is drawn is placed, and exposure and development are performed to form a resist layer 39 (FIG. 16C).

(7) Using an etching solution comprising sulfuric acid-hydrogen peroxide solution, ferric chloride or cupric chloride, or an organic hydrochloric acid-cupric complex, the plating film 37a on which the resist layer 39 is not covered, 37b, the copper foil 31 is removed. After that, the resist layer 39 is peeled off (FIG. 16D). In addition, as the etchant, all those used in the manufacture of printed wiring boards other than those described above can be used. Subsequent steps are the same as those in the first embodiment described above with reference to FIGS.

(Fifth Embodiment) The fifth embodiment is almost the same as the first embodiment.
And two wiring paths 36A, 36B and 62
A and 62B are formed (see FIG. 17). Since a plurality of wiring paths are provided in one through hole, more wiring can be passed through the core substrate,
High density can be achieved.

[0075]

According to the present invention, by forming the above-described two layers of through holes, the number of wirings penetrating the front and back of the core substrate can be increased, and the density of the printed wiring board can be increased. . Also, in order to form a high dielectric layer in the through hole and function as a capacitor,
Even when an IC chip in a high-frequency region of GHz or more is mounted, malfunctions and functional stops can be prevented.

[Brief description of the drawings]

FIG. 1 (A), (B), (C), (D), (E)
It is a manufacturing process figure of the package board concerning a 1st embodiment of the present invention.

FIG. 2 (A), (B), (C), (D), (E)
It is a manufacturing process figure of the package board concerning a 1st embodiment of the present invention.

FIGS. 3A, 3B, 3C, and 3D are manufacturing process diagrams of the package substrate according to the first embodiment of the present invention.

FIGS. 4A, 4B, 4C, and 4D are manufacturing process diagrams of the package substrate according to the first embodiment of the present invention.

FIGS. 5A, 5B, 5C, and 5D are manufacturing process diagrams of the package substrate according to the first embodiment of the present invention.

FIG. 6 is a sectional view of the package substrate according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a state in which an IC chip is mounted on the package substrate according to the first embodiment of the present invention and attached to a daughter board.

FIG. 8 is an explanatory diagram showing a configuration of a through hole according to the first embodiment of the present invention.

FIG. 9 is a sectional view of the package substrate according to the first embodiment of the present invention.

FIGS. 10A, 10B, 10C, and 10D are manufacturing process diagrams of a package substrate according to a second embodiment of the present invention.

FIG. 11 is a sectional view of a package substrate according to a second embodiment of the present invention.

FIG. 12 is an explanatory diagram showing a configuration of a through hole according to a second embodiment of the present invention.

FIG. 13 is a sectional view of a package substrate according to a third embodiment of the present invention.

FIG. 14 is an explanatory diagram showing a configuration of a through hole according to a third embodiment of the present invention.

FIG. 15 (A), (B), (C), (D), (E)
FIG. 14 is a manufacturing process diagram of the package substrate according to the fourth embodiment of the present invention.

FIGS. 16A, 16B, 16C, and 16D are manufacturing process diagrams of a package substrate according to a fourth embodiment of the present invention.

FIG. 17 is a sectional view of a package substrate according to a fifth embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 30 core substrate 34 conduction through hole 36 outer layer through hole 38 inner layer copper pattern 40 outer layer through hole resin filler 42 conduction through hole resin filler 44 interlayer resin insulation layer 48 inner layer through hole through hole 50 metal layer 52 none Electroplating film 56 Electroplating film 58 Conductor circuit 60 Via hole 62 Inner layer through hole 64 Resin filler for inner layer through hole 66 Coaxial through hole 70 Solder resist layer 71 Opening 72 Nickel plating layer 74 Gold plating layer 76U, 76D Solder bump 78 Conductive adhesive 80A, 80B Build-up wiring layer 90 Conductive connection pin 92 Fixed part 94 Cover plating part 144 Interlayer resin insulation layer 158 Conductor circuit 160 Via hole

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Hiroshi Segawa 1-1, Ibikawa-cho, Ibi-gun, Gifu Prefecture F-term in Ogaki-Kita Plant (reference) 4E351 BB03 BB26 BB29 BB49 DD01 DD41 DD42 GG20 5E317 AA24 BB01 BB11 CC31 CC53 CD32 CD34 GG14 5E346 AA12 AA13 AA15 AA42 AA43 AA45 BB01 BB20 CC21 DD07 EE31 EE38 FF04 FF45 GG15 GG17 GG27 HH01 HH25

Claims (6)

[Claims] 1. A printed wiring board in which front and back surfaces are electrically connected via a through hole, wherein the through hole includes an outer layer through hole formed on a wall surface of the through hole of the substrate, and an outer layer formed in the outer layer through hole. A printed wiring board comprising: an inner layer through hole formed with a resin filler interposed; and an inner layer resin filler filled in the inner layer through hole, wherein the outer layer resin filler contains titanate. . 2. A printed wiring board in which the front and back surfaces are electrically connected via a through hole, wherein the through hole is an outer layer through hole formed on a wall surface of the through hole of the substrate, and an outer layer is formed in the outer layer through hole. A printed wiring board comprising an inner layer through hole formed with a resin filler interposed therebetween, wherein the outer layer resin filler contains titanate. 3. The method according to claim 2, wherein the titanate is barium titanate,
3. The printed wiring board according to claim 1, wherein the printed wiring board is at least one of lead titanate, strontium titanate, calcium titanate, bismuth titanate, and magnesium titanate. 4. A printed wiring board in which the front and back surfaces are electrically connected via a through hole, wherein the through hole includes an outer layer through hole formed on a wall surface of the through hole of the substrate, and an outer layer formed in the outer layer through hole. A printed wiring board comprising: an inner layer through hole formed with a resin filler interposed; and an inner layer resin filler filled in the inner layer through hole, wherein the outer layer resin filler contains a perovskite-based material. . 5. A printed wiring board in which front and back surfaces are electrically connected via a through hole, wherein the through hole includes an outer layer through hole formed in a wall surface of the through hole of the substrate, and an outer layer formed in the outer layer through hole. A printed wiring board comprising: an inner layer through hole formed with a resin filler interposed; and the outer layer resin filler contains a perovskite-based material. 6. The perovskite-based material is MgxNy.
The printed wiring board according to claim 4, wherein the printed wiring board is bOz.