JP4947121B2 - Multilayer printed wiring board - Google Patents

Description

  The present invention relates to a multilayer printed wiring board, and improves electrical characteristics and reliability without causing malfunction or error even when a high-frequency IC chip, particularly an IC chip in a high-frequency region of 3 GHz or more is mounted. We propose a multilayer printed wiring board that can be used.

  In a build-up type multilayer printed wiring board that constitutes a package for an IC chip, an interlayer insulating resin is formed on both sides or one side of a core substrate in which a through hole is formed, and a via hole for interlayer conduction is formed by laser or photo. Opening is performed by etching to form an interlayer resin insulation layer. A conductor layer is formed on the via hole by plating or the like, and a pattern is formed through etching or the like to create a conductor circuit. Furthermore, a build-up multilayer printed wiring board can be obtained by repeatedly forming an interlayer insulating layer and a conductor layer. If necessary, by forming solder bumps and external terminals (PGA / BGA, etc.) on the surface layer, a substrate or package substrate on which an IC chip can be mounted is obtained. The IC chip is electrically connected between the IC chip and the substrate by performing C4 (flip chip) mounting.

  As conventional techniques of the build-up type multilayer printed wiring board, there are Patent Document 1, Patent Document 2, and the like. Both lands are formed on the core substrate filled with the filling resin with through holes, an interlayer insulating layer having via holes on both sides is applied, a conductor layer is applied by an additive method, and connected to the lands, A multilayer printed wiring board on which high density and fine wiring are formed can be obtained.

JP-A-6-260756 JP-A-6-275959 JP 2000-156565 A JP 2000-244130 A JP 2000-299404 A

  However, the frequency of malfunctions and errors has increased as IC chips have increased in frequency. In particular, since the frequency exceeds 3 GHz, the degree is increasing. When it exceeded 5 GHz, it sometimes stopped moving at all. For this reason, a computer having the IC chip as a CPU can no longer perform desired functions and operations such as image recognition, switch switching, and data transmission to the outside.

  When non-destructive inspection and disassembly of these IC chips and substrates are desired, the IC chip and the substrate itself are free from problems such as short circuit and open, and an IC chip with a low frequency (particularly less than 1 GHz) is mounted. There were no malfunctions or errors.

  The present invention has been made to solve the above-described problems, and its object is to constitute an IC chip in a high frequency region, particularly a printed circuit board or a package board that does not cause malfunction or error even if it exceeds 3 GHz. It is to propose a multilayer printed wiring board that can be used.

As a result of intensive research aimed at realizing the above object, the inventors have come up with an invention having the following contents as a gist. That is,
The present invention relates to a multilayer printed wiring board in which an interlayer insulating layer and a conductor layer are formed on a core substrate and are electrically connected via via holes. The thickness of the conductor layer of the core substrate is determined by interlayer insulation. The multilayer printed wiring board is characterized by being thicker than the thickness of the conductor layer on the layer.

  As a first effect, by increasing the thickness of the conductor layer of the power supply layer of the core substrate, the strength of the core substrate is increased, and even if the core substrate itself is thinned, warping and the generated stress are alleviated by the substrate itself. Is possible.

  As a second effect, by increasing the thickness of the conductor layer, the volume of the conductor itself can be increased. By increasing the volume, the resistance in the conductor can be reduced. For this reason, electrical transmission such as a flowing signal line is not hindered. Therefore, no loss occurs in the transmitted signal. This is achieved by increasing the thickness of only the substrate serving as the core.

  As a third effect, the power supply capability to the IC chip can be improved by using the conductor layer as the power supply layer. Further, by using the conductor layer as the ground layer, it is possible to reduce the signal superimposed on the signal to the IC chip and the noise superimposed on the power source. The ground for this is that the reduction in the resistance of the conductor described in the second effect does not hinder the supply of power. Therefore, when an IC chip is mounted on the multilayer printed board, the loop inductance from the IC chip to the board to the power source can be reduced. For this reason, the shortage of power supply in the initial operation is reduced, so that the shortage of power supply is less likely to occur. Therefore, even if an IC chip in a high frequency region is mounted, malfunctions and errors at the initial start-up are not caused.

  The same effect can be obtained when power is supplied to the IC chip via the IC chip to the substrate to the capacitor or the power supply layer to the power source. The aforementioned loop inductance can be reduced. Therefore, no loss occurs in the power supply of the capacitor or the dielectric layer. In the first place, an IC chip consumes power instantaneously, and complicated arithmetic processing and operations are performed. Even if an IC chip in a high frequency region is mounted by supplying power to the IC chip from the power supply layer, the power supply is not mounted without mounting a large amount of capacitors in response to a power shortage in the initial operation (a situation where a voltage drop occurs). Can be supplied. In the first place, in order to use an IC chip in a high frequency region, power shortage (voltage drop) at the time of initial operation occurs. However, the capacity of the capacitor or dielectric layer supplied in the conventional IC chip is sufficient.

  In particular, when the thickness of the conductor layer used as the power supply layer of the core substrate is thicker than the thickness of the conductor layer on the interlayer insulating layer on one or both sides of the core substrate, the above three effects are maximized. Can do it. In this case, the conductor layer on the interlayer insulating layer is a via hole that is a non-through hole for connecting the layers to the interlayer resin insulating layer formed of a resin not impregnated with the core material in the insulating layer. It mainly means a conductor layer formed by plating, sputtering, or the like. Other than this, there is no particular limitation, but any via hole formed corresponds to the above conductor layer.

The power supply layer of the core substrate may be disposed on the surface layer, the inner layer, or both of the substrate. In the case of the inner layer, it may be multi-layered over two or more layers. Basically, if the power layer of the core substrate is thicker than the conductor layer of the interlayer insulating layer, the effect is obtained.
However, it is desirable to form in the inner layer. When formed in the inner layer, the power supply layer is disposed between the IC chip and the external end or the capacitor. Therefore, both distances are uniform, the cause of obstruction is reduced, and power shortage can be suppressed.

Further, in the present invention, in the multilayer printed wiring board in which the interlayer insulating layer and the conductor layer are formed on the core substrate and are electrically connected through the via hole,
The multilayer printed wiring board is characterized in that α2 <α1 ≦ 40α2 with respect to α1 for the thickness of the conductor layer on the core substrate and α2 for the thickness of the conductor layer on the interlayer insulating layer.

In the case of α1 ≦ α2, there is no effect on power shortage. In other words, it is not clear to suppress the degree of voltage drop that occurs during initial operation.
The case where α1> 40α2 was exceeded was also examined, but basically the electrical characteristics are almost equivalent to 40α2. That is, it can be understood that this is the critical point of the effect of the present application. Even if it is thicker than this, an improvement in electrical effect cannot be expected. However, if this thickness is exceeded, it will be difficult to form lands or the like for connecting to the core substrate when a conductor layer is formed on the surface layer of the core substrate. If an upper interlayer insulating layer is further formed, the unevenness becomes large, and the interlayer insulating layer is swelled, so that impedance cannot be matched in some cases. However, there may be no problem even in the range (α1> 40α2).

  The thickness α1 of the conductor layer is more preferably 1.2α2 ≦ α1 ≦ 40α2. Within this range, it has been confirmed that no malfunction or error of the IC chip occurs due to power shortage (voltage drop).

  The core substrate in this case is a resin substrate impregnated with a core material such as glass epoxy resin, a ceramic substrate, a metal substrate, a composite core substrate using a composite of resin, ceramic, and metal, and an inner layer of these substrates (power supply For example, a substrate provided with a conductor layer, or a substrate using a multilayer core substrate formed with three or more layers of conductor layers.

  In order to increase the thickness of the conductor of the power supply layer, it is possible to use a printed wiring board formed by a generally performed conductor layer such as plating or sputtering on a metal-embedded substrate. Good.

In the case of a multilayer core substrate, the thickness obtained by adding the surface conductor layer and the inner conductor layer of the core substrate is the thickness of the core conductor layer. In this case, it is applied when the surface conductor layer and the inner conductor layer are electrically connected and have electrical connection at two or more locations. That is, even when the number of layers is increased, it is essential to increase the thickness of the conductor layer of the core substrate, and the effect itself does not change at all. Further, if the area is about the size of a pad or land, the thickness of the conductor layer in that area is not the sum of the thickness. The conductor layer is preferably a power supply layer or an earth layer.
In this case, a core substrate composed of three layers (surface layer + inner layer) may be used. A multilayer core substrate having three or more layers may be used.
If necessary, an electronic component housing core substrate in which components such as capacitors, dielectric layers, and resistors are embedded in the inner layer of the core substrate may be used.

  Further, when the inner conductor layer of the core substrate is thickened, it is better to dispose the corresponding conductor layer directly under the IC chip. By disposing the IC chip immediately below the IC chip, the distance between the IC chip and the power supply layer can be minimized, so that the loop inductance can be further reduced. As a result, power is supplied more efficiently, and the voltage shortage is resolved. Also in this case, it is desirable that α2 <α1 ≦ 40α2 with respect to α1 for the thickness of the conductor layer on the core substrate and α2 for the thickness of the conductor layer on the interlayer insulating layer.

  The core substrate in the present invention is defined as follows. It is a hard base material such as resin impregnated with core material, etc., and via holes are formed by photo vias or lasers on both or one side using an insulating resin layer that does not contain core material, etc. to form a conductor layer Thus, the electrical connection between the layers is performed. In comparison, the thickness of the core substrate is thicker than the thickness of the resin insulating layer. Basically, the core substrate is formed with a conductor layer mainly composed of a power supply layer, and other signal lines are formed only for connecting the front and back sides.

  In addition, if it is the multilayer printed wiring board formed by the material of the same thickness and is laminated | stacked, the layer or board | substrate which has a power supply layer as a conductor layer in a printed circuit board is defined as a core board | substrate.

Further, the multilayer core substrate has a relatively thick conductor layer on the inner layer and a relatively thin conductor layer on the surface layer, and the inner conductor layer is mainly a conductor layer for a power supply layer or a conductor layer for ground. Is preferred. (Relatively thick and thin means that the thickness of all the conductor layers is compared, and in this case, the inner layer is relatively thick compared to the other conductor layers, and the surface layer is Indicating that it is the opposite.)
That is, by disposing a thick conductor layer on the inner layer side, it is possible to form a resin layer so as to cover the inner conductor layer even if the thickness is arbitrarily changed. Sex is obtained. Therefore, no undulation is generated in the conductor layer of the interlayer insulating layer. Even if a thin conductor layer is disposed on the surface layer of the multilayer core substrate, the thickness of the conductor layer sufficient for the core conductor layer can be ensured by the thickness added to the inner conductor layer. By using these as the conductor layer for the power supply layer or the conductor layer for grounding, it becomes possible to improve the electrical characteristics of the multilayer printed wiring board.

  The thickness of the inner conductor layer of the core substrate is made thicker than the conductor layer on the interlayer insulating layer. Thereby, even if it arrange | positions a conductor layer on the surface of a multilayer core board | substrate, sufficient thickness as a conductor layer of a core is securable by adding with the conductor layer with a thick inner layer. In other words, even if a large-capacity power is supplied, it can be started without any problem, so that no malfunction or malfunction is caused. Also in this case, it is desirable that α2 <α1 ≦ 40α2 with respect to α1 for the thickness of the conductor layer on the core substrate and α2 for the thickness of the conductor layer on the interlayer insulating layer.

  When the multi-layer core substrate is used, the inner conductor layer is formed by relatively increasing the thickness of the conductor layer and using it as a power supply layer, and the surface conductor layer sandwiches the inner conductor layer. And it is also desirable that it is used as a signal line. With this structure, the aforementioned power supply can be enhanced.

  Furthermore, since the signal line is disposed between the conductor layers in the core substrate, a microstrip structure can be formed, so that inductance can be reduced and impedance matching can be achieved. Therefore, the electrical characteristics can be stabilized. Further, it is more desirable to make the surface conductive layer relatively thin. The core substrate may have a through hole pitch of 600 μm or less.

  The multilayer core substrate has an inner conductor layer with a resin layer interposed on both surfaces of an electrically connected metal plate, and further a conductor layer on the surface with a resin layer interposed outside the inner conductor layer. It is preferable to be formed. Sufficient mechanical strength can be ensured by arranging a metal plate that is electrically isolated in the central portion. Further, by forming a resin layer on both sides of the metal plate and forming an inner conductor layer, and further forming a surface conductor layer on the outer side of the inner conductor layer, a resin layer is formed on both sides of the metal plate. By providing symmetry, it is possible to prevent warping and undulation from occurring in a heat cycle or the like.

  In FIG. 24, the vertical axis represents the voltage supplied to the IC chip, and the horizontal axis represents time. FIG. 24 is a model of a printed wiring board that does not include a capacitor for high frequency IC chip power supply of 1 GHz or higher. Line A shows the change over time of the voltage to the 1 GHz IC chip, and line B shows the change over time of the voltage to the 3 GHz IC chip. The change over time requires a large amount of power supply instantaneously when the IC chip starts to start. If the supply is insufficient, the voltage drops (points X and X '). Thereafter, the voltage effect is eliminated because the power supply to be supplied is gradually satisfied. However, when the voltage drops, it tends to cause malfunctions and errors of the IC chip. That is, this is a problem that occurs because the function of the IC chip is not fully functioning and activated due to insufficient power supply. This power shortage (voltage drop) becomes larger as the frequency of the IC chip increases. Therefore, it takes time to eliminate the voltage drop, and a time lag occurs in order to perform a desired function and activation.

In order to compensate for the power shortage (voltage drop) described above, the power shortage or voltage drop can be reduced by connecting to an external capacitor and discharging the power stored in the capacitor.
FIG. 25 is a model of a printed circuit board provided with a capacitor. Line C shows a change with time of voltage in a 1 GHz IC chip with a small-capacitance capacitor mounted thereon. The degree of voltage drop is smaller than that of the line A in which no capacitor is mounted. Further, the line D shows a change with time similar to the line C by mounting a capacitor having a larger capacity than that of the line C. Furthermore, even when compared with the line C, the degree of voltage drop is getting smaller. As a result, the desired IC chip can also function and start up in a short time. However, as shown in FIG. 24, when the IC chip is in a higher frequency region, more capacitor capacity is required, so that it is necessary to set a region where the capacitor is mounted. It becomes difficult to improve the operation and function, and it is difficult to increase the density.

  FIG. 26 shows a graph when the thickness α1 of the conductor layer of the core substrate and the conductor layer of the power source and the thickness α2 of the conductor layer on the interlayer insulating layer are set. In FIG. 26, a line C indicates a change with time in voltage when α1 = α2 in a 1 GHz IC chip with a small-capacitance capacitor mounted thereon. Line F is a 1 GHz IC chip with a small-capacitance capacitor mounted, and shows a change in voltage over time at α1 = 1.5α2, and line E is a 1 GHz IC with a small-capacitance capacitor mounted. In the chip, the change with time of voltage at α1 = 2.0α2 is shown. As the thickness of the core conductor layer increases, the power shortage or voltage drop becomes smaller. Therefore, it can be said that the occurrence of defects in the function and operation of the IC chip is reduced. By increasing the thickness of the conductor layer of the core substrate and the conductor layer of the power supply layer, the volume of the conductor layer is increased. When the volume is increased, the conductor resistance is reduced, so that there is no loss in voltage and current in the transmitted power source. Therefore, transmission loss between the IC chip and the power supply is reduced, and power is supplied, so that no malfunction or error is caused. In this case, the factor due to the thickness of the conductor layer of the power supply layer is particularly large, and the effect is achieved by making the thickness of the conductor layer of the power supply layer in the core substrate thicker than the conductor circuit on the other interlayer insulating layer.

  In addition, when the conductor layer on one or both surfaces of the core substrate and the conductor layer of the power supply are thickened, when the multilayer core substrate of three or more layers is used, the inner layer is the conductor layer or the inner layer is for the power layer. It was found that the same effect was obtained even when the core substrate was formed with the conductor layer. That is, there is an effect of reducing power shortage or voltage drop. In the case of a multi-layer core substrate, all the layers of the core substrate are formed even when the conductor layers of all the layers of the core substrate and the conductor layers of the power supply layer are thicker than the conductor layer on the interlayer insulating layer. Even when the thickness of the conductor layer of the conductor layer and the power supply layer is equal to or less than the thickness of the conductor layer on the interlayer insulating layer, the total sum of the thicknesses of the conductors of all the layers is on the interlayer insulating layer. This effect is achieved when the thickness of the conductor layer is increased. In this case, there is no difference in the area of each conductor layer. That is, when the area ratio is almost the same, the effect is exhibited. For example, in the case of two conductor layers, when one is a large area of a solid layer and the other is a via hole and its land, the effect of the conductor layer of the other layer cancels out. Will be.

  Further, even if the substrate includes electronic components such as capacitors, dielectric layers, and resistors in the core substrate, the effect is prominent. By incorporating it, the distance between the IC chip and the capacitor or dielectric layer can be shortened. Therefore, the loop inductance can be reduced. Power shortage or voltage drop can be reduced. For example, even in a core substrate with a built-in capacitor or dielectric layer, the thickness of the conductor layer of the core substrate and the conductor layer of the power supply layer is made larger than the thickness of the conductor layer on the interlayer insulating layer. Since the conductor resistance of both the built-in capacitor and the power source of the dielectric layer can be reduced, the transmission loss can be reduced, and the effect of the substrate with the built-in capacitor can be further exhibited.

  The material of the core substrate was verified with a resin substrate, but it was found that the same effect was obtained with a ceramic or metal core substrate. In addition, although the conductor layer was made of a metal made of copper, it has not been confirmed that other metals offset the effect and increase the number of malfunctions and errors. The difference or the difference in the material forming the conductor layer seems not to have an effect on the effect. More preferably, the conductor layer of the core substrate and the conductor layer of the interlayer insulating layer are formed of the same metal. Since the characteristics and physical properties such as electrical characteristics and thermal expansion coefficient do not change, the effect of the present application is achieved.

It is process drawing which shows the manufacturing method of the multilayer printed wiring board of 1st Example of this invention. It is process drawing which shows the manufacturing method of the multilayer printed wiring board of 1st Example. It is process drawing which shows the manufacturing method of the multilayer printed wiring board of 1st Example. It is process drawing which shows the manufacturing method of the multilayer printed wiring board of 1st Example. It is process drawing which shows the manufacturing method of the multilayer printed wiring board of 1st Example. It is sectional drawing of the multilayer printed wiring board which concerns on 1st Example. It is sectional drawing which shows the state which mounted the IC chip in the multilayer printed wiring board which concerns on 1st Example. It is sectional drawing of the multilayer printed wiring board which concerns on 3rd Example. It is sectional drawing which shows the state which mounted the IC chip in the multilayer printed wiring board which concerns on 3rd Example. It is sectional drawing of the multilayer printed wiring board which concerns on 4th Example. It is sectional drawing which shows the state which mounted the IC chip in the multilayer printed wiring board concerning 4th Example. It is process drawing which shows the manufacturing method of the multilayer printed wiring board of 5th Example of this invention. It is process drawing which shows the manufacturing method of the multilayer printed wiring board of 5th Example. It is process drawing which shows the manufacturing method of the multilayer printed wiring board of 5th Example. It is process drawing which shows the manufacturing method of the multilayer printed wiring board of 5th Example. It is process drawing which shows the manufacturing method of the multilayer printed wiring board of 5th Example. It is process drawing which shows the manufacturing method of the multilayer printed wiring board of 5th Example. It is process drawing which shows the manufacturing method of the multilayer printed wiring board of 5th Example. It is sectional drawing of the multilayer printed wiring board which concerns on 5th Example. It is sectional drawing which shows the state which mounted IC chip in the multilayer printed wiring board which concerns on 5th Example. It is sectional drawing which shows the state which mounted IC chip in the multilayer printed wiring board which concerns on the modification of 5th Example. It is sectional drawing of the multilayer printed wiring board which concerns on 6th Example. It is sectional drawing which shows the state which mounted the IC chip in the multilayer printed wiring board concerning 6th Example. It is the graph which showed the voltage change during operation | movement of an IC chip. It is the graph which showed the voltage change during operation | movement of an IC chip. It is the graph which showed the voltage change during operation | movement of an IC chip. It is a graph which shows the test result of an Example and a comparative example. It is a graph which shows the test result of an Example and a comparative example. It is the graph which showed the result of having simulated the maximum voltage drop amount (V) with respect to (ratio of the power supply layer thickness of a core / interlayer insulation layer thickness).

[Example]
[First Embodiment] Glass Epoxy Resin Substrate First, the configuration of a multilayer printed wiring board 10 according to a first embodiment of the present invention will be described with reference to FIGS. 6 shows a cross-sectional view of the multilayer printed wiring board 10 and FIG. 7 shows a state in which the IC chip 90 is attached to the multilayer printed wiring board 10 shown in FIG. As shown in FIG. 6, in the multilayer printed wiring board 10, the conductor circuit 34 and the conductor layer 34P are formed on the surface of the core substrate 30, and the conductor circuit 34 and the conductor layer 34E are formed on the back surface. The upper conductor layer 34P is formed as a power source plane layer, and the lower conductor layer 34E is formed as a ground plane layer. The front surface and the back surface of the core substrate 30 are connected through a through hole 36. Furthermore, an interlayer resin insulation layer 50 in which via holes 60 and conductor circuits 58 are formed and an interlayer resin insulation layer 150 in which via holes 160 and conductor circuits 158 are formed are disposed on the conductor layers 34P and 34E. ing. A solder resist layer 70 is formed on the via hole 160 and the conductor circuit 158, and bumps 76 U and 76 D are formed on the via hole 160 and the conductor circuit 158 through the opening 71 of the solder resist layer 70. ing.

   As shown in FIG. 7, the solder bumps 76 </ b> U on the upper surface side of the multilayer printed wiring board 10 are connected to the lands 92 of the IC chip 90. Further, a chip capacitor 98 is mounted. On the other hand, the lower solder bump 76D is connected to the land 96 of the daughter board 94.

  Here, the conductor layers 34P and 34E on the core substrate 30 are formed to a thickness of 1 to 250 μm, and the conductor circuit 58 on the interlayer resin insulation layer 50 and the conductor circuit 158 on the interlayer resin insulation layer 150 are 5 to 25 μm ( The desired range is 10 to 20 μm.

  In the multilayer printed wiring board of the first embodiment, the power layer (conductor layer) 34P and the conductor layer 34E of the core substrate 30 are thickened to increase the strength of the core substrate, thereby reducing the thickness of the core substrate itself. However, it becomes possible to relieve the warpage and the generated stress by the substrate itself.

  Further, by increasing the thickness of the conductor layers 34P and 34E, the volume of the conductor itself can be increased. By increasing the volume, the resistance in the conductor can be reduced.

  Furthermore, the ability to supply power to the IC chip 90 can be improved by using the conductor layer 34P as the power supply layer. Therefore, when an IC chip is mounted on the multilayer printed board, the loop inductance from the IC chip to the board to the power source can be reduced. For this reason, the shortage of power supply in the initial operation is reduced, so that the shortage of power supply is less likely to occur. Therefore, even if an IC chip in a high frequency region is mounted, malfunctions and errors at the initial start-up are not caused. Further, by using the conductor layer 34E as an earth layer, noise is not superimposed on the signal and power supply of the IC chip, and malfunctions and errors can be prevented.

Next, a method for manufacturing the multilayer printed wiring board 10 described above with reference to FIG. 6 will be described with reference to FIGS.
(First Example-1)
A. Preparation of resin film of interlayer resin insulation layer 29 parts by weight of bisphenol A type epoxy resin (epoxy equivalent 455, Epicoat 1001 manufactured by Yuka Shell Epoxy), cresol novolak type epoxy resin (epoxy equivalent 215, manufactured by Dainippon Ink and Chemicals, Inc.) N-673) 39 parts by weight, triazine structure-containing phenol novolac resin (phenolic hydroxyl group equivalent 120, Phenolite KA-7052 made by Dainippon Ink & Chemicals) 20 parts by weight ethyl diglycol acetate, 20 parts by weight of solvent naphtha The solution was dissolved by heating with stirring to 15 parts by weight, and 15 parts by weight of terminal epoxidized polybutadiene rubber (Danalex R-45EPT manufactured by Nagase Kasei Kogyo Co., Ltd.) and pulverized 2-phenyl-4,5-bis (hydroxymethyl) imidazole 1.5 Part by weight, fine Crushed silica 2.5 parts by weight, it was added 0.5 part by weight of silicon antifoaming agent to prepare an epoxy resin composition.
The obtained epoxy resin composition was applied on a PET film having a thickness of 38 μm using a roll coater so that the thickness after drying was 50 μm, and then dried at 80 to 120 ° C. for 10 minutes, whereby an interlayer resin was obtained. A resin film for an insulating layer was produced.

B. Preparation of resin filler 100 parts by weight of bisphenol F-type epoxy monomer (manufactured by Yuka Shell Co., Ltd., molecular weight: 310, YL983U), the average particle diameter coated with a silane coupling agent on the surface is 1.6 μm, and the diameter of the largest particle Is 15 μm or less of SiO 2 spherical particles (manufactured by Adtech Co., CRS 1101-CE) 170 parts by weight and leveling agent (San Nopco Perenol S4) 1.5 parts by weight in a container, the viscosity is 23 ± A resin filler of 44 to 49 Pa · s was prepared at 1 ° C. As the curing agent, 6.5 parts by weight of an imidazole curing agent (manufactured by Shikoku Kasei Co., Ltd., 2E4MZ-CN) was used. As the filler resin, thermosetting resins such as other epoxy resins (for example, bisphenol A type, novolac type, etc.), polyimide resins, and phenol resins may be used.

C. Production of multilayer printed wiring board (1) A copper foil 32 of 5 to 250 μm is laminated on both surfaces of an insulating substrate 30 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 0.2 to 0.8 mm. The copper-clad laminate 30A was used as a starting material (FIG. 1A). First, the copper-clad laminate is drilled, subjected to electroless plating treatment and electrolytic plating treatment, and etched into a pattern to form conductor circuits 34, conductor layers 34P and 34E and through holes 36 on both sides of the substrate. It formed (FIG. 1 (B)).

(2) The substrate 30 on which the through hole 36 and the lower conductor circuit 34 are formed is washed with water and dried, and then an aqueous solution containing NaOH (10 g / l), NaClO2 (40 g / l), Na3 PO4 (6 g / l) is blackened. A blackening treatment for forming a oxidizing bath (oxidizing bath) and a reducing treatment using an aqueous solution containing NaOH (10 g / l) and NaBH4 (6 g / l) as a reducing bath are performed. And a roughened surface 34α was formed on the entire surface of the conductor circuit 34 and the conductor layers 34P and 34E (FIG. 1C).

(3) After preparing the resin filler described in B above, the layer of the resin filler 40 is formed in the through hole 36 and in the conductor circuit non-formation portion of the substrate within 24 hours after preparation by the following method. (FIG. 1D).
That is, a resin filling mask having a plate with an opening corresponding to a through hole and a conductor circuit non-forming portion is placed on the substrate, and a lower conductor circuit not forming a recess in the through hole is formed using a squeegee And the outer edge portion of the lower conductor circuit were filled with a resin filler and dried under conditions of 100 ° C./20 minutes.

(4) One side of the substrate after the processing of (3) is subjected to belt sander polishing using # 600 belt polishing paper (manufactured by Sankyo Rikagaku), and the outer edges of the conductor layers 34P and 34E and the land of the through hole 36 In order to remove the scratches caused by the belt sander polishing, the entire surface (including the land surface of the through hole) of the conductor layers 34P and 34E is buffed. It was. Such a series of polishing was similarly performed on the other surface of the substrate. Subsequently, heat treatment was performed at 100 ° C. for 1 hour and 150 ° C. for 1 hour to cure the resin filler 40 (FIG. 2A).

In this way, the surface layer portion of the resin filler 40 and the surfaces of the conductor layers 34P and 34E formed in the through hole 36 and the conductor circuit non-forming portion are flattened, and the resin filler 40 and the side surfaces of the conductor layers 34P and 34E Was firmly adhered through the roughened surface, and the inner wall surface of the through hole 36 and the resin filler were firmly adhered through the roughened surface. That is, by this step, the surface of the resin filler and the surface of the lower conductor circuit become substantially flush.
The thickness of the conductor layer of the core substrate is formed between 1 and 250 μm, and the thickness of the conductor layer of the power supply layer formed on the core substrate is formed between 1 and 250 μm. It was. At this time, in Example 1-1, a copper foil having a thickness of 40 μm was used, the thickness of the conductor layer of the core substrate was 30 μm, and the thickness of the conductor layer of the power supply layer formed on the core substrate was 30 μm. . However, the thickness of the conductor layer may exceed the above thickness range.

(5) After washing the substrate with water and acid degreasing, soft etching is performed, and then an etching solution is sprayed on both surfaces of the substrate to spray the surfaces of the conductor circuit 34, the conductor layers 34P and 34E, and the land surface of the through hole 36. And the inner wall were etched to form a roughened surface 36β on the entire surface of the conductor circuit (FIG. 2B). As an etching solution, an etching solution (MEC Etch Bond, manufactured by MEC) consisting of 10 parts by weight of imidazole copper (II) complex, 7.3 parts by weight of glycolic acid, and 5 parts by weight of potassium chloride was used.

(6) An interlayer resin insulation layer resin film 50γ that is slightly larger than the substrate prepared in A is placed on both sides of the substrate and temporarily mounted under conditions of a pressure of 0.45 MPa, a temperature of 80 ° C., and a pressure bonding time of 10 seconds. After crimping and cutting, an interlayer resin insulating layer was further formed by sticking using a vacuum laminator apparatus by the following method (FIG. 2C). That is, the resin film for an interlayer resin insulation layer was subjected to main pressure bonding on a substrate under conditions of a degree of vacuum of 67 Pa, a pressure of 0.47 MPa, a temperature of 85 ° C., and a pressure bonding time of 60 seconds, and then thermally cured at 170 ° C. for 40 minutes.

(7) Next, with a CO2 gas laser having a wavelength of 10.4 μm through a mask in which a through hole having a thickness of 1.2 mm is formed on the interlayer resin insulation layer, a beam diameter of 4.0 mm, top hat mode, A via hole opening 50a having a diameter of 60 to 100 μm was formed in the interlayer resin insulating layer 2 under the conditions of a pulse width of 8.1 μsec, a mask through-hole diameter of 1.0 mm, and one shot (FIG. 2D )). This time, they were formed with a diameter of 60 μm and 75 μm.

(8) The substrate on which the via-hole opening 6 has been formed is immersed in an 80 ° C. solution containing 60 g / l permanganic acid for 10 minutes to dissolve and remove the epoxy resin particles present on the surface of the interlayer resin insulation layer 2. Thus, a roughened surface 50α was formed on the surface of the interlayer resin insulating layer 50 including the inner wall of the via hole opening 50a (FIG. 2E).

(9) Next, the substrate after the above treatment was immersed in a neutralization solution (manufactured by Shipley Co., Ltd.) and washed with water.
Further, by applying a palladium catalyst to the surface of the substrate subjected to the roughening treatment (roughening depth 3 μm), catalyst nuclei were attached to the surface of the interlayer resin insulating layer and the inner wall surface of the via hole opening. That is, the substrate was immersed in a catalyst solution containing palladium chloride (PbCl2) and stannous chloride (SnCl2), and the catalyst was applied by depositing palladium metal.

(10) Next, a substrate provided with a catalyst is immersed in an electroless copper plating aqueous solution having the following composition to form an electroless copper plating film having a thickness of 0.3 to 3.0 μm on the entire rough surface. A substrate having an electroless copper plating film 52 formed on the surface of the interlayer resin insulation layer 50 including the inner wall of the via hole opening (50a) was obtained (FIG. 3A).
[Electroless plating aqueous solution]
NiSO4 0.003 mol / l
Tartaric acid 0.200 mol / l
Copper sulfate 0.032 mol / l
HCHO 0.050 mol / l
NaOH 0.100 mol / l
α, α'-bipyridyl 100 mg / l
Polyethylene glycol (PEG) 0.10 g / l
[Electroless plating conditions]
45 minutes at a liquid temperature of 34 ° C

(11) A commercially available photosensitive dry film is attached to the substrate on which the electroless copper plating film 52 is formed, and a mask is placed, exposed at 110 mJ / cm ² , and developed with a 0.8% aqueous sodium carbonate solution. Thus, a plating resist 54 having a thickness of 25 μm was provided (FIG. 3B).

(12) Next, the substrate is washed with 50 ° C. water for degreasing, washed with 25 ° C. water and further washed with sulfuric acid, and then subjected to electrolytic plating under the following conditions to form a plating resist 54 non-formed portion. Then, an electrolytic copper plating film 56 having a thickness of 20 μm was formed (FIG. 3C).
[Electrolytic plating solution]
Sulfuric acid 2.24 mol / l
Copper sulfate 0.26 mol / l
Additive 19.5 ml / l
(Manufactured by Atotech Japan, Kaparaside GL)
[Electrolytic plating conditions]
Current density 1 A / dm2
Time 65 minutes Temperature 22 ± 2 ℃

(13) Furthermore, after removing the plating resist 3 with 5% KOH, the electroless plating film under the plating resist is dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide. 58 and via hole 60 (FIG. 3D).

(14) Next, the same processing as in the above (5) was performed to form roughened surfaces 58α and 60α on the surfaces of the conductor circuit 58 and the via hole 60. The thickness of the upper conductor circuit 58 was 15 μm (FIG. 4A). However, you may form the thickness of the upper conductor circuit between 5-25 micrometers.

(15) By repeating the steps (6) to (14) above, an upper conductor circuit was formed to obtain a multilayer wiring board (FIG. 4B).

(16) Next, a photosensitizing agent obtained by acrylating 50% of an epoxy group of a cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) to a concentration of 60% by weight. 45.67 parts by weight of oligomer (molecular weight: 4000), 80% by weight of bisphenol A type epoxy resin dissolved in methyl ethyl ketone (manufactured by Yuka Shell, trade name: Epicoat 1001), 16.0 parts by weight, imidazole curing agent (Shikoku Kasei Co., Ltd., trade name: 2E4MZ-CN) 1.6 parts by weight, photofunctional monomer bifunctional acrylic monomer (Nippon Kayaku Co., Ltd., trade name: R604) 4.5 parts by weight, also polyvalent acrylic monomer ( Kyoei Chemical Co., Ltd., trade name: DPE6A) 1.5 parts by weight, dispersion antifoaming agent (San Nopco, S-65) Take 1 part by weight in a container, stir and mix to prepare a mixed composition, and 1.8 parts by weight of benzophenone (manufactured by Kanto Chemical Co., Inc.) as a photopolymerization initiator for this mixed composition, as a photosensitizer By adding 0.2 part by weight of Michler's ketone (manufactured by Kanto Chemical Co., Inc.), a solder resist composition having a viscosity adjusted to 2.0 Pa · s at 25 ° C. was obtained.
Viscosity measurement was performed using a B-type viscometer (DVL-B type, manufactured by Tokyo Keiki Co., Ltd.). In the case of 4, 6 min-1, the rotor No. 3 according.

(17) Next, after applying the solder resist composition 70 to the thickness of 20 μm on both surfaces of the multilayer wiring board and performing a drying treatment at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes (see FIG. 4 (C)), a photomask having a thickness of 5 mm on which the pattern of the opening of the solder resist is drawn is brought into close contact with the solder resist layer 70, exposed to 1000 mJ / cm @ 2 of ultraviolet light, developed with DMTG solution, and 200 [mu] m in diameter. The opening 71 was formed (FIG. 5A).
Further, the solder resist layer is cured by heating at 80 ° C. for 1 hour, 100 ° C. for 1 hour, 120 ° C. for 1 hour, and 150 ° C. for 3 hours. A solder resist pattern layer having a thickness of 15 to 25 μm was formed. A commercially available solder resist composition can also be used as the solder resist composition.

(18) Next, the substrate on which the solder resist layer 70 is formed is made of nickel chloride (2.3 × 10 ⁻¹ mol / l), sodium hypophosphite (2.8 × 10 ⁻¹ mol / l), A nickel plating layer 72 having a thickness of 5 μm was formed in the opening 71 by dipping in an electroless nickel plating solution containing sodium acid (1.6 × 10 ⁻¹ mol / l) at pH = 4.5 for 20 minutes. Furthermore, the substrate gold potassium cyanide ^{(7.6 × 10 -3 mol / l} ), ammonium chloride ^{(1.9 × 10 -1 mol / l} ), sodium citrate (1.2 × 10 ^-1 mol / l) Immersion in an electroless gold plating solution containing sodium hypophosphite (1.7 × 10 ⁻¹ mol / l) at 80 ° C. for 7.5 minutes to form a thickness on the nickel plating layer 72 A 0.03 μm gold plating layer 74 was formed (FIG. 5B). In addition to the nickel-gold layer, a single layer of tin or a noble metal layer (gold, silver, palladium, platinum, etc.) may be formed.

(19) After that, a solder paste containing tin-lead is printed on the opening 71 of the solder resist layer 70 on the surface on which the IC chip of the substrate is placed, and further, tin-lead is formed on the opening of the solder resist layer on the other surface. After printing the solder paste containing antimony, solder bumps (solder bodies) were formed by reflowing at 200 ° C., and a multilayer printed wiring board having solder bumps 76U and 76D was manufactured (FIG. 6).

  The IC chip 90 is attached via the solder bumps 76U, and the chip capacitor 98 is mounted. And it attaches to the daughter board 94 via the solder bump 76D (FIG. 7).

(First Example-2)
This was the same as the first embodiment-1 described above with reference to FIG.
Core substrate conductor layer thickness: 55 μm Core substrate power layer thickness: 55 μm
Interlayer insulation layer conductor layer thickness: 15 μm

(First Example-3)
The same as Example 1 but manufactured as follows.
Core substrate conductor layer thickness: 75 μm Core substrate power layer thickness: 75 μm
Interlayer insulation layer conductor layer thickness: 15 μm

(First Example-4)
Similar to the first example, but manufactured as follows.
Core substrate conductor layer thickness: 180 μm Core substrate power layer thickness: 180 μm
Interlayer insulation layer conductor layer thickness: 6 μm

(First Example-5)
Similar to the first example, but manufactured as follows.
Core substrate conductor layer thickness: 18 μm Core substrate power layer thickness: 18 μm
Interlayer insulation layer conductor layer thickness: 15 μm

  In the first embodiment, a case where 1 <(the thickness of the conductor layer of the power supply layer of the core substrate / the thickness of the conductor layer of the interlayer insulating layer) ≦ 40 is used as a conforming example. The thickness / thickness of the conductor layer of the interlayer insulating layer) ≦ 1 was used as a comparative example. Further, the reference example was (thickness of conductor layer of power supply layer of core substrate / thickness of conductor layer of interlayer insulating layer)> 40.

[Second Embodiment] Ceramic Substrate A multilayer printed wiring board according to a second embodiment will be described.
In the first embodiment described above with reference to FIG. 6, the core substrate is formed of an insulating resin. In contrast, in the second embodiment, the core substrate is an inorganic hard substrate made of ceramic, glass, ALN, mullite, or the like, but the other configurations are the same as those of the first embodiment described above with reference to FIG. Therefore, illustration and description are omitted.

  Also in the multilayer printed wiring board of the second embodiment, the conductor layers 34P and 34P on the core substrate 30 and the conductor layer 24 in the core substrate are formed of metal such as copper and tongue stem, and the conductor on the interlayer resin insulating layer 50 The circuit 58 and the conductor circuit 158 on the interlayer resin insulation layer 150 are made of copper. In the second embodiment, the same effect as in the first embodiment is obtained. At this time, the thickness of the conductor layer of the core substrate, the thickness of the power supply layer of the core substrate, and the thickness of the interlayer insulating layer were also formed in the same manner as in the first example. Further, in the second embodiment, a case where 1 <(the thickness of the conductor layer of the power supply layer of the core substrate / the thickness of the conductor layer of the interlayer insulating layer) ≦ 40 is used as a conforming example. The thickness / thickness of the conductor layer of the interlayer insulating layer) ≦ 1 was used as a comparative example. Further, the reference example was (thickness of conductor layer of power supply layer of core substrate / thickness of conductor layer of interlayer insulating layer)> 40.

(Second embodiment-1)
Although it was the same as that of 2nd Example mentioned above, it manufactured as follows.
Core substrate conductor layer thickness: 30 μm Core substrate power layer thickness: 30 μm
Interlayer insulation layer conductor layer thickness: 15 μm

(Second embodiment-2)
Although it was the same as that of 2nd Example mentioned above, it manufactured as follows.
Core substrate conductor layer thickness: 50 μm Core substrate power layer thickness: 50 μm
Interlayer insulation layer conductor layer thickness: 15 μm

(Second embodiment-3)
Although it was the same as that of 2nd Example mentioned above, it manufactured as follows.
Core substrate conductor layer thickness: 75 μm Core substrate power layer thickness: 75 μm
Interlayer insulation layer conductor layer thickness: 15 μm

(Second embodiment-4)
Although it was the same as that of 2nd Example mentioned above, it manufactured as follows.
Core substrate conductor layer thickness: 180 μm Core substrate power layer thickness: 180 μm
Interlayer insulation layer conductor layer thickness: 6 μm

[Third Embodiment] Metal Core Board A multilayer printed wiring board according to the third embodiment will be described with reference to FIGS.
In the first embodiment described above with reference to FIG. 6, the core substrate is formed of a resin plate. In contrast, in the third embodiment, the core substrate is made of a metal plate.

  FIG. 8 is a cross-sectional view of the multilayer printed wiring board 10 according to the third embodiment, and FIG. 9 shows a state in which the IC chip 90 is attached to the multilayer printed wiring board 10 shown in FIG. Yes. As shown in FIG. 8, in the multilayer printed wiring board 10, the core substrate 30 is made of a metal plate and is used as a power supply layer. An interlayer resin insulation layer 50 in which via holes 60 and conductor circuits 58 are disposed is formed on both surfaces of the core substrate 30, and an interlayer in which via holes 160 and conductor circuits 158 are disposed on the interlayer resin insulation layer 50. A resin insulating layer 150 is formed. Through holes 36 are formed in the through holes 33 of the core substrate 30, and lid plating layers 37 are disposed at both ends of the via holes. A solder resist layer 70 is formed on the via hole 160 and the conductor circuit 158, and bumps 76 U and 76 D are formed on the via hole 160 and the conductor circuit 158 through the opening 71 of the solder resist layer 70. ing.

  As shown in FIG. 9, the solder bumps 76 </ b> U on the upper surface side of the multilayer printed wiring board 10 are connected to the lands 92 of the IC chip 90. Further, a chip capacitor 98 is mounted. On the other hand, the lower solder bump 76D is connected to the land 96 of the daughter board 94.

Here, the core board | substrate 30 is formed in 200-600 micrometers. The thickness of the metal plate was formed between 15 and 300 μm. You may form the thickness of the conductor layer of an interlayer insulation layer between 5-25 micrometers. However, the thickness of the metal layer may exceed the above range.
In the third embodiment, the same effect as in the first embodiment is obtained.

(Third embodiment-1)
Although it is the same as that of the 3rd Example mentioned above with reference to FIG. 8, it set as follows.
Core substrate thickness: 550 μm Core substrate power layer thickness: 35 μm
Interlayer insulation layer conductor layer thickness: 15 μm

(Third embodiment-2)
Although it was the same as that of 3rd Example, it set as follows.
Core substrate thickness: 600 μm Core substrate power layer thickness: 55 μm
Interlayer insulation layer conductor layer thickness: 15 μm

(Third embodiment-3)
Although it was the same as that of 3rd Example, it set as follows.
Core substrate thickness: 550 μm Core substrate power layer thickness: 100 μm
Conductor layer thickness of the interlayer insulation layer: 10 μm

(Third embodiment-4)
Although it was the same as that of 3rd Example, it set as follows.
Core substrate thickness: 550 μm Core substrate power layer thickness: 180 μm
Interlayer insulation layer conductor layer thickness: 6 μm

(Third embodiment-5)
Although it was the same as that of 3rd Example, it set as follows.
Core substrate thickness: 550 μm Core substrate power layer thickness: 240 μm
Interlayer insulation layer conductor layer thickness: 6 μm

  In the third embodiment, a case where 1 <(thickness of the conductor layer of the power supply layer of the core substrate / thickness of the conductor layer of the interlayer insulating layer) ≦ 40 is used as a suitable example. The thickness / thickness of the conductor layer of the interlayer insulating layer) ≦ 1 was used as a comparative example. Further, the reference example was (thickness of conductor layer of power supply layer of core substrate / thickness of conductor layer of interlayer insulating layer)> 40.

[Fourth Embodiment] Multilayer Core Substrate A multilayer printed wiring board according to a fourth embodiment will be described with reference to FIGS.
In the first embodiment described above with reference to FIG. 6, the core substrate is formed of a single plate. On the other hand, in the fourth embodiment, the core substrate is made of a laminated plate, and a conductor layer is provided in the laminated plate.

  FIG. 10 is a cross-sectional view of the multilayer printed wiring board 10 according to the fourth embodiment, and FIG. 11 shows a state in which the IC chip 90 is attached to the multilayer printed wiring board 10 shown in FIG. Yes. As shown in FIG. 10, in the multilayer printed wiring board 10, the conductor circuit 34 and the conductor layer 34 </ b> P are formed on the front surface and the back surface of the core substrate 30, and the conductor layer 24 is formed in the core substrate 30. The conductor layer 34P and the conductor layer 24 are formed as a power source plane layer. The conductor layer 34P and the conductor layer 24 are connected by a conductive post 26. (The conductive post in this case means a via hole (including a blind through hole, a blind via hole) such as a through hole or a non-through hole filled with a through hole or via hole conductive material). An interlayer resin insulation layer 50 in which via holes 60 and conductor circuits 58 are formed and an interlayer resin insulation layer 150 in which via holes 160 and conductor circuits 158 are formed are disposed on 34P. A solder resist layer 70 is formed on the via hole 160 and the conductor circuit 158, and bumps 76 U and 76 D are formed on the via hole 160 and the conductor circuit 158 through the opening 71 of the solder resist layer 70. ing.

  As shown in FIG. 11, the solder bumps 76 </ b> U on the upper surface side of the multilayer printed wiring board 10 are connected to the lands 92 of the IC chip 90. Further, a chip capacitor 98 is mounted. On the other hand, the lower solder bump 76D is connected to the land 96 of the daughter board 94.

Here, the conductor circuit 34, the conductor layers 34P and 34P on the core substrate 30 and the conductor layer 24 in the core substrate are formed, and the conductor circuit 58 on the interlayer resin insulation layer 50 and the conductor circuit 158 on the interlayer resin insulation layer 150 are formed. Is formed. The thickness of the conductor layer 34P and the conductor layer 24 of the core substrate is such that the thickness of the conductor layer of the core substrate is between 1 and 250 μm and serves as a power supply layer formed on the core substrate. Was formed between 1 and 250 μm. In this case, the thickness of the conductor layer is the sum of the thicknesses of the power supply layers of the core substrate. This means that the conductor layer 34 as the inner layer and the conductor layer 24 as the surface layer are added together. It is not to add what plays the role of a signal line. Also in the fourth embodiment, the same effect as that of the first embodiment is obtained by combining the thicknesses of the three conductor layers 34P, 34P, and 24. The thickness of the power supply layer may exceed the above range.
In the fourth embodiment, a case where 1 <(total thickness of the conductor layers of the power supply layer of the core substrate / the thickness of the conductor layers of the interlayer insulating layer) ≦ 40 is used as a conforming example. The total thickness of the layers / the thickness of the conductor layer of the interlayer insulating layer) ≦ 1 was taken as a comparative example. (The sum of the thicknesses of the conductor layers of the power supply layer of the core substrate / the thickness of the conductor layers of the interlayer insulating layer)> 40 was used as a reference example.

(Fourth embodiment-1)
Although it is the same as that of the 4th Example mentioned above with reference to FIG. 10, it set as follows.
The thickness of the conductor layer (power supply layer) of the core substrate: 15 μm
Intermediate conductor layer (power supply layer) thickness: 20 μm
Sum of thickness of power supply layer of core substrate: 50 μm
Interlayer insulation layer conductor layer thickness: 15 μm

(4th Example-2)
Similar to the fourth example, but manufactured as follows.
Core substrate conductor layer (power supply layer) thickness: 20 μm
Intermediate conductor layer (power supply layer) thickness: 20 μm
Sum of thickness of power supply layer of core substrate: 60 μm
Interlayer insulation layer conductor layer thickness: 15 μm

(4th Example-3)
Similar to the fourth example, but manufactured as follows.
Core substrate conductor layer (power supply layer) thickness: 25 μm
Intermediate conductor layer (power supply layer) thickness: 25 μm
Sum of thickness of power supply layer of core substrate: 75 μm
Interlayer insulation layer conductor layer thickness: 15 μm

(Fourth embodiment-4)
Similar to the fourth example, but manufactured as follows.
Core substrate conductor layer (power supply layer) thickness: 50 μm
Intermediate conductor layer (power supply layer) thickness: 100 μm
Sum of thickness of power supply layer of core substrate: 200 μm
Conductor layer thickness of the interlayer insulation layer: 10 μm

(Fourth embodiment-5)
Similar to the fourth example, but manufactured as follows.
Core substrate conductor layer (power supply layer) thickness: 55 μm
Intermediate conductor layer (power supply layer) thickness: 250 μm
Sum of thickness of power supply layer of core substrate: 360 μm
Conductor layer thickness of interlayer insulation layer: 12 μm

(Fourth embodiment-6)
Similar to the fourth example, but manufactured as follows.
Core substrate conductor layer (power supply layer) thickness: 55 μm
Intermediate conductor layer (power supply layer) thickness: 250 μm
Sum of thickness of power supply layer of core substrate: 360 μm
Conductor layer thickness of the interlayer insulation layer: 9 μm

[Fifth Embodiment] Multilayer Core Board A multilayer printed wiring board according to a fifth embodiment of the present invention will be described with reference to FIGS.
First, the configuration of the multilayer printed wiring board 10 according to the fifth embodiment will be described with reference to FIGS. FIG. 19 is a sectional view of the multilayer printed wiring board 10 and FIG. 20 shows a state in which the IC chip 90 is attached to the multilayer printed wiring board 10 shown in FIG. As shown in FIG. 19, the multilayer printed wiring board 10 uses a multilayer core substrate 30. A conductor circuit 34 and a conductor layer 34P are formed on the front surface side of the multilayer core substrate 30, and a conductor circuit 34 and a conductor layer 34E are formed on the back surface. The upper conductor layer 34P is formed as a power source plane layer, and the lower conductor layer 34E is formed as a ground plane layer. Furthermore, the inner layer conductor circuit 16 and conductor layer 16E are formed on the inner surface of the multilayer core substrate 30, and the conductor circuit 16 and conductor layer 16P are formed on the rear surface. The upper conductor layer 16E is formed as a ground plane layer, and the lower conductor layer 16P is formed as a power source plane layer. Connection to the power plane layer is made through a through hole or a via hole. The plain layer may be a single layer on one side or may be arranged in two or more layers. It is desirable to form with 2 to 4 layers. Since the improvement of electrical characteristics has not been confirmed with four or more layers, the effect is the same as that of four layers even when the number of layers is increased. In particular, the formation of two layers makes it difficult for warpage to occur because the elongation of the substrate is uniform in terms of rigidity matching of the multilayer core substrate. An electrically isolated metal plate 12 is accommodated in the center of the multilayer core substrate 30. (The metal plate 12 also plays a role as a core material, but is not electrically connected such as a through hole or a via hole. Mainly, the metal plate 12 is improved in rigidity against warping of the substrate.) 12, the inner layer conductor circuit 16 and conductor layer 16 </ b> E on the front side through the insulating resin layer 14, the conductor circuit 16 and conductor layer 16 </ b> P on the back side, and the conductor circuit 34 on the front side through the insulating resin layer 18. The conductor layer 34P and the conductor circuit 34 and the conductor layer 34E are formed on the back surface. The multilayer core substrate 30 is connected to the front surface side and the back surface side through a through hole 36.

  On the conductor layers 34P and 34E on the surface of the multilayer core substrate 30, an interlayer resin insulation layer 50 in which via holes 60 and conductor circuits 58 are formed, and an interlayer resin insulation layer in which via holes 160 and conductor circuits 158 are formed. 150 is arranged. A solder resist layer 70 is formed on the via hole 160 and the conductor circuit 158, and bumps 76 U and 76 D are formed on the via hole 160 and the conductor circuit 158 through the opening 71 of the solder resist layer 70. ing.

   As shown in FIG. 20, the solder bumps 76 </ b> U on the upper surface side of the multilayer printed wiring board 10 are connected to the lands 92 of the IC chip 90. Further, a chip capacitor 98 is mounted. On the other hand, the lower external terminal 76D is connected to the land 96 of the daughter board 94. The external terminals in this case refer to PGA, BGA, solder bumps, and the like.

  Here, the conductor layers 34P and 34E on the surface layer of the core substrate 30 are formed to have a thickness of 10 to 60 μm, the inner conductor layers 16P and 16E are formed to have a thickness of 10 to 250 μm, and the conductors on the interlayer resin insulation layer 50 are formed. The circuit 58 and the conductor circuit 158 on the interlayer resin insulation layer 150 are formed to 10 to 25 μm.

  In the multilayer printed wiring board of the fifth embodiment, the surface power layer (conductor layer) 34P, the conductor layer 34, the inner power layer (conductor layer) 16P, the conductor layer 16E, and the metal plate 12 of the core substrate 30 are thickened. This increases the strength of the core substrate. As a result, even if the core substrate itself is thinned, it is possible to relieve warpage and the generated stress by the substrate itself.

  Further, by increasing the thickness of the conductor layers 34P and 34E and the conductor layers 16P and 16E, the volume of the conductor itself can be increased. By increasing the volume, resistance in the conductor can be reduced.

  Furthermore, the power supply capability to the IC chip 90 can be improved by using the conductor layers 34P and 16P as the power supply layer. Therefore, when an IC chip is mounted on the multilayer printed board, the loop inductance from the IC chip to the board to the power source can be reduced. For this reason, the shortage of power supply in the initial operation is reduced, so that the shortage of power supply is less likely to occur. Therefore, even if an IC chip in a high frequency region is mounted, malfunctions and errors at the initial start-up are not caused. Furthermore, by using the conductor layers 34E and 16E as the ground layer, noise is not superimposed on the signal and power supply of the IC chip, and malfunctions and errors can be prevented. By mounting the capacitor, the power source stored in the capacitor can be used supplementarily, so that it becomes difficult to cause power shortage. In particular, the effect (which makes it difficult to cause a shortage of power supply) is significantly improved by disposing the IC chip immediately below the IC chip. This is because the wiring length in the multilayer printed wiring board can be shortened immediately below the IC chip.

  In the fifth embodiment, the multilayer core substrate 30 has thick conductor layers 16P and 16E on the inner layer and thin conductor layers 34P and 34E on the surface, and the inner conductor layers 16P and 16E and the conductor layers 34P and 34E on the surface. Are used as a power source layer conductor layer and a ground conductor layer. That is, even if the thick conductor layers 16P and 16E are arranged on the inner layer side, a resin layer covering the conductor layer is formed. Therefore, the surface of the multilayer core substrate 30 can be flattened by offsetting the unevenness due to the conductor layer. For this reason, even if the thin conductor layers 34P and 34E are arranged on the surface of the multilayer core substrate 30 so that the conductor layers 58 and 158 of the interlayer insulating layers 50 and 150 are not wavy, the inner conductor layers 16P and 16E are disposed. The sufficient thickness as the conductor layer of the core can be ensured by the added thickness. Since no undulation occurs, there is no problem with the impedance of the conductor layer on the interlayer insulating layer. By using the conductor layers 16P and 34P as the power supply layer conductor layers and the conductor layers 16E and 34E as the ground conductor layers, the electrical characteristics of the multilayer printed wiring board can be improved.

  Further, the microstrip structure can be formed by arranging the signal line 16 (same layer as the conductor layer 16E) between the conductor layer 34P and the conductor layer 16P in the core substrate. Similarly, a microstrip structure can be formed by arranging the signal line 16 (same layer as the conductor layer 16P) between the conductor layer 16E and the conductor layer 34E. By forming the microstrip structure, the inductance is reduced and impedance matching can be achieved. Therefore, electrical characteristics can also be stabilized.

  That is, the thickness of the inner conductor layers 16P and 16E of the core substrate is made thicker than the conductor layers 58 and 158 on the interlayer insulating layers 50 and 150. Thereby, even if the thin conductor layers 34E and 34P are arranged on the surface of the multi-layer core substrate 30, a sufficient thickness as the conductor layer of the core can be secured by adding the thick conductor layers 16P and 16E. The ratio is desirably 1 <(conductor layer of the inner layer of the core / conductor layer of the interlayer insulating layer) ≦ 40. It is further desirable that 1.2 ≦ (conductor layer of core inner layer / conductor layer of interlayer insulating layer) ≦ 30.

  The multilayer core substrate 30 has an inner conductor layer 16P, 16E on both surfaces of the electrically isolated metal plate 12 with a resin layer 14 interposed therebetween, and further a resin layer on the outer side of the inner conductor layer 16P, 16E. The surface conductor layers 34P and 34E are formed with 18 interposed. By disposing the electrically isolated metal plate 12 in the center, sufficient mechanical strength can be ensured. Further, the inner conductor layers 16P and 16E are disposed on both surfaces of the metal plate 12, and the inner conductor layers 16P and 16E are further disposed on the outer surface of the inner conductor layers 16P and 16E. By forming 34E, symmetry is provided on both surfaces of the metal plate 12, and warpage and undulation can be prevented from occurring in a heat cycle or the like.

  FIG. 21 shows a modification of the fifth embodiment. In this modified example, a capacitor 98 is disposed immediately below the IC chip 90. For this reason, the distance between the IC chip 90 and the capacitor 98 is short, and the voltage drop of the power source supplied to the IC chip 90 can be prevented.

Next, a method for manufacturing the multilayer printed wiring board 10 shown in FIG. 19 will be described with reference to FIGS.
(1) Formation of metal layer An opening 12a through which the front and back surfaces are purchased is provided in the inner metal layer (metal plate) 12 having a thickness of 50 to 400 μm shown in FIG. 12A (FIG. 12B). As a material for the metal layer, a material containing a metal such as copper, nickel, zinc, aluminum, or iron can be used. The opening 12a is formed by punching, etching, drilling, laser, or the like. In some cases, the entire surface of the metal layer 12 in which the opening 12a is formed may be coated with the metal film 13 by electrolytic plating, electroless plating, displacement plating, or sputtering (FIG. 12C). The metal plate 12 may be a single layer or a plurality of layers of two or more layers. The metal film 13 is preferably formed with a curved surface at the corner of the opening 12a. Thereby, there is no point where stress is concentrated, and it is difficult to cause defects such as cracks in the vicinity.

(2) Formation of inner insulating layer Insulating resin is used to cover the entire metal layer 12 and fill the opening 12a. As a forming method, for example, an insulating resin layer 14 can be formed by sandwiching a B-stage resin film having a thickness of about 30 to 200 μm between the metal plates 12 and thermosetting and then curing (FIG. 12D )). In some cases, coating, mixing of coating and film crimping, or coating only a quiet part, and then forming with a film.
As a material, it is desirable to use a prepreg in which a core material such as a glass cloth is impregnated with a thermosetting resin such as a polyimide resin, an epoxy resin, a phenol resin, or a BT resin. Besides that, a resin may be used.

(3) Affixing the metal foil The inner metal layer 16α is formed on both surfaces of the metal layer 12 covered with the resin layer 14 (FIG. 12E). As an example, a metal foil having a thickness of 12 to 275 μm was laminated. As a method other than forming the metal foil, a single-sided copper-clad laminate is laminated. It is formed on the metal foil by plating or the like.

(4) Two or more circuit formation layers of the inner metal layer may be used. The metal layer may be formed by an additive method.
Through the tenting method, the etching process, and the like, the inner conductor layers 16, 16P, and 16E were formed from the inner metal layer 16α (FIG. 12F). At this time, the inner conductor layer had a thickness of 10 to 250 μm. However, the above range may be exceeded.

(5) Formation of outer insulating layer Insulating resin is used to cover the entire inner conductor layers 16, 16P, 16E and to fill the gap between the outer metal layer and the circuit. As a forming method, for example, a B-stage resin film having a thickness of about 30 to 200 μm is sandwiched between metal plates, then thermocompression bonded and cured to form the outer insulating resin layer 18 (FIG. 13A). . In some cases, application, mixing of application and film crimping, or application of only the opening may be performed, and then the film may be formed. The surface can be flattened by applying pressure.

(6) Affixing the outermost metal foil The outermost metal layer 34β is formed on both surfaces of the substrate covered with the outer insulating resin layer 18 (FIG. 13B). As an example, a metal foil having a thickness of 10 to 275 μm is laminated. As a method other than forming the metal foil, a single-sided copper-clad laminate is laminated. Two or more layers may be formed on the metal foil by plating or the like. The metal layer may be formed by an additive method.

(7) Through-hole formation A through-hole 36α having an opening diameter of 50 to 400 μm penetrating the front and back of the substrate is formed (FIG. 13C). As a forming method, it is formed by drilling, laser or a combination of laser and drill (opening of the outermost insulating layer is performed by laser, and in some cases, the opening of the laser is used as a target mark, and then drilling is performed. Open and penetrate). As a shape, it is desirable to have a straight side wall. In some cases, it may be tapered.

In order to ensure the conductivity of the through hole, it is desirable to fill the filling resin 23 after forming the plating film 22 in the through hole 36α and roughening the surface (FIG. 13D) ( FIG. 13 (E)). Filling resins include electrically insulated resin materials (for example, those containing resin components, curing agents, particles, etc.), and conductive materials that are electrically connected by metal particles (for example, Any of those containing metal particles such as gold and copper, resin materials, curing agents, etc.) can be used.
As plating, electrolytic plating, electroless plating, panel plating (electroless plating and electrolytic plating), or the like can be used. The metal is formed because it contains copper, nickel, cobalt, phosphorus, or the like. The thickness of the plated metal is preferably formed between 5 and 30 μm.

  As the filling resin 23 to be filled in the through hole 36α for the through hole, it is desirable to use an insulating material made of a resin material, a curing agent, particles and the like. As the particles, inorganic particles such as silica and alumina, metal particles such as gold, silver and copper, and resin particles are used alone or in combination. A mixture of particles having a particle diameter of 0.1 to 5 μm having the same diameter or a composite diameter can be used. The resin material is a single or mixed epoxy resin (for example, bisphenol type epoxy resin, novolac type epoxy resin, etc.), thermosetting resin such as phenol resin, photosensitive ultraviolet curable resin, thermoplastic resin, etc. Can be used. As the curing agent, an imidazole curing agent, an amine curing agent, or the like can be used. In addition, a curing stabilizer, a reaction stabilizer, particles, and the like may be included. A conductive material may be used. In this case, what consists of a metal particle, a resin component, a hardening | curing agent, etc. becomes the electrically conductive paste which is an electroconductive material. Depending on the case, a material in which a conductive metal film is formed on the surface layer of an insulating material such as solder or insulating resin may be used. It is also possible to fill the through-hole through hole 36α by plating. This is because the conductive paste undergoes curing shrinkage, and may form recesses in the surface layer.

(8) Formation of outermost conductor circuit Cover plating 25 may be formed immediately above the through hole 36 by covering the entire surface with a plating film (FIG. 14A). After that, the outer layer conductor circuits 34, 34P, and 34E are formed through a tenting method, an etching process, and the like (FIG. 14B). Thereby, the multilayer core substrate 30 is completed.
At this time, although not shown, electrical connection with the inner conductor layer 16 and the like of the multilayer core substrate may be performed by a via hole, a blind through hole, or a blind via hole.

  In the subsequent manufacturing method, the interlayer resin insulating layers 50 and 150 and the conductor circuits 58 and 158 are formed on the multilayer core substrate 30 as in the first embodiment described above with reference to FIGS.

(9) The multilayer core substrate 30 on which the conductor circuit 34 is formed is blackened and reduced to form a roughened surface 34β on the entire surface of the conductor circuit 34 and the conductor layers 34P and 34E (FIG. 14C )).

(10) A layer of the resin filler 40 is formed on the conductor circuit non-forming portion of the multilayer core substrate 30 (FIG. 15A).

(11) Polishing one side of the substrate after the above processing by polishing with a belt sander or the like so that the resin filler 40 does not remain on the outer edges of the conductor layers 34P and 34E, and then removing scratches due to the polishing Further, the entire surfaces (including the land surfaces of the through holes) of the conductor layers 34P and 34E were further polished with a buff or the like. Such a series of polishing was similarly performed on the other surface of the substrate. Next, heat treatment was performed at 100 ° C. for 1 hour and 150 ° C. for 1 hour to cure the resin filler 40 (FIG. 15B).
Moreover, it is not necessary to perform resin filling between conductor circuits. In this case, the insulating layer is formed with a resin layer such as an interlayer insulating layer and the conductor circuit is filled.

(12) An etching solution is sprayed on both surfaces of the multilayer core substrate 30 by spraying to etch the surface of the conductor circuit 34, the conductor layers 34P, 34E, the land surface and the inner wall of the through hole 36, etc. A roughened surface 36β was formed on the entire surface of the circuit (FIG. 15C).

(13) The resin film 50γ for the interlayer resin insulation layer is placed on both sides of the multilayer core substrate 30, and after temporarily crimping and cutting, the interlayer resin insulation is further adhered by using a vacuum laminator device. A layer was formed (FIG. 16A).

(14) Next, with a CO2 gas laser having a wavelength of 10.4 μm, a beam diameter of 4.0 mm, a top hat mode, through a mask in which a through hole having a thickness of 1.2 mm is formed on the interlayer resin insulating layer, A via hole opening 50a having a diameter of 80 μm was formed in the interlayer resin insulating layer 2 under the conditions of a pulse width of 7.9 μs, a through-hole diameter of the mask of 1.0 mm, and one shot (FIG. 16B).

(15) The multilayer core substrate 30 is immersed in an 80 ° C. solution containing 60 g / l of permanganic acid for 10 minutes, and the roughened surface 50α is formed on the surface of the interlayer resin insulating layer 50 including the inner wall of the via hole opening 50a. Formed (FIG. 15C). The roughened surface was formed between 0.1 and 5 μm.

(16) Next, the multilayer core substrate 30 having been subjected to the above treatment was immersed in a neutralization solution (manufactured by Shipley Co., Ltd.) and then washed with water. Further, by applying a palladium catalyst to the surface of the substrate subjected to the roughening treatment (roughening depth 3 μm), catalyst nuclei were attached to the surface of the interlayer resin insulating layer and the inner wall surface of the via hole opening.

(17) Next, a substrate provided with a catalyst is immersed in an electroless copper plating aqueous solution to form an electroless copper plating film having a thickness of 0.6 to 3.0 μm on the entire rough surface. A substrate having an electroless copper plating film 52 formed on the surface of the interlayer resin insulation layer 50 including the inner wall of the opening 50a is obtained (FIG. 15D).

(18) A plating resist 54 is provided by pasting a commercially available photosensitive dry film on the substrate on which the electroless copper plating film 52 is formed, placing a mask, and developing (FIG. 17A). . The thickness of the plating resist was between 10 and 30 μm.

(19) Next, electrolytic plating was applied to the multilayer core substrate 30 to form an electrolytic copper plating film 56 having a thickness of 5 to 20 μm in the portion where the plating resist 54 was not formed (FIG. 17B).

(20) Further, after removing the plating resist with about 5% KOH, the electroless plating film under the plating resist is removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide to remove an independent conductor. A circuit 58 and a via hole 60 were formed (FIG. 17C).

(21) Next, the same processing as in the above (12) was performed to form roughened surfaces 58α and 60α on the surfaces of the conductor circuit 58 and the via hole 60. The upper conductor circuit 58 was formed to have a thickness of 5 to 25 μm. The thickness this time was 15 μm (FIG. 17D).

(22) By repeating the above steps (14) to (21), a further upper conductor circuit was formed to obtain a multilayer wiring board (FIG. 18A).

(23) Next, after applying a solder resist composition 70 to a thickness of 12 to 30 μm on both surfaces of the multilayer wiring board and performing a drying treatment at 70 ° C. for 20 minutes and 70 ° C. for 30 minutes ( FIG. 18B), a photomask having a thickness of 5 mm on which a pattern of the opening of the solder resist is drawn is brought into close contact with the solder resist layer 70, exposed to 1000 mJ / cm ² of ultraviolet light, developed with DMTG solution, and 200 μm. An opening 71 having a diameter of 5 mm was formed (FIG. 18C).
Further, the solder resist layer is cured by heating at 80 ° C. for 1 hour, 100 ° C. for 1 hour, 120 ° C. for 1 hour, and 150 ° C. for 3 hours. A solder resist pattern layer having a thickness of 10 to 25 μm was formed.

(24) Next, the substrate on which the solder resist layer 70 was formed was immersed in an electroless nickel plating solution to form a nickel plating layer 72 having a thickness of 5 μm in the opening 71. Further, the substrate was immersed in an electroless gold plating solution to form a 0.03 μm thick gold plating layer 74 on the nickel plating layer 72 (FIG. 18D). In addition to the nickel-gold layer, a single layer of tin or a noble metal layer (gold, silver, palladium, platinum, etc.) may be formed.

(25) After that, a solder paste containing tin-lead is printed in the opening 71 of the solder resist layer 70 on the surface on which the IC chip of the substrate is placed, and further, tin-lead is formed in the opening of the solder resist layer on the other surface. After printing a solder paste containing antimony, external terminals were formed by reflowing at 200 ° C. to produce a multilayer printed wiring board having solder bumps (FIG. 19).

The IC chip 90 is attached via the solder bumps 76U, and the chip capacitor 98 is mounted. And it attaches to the daughter board 94 via the external terminal 76D (FIG. 20).
Further, in the fifth embodiment, a case where 1 <(thickness of the power layer of the core substrate / thickness of the conductor layer of the interlayer insulating layer) ≦ 40 is used as a conforming example, and (thickness of the power layer of the core substrate / thickness of the interlayer insulating layer) The thickness of the conductor layer) ≦ 1 was taken as a comparative example. (The thickness of the power supply layer of the core substrate / the thickness of the conductor layer of the interlayer insulating layer)> 40 was used as a reference example.

(5th Example-1)
Although it is the same as that of 5th Example mentioned above with reference to FIG. 19, it set as follows.
The thickness of the inner conductor layer of the core substrate: 50 μm The thickness of the outer conductor layer: 20 μm
Sum of conductor circuit thickness of core substrate: 100 μm
Interlayer insulation layer conductor layer thickness: 15 μm
The inner conductor layer and the outer conductor layer served as the power supply layer. However, since the area of the surface conductor layer was about the land, the area was smaller than that of the inner conductor layer, so the effect of lowering the power supply was offset. Therefore, the sum of the thicknesses of the conductor layers of the core substrate is the sum of the two inner conductor layers.

(5th Example-2)
The inner conductor layer and the outer conductor layer served as the power supply layer. Electrical connections were made by through holes in each of the surface and inner layers.
The thickness of the inner conductor layer of the core substrate: 60 μm The thickness of the outer conductor layer: 20 μm
Sum of conductor circuit thickness of core substrate: 80 μm
Interlayer insulation layer conductor layer thickness: 15 μm
The inner conductor layer and the surface conductor layer each served as a power source layer. The area of the surface conductor layer was the same as the area of the inner conductor layer. It has the effect of lowering the power supply. Therefore, the sum of the thicknesses of the conductor layers of the core substrate is the sum of the inner conductor layer and the surface conductor layer.

(5th Example-3)
The inner conductor layer and the outer conductor layer served as the power supply layer. Electrical connections were made by through holes in each of the surface and inner layers.
The thickness of the inner conductor layer of the core substrate: 75 μm The thickness of the outer conductor layer: 20 μm
Sum of conductor circuit thickness of core substrate: 150 μm
Interlayer insulation layer conductor layer thickness: 15 μm
The inner conductor layer and the outer conductor layer served as the power supply layer. However, since the area of the surface conductor layer was about the land, the area was smaller than that of the inner conductor layer, so the effect of lowering the power supply was offset. Therefore, the sum of the thicknesses of the conductor layers of the core substrate is the thickness of the conductor layer of one inner layer.

(5th Example-4)
Same as Example 5 but manufactured as follows.
The thickness of the inner conductor layer (power supply layer) of the core substrate: 200 μm
Surface conductor layer (power supply layer) thickness: 20 μm
Sum of conductor circuit thickness of core substrate: 200 μm
Conductor layer thickness of the interlayer insulation layer: 10 μm
The sum of the conductor circuit thicknesses of the core substrate is obtained by adding the conductor layers of the inner layers.

(5th Example-5)
Same as Example 5 but manufactured as follows.
The thickness of the inner conductor layer (power supply layer) of the core substrate: 240 μm
Surface conductor layer (power supply layer) thickness: 20 μm
Sum of conductor circuit thickness of core substrate: 240 μm
Conductor layer thickness of the interlayer insulation layer: 8 μm
The sum of the conductor circuit thicknesses of the core substrate is obtained by adding the conductor layers of the inner layers.

(5th Example-6)
Same as Example 5 but manufactured as follows.
The thickness of the inner conductor layer (power supply layer) of the core substrate: 250 μm
Surface conductor layer (power supply layer) thickness: 25 μm
Sum of thickness of conductor circuit on core substrate: 300 μm
Conductor layer thickness of the interlayer insulation layer: 7.5 μm

[Sixth Embodiment] Core Board with Built-in Capacitor A multilayer printed wiring board according to a sixth embodiment will be described with reference to FIGS.
In the multilayer printed wiring board of the sixth embodiment, the chip capacitor 20 is built in the core substrate 30.

  FIG. 22 is a sectional view of the multilayer printed wiring board 10 according to the sixth embodiment, and FIG. 23 shows a state in which the IC chip 90 is attached to the multilayer printed wiring board 10 shown in FIG. As shown in FIG. 22, in the multilayer printed wiring board 10, the core substrate 30 includes a resin substrate 30A and a resin layer 30B. An opening 31a for accommodating the capacitor 20 is provided in the resin substrate 30A. The electrodes of the capacitor 20 are connected by via holes 33 provided in the resin layer 30B. A conductor layer 34P that forms a conductor circuit 34 and a power supply layer is formed on the upper surface of the core substrate 30, and an interlayer resin insulation layer 50 in which a via hole 60 and a conductor circuit 58 are disposed on both surfaces of the core substrate 30. Is formed. A through hole 36 is formed in the core substrate 30. A solder resist layer 70 is formed on the interlayer resin insulation layer 50. Bumps 76 U and 76 D are formed in the via hole 160 and the conductor circuit 158 through the opening 71 of the solder resist layer 70.

  As shown in FIG. 23, the solder bumps 76 </ b> U on the upper surface side of the multilayer printed wiring board 10 are connected to the lands 92 of the IC chip 90. Further, a chip capacitor 98 is mounted. On the other hand, conductive connection pins 99 for connection to the lower solder bumps are attached.

  Here, the conductor layer 34E is formed to be 30 μm. In the sixth embodiment, since the capacitor 20 is built in the core substrate 30, an effect superior to that of the first embodiment can be obtained.

(Sixth embodiment-1)
Although it is the same as that of the 6th Example mentioned above with reference to FIG. 22, it set as follows.
Core substrate conductor layer thickness: 30 μm Core substrate power layer thickness: 30 μm
Interlayer insulation layer conductor layer thickness: 15 μm

(6th Example-2)
Although it was the same as that of 6th Example, it set as follows.
Core substrate conductor layer thickness: 55 μm Core substrate power layer thickness: 55 μm
Interlayer insulation layer conductor layer thickness: 15 μm

(Sixth embodiment-3)
Core substrate conductor layer thickness: 75 μm Core substrate power layer thickness: 75 μm
Interlayer insulation layer conductor layer thickness: 15 μm

(Sixth embodiment-4)
Although it was the same as that of 6th Example-1, it set as follows.
Core substrate conductor layer (power supply layer) thickness: 180 μm
Conductor layer thickness of interlayer insulation layer: 6.0 μm

(Comparative example)
In the first to fifth examples, (the thickness of the power layer of the core substrate / the thickness of the conductor layer of the interlayer insulating layer) ≦ 1 was set as a comparative example. As an example, the thickness of the power layer of the core substrate was set to 15 μm, and the thickness of the conductor layer of the interlayer insulating layer was set to 15 μm.

(Reference example)
In the first to fifth embodiments, (the thickness of the power supply layer of the core substrate / the thickness of the conductor layer of the interlayer insulating layer) ≦ 40 was referred to. As an actual example, the thickness of the power supply layer of the core substrate was set to 415 μm, and the thickness of the conductor layer of the interlayer insulating layer was set to 10 μm.
In the reference example, the same effect as that of the conforming example can be obtained, but there is a possibility that a malfunction may occur in other cases, and the conforming example is not adapted slightly.

An IC chip with a frequency of 3.1 GHz was mounted on the substrates of each of the examples, comparative examples, and reference examples, and the same amount of power was supplied to measure the amount of voltage drop when starting. The average value of the voltage drop at this time is shown. It is an average value of the amount of voltage drop that fluctuates when the power supply voltage is 1.0V.
Moreover, the reliability test under the bias high temperature high humidity conditions (130, humidity 85 wt%, 2V application) of each Example, the comparative example, and the reference example was done. The test time was 100 hr, 300 hr, 500 hr, and 1000 hr, and the examples and comparative examples were verified for the presence or absence of malfunction of the IC and the presence or absence of via connection open of the core conductor layer. The results are shown in the charts of FIGS.
Furthermore, the thickness of the conductor layer was also verified. FIG. 29 shows the result of simulation with the horizontal axis (ratio of power supply layer thickness / interlayer insulating layer thickness) set and the maximum voltage drop (V) set on the vertical axis.

  This is based on the measurement results of all Examples, Comparative Examples, and Reference Examples. Others were created by simulation.

From FIG. 27 and FIG. 28, the IC created with the conforming example is unlikely to malfunction or open the IC chip. That is, electrical connectivity and reliability are ensured.
In the comparative example, since the IC chip malfunctions, there is a problem in electrical connectivity, and since the thickness of the conductor is thin, the stress generated under the reliability test cannot be buffered, and peeling at the via connection portion occurs. It has occurred. Therefore, the reliability has been reduced. However, when the ratio of the thickness of the power source layer of the core substrate / the thickness of the conductor layer of the interlayer insulating layer exceeds 1.2, the effect appears.
If the ratio of the thickness of the power layer of the core substrate / the thickness of the conductor layer of the interlayer insulating layer exceeds 40 (reference example), defects in the upper layer conductor circuit (for example, adhesion to the upper layer conductor circuit due to the occurrence of stress or undulation) The reliability has decreased due to a decrease in the value. Usually, there is no problem, but depending on factors such as materials, the tendency may appear.
It is 1 <(thickness of the power supply layer of the core substrate / thickness of the conductor layer of the interlayer insulating layer) that satisfies the electrical characteristics from the result of the test. Further, it is 1 <(thickness of conductor layer of core substrate / thickness of interlayer insulating layer) ≦ 40 that satisfies factors of electrical characteristics and reliability.

According to the results of FIGS. 27 and 28, in this case, when the power supply voltage is 1.0 V, if the fluctuation allowable range is ± 10%, the behavior of the voltage is stable and the IC chip does not malfunction. . That is, in this case, if the voltage drop amount is within 0.1V, malfunctions to the IC chip due to the voltage drop will not be caused. If it is 0.09 V or less, stability will increase. Therefore, the ratio of (the thickness of the power supply layer of the core substrate / the thickness of the interlayer insulating layer) should preferably exceed 1.2. Furthermore, if the range is 1.2 ≦ (thickness of the power supply layer of the core substrate / thickness of the interlayer insulating layer) ≦ 40, the numerical value tends to decrease, so that the effect is easily obtained. In addition, in the range of 40 <(thickness of power layer of core substrate / thickness of interlayer insulating layer), the voltage drop amount is increased, and thus there is a problem in voltage supply due to via peeling at the core portion. Will be. If via peeling can be suppressed by selecting a material, the above problem can be solved. There is no problem in the normal use range.
Further, if 5.0 <(thickness of the power supply layer of the core substrate / thickness of the interlayer insulating layer) ≦ 40, the voltage drop amount is almost the same, so that it is stable. That is, it can be said that this range is the most desirable ratio range.

By this invention, the resistance in the conductor of IC chip-board | substrate-power supply can be reduced, and transmission loss is reduced. For this reason, the signal and power to be transmitted exert the desired ability. For this reason, since the function and operation of the IC chip operate normally, no malfunction or error occurs. Resistance in the IC chip to substrate to ground conductors can be reduced, noise superimposed on signal lines and power supply lines can be reduced, and malfunctions and errors can be prevented.
It can also be seen that the present invention reduces the degree of power shortage (voltage drop) that occurs at the time of initial startup of the IC chip, and even if an IC chip in a high frequency region, particularly an IC chip of 3 GHz or more is mounted, startup without problems I found out that I can do it. Therefore, electrical characteristics and electrical connectivity can be improved.
Furthermore, the resistance in the circuit of the printed circuit board can be reduced as compared with the conventional printed circuit board. Therefore, even when a reliability test (high temperature and high humidity bias test) performed under high temperature and high humidity with a bias applied is performed, the time for destruction increases, so that the reliability can be improved.

12 Metal layer (metal plate)
14 resin layer 16 conductor circuit 16P conductor layer 16E conductor layer 18 resin layer 30 substrate 32 copper foil 34 conductor circuit 34P conductor layer 34E conductor layer 36 through hole 40 resin filling layer 50 interlayer resin insulation layer 58 conductor circuit 60 via hole 70 solder resist Layer 71 Opening 76U, 76D Solder bump 90 IC chip 94 Daughter board 98 Chip capacitor

Claims (13)

A resin core substrate having a conductor layer formed on the surface, an interlayer resin insulation layer formed on the core substrate, a conductor layer formed on the interlayer resin insulation layer, and the core substrate surface In the multilayer printed wiring board having a via hole for electrically connecting the conductor layer and the conductor layer on the interlayer resin insulation layer,
Capacitor component, or a built-in resistor components before Symbol core substrate,
The conductor layer on the surface of the core substrate connected to the capacitor component or the electrode of the resistor component through a via hole is a conductor layer for power supply or a conductor layer for ground ,
The capacitor component through the via hole, or the thickness of the conductor layer of the core substrate surface to be connected to the resistive component of the electrode, the multilayer characterized thicker than thickness of the conductive layer on the interlayer insulating layer Printed wiring board. A resin core substrate having a conductor layer formed on the surface, an interlayer resin insulation layer formed on the core substrate, a conductor layer formed on the interlayer resin insulation layer, and the core substrate surface In the multilayer printed wiring board having a via hole for electrically connecting the conductor layer and the conductor layer on the interlayer resin insulation layer,
The conductor layer on the surface of the core substrate is a conductor layer for power supply or a conductor layer for ground, and at least one of a capacitor component, a dielectric layer for constituting a capacitor , and a resistor component in the core substrate. Built-in and
A multilayer printed wiring board, wherein α2 <α1 ≦ 40α2 with respect to α1 for the thickness of the conductor layer on the core substrate and α2 for the thickness of the conductor layer on the interlayer insulating layer. The multilayer printed wiring board according to claim 2, wherein the α1 satisfies 1.2α2 ≦ α1 ≦ 40α2. The multilayer printed wiring board according to claim 1, wherein a capacitor is mounted on the surface. A resin core substrate having a conductor layer formed on the surface, an interlayer resin insulation layer formed on the core substrate, a conductor layer formed on the interlayer resin insulation layer, and the core substrate surface In the multilayer printed wiring board having a via hole for electrically connecting the conductor layer and the conductor layer on the interlayer resin insulation layer,
The core substrate is a multilayer core substrate of three or more layers having a conductor layer on the front and back and a thick conductor layer on the inner layer, and the inner conductor layer of the core substrate is formed thicker than the conductor layer on the interlayer insulating layer And
At least one of the inner conductor layer and the front and back conductor layers of the core substrate is a power source conductor layer or a ground conductor layer,
A multilayer printed wiring board, wherein at least one of a capacitor component, a dielectric layer for constituting a capacitor , and a resistor component is built in the core substrate. A resin core substrate having a conductor layer formed on the surface, an interlayer resin insulation layer formed on the core substrate, a conductor layer formed on the interlayer resin insulation layer, and the core substrate surface In the multilayer printed wiring board having a via hole for electrically connecting the conductor layer and the conductor layer on the interlayer resin insulation layer,
The core substrate is a multilayer core substrate of three or more layers having a conductor layer on the front and back and a thick conductor layer on the inner layer, and the inner conductor layer of the core substrate is formed thicker than the conductor layer on the interlayer insulating layer And
Among the conductor layers of the inner layer of the core substrate, at least one layer is a conductor layer for a power supply layer or a conductor layer for ground, and at least one conductor layer of the front and back is composed of a signal line,
A multilayer printed wiring board, wherein at least one of a capacitor component, a dielectric layer for constituting a capacitor , and a resistor component is built in the core substrate. The multilayer printed wiring board according to claim 5, wherein the inner conductor layer of the core substrate has two or more layers. The core substrate incorporates an electrically isolated metal plate , a resin layer is interposed on both surfaces of the metal plate, the inner layer conductor layer is further disposed, and the resin layer is disposed outside the inner layer conductor layer. The multilayer printed wiring board according to any one of claims 5 to 7, wherein the front and back conductor layers are formed so as to intervene. The multilayer printed wiring board according to any one of claims 5 to 8, wherein the inner conductor layer of the core substrate is thicker than the conductor layers on the front surface and the back surface. The multilayer printed wiring board according to any one of claims 5 to 9, wherein each conductor layer of the inner layer of the core substrate is either a power source conductor layer or a ground conductor layer. The conductor layer on the surface of the core substrate is a power source conductor layer or a ground conductor layer, and the back conductor layer is a power source conductor layer or a ground conductor layer. Item 11. The multilayer printed wiring board according to any one of Items 10. 7. The multilayer printed wiring board according to claim 5, wherein a power supply layer of an inner layer of the core substrate is disposed immediately below the IC chip. The multilayer printed wiring board according to claim 5 or 6, wherein a signal line is disposed between conductor layers of the core substrate.

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