JP2009099621A - Method of manufacturing substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a substrate, that correctly etches a conductor formed on the surface of the substrate in the production steps for substrates including a step of forming a through-hole in the substrate and fill it with an insulating material. <P>SOLUTION: The method includes the steps of: forming a through-hole 18 in a substrate 16; filling the through-hole 18 with an insulating material 20 and performing electroless plating to coat the surface of the substrate 16; applying photoresist on the electroless-plated layer 80 formed on the surface of the substrate 16; optically exposing and developing the photoresist so as to form a resist pattern 72 coating an end face of the through-hole 18 filled with the insulating material 20; etching conductor layers 14 and 19 formed on the surface of the substrate 16 while using the resist pattern 72 as a mask; and removing the resist pattern 72 coating the end face of the through-hole 18 from the substrate 16 while using the electroless-plated layer 80 as a release layer. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a core substrate and a method for manufacturing a substrate that can be applied to manufacturing a wiring substrate using the core substrate, and more particularly to a method for manufacturing a substrate having a step of filling a through hole formed in the substrate with a resin.

  There are products in which a core substrate is provided with a carbon fiber reinforced plastic (CFRP) as a test substrate used for inspecting a wiring board on which a semiconductor element is mounted or a semiconductor wafer. The core substrate equipped with this carbon fiber reinforced plastic has a lower coefficient of thermal expansion than the core substrate made of the conventional glass epoxy substrate, and matches the thermal expansion coefficient of the substrate with the thermal expansion coefficient of the semiconductor element mounted on the substrate. The thermal stress generated between the semiconductor element and the wiring board can be avoided.

  The wiring board is formed by laminating wiring layers on both sides of the core board, and a conductive through hole PTH (Plated through hole) is formed on the core board for electrical connection with the wiring layer laminated on both sides of the core board. The The conductive through hole is formed by forming a through hole in the substrate and forming a conductive portion (plating layer) on the inner wall surface of the through hole by plating.

By the way, in the case of a core substrate having a conductive core portion such as a carbon fiber reinforced plastic, simply forming a through hole in the substrate and plating the inner wall surface of the through hole results in a conduction through hole and a core portion. Are electrically short-circuited. For this reason, when a conductive through hole is formed in a core substrate having a conductive core portion, a hole having a diameter larger than that of the conductive through hole is formed in the core substrate, and the insulating resin is formed in the lower hole. After filling the conductive hole, the conductive through hole is passed through the lower hole so that the conductive through hole and the core portion are not electrically short-circuited (see Patent Documents 1 and 2).
Table 2004/064467 JP 2006-222216 A JP 2001-203458 A

  By the way, when the pilot hole provided in the core part constituting the core substrate is formed by drilling, a burr is generated on the inner wall surface of the pilot hole, and the conductive through hole penetrated through the pilot hole and the core part are electrically connected. There is a risk of conduction. For this reason, in Patent Document 2, for example, a method is adopted in which the inner wall surface of the lower hole is covered with an insulating layer so that the conductive through hole and the core portion having conductivity are not electrically short-circuited. However, it is not always easy to reliably cover the inner wall surface of the rough hole with the insulating layer.

In addition, when a conductive through hole is formed so as to penetrate the lower hole, the lower hole is filled with a resin material, but the end surface of the resin material filled in the lower hole is not electrically short-circuited with the conductive through hole. Thus, it is necessary to prevent the conductor layer from being deposited.
The core substrate is formed by laminating wiring layers on both sides of the core portion. When the core portion is formed of a material having a low thermal expansion coefficient, such as carbon fiber reinforced plastic, the thermal expansion coefficient of the wiring layer is low. Because it is quite large, a large thermal stress due to the difference in thermal expansion coefficient acts between the core and the wiring layer, causing problems such as peeling or cracking at the interface between the core and the wiring layer. To do.

  The present invention relates to a method for manufacturing a substrate, in particular, a manufacturing process of a substrate having a core part having conductivity, in which a prepared hole is formed in the substrate, an insulating material is filled in the prepared hole, and a conductive through is further formed in the prepared hole. It is an object of the present invention to provide a substrate manufacturing method that can be suitably applied to a substrate manufacturing method including a process of forming a hole.

The present invention has the following configuration in order to achieve the above object.
That is, a step of forming a through hole in the substrate, a step of filling the through hole with an insulating material, a step of performing electroless plating on the surface of the substrate filled with the insulating material, and a surface of the substrate Laminating a photoresist on the formed electroless copper plating layer, exposing and developing the photoresist, and forming a resist pattern covering the end face of the through-hole filled with the insulating material; and the resist pattern And etching the conductive layer deposited on the surface of the substrate, and removing the resist pattern covering the end face of the through-hole from the substrate using the electroless plating layer as a release layer. It is characterized by providing.
The present invention can be applied not only to a substrate having a conductive core part but also to a substrate having a resin core and other wiring boards. The electroless plating formed on the surface of the substrate is provided so that the resist pattern can be easily peeled off from the insulating material filled in the through holes after etching the conductor layer deposited on the surface of the substrate. Yes. As electroless plating, for example, electroless copper plating can be used.

In addition, the through hole is formed as a lower hole that penetrates the conductive through hole, and is applied as a method of performing electroless plating on the surface of the substrate in which the lower hole is filled with an insulating material and the lower hole is filled with an insulating material. can do.
In addition, electroless plating is performed on the substrate, the end surface of the pilot hole filled with the insulating material is covered with a resist pattern, the conductive layer deposited on the surface of the substrate is etched, and the resist pattern is removed. Then, a through-hole penetrating the pilot hole is formed, and the inner wall surface of the through-hole is covered with plating to form a conductive through-hole.
Further, following the step of removing the resist pattern from the substrate, a step of laminating and forming a wiring layer on both surfaces of the substrate is provided, and a through hole penetrating the pilot hole is formed in the substrate on which the wiring layer is integrally formed. And forming the conductive through hole. As a result, a core substrate having wiring layers formed on both sides of the substrate is obtained.

In addition, the substrate includes a conductive core portion, and after the through hole is formed, the substrate is plated, and the inner wall surface of the through hole is covered with a plating layer, and is insulated from the through hole. After filling the material, the surface of the substrate is subjected to electroless plating.
Further, the through hole is formed as a lower hole penetrating the conductive through hole, and includes a step of plating the substrate to cover the inner wall surface of the lower hole with a plating layer, and filling the lower hole with an insulating material Then, electroless plating is performed on the surface of the substrate.
Even when the inner surface of the lower hole formed by drilling is coated by coating the inner wall surface of the lower hole formed in the core portion having conductivity with the plating layer, the inner surface of the lower hole becomes rough. By covering the inner wall surface with the plating layer, an electrical short circuit between the conductive through hole and the core portion can be prevented.
In addition, by coating the inner wall surface of the lower hole with a plating layer, the inner wall surface of the lower hole is smoothed, and when the insulating material such as resin is filled in the lower hole, voids can be prevented from being generated, This can also prevent electrical short-circuiting between the conductive through hole and the core portion.

  Further, following the step of coating the inner wall surface of the lower hole with a plating layer, the method includes a step of coating the inner wall surface of the lower hole with an insulating film by an electrodeposition method using the plating layer as a power supply layer, The insulating material is filled in a prepared hole whose inner wall surface is covered with an insulating coating. By covering the inner wall surface of the pilot hole with an insulating film in addition to the plating layer, an electrical short circuit between the conductive through hole and the core portion can be prevented more reliably.

In addition, after the step of electroless plating on the surface of the substrate, the step of forming the resist pattern, the step of etching the conductor layer deposited on the surface of the substrate, the step of removing the resist pattern from the substrate, The method includes a step of forming a through hole penetrating the lower hole, and coating the inner wall surface of the through hole with plating to form a conductive through hole.
Further, after the step of removing the resist pattern from the substrate, a step of laminating and forming a wiring layer on both surfaces of the substrate, and a through hole penetrating the pilot hole in the substrate on which the wiring layer is integrally formed And forming the conductive through hole.
Further, following the step of forming the conductive through hole, a step of filling the through hole with a resin, and etching the conductive layer deposited on the surface of the substrate into a predetermined pattern, through the conductive through hole. Forming a wiring pattern electrically connected to the surface of the substrate. As a result, a core substrate is obtained in which the wiring layers are formed on both surfaces of the substrate and the wiring layers are electrically connected through the conductive through holes.

Further, a wiring board in which wiring layers are laminated on both surfaces of the core substrate is obtained by providing a step of laminating wiring layers on both surfaces of the substrate formed by the substrate manufacturing method.
The wiring layer can be formed in any number of layers on both sides of the substrate by a build-up method.
In addition, the step of forming the core portion includes a step of superposing a plurality of prepregs containing carbon fibers, pressurizing and heating to form a flat plate. By pressure bonding a prepreg containing carbon fiber to form a core portion, a substrate having a smaller thermal expansion coefficient than that of the resin substrate can be obtained.

The method for producing a substrate according to the present invention is characterized in that a step of performing electroless plating on the surface of the substrate in which the through hole is filled with an insulating material is employed. By forming a resist pattern so as to cover the end face of the through hole filled with the insulating material, the conductor layer formed on the surface of the substrate can be removed by etching, and the through hole filled with the insulating material can be removed. The resist pattern can be easily peeled off from the end face of the hole.
Thereby, a manufacturing process can be made exactly and easily. In addition, by appropriately removing the conductive layer deposited on the surface of the substrate by etching, the adhesion between the substrate and the wiring layer when forming the core substrate or the wiring substrate by stacking the wiring layer on the substrate. As a result, the thermal expansion coefficient is different between the substrate and the wiring layer, so that the problem that peeling occurs at the interface between the substrate and the wiring layer can be avoided.

(Manufacturing method of core substrate)
Hereinafter, as an embodiment of a method for manufacturing a substrate according to the present invention, a method for manufacturing a core substrate having a conductive core portion will be described.
1 and 2 show a process from forming a pilot hole penetrating a conductive through hole of a core substrate to a substrate, forming a gas venting hole, and filling the pilot hole with an insulating material.
FIG. 1A shows a substrate 16 formed into a flat plate by bonding a copper foil 14 to both surfaces of a core portion 10 made of carbon fiber reinforced plastic via a prepreg 12. The core portion 10 is integrally formed by stacking four prepregs in which a carbon cloth is impregnated with a polymer material such as an epoxy resin, and heating and pressing. It should be noted that the number of prepregs including the carbon fiber constituting the core 10 can be arbitrarily selected.

  In the present embodiment, the core portion 10 is formed using a carbon fiber cloth made of long-fiber carbon fiber, but in addition to the carbon fiber cloth, a carbon fiber nonwoven fabric, a carbon fiber mesh, or the like can be used. The thermal expansion coefficient of the carbon fiber is about 0 ppm / ° C., and the thermal expansion of the core 10 is selected by selecting the carbon fiber content in the carbon fiber reinforced plastic, the resin impregnated in the carbon fiber, and the filler material mixed in the resin. The coefficient can be adjusted. The thermal expansion coefficient of the core part 10 of this embodiment is about 1 ppm / ° C.

  Also, the thermal expansion coefficient of the entire core substrate including the core portion 10 made of carbon fiber reinforced plastic can be adjusted by selecting the thermal expansion coefficient of the wiring layer constituting the core substrate and the insulating layer interposed between the wiring layers. it can. In addition, the thermal expansion coefficient of the wiring board formed by laminating wiring layers on both sides of the core board by the build-up method etc. is the thermal expansion coefficient of the core board and the wiring layer (build-up layer) formed on both sides thereof. It can be adjusted by selecting. The thermal expansion coefficient of the semiconductor element is about 3.5 ppm / ° C. It is easy to match the thermal expansion coefficient of the wiring board with the thermal expansion coefficient of the semiconductor element mounted thereon.

  FIG. 1B shows a state in which a prepared hole 18 is formed in the substrate 16. The lower hole 18 is formed by drilling so as to penetrate the substrate 16 in the thickness direction. The lower hole 18 is formed to have a larger diameter than the through hole of the conductive through hole formed in a later step. In this embodiment, the hole diameter of the lower hole 18 is 0.8 mm, and the hole diameter of the conduction through hole is 0.35 mm. The lower hole 18 is formed in accordance with the planar arrangement position of each conductive through hole formed in the core substrate.

When the lower hole 18 is drilled, the inner wall surface of the lower hole 18 is flashed due to wear of the drill, the inner wall surface becomes a rough surface (irregular surface), and the chips 11 of the core portion 10 adhere to the inner wall surface. May remain.
In the case of the core part 10 made of carbon fiber reinforced plastic, the carbon chips 11 remain attached to the inner wall surface of the lower hole 18 and the chips 11 have conductivity. When mixed in the resin 20 serving as an insulating material filled in 18, the insulation of the resin 20 is hindered, resulting in an obstacle that the conductive through hole and the core portion 10 are electrically short-circuited.

  In the present embodiment, in order to prevent short-circuiting between the conductive through hole and the core portion 10, a hole 18 is formed in the substrate 16, and then electroless copper plating and electrolytic copper plating are applied to the substrate 16 in this order. A step of coating the inner wall surface of the substrate with the plating layer 19 is employed. By applying electroless copper plating to the substrate 16, an electroless copper plating layer is formed on the entire inner surface of the pilot hole 18 and the entire front and back surfaces of the substrate 16. By performing electrolytic copper plating using the electroless copper plating layer as a plating power feeding layer, the plating layer 19 can be formed on the inner surface of the pilot hole 18 and on both surfaces of the substrate 16. The thickness of the electroless copper plating layer is about 0.5 μm, and the thickness of the electrolytic copper plating layer is about 10 to 20 μm.

  As described above, when the inner wall surface of the lower hole 18 is covered with the plating layer 19, the inner wall surface of the lower hole 18 becomes a smooth surface, so that the resin 20 is easily filled in the lower hole 18, and voids are generated in the resin 20. Therefore, it is possible to prevent the conductive through hole and the core portion 10 from being electrically short-circuited at the void portion. Further, the chips 11 attached to the inner wall surface of the lower hole 18 are shielded by the plating layer 19, and are difficult to peel off from the inner wall surface of the lower hole 18, so that the insulating property of the resin 20 is maintained.

  By the way, in the process of filling the resin 20 in the lower hole 18, a heat curing process is passed to thermally cure the resin 20, and in this case, the resin 20 is decomposed from the solvent or the like contained in the resin constituting the core portion 10. Gas is generated, and moisture absorbed in the core 10 during the manufacturing process is generated as water vapor.

  The decomposable gas or water vapor generated in the heat curing process tends to escape to the outside of the core portion 10 via some path, but the plating layer 19 is formed on the substrate 16 including the inner wall surface of the lower hole 18. Since the entire surface is completely covered, there is no escape of gas, and the plating layer 19 on the inner wall surface of the lower hole 18 swells, and the copper foil 14 and the plating layer 19 on the surface of the substrate 16 swell. Since the plating layer 19 is provided for the purpose of smoothing the inner wall surface of the lower hole 18 and covering the inner wall surface of the lower hole 18, if the plating layer 19 is swollen, the purpose is not achieved.

The configuration in which the entire surface including the inner wall surface of the lower hole 18 of the substrate 16 is completely covered with the plating layer 19 or the copper foil 14 is a problem in heating in the process of filling the lower hole 18 with the resin 20. In addition to this, there is a problem in forming a wiring layer on both surfaces of the substrate 16 by heating and pressing the wiring sheet via a prepreg.
Further, when a build-up layer is formed on both surfaces of the core substrate to form a wiring substrate, there is a heating step during the manufacturing process. In this case as well, copper is generated by the gas generated from the core portion 10 of the inner layer or the substrate. There may be a problem that the foil 14 or the plating layer 19 swells.

For this reason, in this embodiment, in order to secure a path through which the decomposable gas or water vapor generated from the core portion 10 is extracted, the gas vent holes 140 are formed on the surface of the substrate 16. FIG. 1D shows a portion where a dry film resist (photoresist) is laminated on the surface of the substrate 16 to form the gas vent holes 140 on the surface of the substrate 16, and the gas vent holes 140 are formed by exposure and development. A state in which a resist pattern 70 is formed in which is exposed is shown.
The vent holes 140 are formed by partially drilling the copper foil 14 covering the surface of the substrate 16 and the plating layer 19 laminated on the copper foil 14 to expose the surface of the prepreg 12 covering the outer surface of the core portion 10. This is for forming a path for communicating the core portion 10 and the outside.

  The position and size of the gas vent hole 140 can be selected as appropriate. In this embodiment, in order to avoid the swelling of the plating layer 19 on the inner wall surface of the lower hole 18, the gas vent hole 140 is arranged in the vicinity of the lower hole 18. In the present embodiment, the interval D between the gas vent hole 140 and the opening edge of the lower hole 18 is set to 300 to 350 μm, but the position where the gas vent hole 140 is disposed is a side surface when the gas vent hole 140 is formed by etching. It may be determined in consideration of the etching amount.

  FIG. 2A shows a state in which the vent layer 140 is formed by etching the plating layer 19 and the copper foil 14 using the resist pattern 70 as a mask. At the portion where the gas vent hole 140 is formed, the surface of the lower prepreg 12 is exposed, the core portion 10 communicates with the outside of the substrate 16 via the gas vent hole 140, and the core portion 10 communicates with the outside. A path is formed.

  FIG. 3 shows a state in which the vent holes 140 are formed on the surface of the substrate 16 as viewed from the plane direction of the substrate 16. The lower holes 18 penetrating the substrate 16 are aligned and arranged at predetermined intervals in the vertical and horizontal directions, and four degassing holes 140 are arranged in the vicinity of the periphery of the lower hole 18 as a cross arrangement. The surface of the prepreg 12 is exposed on the bottom surface of the gas vent hole 140. The surface of the substrate 16 is a plating layer 19. FIG. 2A is a cross-sectional view taken along line AA in FIG.

The arrangement of the pilot holes 18 formed in the substrate 16 is not limited to a method of arranging them in the vertical and horizontal directions, and any arrangement can be adopted. Of course, a plurality of the gas vent holes 140 may be arranged in the middle of the adjacent lower holes 18, arranged around the lower holes 18 in a radial direction, or arranged at predetermined intervals in the plane of the substrate 16. You can also
As described above, the gas vent hole 140 is disposed in the vicinity of the opening edge of the lower hole 18 in order to make the gas venting action from the vicinity of the lower hole 18 effective. If a large number of gas vent holes 140 are formed on the surface of the substrate 16 in addition to the periphery of the lower hole 18, the gas can easily escape from the core portion 10, and a large number of irregularities are formed on the surface of the substrate 16. When the insulating layer is deposited on the surface of the substrate 16, an effect of increasing the bonding strength between the insulating layer and the substrate 16 can be obtained.

FIG. 2B shows a state in which the lower hole 18 is filled with a resin 20 as an insulating material. The resin 20 can be filled in the prepared holes 18 using a screen printing method or a metal mask.
After filling the prepared hole 18 with the resin 20, the resin 20 is cured by a heat curing process. In the present embodiment, a thermosetting epoxy resin is used, and the resin 20 is heated to about 160 ° C. in the step of heat curing. Since the gas vent hole 140 is formed on the surface of the substrate 16, the decomposable gas or water vapor generated from the core portion 10 in the heating process is discharged to the outside through the gas vent hole 140, and the plating layer 19 or the copper foil 14. It is possible to prevent an obstacle such as swelling.
After filling the lower hole 18 with the resin 20 and thermosetting, the end face of the resin 20 protruding from the lower hole 18 is polished to flatten the end face of the resin 20, and the surface of the substrate 16 and the end face of the resin 20 are Polishing to be flush.

FIG. 4 shows a process example in which the inner wall surface of the lower hole 18 is covered with the plating layer 19 and then the inner wall surface of the lower hole 18 is further covered with the insulating coating 21. FIG. 4A shows a state in which the prepared hole 18 shown in FIG.
FIG. 4B shows an insulating coating 21 on the surface of the copper foil 14 and the plating layer 19 deposited on the inner wall surface of the pilot hole 18 and the surface of the substrate 18 by an electrodeposition method using the plating layer 19 as a power supply layer. The state which formed is shown. Since the plating layer 19 is deposited on the inner wall surface of the lower hole 18 and the entire surface of the substrate 16, by applying an electrodeposition method using the plating layer 19 as a power supply layer, the entire inner surface of the lower hole 18 is formed. An insulating coating 21 can be applied to the entire surface of the substrate 16. For example, the insulating coating 21 can be electrodeposited by a constant current method by immersing the substrate 16 in an electrodeposition solution of epoxy resin, connecting the plating layer 19 to a DC power source.
This insulating coating 21 is provided to more reliably prevent an electrical short circuit between the lower hole 18 and the conductive through hole.
After the insulating coating 21 is deposited on the surface of the substrate 16 and the inner wall surface of the lower hole 18, the insulating coating 21 is cured by performing a drying process and a heating process. The thickness of the insulating coating 21 is 10 to 20 μm.

FIG. 4C shows a state in which the resin hole 20 is filled in the prepared hole 18 whose inner wall surface is covered with the insulating coating 21. Since the gas vent hole 140 is provided on the surface of the substrate 16 even when the resin 20 is thermally cured by heating curing after filling the resin 20 in the lower hole 18, the gas generated from the core 10, the substrate The water vapor absorbed by the water is discharged from the gas vent hole 140 and can be processed without causing deformation such as swelling of the copper foil 14, the plating layer 19 and the insulating coating 21.
After filling the lower hole 18 with the resin 20 and thermosetting, the end surface of the resin 20 protruding from the lower hole 18 is polished and processed into a flat surface. During this polishing process, the insulating coating 21 on the surface of the substrate 16 is removed by polishing, so that the surface of the substrate 16 and the end surface of the resin 20 are flush with each other.

  The reason why the inner wall surface of the lower hole 18 is covered with the plating layer 19 is that the inner wall surface of the rough hole 18 is a smooth surface so that no voids are generated when the lower hole 18 is filled with the resin 20. This is to prevent electrical short-circuit between the conductive through hole and the conductive core portion 10 at the void portion generated in the resin 20. When laminated on the plating layer 19 and further covered with the insulating coating 21, the smoothness of the inner wall surface of the lower hole 18 is further improved, the filling property of the resin 20 is improved, and the insulating coating 21 is electrically connected to the lower hole 18. By being interposed between the through hole, an electrical short circuit between the core portion 10 and the conductive through hole can be more reliably prevented.

As shown in FIG. 2B or FIG. 4C, the core substrate is formed by filling the resin hole 20 in the lower hole 18 provided in the substrate 16 and then laminating wiring layers on both surfaces of the substrate 16. The through hole is made to pass through the lower hole 18.
In this case, if there is a large difference between the thermal expansion coefficient of the core portion 10 of the substrate 16 and the thermal expansion coefficient of the wiring layer, the interface between the substrate 16 and the wiring layer is peeled off or cracks are generated at the interface. Therefore, a conductor such as a copper foil is not interposed between the substrate 16 and the wiring layer, and the prepreg (resin layer) 12 is exposed on the surface of the substrate 16, and the insulating layer of the wiring layer and the insulating layer of the substrate 16 are It is good to make it join. This is because the adhesion between the resins is much stronger than the adhesion between the resin and the copper foil.

(Conductor layer etching process)
For this reason, FIG. 5 shows that the dry film resist (photoresist) is laminated on the surface of the substrate 16, and the copper foil 14 and the plating layer 19 are left with a predetermined width along the outer peripheral edge of the lower hole 18. The process of removing the copper foil 14 and the plating layer 19 from the surface is shown.
FIG. 5A shows a state in which the prepared hole 18 provided in the substrate 16 is filled with the resin 20 and then the surface of the substrate 16 is subjected to electroless copper plating, and the surface of the substrate 16 is covered with the electroless copper plating layer 80. Indicates.
FIG. 5B shows a state in which a dry film resist (photoresist) is laminated on the front and back surfaces of the substrate 16 subjected to electroless copper plating, and is exposed and developed to form a resist pattern 72. The resist pattern 72 is formed so as to cover with a predetermined width along the outer peripheral edge of the lower hole 18.

FIG. 5C shows a state in which chemical etching is performed using the resist pattern 72 as a mask, and the electroless copper plating layer 80, the plating layer 19, and the copper foil 14 are removed from the portion exposed on the surface of the substrate 16. .
Since the resist pattern 72 is provided so as to cover with a predetermined width along the region of the lower hole 18 and the outer peripheral edge of the lower hole 18, when the resist pattern 72 is etched as a mask, the copper foil 14 is ring-shaped around the lower hole 18. And the plating layer 19 remains.
FIG. 5D shows a state in which the land 142 is formed by the copper foil 14 and the plating layer 19 remaining along the outer peripheral edge of the lower hole 18. The prepreg 12 is exposed on the surface of the substrate 16, and the lower hole 18 is filled with a resin 20. The end surface of the resin 20 filled in the lower hole 18 and the end surface (upper surface) of the land 142 are flush with each other.

In the step shown in FIG. 5A, the electroless copper plating is performed on both surfaces of the substrate 16 because the resist pattern 72 is removed after the copper foil 14 and the plating layer 19 are etched. This is because only the resist pattern 72 can be easily removed from the filled resin 20.
That is, when the dry film resist is laminated on both surfaces of the substrate 16 as it is without performing electroless copper plating on both surfaces of the substrate 16, the dry film resist and the resin 20 are resin-to-resin, so the adhesion is strong, and after etching This is because the resist pattern 72 cannot be easily removed from the resin 20. In this case, if the dry film resist (resist pattern 72) is forcibly removed from the resin 20 or chemically removed, a residue is generated on the end face of the resin 20 or the end face of the resin 20 is deteriorated. The problem arises.

On the other hand, if the dry film resist is laminated after the electroless copper plating is applied to the surface of the substrate 16 in advance, the removal of the dry film resist (resist pattern 72) after the etching can be performed by a peeling method. Even a method of chemically dissolving and removing the electroless copper plating layer 80 can be simplified. By applying electroless copper plating, the electroless copper plating layer 80 is interposed between the end face of the resin 20 and the resist pattern 72, and the electroless copper plating layer 80 acts as a release layer.
The thickness of the electroless copper plating layer used for peeling may be about 0.5 μm to 1 μm. The electroless plating layer used for peeling the dry film resist may be metal plating other than electroless copper plating, but electroless copper plating can be effectively used from the viewpoint of ease of plating and etching.

  Further, as shown in FIG. 5B, in this embodiment, when forming the resist pattern 72 on both surfaces of the substrate 16, the copper foil 14 and the plating layer 19 have a width w along the outer peripheral edge of the lower hole 18. The dry film is patterned to leave As described above, the copper foil 14 and the plating layer 19 are left along the outer peripheral edge of the lower hole 18 because the inner wall surface of the lower hole 18 is covered when the copper foil 14 and the plating layer 19 are etched. This is to prevent the plating layer 19 to be etched from being etched. This is because if only the planar region range of the lower hole 18 is covered with the resist pattern 72, when the copper foil 14 and the plating layer 19 are etched, the etching solution wraps around the inner wall surface of the lower hole 18. This is because the plating layer 19 covering the inner wall surface is etched.

    FIG. 5B shows a state in which the lower hole 18 is covered with the resist pattern 72 so as to protrude from the outer peripheral edge of the lower hole 18 by the width W. When the copper foil 14 and the plating layer 19 are chemically etched in this state, the land 142 is etched on the side surface. The amount of this side etching varies depending on the etching conditions such as the thickness of the copper foil 14 and the plating layer 19, the etching solution used, the jet pressure of the etching solution, etc., but about 70% of the thickness of the layer to be etched is the side etching amount. It becomes. Therefore, when setting the amount W for projecting the resist pattern 72 from the outer peripheral edge of the lower hole 18, the etching solution does not reach the inner wall surface of the lower hole 18 during the etching in consideration of the side surface etching amount. It is necessary to set so as to protect the plating layer 19 on the inner wall surface of the lower hole 18.

(Wiring layer formation process)
6 and 7 show a process of forming a core substrate by forming a wiring layer on both surfaces of a substrate having lands 142 formed on the outer peripheral edge of the lower hole 18 and then forming a conductive through hole by the manufacturing process described above. A process is shown.
FIG. 6A shows a state in which the prepreg 40, the wiring sheet 42, the prepreg 44, and the copper foil 46 are aligned and arranged on both surfaces of the substrate 16. The wiring sheet 42 is obtained by forming wiring patterns 42 a on both surfaces of the insulating resin sheet 41. The wiring sheet 42 is formed, for example, by etching a copper foil layer of a double-sided copper-clad substrate in which a copper foil is attached on both sides of an insulating resin sheet made of glass cloth into a predetermined pattern.

  The prepreg 40, the wiring sheet 42, the prepreg 44, and the copper foil 46 are heated and pressed on both sides of the substrate 16 to thermally cure the prepregs 40, 44, and the wiring layer 48 is formed integrally with the substrate 16 (FIG. 6 ( b)). The prepregs 40 and 44 are formed by impregnating a glass cloth with a thermosetting resin material, and are interposed between layers in an uncured state and heated and pressed to electrically insulate the respective layers from each other. 48 is integrated.

  Next, a through hole 50 for forming a conductive through hole is formed in the substrate 16 on which the wiring layer 48 is laminated. The through hole 50 is formed by drilling through the wiring layer 48 and the substrate 16 in the thickness direction so as to be concentric with the lower hole 18 (FIG. 6C). Since the through hole 50 is formed to have a smaller diameter than the lower hole 18, the resin 20 is exposed to the inner wall surface of the through hole 50 at a portion of the through hole 50 that passes through the resin 20.

  FIG. 7A shows a state in which after the through hole 50 is formed, electroless copper plating and electrolytic copper plating are applied to the substrate, and the conductive through hole 52 is formed on the inner surface of the through hole 50. By electroless copper plating, an electroless copper plating layer is formed on the entire inner surface of the through hole 50 and the surface of the substrate. By performing electrolytic copper plating using the electroless copper plating layer as a plating power supply layer, a plating layer 52a is deposited on the entire inner wall surface of the through hole 50 and the entire surface of the substrate. The plating layer 52a formed on the inner wall surface of the through hole 50 becomes a conductive through hole 52 that electrically connects the wiring patterns on the front and back surfaces of the substrate.

After the conductive through hole 52 is formed, the through hole 50 is filled with the resin 54 and subjected to lid plating, and then the copper foil 46, the plating layer 52a, and the lid plating layer 55 formed on the surface of the substrate are predetermined. The core substrate 58 is obtained by etching the pattern to form the wiring pattern 56 on the surface of the substrate (FIG. 7B).
The wiring patterns 56 formed on the front and back surfaces of the core substrate 58 are electrically connected through the conductive through holes 52. Further, the wiring pattern 42a formed in the inner layer of the wiring layer 48 is connected to the conduction through hole 52 at an appropriate position.
The core substrate 58 is electrically short-circuited between the core portion 10 and the conductive through hole 52 when the plating layer 19 is formed on the inner wall surface of the lower hole 18 formed in the substrate 16 including the core portion 10. Is prevented.

FIG. 8 shows an example in which the core substrate 58 is manufactured by using the substrate 16 shown in FIG. 4C in which the plating layer 19 and the insulating coating 21 are laminated on the inner wall surface of the lower hole 18.
Also in this case, the core substrate 58 can be formed by laminating and integrating the wiring layers 48 on both sides of the substrate 16 in the same manner as the method for forming the wiring layers 48 shown in FIGS. Wiring patterns 56 are formed on both surfaces of the core substrate 58, and the wiring patterns 56 formed on both surfaces of the core substrate 58 are electrically connected through the conductive through holes 52.

  In the core substrate 58 of the present embodiment, the inner wall surface of the lower hole 18 formed in the core portion 10 is doubly laminated by the plating layer 19 and the insulating film 21, and the inner side of the lower hole 18 is the insulating film 21. Even when the resin 20 is filled in the lower hole 18, even if a void is generated in the resin 20, and the expansion portion 52 b is generated in the conduction through hole 52 at the void portion, the insulating coating 21 is not in contact with the plating layer 19. By interposing, the conductive through hole 52 and the core portion 10 can be reliably prevented from being short-circuited.

(Wiring board)
The wiring substrate is obtained by forming a wiring layer on both surfaces of the core substrate 58 by, for example, a build-up method.
FIG. 9 shows a wiring board provided with a buildup layer 60 in which two buildup layers 60a and 60b are laminated on both surfaces of the substrate 16 shown in FIG. 7B.
The first buildup layer 60a includes an insulating layer 61a and a wiring pattern 62a, and a via 63a that electrically connects the lower wiring pattern 56 and the wiring pattern 62a. The second buildup layer 60b includes an insulating layer 61b, a wiring pattern 62b, and a via 63b.
The wiring patterns 62a and 62b of the buildup layer 60 formed on both surfaces of the core substrate 58 are electrically connected through the conductive through hole 52 and the vias 63a and 63b.

The buildup layer 60 is formed by a general buildup method. That is, an insulating resin film such as an epoxy film is laminated on both surfaces of the core substrate 58 to form the insulating layer 61a, and via holes for forming the vias 63a are formed on the surface of the core substrate 58 on the bottom surface by laser processing. The insulating layer 61a is opened so that the wiring pattern 56 is exposed.
Next, the inner surface of the via hole is roughened by desmearing treatment, and electroless copper plating is performed to form an electroless copper plating layer on the inner surface of the via hole and the surface of the insulating layer 61a.
Next, a photoresist is deposited on the surface of the electroless copper plating layer, and a resist pattern is formed by exposing and developing the exposed portions of the electroless copper plating layer.

Next, using the resist pattern as a mask, electrolytic copper plating is performed using the electroless copper plating layer as a plating power feeding layer, and the electrolytic copper plating is raised and formed at a portion where the electroless copper plating layer is exposed. In this step, the via hole is filled with electrolytic copper plating to form a via 63a.
Next, the resist pattern is removed, and the exposed region of the electroless copper plating layer is removed by etching, whereby the wiring pattern 62a is formed on the surface of the insulating layer 61a.

The second buildup layer 60b can be formed in the same manner.
In the uppermost layer of the wiring layer, an electrode for connecting a semiconductor element or a connection pad for joining an external connection terminal is formed in a pattern, and the electrode or connection pad exposed to the outside is removed and covered with a protective film. The electrode or connection pad exposed to the outside is subjected to necessary protective plating such as gold plating.
There are various methods for manufacturing a wiring board. The formation method of the wiring layer formed on both surfaces of the core substrate 58 is not limited to the method described above.

In the said embodiment, the manufacturing method of the core board | substrate provided with the core part 10 which consists of a carbon fiber reinforced plastic which has electroconductivity was demonstrated as an example of application of this invention. The present invention can be similarly applied to the manufacture of a core substrate including a core portion having conductivity other than carbon fiber reinforced plastic.
The present invention also relates to a conductor formed by laminating a dry film resist (photoresist) on a substrate surface and depositing it on the substrate surface in a general wiring board manufacturing process in which a resin is filled in a prepared hole or a through hole. Of course, it can also be applied to the case of patterning a layer. Even in that case, do not laminate the dry film resist directly on the substrate filled with resin in the lower hole or through hole, but once the electroless plating is applied to the substrate to form a release layer that peels the dry film from the resin A dry film resist may be laminated.

It is sectional drawing which shows the process of forming a pilot hole and a vent hole in a board | substrate. It is sectional drawing which shows the process of forming a vent hole in a board | substrate and filling resin in a lower hole. It is a top view of a pilot hole and a vent hole. It is sectional drawing which shows the other process of forming a vent hole in a board | substrate and filling resin in a lower hole. It is sectional drawing which shows the process of etching the conductor layer of a substrate surface. It is sectional drawing which shows the manufacturing process of a core board | substrate. It is sectional drawing which shows the manufacturing process of a core board | substrate. It is sectional drawing which shows the other structural example of a core board | substrate. It is sectional drawing of a wiring board.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Core part 11 Chip 12 Prepreg 14 Copper foil 16 Board | substrate 18 Lower hole 19 Plating layer 20 Resin 21 Insulating film 40, 44 Prepreg 41 Insulating resin sheet 42 Wiring sheet 42a Wiring pattern 46 Copper foil 48 Wiring layer 50 Through-hole 52 Conductive through Hole 52a Plating layer 54 Resin 56 Wiring pattern 58 Core substrate 60, 60a, 60b Build-up layer 62a, 62b Wiring pattern 63a, 63b Via 70, 72 Resist pattern 80 Electroless copper plating layer 140 Gas vent hole 142 Land

Claims (14)

Forming a through hole in the substrate;
Filling the through hole with an insulating material;
Applying electroless plating to the surface of the substrate filled with an insulating material in the through hole;
Laminating a photoresist on the electroless plating layer formed on the surface of the substrate, exposing and developing the photoresist, and forming a resist pattern covering the end face of the through-hole filled with the insulating material; ,
Etching the conductive layer deposited on the surface of the substrate using the resist pattern as a mask;
And a step of removing from the substrate a resist pattern covering the end face of the through-hole using the electroless plating layer as a release layer. The through hole is formed as a pilot hole that penetrates the conduction through hole,
2. The method for manufacturing a substrate according to claim 1, wherein the lower hole is filled with an insulating material, and the surface of the substrate with the lower hole filled with an insulating material is subjected to electroless plating. After electroless plating is applied to the substrate, the end face of the pilot hole filled with the insulating material is covered with a resist pattern, the conductive layer deposited on the surface of the substrate is etched, and the resist pattern is removed ,
3. The method for manufacturing a substrate according to claim 2, further comprising a step of forming a through hole penetrating the lower hole, and coating the inner wall surface of the through hole with plating to form a conductive through hole. Following the step of removing the resist pattern from the substrate,
Comprising the step of laminating and forming wiring layers on both sides of the substrate,
4. The method of manufacturing a substrate according to claim 3, further comprising a step of forming a through hole penetrating the lower hole in the substrate on which the wiring layer is integrally formed to form the conductive through hole. The substrate includes a conductive core portion,
After forming the through hole, the step of plating the substrate to cover the inner wall surface of the through hole with a plating layer,
2. The method of manufacturing a substrate according to claim 1, wherein after the through hole is filled with an insulating material, electroless plating is applied to the surface of the substrate. The through hole is formed as a lower hole penetrating a conductive through hole, and includes a step of plating the substrate and covering an inner wall surface of the lower hole with a plating layer,
6. The method of manufacturing a substrate according to claim 5, wherein after the lower hole is filled with an insulating material, electroless plating is applied to the surface of the substrate. Following the step of coating the inner wall surface of the pilot hole with a plating layer,
The electrodeposition method using the plating layer as a power supply layer comprises a step of coating the inner wall surface of the pilot hole with an insulating film,
The method for manufacturing a substrate according to claim 6, wherein the insulating material is filled in a prepared hole whose inner wall surface is covered with the insulating coating. After the step of performing electroless plating on the surface of the substrate, the step of forming the resist pattern, the step of etching the conductor layer deposited on the surface of the substrate, the step of removing the resist pattern from the substrate,
8. The method of manufacturing a substrate according to claim 6, further comprising a step of forming a through hole penetrating the lower hole, and coating the inner wall surface of the through hole with plating to form a conductive through hole. After removing the resist pattern from the substrate,
Comprising the step of laminating and forming wiring layers on both sides of the substrate;
9. The method for manufacturing a substrate according to claim 8, further comprising a step of forming a through hole penetrating the lower hole and forming the conductive through hole in the substrate on which the wiring layer is integrally formed. Following the step of forming the conductive through hole,
Filling the through hole with resin;
Etching a conductive layer deposited on the surface of the substrate into a predetermined pattern, and forming a wiring pattern electrically connected through the conductive through hole on the surface of the substrate. The method for manufacturing a substrate according to claim 9.   A method for manufacturing a substrate, comprising: forming a multilayer wiring substrate by laminating wiring layers on both sides of the substrate formed by the substrate manufacturing method according to claim 10.   The method for manufacturing a substrate according to claim 11, wherein a wiring layer is formed on both surfaces of the substrate by a build-up method.   The step of forming the core portion includes a step of superposing a plurality of prepregs containing carbon fibers, pressurizing and heating to form a flat plate body. The manufacturing method of the board | substrate of description.   The method for manufacturing a substrate according to any one of claims 1 to 13, wherein electroless copper plating is performed as electroless plating applied to the surface of the substrate in which the through hole is filled with an insulating material.