JP4863564B2 - Printed wiring board and printed wiring board manufacturing method - Google Patents

Description

【０１３８】
Steam試験は、蒸気に当て湿度１００％に保った。また、ＨＡＳＴ試験では、相対湿度１００％、印加電圧１．３Ｖ、温度１２１℃で１００時間放置した。ＴＳ試験では、−１２５℃で３０分、５５℃で３０分放置する試験を１０００回線り返した。
【０１３９】
上記信頼性試験において、チップコンデンサを内蔵するプリント配線板においても、既存のコンデンサ表面実装形と同等の信頼性が達成できていることが分かった。また、上述したように、ＴＳ試験において、セラミックから成るコンデンサと、樹脂からなるコア基板３０及び樹脂絶縁層４０の熱膨張率の違いから、内部応力が発生しても、チップコンデンサ２０の第１端子２１、第２端子２２とバイアホール６０との間に断線、チップコンデンサ２０と樹脂絶縁層４０との間で剥離、樹脂絶縁層４０にクラックが発生せず、長期に渡り高い信頼性を達成できることが判明した。
【０１４０】
【発明の効果】
本発明では上述したように、広く凹部を形成し、複数個のコンデンサを凹部に収容するため、ザグリ加工の精度が低くても確実に複数個のコンデンサを、正確に位置決めしてコア基板内に高密度で配設することが可能となる。また、凹部内に複数個のコンデンサを載置するため、複数個のコンデンサの高さが揃うので、コンデンサ上の絶縁層を均一の厚みにすることができる。よって、バイアホールおよび導体回路を適切に形成することができるので、プリント配線板の不良品発生率を低下させることができる。
【０１４１】
また、コンデンサの電極の表面に導電性ペーストを塗布してあるため、表面が完全にフラットになる。このため、樹脂層にレーザで開口を穿設した際に、電極の表面に樹脂が残ることが無くなり、該電極とめっきによるバイアホールとの接続性を高めることができる。
更に、コア基板とコンデンサの間に樹脂が充填されているので、コンデンサなどが起因する応力が発生しても緩和されるし、マイグレーションの発生がない。そのために、コンデンサの電極とバイアホールの接続部への剥離や溶解などの影響がない。そのために、信頼性試験を実施しても所望の性能を保つことができるのである。
また、コンデンサを銅によって被覆されている場合にも、マイグレーションの発生を防止することができる。
【図面の簡単な説明】
【図１】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、本発明の第１実施形態に係るプリント配線板の製造工程図である。
【図２】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、本発明の第１実施形態に係るプリント配線板の製造工程図である。
【図３】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、本発明の第１実施形態に係るプリント配線板の製造工程図である。
【図４】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、本発明の第１実施形態に係るプリント配線板の製造工程図である。
【図５】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、本発明の第１実施形態に係るプリント配線板の製造工程図である。
【図６】（Ａ）、（Ｂ）は、本発明の第１実施形態に係るプリント配線板の製造工程図である。
【図７】本発明の第１実施形態に係るプリント配線板の断面図である。
【図８】本発明の第１実施形態に係るプリント配線板にＩＣチップを搭載した状態を示す断面図である。
【図９】（Ａ）は、第１実施形態のチップコンデンサの断面図であり、（Ｂ）は、第１実施形態の第１改変例のチップコンデンサの断面図である。
【図１０】本発明の第１実施形態の改変例に係るプリント配線板の断面図である。
【図１１】ＩＣチップへの供給電力と時間との変化を示すグラフである。
【図１２】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、本発明の第２実施形態に係るプリント配線板の製造工程図である。
【図１３】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、本発明の第２実施形態に係るプリント配線板の製造工程図である。
【図１４】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、本発明の第２実施形態に係るプリント配線板の製造工程図である。
【図１５】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、本発明の第２実施形態に係るプリント配線板の製造工程図である。
【図１６】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、本発明の第２実施形態に係るプリント配線板の製造工程図である。
【図１７】（Ａ）、（Ｂ）は、本発明の第２実施形態に係るプリント配線板の製造工程図である。
【図１８】本発明の第２実施形態に係るプリント配線板にＩＣチップを搭載した状態を示す断面図である。
【図１９】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、本発明の第２実施形態の改変例に係るプリント配線板の製造工程図である。
【図２０】（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は、第３実施形態のプリント配線板のチップコンデンサの平面図である。
【図２１】第３実施形態に係るプリント配線板のチップコンデンサの平面図である。
【図２２】（Ａ）、（Ｂ）は、第３実施形態の改変例に係るプリント配線板のチップコンデンサの平面図である。
【符号の説明】
２０ チップコンデンサ
２１ 第１電極
２２ 第２電極
２３ 誘電体
２３ａ 粗化面
２３ｂ ポイリミド膜
２６ 導電性ペースト
２８ａ 無電解銅めっき膜
２８ｂ 電解銅めっき膜
２８ 複合金属膜
３０ コア基板
３１ コア基板
３２ 凹部
３６ 樹脂層
３７ 凹部
４０ 層間樹脂絶縁層
４６ バイアホール
５０ 層間樹脂絶縁層
６０ バイアホール
７０ ソルダーレジスト層
７１Ｕ、７１Ｄ 開口部
７２ ニッケルめっき層
７４ 金めっき層
７６ 半田バンプ
９０ ＩＣチップ
９２ 半田パッド（ＩＣチップ側）
９４ ドータボード
９５ 半田パッド（ドータボード側）
９６ 導電性接続ピン
９７ 導電性接着剤
９８ 固定部
１５０ 層間樹脂絶縁層
１５８ 導体回路
１６０ バイアホール
２５８ 導体回路
２６０ バイアホール[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a printed circuit board on which an electronic component such as an IC chip is placed, and more particularly to a printed wiring board having a capacitor built therein.
[0002]
[Prior art]
Currently, in a printed wiring board for a package substrate, a chip capacitor is sometimes surface-mounted in order to facilitate power supply to an IC chip.
[0003]
Since the reactance component between the chip capacitor and the IC chip depends on the frequency, even if the chip capacitor is surface-mounted, the operation cannot be performed sufficiently as the driving frequency of the IC chip increases. In order to solve the above-mentioned problems, the present applicant has proposed a technique for incorporating a capacitor in a printed wiring board in Japanese Patent Application No. 11-248311. Moreover, as a technique for embedding a capacitor in a substrate, JP-A-6-326472, JP-A-7-263619, JP-A-10-256429, JP-A-11-45955, JP-A-11-126978, JP-A-11- No. 31868 etc.
[0004]
Japanese Patent Application Laid-Open No. 6-326472 discloses a technique of embedding a capacitor in a resin substrate made of glass epoxy. With this configuration, it is possible to reduce power supply noise, eliminate the need for a space for mounting a chip capacitor, and reduce the size of the insulating substrate. Japanese Patent Application Laid-Open No. 7-263619 discloses a technique for embedding a capacitor in a substrate such as ceramic or alumina. With this configuration, by connecting between the power supply layer and the ground layer, the wiring length is shortened and the wiring inductance is reduced.
[0005]
[Problems to be solved by the invention]
However, the above-mentioned Japanese Patent Laid-Open Nos. 6-326472 and 7-263619 cannot reduce the distance from the IC chip to the capacitor so much, and in the higher frequency region of the IC chip, the inductance is required as it is currently required. Could not be reduced. In particular, in the resin-made multilayer build-up wiring board, due to the difference in thermal expansion coefficient between the ceramic capacitor and the resin core substrate and the interlayer resin insulation layer, the disconnection between the terminal of the chip capacitor and the via hole, Peeling occurred between the chip capacitor and the interlayer resin insulation layer, and cracks occurred in the interlayer resin insulation layer, and high reliability could not be achieved over a long period of time.
[0006]
Further, in the invention of Japanese Patent Application No. 11-248311, since a concave portion is formed for each capacitor, the concave portion cannot be formed accurately when the accuracy of counterbore processing is low, and the capacitor is located at an accurate position. Sometimes it did not enter the recess. In addition, the depth of the recess becomes smaller than the height of the capacitor, and the capacitor sometimes protrudes from the recess. Therefore, the core substrate cannot be smoothed, and even if an interlayer resin insulation layer and wiring are formed on the core substrate to produce a printed wiring board, disconnection is likely to occur and the defective product occurrence rate is increased. found. Furthermore, it has been difficult to increase the mounting density of the capacitor.
[0007]
The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a printed wiring board having a built-in capacitor at a high density and a low defect generation rate, and a method for manufacturing the printed wiring board. There is to do.
[0008]
[Means for Solving the Problems]
  In order to achieve the above-described problem, the invention of claim 1 is a printed wiring board in which a resin insulating layer and a conductor circuit are laminated on a core substrate,
  A recess is formed in the core substrate, and a plurality of capacitors are accommodated in the recess.
  The surface of the electrode made of metallization of the capacitor is electrically conductiveresinPaste is applied,
The conductivityresinA copper plating film is provided on the paste,
  Connected to the capacitor electrode by a via hole made of plating,
Between the plurality of capacitors in the recess, the core substrate containing an inorganic filler and a resin having a lower coefficient of thermal expansion than the resin insulating layer were filled.This is a technical feature.
[0009]
According to the first aspect of the present invention, the core substrate is formed with a wide recess, and a plurality of capacitors are accommodated in the recess. Therefore, a plurality of capacitors can be reliably arranged in the core substrate. Since the capacitors can be arranged densely in the recess, the mounting density of the capacitors can be increased. In addition, since the plurality of capacitors are placed in the recess, the height of the plurality of capacitors is uniform, so that the resin layer formed on the core substrate can have a uniform thickness, and the formation of the via hole is stabilized. Further, since the concave portion is formed widely, the capacitor can be accurately positioned. Therefore, since the interlayer resin insulation layer and the conductor circuit can be appropriately formed on the core substrate, the defective product occurrence rate of the printed wiring board can be reduced.
[0010]
It is desirable to fill the recess with resin. By eliminating the gap between the capacitor and the core substrate, the built-in capacitor is less likely to behave, and even if stress originating from the capacitor is generated, it can be relaxed by the filled resin. The resin also has an effect of reducing adhesion and migration between the capacitor and the core substrate.
[0011]
Further, since the conductive paste is applied to the surface of the electrode made of metallization of the capacitor, the surface becomes completely flat. For this reason, when an opening is formed in the resin layer with a laser, the resin does not remain on the surface of the electrode, and the connection reliability between the electrode and a via hole formed by plating can be improved.
[0012]
  Claim1On the capacitor electrode conductive pasteCopper plating filmTherefore, the occurrence of migration at the electrode can be prevented, and the connection resistance can be further reduced.
[0013]
  Claim2Then, a roughening process is performed on the surface of the capacitor. As a result, the adhesion between the ceramic chip capacitor and the resin connection layer and the interlayer resin insulation layer is improved, and the connection layer and the interlayer resin insulation layer are peeled off at the interface even when the heat cycle test is performed. There is nothing.
[0014]
  Claim3Then, a wettability improving process such as silane coupling or application of a resin film is performed on the surface of the capacitor. As a result, the adhesion between the ceramic chip capacitor and the connection layer and the interlayer resin insulation layer is improved, and even if the heat cycle test is performed, the connection layer and the interlayer resin insulation layer are not peeled off at the interface. .
[0015]
  Claim1In this invention, since the resin is filled between the capacitors in the recess, the capacitor can be positioned and fixed in the recess. The thermal expansion coefficient of the resin is set to be smaller than that of the core substrate, that is, close to a capacitor made of ceramic. For this reason, in the heat cycle test, even if an internal stress occurs due to a difference in thermal expansion coefficient between the core substrate and the capacitor, cracks, peeling, and the like hardly occur in the core substrate, and high reliability can be achieved. Further, since migration does not occur, the connection with the capacitor is stabilized.
[0016]
  Claim4In this invention, since the through hole is formed in the resin layer between the capacitors, the signal line does not pass through the capacitor, so that reflection due to impedance discontinuity due to the high dielectric and propagation delay due to passage through the high dielectric do not occur.
[0017]
In addition, electrical connection between the front and back sides can be established through the through-holes, and wiring can be provided below the capacitor via the build-up layer, and capacitor pins and BGA can be provided.
[0018]
  Claim5Then, in addition to the capacitor accommodated in the substrate, a capacitor is provided on the surface. Since the capacitor is accommodated in the printed wiring board, the distance between the IC chip and the capacitor is shortened, the loop inductance can be reduced, and the power can be supplied instantaneously. Since the capacitor is disposed, a large-capacity capacitor can be attached, and a large amount of power can be easily supplied to the IC chip.
[0019]
  Claim6Then, since the capacitance of the capacitor on the surface is equal to or greater than the capacitance of the capacitor on the inner layer, there is no shortage of power supply in the high frequency region, and the desired operation of the IC chip is ensured.
[0020]
  Claim7Then, since the inductance of the capacitor on the surface is equal to or higher than the inductance of the capacitor on the inner layer, there is no shortage of power supply in the high frequency region, and the desired operation of the IC chip is ensured.
[0021]
  Claim8Then, since a chip capacitor having an electrode formed inside the outer edge is used, even if conduction is made through a via hole, the external electrode can be made large, and the allowable range of alignment is widened.
[0022]
  Claim9Then, since a capacitor having electrodes formed in a matrix is used, a large chip capacitor can be easily accommodated in the core substrate. As a result, the capacitance can be increased, and the electrical problem can be solved. Further, even after various thermal histories, the printed wiring board is hardly warped.
[0023]
  Claim10Then, a plurality of chip capacitors may be connected to the capacitor. Thereby, the capacitance can be adjusted as appropriate, and the IC chip can be operated appropriately.
[0024]
  Claim11According to the present invention, there is a printed wiring board manufacturing method characterized in that it includes at least the following steps (a) to (d):
(A) forming a recess in the core substrate;
(B) Conductivity on the plurality of metallized electrodes in the recess.resinApply paste to make it conductiveresinPlacing a capacitor with a copper plating film on the paste;
(C) saidMultipleBetween capacitors,Lower thermal expansion coefficient than the core substrate and insulating layerFilling the resin;
(D) A step of forming a resin layer on the capacitor and forming via holes reaching the electrodes of the capacitor by plating.
[0025]
  Claim11Then, since the concave portion is widely formed in the core substrate, a plurality of capacitors can be reliably disposed in the core substrate. Furthermore, since the plurality of capacitors are placed in the recess, the height of the plurality of capacitors is uniform, so that the core substrate can be smoothed. Further, since the concave portion is formed widely, the capacitor can be accurately positioned. Therefore, the smoothness of the core substrate is not impaired, and the interlayer resin insulation layer and the conductor circuit can be appropriately formed on the core substrate, so that the defective product occurrence rate of the printed wiring board can be reduced. Further, since the resin is filled between the capacitors, the capacitor can be positioned and fixed in the recess.
[0026]
Further, since the conductive paste is applied to the surface of the capacitor electrode, the surface becomes completely flat. For this reason, when an opening is formed in the resin layer with a laser, the resin does not remain on the surface of the electrode, and the connection reliability between the electrode and a via hole formed by plating can be improved.
[0027]
  Claim12In this invention, the heights of the upper surfaces of the capacitors are made uniform by applying pressure or hitting the upper surfaces of the capacitors in the recesses. Thereby, when the capacitors are disposed in the recesses, the heights can be made uniform even if the sizes of the plurality of capacitors vary, and the core substrate can be made smooth. Therefore, the smoothness of the core substrate is not impaired, and the upper interlayer resin insulation layer and the conductor circuit can be appropriately formed, so that the defective product occurrence rate of the printed wiring board can be reduced.
[0028]
  Claim13In this invention, since the through hole is formed in the resin layer between the capacitors, the signal line does not pass through the capacitor, so that reflection due to impedance discontinuity due to the high dielectric and propagation delay due to passage through the high dielectric do not occur. In addition, electrical connection between the front and back sides can be established through the through-holes, and wiring can be provided below the capacitor via the build-up layer, and capacitor pins and BGA can be provided.
[0029]
  Claim14According to the present invention, at least the following steps (a) to (e) are provided.
(A) forming a through hole in a resin material containing a resin as a core material;
(B) a step of attaching a resin material to the resin material in which the through holes are formed to form a core substrate having a recess;
(C) Conductivity on the plurality of metallized electrodes in the recess of the core substrateresinApply paste to make it conductiveresinPlacing a capacitor with a copper plating film on the paste;
(D) saidMultipleBetween capacitors,Lower thermal expansion coefficient than the core substrate and insulating layerFilling the resin;
(E) A step of forming a resin layer on the capacitor and forming a via hole reaching the electrode of the capacitor by plating.
[0030]
  Claim14Then, since a recessed part is widely formed in a core board | substrate, it becomes possible to arrange | position a some capacitor | condenser in a core board | substrate reliably. Furthermore, since the plurality of capacitors are placed in the recess, the height of the plurality of capacitors is uniform, so that the core substrate can be smoothed. Further, since the concave portion is formed widely, the capacitor can be accurately positioned. Therefore, since the interlayer resin insulation layer and the conductor circuit can be appropriately formed on the core substrate, the defective product occurrence rate of the printed wiring board can be reduced. Further, since the resin is filled between the capacitors, the capacitor can be positioned and fixed in the recess.
[0031]
Further, since the conductive paste is applied to the surface of the capacitor electrode, the surface becomes completely flat. For this reason, when an opening is formed in the resin layer with a laser, the resin does not remain on the surface of the electrode, and the connection reliability between the electrode and a via hole formed by plating can be improved.
[0032]
  Claim15In this invention, the heights of the top surfaces of the capacitors are made uniform by pushing or hitting the top surfaces of the plurality of capacitors in the recess from above. Thereby, when the capacitors are arranged in the recesses, the heights can be made uniform even if the sizes of the plurality of capacitors vary. Therefore, the smoothness is not impaired, and the interlayer resin insulation layer and the conductor circuit can be appropriately formed on the core substrate, so that the defective product occurrence rate of the printed wiring board can be reduced.
[0033]
  Claim16In this invention, since the through hole is formed in the resin layer between the capacitors, the signal line does not pass through the capacitor, so that reflection due to impedance discontinuity due to the high dielectric and propagation delay due to passage through the high dielectric do not occur. In addition, electrical connection between the front and back sides can be established through the through-hole, and wiring can be disposed under the capacitor via the build-up layer, so that the capacitor pins and BGA can be cast.
[0034]
In the present invention, the resin film used as the interlayer resin insulation layer and connection layer is a resin in which particles soluble in an acid or oxidant (hereinafter referred to as soluble particles) are hardly soluble in an acid or oxidant (hereinafter referred to as hardly soluble resin). ).
As used herein, the terms “poorly soluble” and “soluble” refer to those having a relatively fast dissolution rate as “soluble” for convenience when immersed in a solution of the same acid or oxidizing agent for the same time. A relatively slow dissolution rate is referred to as “slightly soluble” for convenience.
[0035]
Examples of the soluble particles include resin particles soluble in an acid or an oxidizing agent (hereinafter, soluble resin particles), inorganic particles soluble in an acid or an oxidizing agent (hereinafter, soluble inorganic particles), and a metal soluble in an acid or an oxidizing agent. Examples thereof include particles (hereinafter, soluble metal particles). These soluble particles may be used alone or in combination of two or more.
[0036]
The shape of the soluble particles is not particularly limited, and examples thereof include spherical shapes and crushed shapes. Moreover, it is desirable that the soluble particles have a uniform shape. This is because a roughened surface having unevenness with uniform roughness can be formed.
[0037]
The average particle size of the soluble particles is preferably 0.1 to 10 μm. If it is the range of this particle size, you may contain the thing of a 2 or more types of different particle size. That is, it contains soluble particles having an average particle diameter of 0.1 to 0.5 μm and soluble particles having an average particle diameter of 1 to 3 μm. Thereby, a more complicated roughened surface can be formed and it is excellent also in adhesiveness with a conductor circuit. In the present invention, the particle size of the soluble particles is the length of the longest part of the soluble particles.
[0038]
Examples of the soluble resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like, as long as the dissolution rate is higher than that of the hardly soluble resin when immersed in a solution made of an acid or an oxidizing agent. There is no particular limitation.
Specific examples of the soluble resin particles include, for example, an epoxy resin, a phenol resin, a polyimide resin, a polyphenylene resin, a polyolefin resin, a fluorine resin, and the like, and may be composed of one of these resins. And it may consist of a mixture of two or more resins.
[0039]
Moreover, as the soluble resin particles, resin particles made of rubber can be used. Examples of the rubber include polybutadiene rubber, epoxy-modified, urethane-modified, (meth) acrylonitrile-modified various modified polybutadiene rubber, carboxyl group-containing (meth) acrylonitrile-butadiene rubber, and the like. By using these rubbers, the soluble resin particles are easily dissolved in an acid or an oxidizing agent. That is, when soluble resin particles are dissolved using an acid, acids other than strong acids can be dissolved. When soluble resin particles are dissolved using an oxidizing agent, permanganese having a relatively low oxidizing power is used. Even acid salts can be dissolved. Even when chromic acid is used, it can be dissolved at a low concentration. Therefore, no acid or oxidant remains on the resin surface, and as described later, when a catalyst such as palladium chloride is applied after the roughened surface is formed, the catalyst is not applied or the catalyst is oxidized. There is nothing to do.
[0040]
Examples of the soluble inorganic particles include particles composed of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds, and silicon compounds.
[0041]
Examples of the aluminum compound include alumina and aluminum hydroxide. Examples of the calcium compound include calcium carbonate and calcium hydroxide. Examples of the potassium compound include potassium carbonate. Examples of the magnesium compound include magnesia, dolomite, basic magnesium carbonate and the like, and examples of the silicon compound include silica and zeolite. These may be used alone or in combination of two or more.
[0042]
Examples of the soluble metal particles include particles composed of at least one selected from the group consisting of copper, nickel, iron, zinc, lead, gold, silver, aluminum, magnesium, calcium, and silicon. Further, the surface layer of these soluble metal particles may be coated with a resin or the like in order to ensure insulation.
[0043]
When two or more kinds of the soluble particles are used in combination, the combination of the two kinds of soluble particles to be mixed is preferably a combination of resin particles and inorganic particles. Both of them have low electrical conductivity, so that the insulation of the resin film can be ensured, and the thermal expansion can be easily adjusted between the poorly soluble resin, and no crack occurs in the interlayer resin insulation layer made of the resin film. This is because no peeling occurs between the interlayer resin insulation layer and the conductor circuit.
[0044]
The poorly soluble resin is not particularly limited as long as it can maintain the shape of the roughened surface when the roughened surface is formed using an acid or an oxidizing agent in the interlayer resin insulation layer. For example, thermosetting Examples thereof include resins, thermoplastic resins, and composites thereof. Moreover, the photosensitive resin which provided photosensitivity to these resin may be sufficient. By using a photosensitive resin, a via hole opening can be formed in the interlayer resin insulating layer by exposure and development.
Among these, those containing a thermosetting resin are desirable. This is because the shape of the roughened surface can be maintained by the plating solution or various heat treatments.
[0045]
Specific examples of the hardly soluble resin include, for example, an epoxy resin, a phenol resin, a polyimide resin, a polyphenylene resin, a polyolefin resin, and a fluorine resin. These resins may be used alone or in combination of two or more. Furthermore, an epoxy resin having two or more epoxy groups in one molecule is more desirable. Not only can the aforementioned roughened surface be formed, but also has excellent heat resistance, etc., so that stress concentration does not occur in the metal layer even under heat cycle conditions, and peeling of the metal layer is unlikely to occur. Because.
[0046]
Examples of the epoxy resin include cresol novolac type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolac type epoxy resin, alkylphenol novolac type epoxy resin, biphenol F type epoxy resin, naphthalene type epoxy resin, Examples thereof include cyclopentadiene type epoxy resins, epoxidized products of condensates of phenols and aromatic aldehydes having a phenolic hydroxyl group, triglycidyl isocyanurate, and alicyclic epoxy resins. These may be used alone or in combination of two or more. Thereby, it will be excellent in heat resistance.
[0047]
In the resin film used in the present invention, it is desirable that the soluble particles are dispersed almost uniformly in the hardly soluble resin. A roughened surface with unevenness of uniform roughness can be formed, and even if a via hole or a through hole is formed in a resin film, the adhesion of the metal layer of the conductor circuit formed thereon can be secured. Because it can. Moreover, you may use the resin film containing a soluble particle only in the surface layer part which forms a roughening surface. As a result, since the portion other than the surface layer portion of the resin film is not exposed to the acid or the oxidizing agent, the insulation between the conductor circuits via the interlayer resin insulation layer is reliably maintained.
[0048]
In the resin film, the blending amount of the soluble particles dispersed in the hardly soluble resin is preferably 3 to 40% by weight with respect to the resin film. When the blending amount of the soluble particles is less than 3% by weight, a roughened surface having desired irregularities may not be formed. When the blending amount exceeds 40% by weight, the soluble particles are dissolved using an acid or an oxidizing agent. In addition, the resin film is melted to the deep part of the resin film, and the insulation between the conductor circuits through the interlayer resin insulating layer made of the resin film cannot be maintained, which may cause a short circuit.
[0049]
The resin film preferably contains a curing agent, other components and the like in addition to the soluble particles and the hardly soluble resin.
Examples of the curing agent include imidazole curing agents, amine curing agents, guanidine curing agents, epoxy adducts of these curing agents, microcapsules of these curing agents, triphenylphosphine, and tetraphenylphosphorus. And organic phosphine compounds such as nium tetraphenylborate.
[0050]
The content of the curing agent is desirably 0.05 to 10% by weight with respect to the resin film. If it is less than 0.05% by weight, since the resin film is not sufficiently cured, the degree of penetration of the acid and the oxidant into the resin film increases, and the insulating properties of the resin film may be impaired. On the other hand, if it exceeds 10% by weight, an excessive curing agent component may denature the composition of the resin, which may lead to a decrease in reliability.
[0051]
  Examples of the other components include fillers such as inorganic compounds or resins that do not affect the formation of the roughened surface. Examples of the inorganic compound include silica, alumina, and dolomite. Examples of the resin include polyimide resin, polyacrylic resin, polyamideimide resin, polyphenylene resin, and melaMiResin, olefin resin and the like. By containing these fillers, it is possible to improve the performance of the printed wiring board by matching the thermal expansion coefficient, improving heat resistance, and chemical resistance.
[0052]
Moreover, the said resin film may contain the solvent. Examples of the solvent include ketones such as acetone, methyl ethyl ketone, and cyclohexanone, and aromatic hydrocarbons such as ethyl acetate, butyl acetate, cellosolve acetate, toluene, and xylene. These may be used alone or in combination of two or more.
[0053]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
First, the configuration of the printed wiring board according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 7 shows a cross section of the printed wiring board 10, and FIG. 8 shows a state in which the IC chip 90 is mounted on the printed wiring board 10 shown in FIG.
[0054]
As shown in FIG. 7, the printed wiring board 10 includes a core substrate 30 that houses a plurality of chip capacitors 20 and build-up wiring layers 80A and 80B. Build-up wiring layer 80A and build-up wiring layer 80B are made of interlayer resin insulation layers 50 and 150. A via hole 160 and a conductor circuit 158 are formed in the interlayer resin insulation layer 50, and a via hole 260 and a conductor circuit 258 are formed in the interlayer resin insulation layer 150. A solder resist layer 70 is disposed on the interlayer resin insulating layer 150.
[0055]
As shown in FIG. 9A, the chip capacitor 20 includes a first electrode 21, a second electrode 22, and a dielectric 23 sandwiched between the first and second electrodes. A plurality of first conductive films 24 connected to the electrode 21 side and second conductive films 25 connected to the second electrode 22 side are arranged to face each other. The surface of the first electrode 21 and the second electrode 22 is covered with a conductive paste 26.
[0056]
Here, the 1st electrode 21 and the 2nd electrode 22 consist of metallization of Ni, Pb, or Ag metal. The conductive paste 26 is made of a paste containing metal particles such as Cu, Ni, or Ag. Here, the particle diameter of the metal particles is desirably 0.1 to 10 μm, and particularly 1 to 5 μm is optimal. As the conductive paste, an organic conductive paste in which a thermosetting resin such as an epoxy resin or a polyphenylene sulfide (PPS) resin is added to metal particles is desirable. The thickness of the conductive paste 26 is desirably 1 to 30 μm. If the thickness is less than 1 μm, unevenness on the electrode surface cannot be eliminated. On the other hand, if the thickness exceeds 30 μm, the effect is not particularly improved. Here, a thickness of 5 to 20 μm is most desirable. In addition, it is possible to use a paste in which particles having two or more types of different diameters are blended, and it is also possible to coat a metal paste having two or more types of different diameters.
[0057]
The electrodes 21 and 22 of the chip capacitor are made of metallization and have irregularities on the surface. For this reason, if the metal layer is used in a state where it is exposed, the resin may remain on the unevenness in the step of forming the via hole opening 48 in the resin insulating layer 40 with a laser. At this time, a poor connection between the first and second electrodes 21 and 22 and the via hole 60 occurs due to the resin residue. In the present embodiment, the surfaces of the first and second electrodes 21 and 22 are smoothed by the conductive paste 26, and no resin residue remains when the via hole opening 48 covered on the electrode is formed. The connection reliability with the electrodes 21 and 22 when the via hole 60 is formed can be improved.
[0058]
Further, a roughened layer 23 a is provided on the surface of the dielectric 23 made of ceramic of the chip capacitor 20. Therefore, the adhesiveness between the ceramic chip capacitor 20 and the resin adhesive material 34 and the resin insulating layer 40 is high, and the resin adhesive material 34 and the resin insulating layer 40 at the interface even when the heat cycle test is performed. No peeling occurs. The roughened layer 23a can be formed by polishing the surface of the chip capacitor 20 after firing, or by performing a roughening treatment before firing.
[0059]
As shown in FIG. 8, solder bumps 76U for connection to the pads 92 of the IC chip 90 are formed in the via holes 260 of the upper buildup wiring layer 80A. On the other hand, solder bumps 76D for connection to the pads 95 of the daughter board 94 are formed in the via holes 260 of the lower buildup wiring layer 80B. Further, a through hole 46 is formed in the core substrate 30.
[0060]
In the printed wiring board 10 of the present embodiment, since the concave portions 32 are formed widely, it is possible to reliably dispose a plurality of chip capacitors 20 on the substrate even if the accuracy of counterboring is low. Since the chip capacitor 20 can be arranged densely in the recess 32, the mounting density of the capacitor can be increased. In addition, since the heights of the plurality of chip capacitors 20 in the recess 32 are uniform, the resin layer formed on the core substrate can have a uniform thickness as will be described later, and the formation of the via hole is stabilized. Therefore, since the interlayer resin insulation layers 50 and 150 and the conductor circuits 158 and 258 can be appropriately formed on the core substrate 30, the defective product occurrence rate of the printed wiring board 10 can be reduced.
[0061]
  As the core substrate, one made of resin was used. For example, a resin material used in a general printed wiring board such as a glass epoxy resin-impregnated base material or a phenol resin-impregnated base material can be used. But the core substrateInCeramimiTheA substrate such as could not be used. This is because the substrate has poor external formability and cannot accommodate a capacitor, and even if it is filled with resin, voids are generated.
[0062]
Further, since the resin filler 36 is filled between the chip capacitors 20, the chip capacitor 20 disposed at an accurate position in the recess 32 can be positioned and fixed. Further, migration at the connection portion between the capacitor and the via hole can be prevented.
Here, the thermal expansion coefficient of the resin filler 36 and the adhesive material 34 under the chip capacitor 20 is set to be smaller than that of the core substrate 30 and the resin insulating layer 40, that is, close to the chip capacitor 20 made of ceramic. . For this reason, in the heat cycle test, even if an internal stress occurs due to a difference in thermal expansion coefficient between the core substrate 30 and the resin insulating layer 40 and the chip capacitor 20, the core substrate 30 and the resin insulating layer 40 are cracked, peeled off, etc. It is difficult to occur and high reliability can be achieved.
[0063]
Further, since the through hole 46 is formed in the resin layer 36 between the chip capacitors 20, the signal line does not pass through the ceramic chip capacitor 20, so that reflection due to impedance discontinuity due to the high dielectric and passage through the high dielectric Propagation delay does not occur. Since wiring can also be provided under the capacitor, the degree of freedom of external terminals such as wiring and pins is increased, and the density and size are reduced.
[0064]
Next, a method for manufacturing the printed wiring board described above with reference to FIG. 7 will be described with reference to FIGS.
[0065]
(1) First, a core substrate 30 made of an insulating resin substrate is used as a starting material (see FIG. 1A). Next, a concave portion 32 for capacitor placement is formed on one side of the core substrate 30 by counterboring (see FIG. 1B). At this time, the concave portion 32 is formed wider and larger than an area where a plurality of capacitors can be disposed. Thereby, a plurality of capacitors can be reliably disposed on the core substrate 30.
[0066]
(2) Thereafter, the adhesive material 34 is applied to the recess 32 using a printing machine (see FIG. 1C). At this time, potting or the like may be performed in addition to the application. As the adhesive material 34, a material having a thermal expansion coefficient smaller than that of the core substrate 30 and the resin insulating layer 40 is used. Next, the chip capacitor 20 (see FIG. 9) made of a plurality of ceramics is placed on the adhesive material 34 in the recess 32 (see FIG. 1D). Here, as described later, by disposing the plurality of chip capacitors 20 in the recesses 32 having a smooth bottom, the heights of the plurality of chip capacitors 20 are aligned, so that the core substrate 30 can be smoothed. . Moreover, since the recessed part 32 is formed widely, the positioning of the chip capacitor 20 can be performed accurately and can be arranged with high density.
[0067]
(3) Then, the top surfaces of the chip capacitors 20 are pushed or hit so that the top surfaces of the plurality of chip capacitors 20 have the same height (see FIG. 2A). With this process, when the plurality of chip capacitors 20 are disposed in the recesses 32, the heights can be completely aligned even if the sizes of the plurality of chip capacitors 20 vary. Can be smoothed.
[0068]
(4) After that, a thermosetting resin is filled between the chip capacitors 20 in the recess 32, and the resin layer 36 is formed by heat curing (see FIG. 2B). At this time, epoxy, phenol, polyimide, and triazine are preferable as the thermosetting resin. Thereby, the chip capacitor 20 in the recess 32 can be fixed. As the resin layer 36, one having a thermal expansion coefficient smaller than that of the core substrate 30 and the resin insulating layer 40 is used.
[0069]
In addition, a resin such as a thermoplastic resin may be used. Further, a filler may be impregnated in order to match the thermal expansion coefficient in the resin. Examples of the filler include an inorganic filler, a ceramic filler, and a metal filler.
[0070]
(5) Further, a resin made of an epoxy resin, which will be described later, is applied from above using a printing machine to form the resin insulating layer 40 (see FIG. 2C). In addition, you may affix a resin film instead of apply | coating resin.
[0071]
In addition, one or more resins such as a thermosetting resin, a thermoplastic resin, a photosensitive resin thermosetting resin / thermoplastic resin composite, and a photosensitive resin / thermoplastic resin composite can be used. . You may make them into 2 layer structure.
[0072]
(6) Next, a via hole opening 48 is formed in the resin insulating layer 40 by a laser (see FIG. 2D). At this time, since the surfaces of the electrodes 21 and 22 of the chip capacitor 20 are smooth by the conductive paste 26, the resin does not remain on the electrodes. Thereafter, desmear processing is performed. An exposure / development process can be used instead of the laser. Then, through holes 46a for through holes are formed in the resin layer 36 by a drill or a laser, and are cured by heating (see FIG. 3A). You may perform the desmear process by chemical | medical solutions, such as permanganic acid, and a plasma process.
[0073]
(7) Thereafter, a copper plating film 52 is formed on the surface of the resin insulating layer 40 by electroless copper plating (see FIG. 3B). Instead of electroless plating, sputtering using a Ni—Cu alloy as a target can be performed to provide a Ni—Cu alloy layer. In some cases, an electroless plating film may be formed after sputtering. At this time, since no resin remains on the surfaces of the electrodes 21 and 22 of the chip capacitor 20, the copper plating film 52 can be appropriately formed on the electrodes 21 and 22.
[0074]
(8) Next, a photosensitive dry film is affixed to the surface of the copper plating film 52, a mask is placed thereon, exposure and development are performed, and a plating resist 54 having a predetermined pattern is formed. Then, the core substrate 30 is immersed in the electrolytic plating solution, and an electric current is passed through the copper plating film 52 to deposit the electrolytic plating film 56 (see FIG. 3C).
[0075]
(9) Next, after the plating resist 54 is peeled and removed with 5% NaOH, the copper plating film 52 under the plating resist 54 is etched and removed with a mixed solution of sulfuric acid and hydrogen peroxide, and the copper plating film 52 is removed. Then, a conductor circuit 58 (including the via hole 60) and the through hole 46 made of the electrolytic copper plating film 56 are formed. Here, since the signal line does not pass through the chip capacitor 20 by forming the through hole 46, reflection due to impedance discontinuity due to the high dielectric and propagation delay due to passage through the high dielectric do not occur.
Next, an etching solution is sprayed on both sides of the substrate by spraying to etch the surface of the conductor circuit 58 and the land surface of the through hole 46, thereby forming a roughened surface 58α on the entire surface of the conductor circuit 58 (FIG. 3 (D)).
[0076]
(10) Thereafter, the resin filler 62 mainly composed of an epoxy resin is filled in the through hole 46 and dried (see FIG. 4A). A thermosetting resin, a thermoplastic resin, an ultraviolet curable resin, or the like can be used. Among these, it is desirable to use a thermosetting resin. This is because it is easy to handle when filling the through hole.
[0077]
(11) A pressure of 5 kg / cm while heating a thermosetting resin film having a thickness of 50 μm to a temperature of 50 to 150 ° C. on both surfaces of the substrate that has undergone the above process.²Then, an interlayer resin insulation layer 50 is provided by vacuum compression lamination (see FIG. 4B). The degree of vacuum at the time of vacuum bonding is 10 mmHg. An epoxy resin or an olefin resin can also be used for the interlayer resin insulation layer 50.
[0078]
(12) Next, CO with a wavelength of 10.4 μm₂A via hole opening 148 having a diameter of 80 μm is provided in the interlayer resin insulating layer 50 with a gas laser under conditions of a beam diameter of 5 mm, a top hat mode, a pulse width of 5.0 μsec, a mask hole diameter of 0.5 mm, and three shots ( (See FIG. 4C). Thereafter, desmear treatment is performed using oxygen plasma.
[0079]
(13) Next, plasma processing is performed using SV-4540 manufactured by Nippon Vacuum Technology Co., Ltd. to roughen the surface of the interlayer resin insulation layer 50 to form a roughened surface 50α (see FIG. 4D). . At this time, argon gas is used as the inert gas, and plasma treatment is performed for 2 minutes under the conditions of power 200 W, gas pressure 0.6 Pa, and temperature 70 ° C. You may roughen by an acid or an oxidizing agent. The roughened layer is preferably 0.1 to 5 μm.
[0080]
(14) Next, using the same apparatus, after replacing the argon gas inside, sputtering using Ni—Cu alloy as a target is performed under conditions of atmospheric pressure 0.6 Pa, temperature 80 ° C., power 200 W, and time 5 minutes. The Ni—Cu alloy 152 is formed on the surface of the interlayer resin insulation layer 50. At this time, the formed Ni—Cu alloy layer 152 has a thickness of 0.2 μm (see FIG. 5A).
[0081]
(15) A commercially available photosensitive dry film is pasted on both surfaces of the substrate 30 after the above-described treatment, and a photomask film is placed thereon, and 100 mJ / cm.²After the exposure, a development process is performed with 0.8% sodium carbonate to provide a plating resist 154 having a thickness of 15 μm. Next, electrolytic plating is performed under the following conditions to form an electrolytic plating film 156 having a thickness of 15 μm (see FIG. 5B). In addition, with this electrolytic plating film 156, the thickness of the portion to be the conductor circuit 158 and the plating filling of the portion to be the via hole 160 are performed in the steps described later. The additive in the electrolytic plating aqueous solution is Kaparaside HL manufactured by Atotech Japan.
[0082]
(Electrolytic plating aqueous solution)
Sulfuric acid 2.24 mol / l
Copper sulfate 0.26 mol / l
Additive (manufactured by Atotech Japan, Kaparaside HL) 19.5 ml / l
[Electrolytic plating conditions]
Current density 1A / dm²
65 minutes
Temperature 22 ± 2 ° C
[0083]
(16) After stripping and removing the plating resist 154 with 5% NaOH, the Ni—Cu alloy layer 152 under the plating resist is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid, and hydrogen peroxide. A conductor circuit 158 having a thickness of 16 μm and a via hole 160 formed of the alloy layer 152 and the electrolytic plating film 156 are formed (see FIG. 5C).
[0084]
(17) Next, by repeating the steps (11) to (16), an upper interlayer resin insulation layer 150 and a conductor circuit 258 (including via holes 260) are further formed (see FIG. 5D). ).
[0085]
(18) Next, the photosensitizing property obtained by acrylated 50% of an epoxy group of a cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) to a concentration of 60% by weight. 46.67 parts by weight of oligomer (molecular weight 4000), 80 parts by weight of bisphenol A type epoxy resin dissolved in methyl ethyl ketone (manufactured by Yuka Shell, trade name: Epicoat 1001), 15 parts by weight of imidazole curing agent (manufactured by Shikoku Chemicals) , Trade name: 2E4MZ-CN) 1.6 parts by weight, polyfunctional acrylic monomer (manufactured by Kyoei Chemical Co., Ltd., trade name: R604) which is a photosensitive monomer, polyvalent acrylic monomer (manufactured by Kyoei Chemical Co., Ltd., product) Name: DPE6A) 1.5 parts by weight, dispersion antifoaming agent (manufactured by San Nopco, trade name: S-65) 0.7 A weight part is put into a container, and a mixed composition is prepared by stirring and mixing. 2.0 parts by weight of benzophenone (manufactured by Kanto Chemical Co., Inc.) as a photoweight initiator and Michler's ketone as a photosensitizer for the mixed composition. (Kanto Chemical Co., Ltd.) 0.2 part by weight is added to obtain a solder resist composition (organic resin insulating material) having a viscosity adjusted to 2.0 Pa · s at 25 ° C.
Viscosity was measured using a B-type viscometer (manufactured by Tokyo Keiki Co., Ltd., DVL-B type) at 60 rpm for rotor No. 4 and at 6 rpm for rotor No. 3.
[0086]
(19) Next, the solder resist composition is applied to both surfaces of the substrate 30 to a thickness of 20 μm, and after drying at 70 ° C. for 20 minutes and 70 ° C. for 30 minutes, the opening of the solder resist is performed. A photomask having a thickness of 5 mm on which the pattern of the portion is drawn is brought into close contact with the solder resist layer 70 to 1000 mJ / cm²Are exposed to UV light and developed with a DMTG solution to form openings 71U and 71D having a diameter of 200 μm (see FIG. 6A). A commercially available solder resist such as LPSR may also be used.
[0087]
(20) Next, the substrate on which the solder resist layer (organic resin insulating layer) 70 is formed is made of nickel chloride (2.3 × 10^-1mol / l), sodium hypophosphate (2.8 × 10 6)^-1mol / l), sodium citrate (1.6 × 10^-1The nickel plating layer 72 having a thickness of 5 μm is formed in the openings 71U and 71D by immersing in an electroless nickel plating solution having a pH of 4.5 containing 1 mol / l). Further, the substrate was made of potassium gold cyanide (7.6 × 10 6^-3mol / l), ammonium chloride (1.9 × 10^-1mol / l), sodium citrate (1.2 × 10^-1mol / l), sodium hypophosphite (1.7 × 10^-1mol-l) is immersed in an electroless plating solution at 80 ° C. for 7.5 minutes to form a gold plating layer 74 having a thickness of 0.03 μm on the nickel plating layer 72. Solder pads 75 are formed on the conductor circuit 258 (see FIG. 6B).
[0088]
(21) Thereafter, solder bumps (solder bodies) 76U and 76D are formed by printing solder paste on the openings 71U and 71D of the solder resist layer 70 and reflowing at 200 ° C. Thereby, the printed wiring board 10 having the solder bumps 76U and 76D can be obtained (see FIG. 7).
[0089]
Next, placement of the IC chip on the printed wiring board 10 completed in the above-described process and attachment to the daughter board will be described with reference to FIG. The IC chip 90 is mounted so that the solder pads 92 of the IC chip 90 correspond to the solder bumps 76U of the completed printed wiring board 10, and the IC chip 90 is attached by performing reflow. Similarly, the printed wiring board 10 is attached to the daughter board 94 by reflowing so that the pads 95 of the daughter board 94 correspond to the solder bumps 76 </ b> D of the printed wiring board 10.
[0090]
Next, a printed wiring board according to a modification of the first embodiment of the present invention will be described with reference to FIG. In the first embodiment described above, only the chip capacitor 20 accommodated in the core substrate is provided. However, in the modified example, large-capacity chip capacitors 98 are mounted on the front surface and the back surface.
[0091]
FIG. 9B shows a cross section of a chip capacitor 20 according to a first modification of the first embodiment. In the first embodiment, the surface of the capacitor is roughened to improve the adhesion with the resin. However, in the first modified example, the surface wettability is obtained by forming the polyimide film 23b instead. Has been improved. Instead of the polyimide film, a silane coupling process can be applied to the surface of the capacitor.
[0092]
In the first modified example, a composite metal film 28 composed of an electroless copper plating film 28 a and an electrolytic copper plating film 28 b is formed on the conductive paste 26. The thickness of the composite metal film 28 is desirably 0.1 to 10 μm, and optimally 1 to 5 μm. Instead of the composite metal film, it is also possible to form a single-layer metal film.
[0093]
In the first modified example, since the metal layer 28 is provided on the conductive paste 26 of the electrodes 21 and 22 of the capacitor 20, the occurrence of migration at the electrodes 21 and 22 can be prevented, and the connection resistance is reduced. Further reduction can be achieved. The electrodes 21 and 22 made of metallization have irregularities on the surface, but by applying the conductive paste 26 and further providing the metal layer 28, the irregularities can be completely eliminated and the adhesion to the via hole 60 can be improved. Can increase the connection resistance.
[0094]
An IC chip consumes a large amount of power instantaneously and performs complicated arithmetic processing. Here, in order to supply large power to the IC chip side, in the modified example, a chip capacitor 20 for power supply and a chip capacitor 98 are provided on the printed wiring board. The effect of this chip capacitor will be described with reference to FIG.
[0095]
In FIG. 11, the vertical axis indicates the voltage supplied to the IC chip, and the horizontal axis indicates time. Here, an alternate long and two short dashes line C indicates a voltage fluctuation of a printed wiring board that does not include a power supply capacitor. When the power supply capacitor is not provided, the voltage is greatly attenuated. A broken line A indicates voltage fluctuation of a printed wiring board having a chip capacitor mounted on the surface. The voltage does not drop much as compared with the two-dot chain line C, but the loop length becomes long, so the rate-determining power supply cannot be sufficiently performed. That is, the voltage drops at the start of power supply. A two-dot chain line B indicates a voltage drop of the printed wiring board incorporating the chip capacitor described above with reference to FIG. Although the loop length can be shortened, the voltage fluctuates because a large-capacity chip capacitor cannot be accommodated in the core substrate 30. Here, the solid line E shows the voltage fluctuation of the modified printed wiring board in which the chip capacitor 20 in the core substrate described above with reference to FIG. 10 and the large-capacity chip capacitor 98 are mounted on the surface. By providing a chip capacitor 20 in the vicinity of the IC chip, a chip capacitor 20 having a large capacity (and relatively large inductance), and a chip capacitor 98 having a large capacity (and relatively large inductance), a voltage can be obtained. Minimizes fluctuations.
[0096]
Next, the printed wiring board 110 according to the second embodiment of the present invention will be described with reference to FIG. In 1st Embodiment mentioned above, the case where BGA was arrange | positioned demonstrated. The second embodiment is substantially the same as the first embodiment, but is configured in a PGA system in which connection is established via a conductive pin 96 as shown in FIG. The electrode is formed with a conductive paste as in the first embodiment, or with a conductive paste and a composite metal layer as in the first modification of the first embodiment.
[0097]
Next, a method for manufacturing the printed wiring board described above with reference to FIG. 18 will be described with reference to FIGS.
[0098]
(1) First, a through hole 37a for accommodating a chip capacitor is formed in a laminate 31α obtained by laminating four prepregs 33 impregnated with an epoxy resin. On the other hand, a laminated plate 31β formed by laminating two prepregs 33 is prepared (see FIG. 12A). Here, as the prepreg 33, in addition to epoxy, a material containing a reinforcing material such as BT, phenol resin, or glass cloth can be used.
By forming the through holes 37a for accommodating the chip capacitors widely, it is possible to reliably accommodate the plurality of chip capacitors 20 in the recesses 37 in the process described later.
[0099]
(2) Next, the laminated board 31α and the laminated board 31β are pressure-bonded and heated and cured to form the core substrate 31 having the recesses 37 that can accommodate the plurality of chip capacitors 20 (FIG. 12 (B)).
[0100]
(3) Then, the adhesive material 34 is applied to the capacitor placement position of the recess 37 using a printing machine. Thereafter, the chip capacitor 20 made of a plurality of ceramics is accommodated in the recess 37 via the adhesive material 34 (see FIG. 12C). Here, by disposing the plurality of chip capacitors 20 in the recesses 37, the height of the plurality of chip capacitors 20 is uniform, so that the core substrate 31 can be made smooth. Moreover, since the recessed part 37 is formed widely, the positioning of the chip capacitor 20 can be performed accurately and can be arranged with high density. Therefore, the resin layer can be formed with a uniform thickness on the core substrate, and the via hole can be appropriately formed on the core substrate 31 as will be described later, thereby reducing the defective product generation rate of the printed wiring board. Is possible.
[0101]
(4) Then, the top surfaces of the chip capacitors 20 are pushed or hit so that the top surfaces of the plurality of chip capacitors 20 have the same height. (See FIG. 12D). With this process, when the plurality of chip capacitors 20 are disposed in the recesses 37, the heights can be made uniform even if the sizes of the plurality of chip capacitors 20 vary, and the core 31 substrate is smoothed. Can be.
[0102]
(5) Thereafter, a thermosetting resin is filled between the chip capacitors 20 in the recesses 37, and heat-cured to form the resin layer 36 (see FIG. 13A). At this time, epoxy, phenol, polyimide, and triazine are preferable as the thermosetting resin. Thereby, the chip capacitor 20 in the recess 37 can be fixed.
[0103]
(6) Further, the above-described epoxy resin or polyolefin resin is applied from above using a printing machine to form the resin insulating layer 40 (see FIG. 13B). In addition, you may affix a resin film instead of apply | coating resin.
[0104]
(7) Next, a via hole opening 48 is formed in the resin insulating layer 40 by exposure / development processing or laser (see FIG. 13C). Then, through holes 46a for through holes are formed in the resin layer 36 with a drill or a laser, and are cured by heating (see FIG. 13D).
[0105]
(8) After applying a palladium catalyst to the substrate 31, the core substrate is immersed in an electroless plating solution to uniformly deposit the electroless plating film 53 (see FIG. 14A). Although electroless plating is used here, a metal layer such as copper or nickel may be formed by sputtering. In some cases, the electroless plating film may be formed after the sputtering.
[0106]
(9) After that, a photosensitive dry film is attached to the surface of the electroless plating film 53, a mask is placed thereon, exposure / development processing is performed, and a resist 54 having a predetermined pattern is formed. Then, the core substrate 31 is immersed in the electrolytic plating solution, and an electric current is passed through the electroless plating film 53 to deposit the electrolytic plating film 56 (see FIG. 14B).
[0107]
(10) After the above process, the resist 54 is peeled off with 5% NaOH, and then the electroless plating film 53 under the resist 54 is removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide. Then, a conductor circuit 58 (including the via hole 60) and the through hole 46 made of the electrolytic copper plating film 56 are formed. Here, since the signal line does not pass through the chip capacitor 20 by forming the through hole 46, reflection due to impedance discontinuity due to the high dielectric and propagation delay due to passage through the high dielectric do not occur.
[0108]
(11) Then, the substrate 31 is washed with water, acid degreased, soft-etched, and then sprayed onto the both surfaces of the substrate 31 by spraying, so that the surface of the conductor circuit 58, the land surface of the through hole 46, the inner wall, Is etched to form a roughened surface 58α on the entire surface of the conductor circuit 58 (see FIG. 14C). As an etching solution, an etching solution (MEC Etch Bond, manufactured by MEC) comprising 10 parts by weight of imidazole copper (II) complex, 7 parts by weight of glycolic acid, and 5 parts by weight of potassium chloride is used.
[0109]
(12) Next, 100 parts by weight of a bisphenol F-type epoxy monomer (manufactured by Yuka Shell Co., Ltd., molecular weight: 310, YL983U), the average particle diameter coated with a silane coupling agent on the surface is 1.6 μm, and the largest particle SiO with a diameter of 15 μm or less₂ 170 parts by weight of spherical particles (manufactured by Adtech, CRS 1101-CE) and 1.5 parts by weight of a leveling agent (Perenol S4, manufactured by San Nopco) are placed in a container and mixed by stirring. A resin filler 62 of 49 Pa · s is prepared. As the curing agent, 6.5 parts by weight of an imidazole curing agent (manufactured by Shikoku Kasei Co., Ltd., 2E4MZ-CN) was used.
Thereafter, the resin filler 62 is filled in the through hole 46 and dried (see FIG. 14D).
[0110]
(13) Next, 30 parts by weight of bisphenol A type epoxy resin (epoxy equivalent 469, Epicoat 1001 manufactured by Yuka Shell Epoxy), cresol novolac type epoxy resin (epoxy equivalent 215, Epicron N-673 manufactured by Dainippon Ink & Chemicals, Inc.) 40 parts by weight, 30 parts by weight of triazine structure-containing phenol novolac resin (phenolic hydroxyl group equivalent 120, Phenolite KA-7052 made by Dainippon Ink & Chemicals, Inc.) to 20 parts by weight of ethyl diglycol acetate and 20 parts by weight of solvent naphtha Then, it was dissolved by heating, 15 parts by weight of terminal epoxidized polybutadiene rubber (Denalex R-45EPT manufactured by Nagase Kasei Kogyo Co., Ltd.) and 1.5 parts by weight of pulverized 2-phenyl-4,5-bis (hydroxymethyl) imidazole, 2 parts by weight of finely pulverized silica It was added 0.5 part by weight of silicon antifoaming agent to prepare an epoxy resin composition.
The obtained epoxy resin composition was applied on a PET film having a thickness of 38 μm using a roll coater so that the thickness after drying was 50 μm, and then dried at 80 to 120 ° C. for 10 minutes, whereby an interlayer resin was obtained. A resin film for an insulating layer is prepared.
[0111]
(14) A resin film for an interlayer resin insulation layer slightly larger than the substrate 31 produced in (13) is placed on the substrate 31 on both sides of the substrate, and the pressure is 4 kgf / cm.² Then, after temporarily crimping and cutting under the conditions of a temperature of 80 ° C. and a crimping time of 10 seconds, the interlayer resin insulation layer 50 is further formed by pasting using a vacuum laminator apparatus by the following method (FIG. 15A). reference). That is, the resin film for the interlayer resin insulation layer is placed on the substrate 31 with a vacuum degree of 0.5 Torr and a pressure of 4 kgf / cm.² The final pressure bonding is performed under the conditions of a temperature of 80 ° C. and a pressure bonding time of 60 seconds, and then thermosetting at 170 ° C. for 30 minutes.
[0112]
(15) Next, CO 2 having a wavelength of 10.4 μm is passed through a mask 47 in which a through hole 47a having a thickness of 1.2 mm is formed on the interlayer resin insulation layer 50.₂ With a gas laser, a via hole opening with a diameter of 80 μm in the interlayer resin insulation layer 50 under the conditions of a beam diameter of 4.0 mm, a top hat mode, a pulse width of 8.0 μsec, a mask through-hole diameter of 1.0 mm, and one shot. 148 is formed (see FIG. 15B).
[0113]
(16) The substrate 31 on which the via hole opening 148 is formed is immersed in an 80 ° C. solution containing 60 g / l of permanganic acid for 10 minutes to dissolve and remove the epoxy resin particles present on the surface of the interlayer resin insulation layer 50. As a result, the surface of the interlayer resin insulating layer 50 including the inner wall of the via hole opening 148 is made roughened surface 50α (see FIG. 15C). You may roughen by an acid or an oxidizing agent. The roughened layer is preferably 0.1 to 5 μm.
[0114]
(17) Next, the substrate 31 after the above treatment is immersed in a neutralization solution (manufactured by Shipley Co., Ltd.) and then washed with water. Further, by applying a palladium catalyst to the surface of the substrate 31 that has been roughened (roughening depth: 3 μm), catalyst nuclei are attached to the surface of the interlayer resin insulation layer 50 and the inner wall surface of the via hole opening 148. Let
[0115]
(18) Next, the substrate is immersed in an electroless copper plating aqueous solution having the following composition to form an electroless copper plating film 153 having a thickness of 0.6 to 3.0 μm over the entire roughened surface 50α (FIG. 15 (D)).
[Electroless plating aqueous solution]
NiSO_Four                  0.003 mol / l
Tartaric acid 0.200 mol / l
Copper sulfate 0.030 mol / l
HCHO 0.050 mol / l
NaOH 0.100 mol / l
α, α'-bipyridyl 40 mg / l
Polyethylene glycol (PEG) 0.10 g / l
[Electroless plating conditions]
40 minutes at 35 ° C liquid temperature
[0116]
(19) A commercially available photosensitive dry film is attached to the electroless copper plating film 153, a mask is placed, and 100 mJ / cm.² And a plating resist 154 having a thickness of 30 μm is provided by developing with a 0.8% aqueous sodium carbonate solution. (See FIG. 16A).
[0117]
(20) Next, the substrate 31 is washed and degreased with water at 50 ° C., washed with water at 25 ° C., and further washed with sulfuric acid, and then subjected to electrolytic copper plating under the following conditions to provide an electrolysis having a thickness of 20 μm. A copper plating film 156 is formed (see FIG. 16B).
(Electrolytic plating aqueous solution)
Sulfuric acid 2.24 mol / l
Copper sulfate 0.26 mol / l
Additive 19.5 ml / l
(Manufactured by Atotech Japan, Kaparaside HL)
[Electrolytic plating conditions]
Current density 1 A / dm²
65 minutes
Temperature 22 ± 2 ° C
[0118]
(21) After stripping and removing the plating resist 154 with 5% NaOH, the electroless plating film 153 under the plating resist 154 is removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide to remove the electroless copper plating film. A conductor circuit 158 (including the via hole 160) having a thickness of 18 μm and formed of 153 and the electrolytic copper plating film 156 is formed. Then, the process similar to (11) is performed and the roughening surface 158 (alpha) is formed with the etching liquid containing a cupric complex and an organic acid (refer FIG.16 (C)).
[0119]
(22) Subsequently, the steps (14) to (21) are repeated to further form an upper interlayer resin insulation layer 150 and a conductor circuit 258 (including via holes 260) (see FIG. 16D). ).
[0120]
(23) Next, a photosensitizing agent obtained by acrylated 50% of an epoxy group of a cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) to a concentration of 60% by weight. 46.67 parts by weight of oligomer (molecular weight 4000), 15 parts by weight of 80% by weight of bisphenol A type epoxy resin (manufactured by Yuka Shell Co., Ltd., trade name: Epicoat 1001) dissolved in methyl ethyl ketone, imidazole curing agent (manufactured by Shikoku Kasei Co., Ltd.) , Trade name: 2E4MZ-CN) 1.6 parts by weight, bifunctional acrylic monomer as a photosensitive monomer (manufactured by Kyoei Chemical Co., Ltd., trade name: R604), 4.5 parts by weight; , Trade name: DPE6A) 1.5 parts by weight, dispersion antifoaming agent (manufactured by San Nopco, trade name: S-65) 0 71 parts by weight is placed in a container, and the mixture composition is prepared by stirring and mixing. 2.0 parts by weight of benzophenone (manufactured by Kanto Chemical Co., Inc.) as a photoweight initiator for this mixture composition, and as a photosensitizer 0.2 parts by weight of Michler's ketone (manufactured by Kanto Chemical Co., Inc.) is added to obtain a solder resist composition (organic resin insulating material) having a viscosity adjusted to 2.0 Pa · s at 25 ° C.
Viscosity was measured using a B-type viscometer (manufactured by Tokyo Keiki Co., Ltd., DVL-B type) at 60 rpm for rotor No. 4 and at 6 rpm for rotor No. 3.
[0121]
(24) Next, the solder resist composition prepared in (23) is applied to both surfaces of the substrate 30 to a thickness of 20 μm. Then, after drying at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, a photomask having a thickness of 5 mm on which the pattern of the opening of the solder resist was drawn was brought into close contact with the solder resist composition and 1000 mJ / cm²Are exposed to UV light and developed with DMTG solution to form openings 71U and 71D having a diameter of 200 μm.
Further, the solder resist composition is cured by heating at 80 ° C. for 1 hour, at 100 ° C. for 1 hour, at 120 ° C. for 1 hour, and at 150 ° C. for 3 hours, and has openings 71U and 71D. Then, a solder resist layer 70 having a thickness of 20 μm is formed (see FIG. 17A). A commercially available solder resist composition can also be used as the solder resist composition.
[0122]
(25) Next, the substrate on which the solder resist layer 70 is formed is nickel chloride (2.3 × 10^-1mol / l), sodium hypophosphate (2.8 × 10 6)^-1mol / l), sodium citrate (1.6 × 10^-1The nickel plating layer 72 having a thickness of 5 μm is formed in the openings 71U and 71D by immersing in an electroless nickel plating solution having a pH of 4.5 containing 1 mol / l). Further, the substrate was made of potassium gold cyanide (7.6 × 10 6^-3mol / l), ammonium chloride (1.9 × 10^-1mol / l), sodium citrate (1.2 × 10^-1mol / l), sodium hypophosphite (1.7 × 10^-1mol / l) is immersed in an electroless gold plating solution at 80 ° C. for 7.5 minutes to form a 0.03 μm thick gold plating layer 74 on the nickel plating layer 72 (FIG. 17B). reference).
[0123]
(26) Thereafter, a solder paste containing tin-lead is printed in the opening 71U of the solder resist layer 70 on the surface on which the IC chip of the substrate is placed. Further, a solder paste is printed as the conductive adhesive 97 in the opening 71D on the other surface. Next, the conductive connection pin 96 is attached to and supported by an appropriate pin holding device, and the fixing portion 98 of the conductive connection pin 96 is brought into contact with the conductive adhesive 97 in the opening 71D. Then, reflow is performed to fix the conductive connection pin 96 to the conductive adhesive 97. As a method for attaching the conductive connection pin 96, a conductive adhesive 97 formed in a ball shape or the like is put into the opening 71D, or the conductive adhesive 97 is joined to the fixing portion 98 to conduct the conductive. May be attached and then reflowed.
[0124]
Thereafter, the IC chip 90 is mounted so that the solder pads 92 of the IC chip 90 correspond to the solder bumps 76 on the opening 71U side of the printed wiring board 110, and the IC chip 90 is attached by performing reflow (FIG. 18).
[0125]
Subsequently, a manufacturing method according to a modified example of the printed wiring board of the second embodiment will be described with reference to FIG. The electrode is formed with a conductive paste as in the first embodiment, or with a conductive paste and a composite metal layer as in the first modification of the first embodiment.
(1) First, through holes 37a for accommodating chip capacitors are formed in a laminated plate 31α obtained by laminating and curing four prepregs 33 impregnated with an epoxy resin. On the other hand, a sheet 31γ made of uncured prepreg 33 and a plate 31β made by curing prepreg 33 are prepared (see FIG. 19A).
[0126]
(2) Next, the laminated plate 31α and the plate 31β are pressure-bonded by the sheet 31γ to form the substrate 31 having the recesses 37 (see FIG. 19B).
[0127]
(3) Then, the chip capacitor 20 made of a plurality of ceramics is accommodated on a sheet 31γ made of an uncured prepreg 33 (see FIG. 19C).
[0128]
(4) Then, the top surfaces of the chip capacitors 20 are pushed or hit so that the top surfaces of the plurality of chip capacitors 20 have the same height (see FIG. 2A). Thereafter, the core substrate 31 for curing the uncured prepreg 33 by heating is formed. The following steps are the same as those in the second embodiment described above with reference to FIGS.
[0129]
The configuration of the printed wiring board according to the third embodiment of the present invention will be described with reference to FIG.
The configuration of the printed wiring board of the third embodiment is substantially the same as that of the first embodiment described above. However, the chip capacitor 20 accommodated in the core substrate 30 is different. FIG. 20 shows a plan view of the chip capacitor. FIG. 20A shows a chip capacitor before cutting for multi-piece taking, and a one-dot chain line in the drawing indicates a cutting line. In the printed wiring board of the first embodiment described above, the first electrode 21 and the second electrode 22 are arranged on the side edge of the chip capacitor as shown in the plan view of FIG. FIG. 20C shows the chip capacitor before cutting for multi-piece fabrication according to the third embodiment, and the alternate long and short dash line in the drawing indicates the cutting line. In the printed wiring board of the third embodiment, the first electrode 21 and the second electrode 22 are arranged inside the side edge of the chip capacitor as shown in the plan view of FIG. The electrode is formed with a conductive paste as in the first embodiment, or with a conductive paste and a composite metal layer as in the first modification of the first embodiment.
[0130]
In the printed wiring board of the third embodiment, since the chip capacitor 20 having electrodes formed inside the outer edge is used, a chip capacitor having a large capacity can be used.
[0131]
Next, a printed wiring board according to a first modification of the third embodiment will be described with reference to FIG.
FIG. 21 is a plan view of the chip capacitor 20 accommodated in the core substrate of the printed wiring board according to the first modification. In the first embodiment described above, a plurality of small-capacity chip capacitors are accommodated in the core substrate. However, in the first modification, a large-capacity large-sized chip capacitor 20 is accommodated in the core substrate. Here, the chip capacitor 20 includes a first electrode 21, a second electrode 22, a dielectric 23, a first conductive film 24 connected to the first electrode 21, and a second electrode connected to the second electrode 22 side. The conductive film 25 and the connection electrodes 27 on the upper and lower surfaces of the chip capacitor not connected to the first conductive film 24 and the second conductive film 25 are formed. The IC chip side and the daughter board side are connected via this electrode 27. The electrode is formed with a conductive paste as in the first embodiment, or with a conductive paste and a composite metal layer as in the first modification of the first embodiment.
[0132]
Since the large-sized chip capacitor 20 is used in the printed wiring board of the first modified example, a chip capacitor having a large capacity can be used. Further, since the large chip capacitor 20 is used, the printed wiring board is not warped even when the heat cycle is repeated.
[0133]
A printed wiring board according to a second modification will be described with reference to FIG. FIG. 22A shows a chip capacitor before cutting for multi-piece cutting, in which a one-dot chain line shows a normal cutting line, and FIG. 22B shows a plan view of the chip capacitor. . As shown in FIG. 22B, in the second modified example, a plurality of chip capacitors (three in the example in the figure) are connected and used in a large format. The electrode is formed with a conductive paste as in the first embodiment, or with a conductive paste and a composite metal layer as in the first modification of the first embodiment.
[0134]
In the second modified example, since a large chip capacitor 20 is used, a chip capacitor having a large capacity can be used. Further, since the large chip capacitor 20 is used, the printed wiring board is not warped even when the heat cycle is repeated.
[0135]
In the third embodiment described above, the chip capacitor is built in the printed wiring board. However, instead of the chip capacitor, it is also possible to use a plate-like capacitor in which a conductive film is provided on a ceramic plate.
[0136]
Here, with respect to the printed wiring board of the first embodiment, values obtained by measuring the inductance of the chip capacitor 20 embedded in the core substrate and the inductance of the chip capacitor mounted on the back surface (surface on the daughter board side) of the printed wiring board are as follows. It is shown below.
In the case of a single capacitor
Embedded type 137pH
Back mounting type 287pH
When 8 capacitors are connected in parallel
Embedded type 60pH
Back mounting type 72pH
As described above, even when the capacitor is used alone, the inductance can be reduced by incorporating the chip capacitor even when they are connected in parallel to increase the capacitance.
[0137]
Next, the results of the reliability test will be described. Here, in the printed wiring board of the first embodiment, the change rate of the capacitance of one chip capacitor was measured.

[0138]
The steam test was kept at 100% humidity by exposure to steam. In the HAST test, the sample was left for 100 hours at a relative humidity of 100%, an applied voltage of 1.3 V, and a temperature of 121 ° C. In the TS test, a test that was allowed to stand at -125 ° C for 30 minutes and at 55 ° C for 30 minutes was repeated 1000 lines.
[0139]
In the above reliability test, it was found that a printed wiring board with a built-in chip capacitor can achieve the same reliability as the existing capacitor surface mount type. Further, as described above, in the TS test, even if internal stress occurs due to the difference in thermal expansion coefficient between the ceramic capacitor, the resin core substrate 30 and the resin insulating layer 40, the first capacitor of the chip capacitor 20 is used. Disconnection between the terminal 21 and the second terminal 22 and the via hole 60, separation between the chip capacitor 20 and the resin insulating layer 40, no cracks in the resin insulating layer 40, and high reliability is achieved over a long period of time. It turns out that you can.
[0140]
【The invention's effect】
In the present invention, as described above, since the concave portions are formed widely and the plurality of capacitors are accommodated in the concave portions, the plurality of capacitors are surely positioned accurately in the core substrate even if the accuracy of counterboring is low. It becomes possible to arrange with high density. In addition, since the plurality of capacitors are placed in the recess, the height of the plurality of capacitors is uniform, so that the insulating layer on the capacitor can have a uniform thickness. Therefore, since a via hole and a conductor circuit can be formed appropriately, the defective product generation rate of a printed wiring board can be reduced.
[0141]
Further, since the conductive paste is applied to the surface of the capacitor electrode, the surface becomes completely flat. For this reason, when an opening is made in the resin layer with a laser, the resin does not remain on the surface of the electrode, and the connectivity between the electrode and a via hole formed by plating can be improved.
Further, since the resin is filled between the core substrate and the capacitor, even if a stress caused by the capacitor or the like is generated, the stress is alleviated and no migration occurs. Therefore, there is no influence of peeling or dissolution on the connection portion between the capacitor electrode and the via hole. Therefore, the desired performance can be maintained even if the reliability test is performed.
Also, migration can be prevented when the capacitor is covered with copper.
[Brief description of the drawings]
1A, 1B, 1C and 1D are manufacturing process diagrams of a printed wiring board according to a first embodiment of the present invention.
FIGS. 2A, 2B, 2C, and 2D are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention. FIGS.
FIGS. 3A, 3B, 3C and 3D are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention. FIGS.
4A, 4B, 4C, and 4D are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.
5A, 5B, 5C, and 5D are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.
6A and 6B are manufacturing process diagrams of the printed wiring board according to the first embodiment of the present invention.
FIG. 7 is a cross-sectional view of the printed wiring board according to the first embodiment of the present invention.
FIG. 8 is a cross-sectional view showing a state where an IC chip is mounted on the printed wiring board according to the first embodiment of the present invention.
FIG. 9A is a cross-sectional view of the chip capacitor of the first embodiment, and FIG. 9B is a cross-sectional view of the chip capacitor of the first modified example of the first embodiment.
FIG. 10 is a cross-sectional view of a printed wiring board according to a modification of the first embodiment of the present invention.
FIG. 11 is a graph showing changes in power supplied to an IC chip and time.
12A, 12B, 12C, and 12D are manufacturing process diagrams of a printed wiring board according to a second embodiment of the present invention.
13A, 13B, 13C, and 13D are manufacturing process diagrams of the printed wiring board according to the second embodiment of the present invention.
14A, 14B, 14C, and 14D are manufacturing process diagrams of a printed wiring board according to a second embodiment of the present invention.
15A, 15B, 15C, and 15D are manufacturing process diagrams of a printed wiring board according to a second embodiment of the present invention.
16A, 16B, 16C, and 16D are manufacturing process diagrams of a printed wiring board according to the second embodiment of the present invention.
17A and 17B are manufacturing process diagrams of the printed wiring board according to the second embodiment of the present invention.
FIG. 18 is a cross-sectional view showing a state where an IC chip is mounted on a printed wiring board according to a second embodiment of the present invention.
FIGS. 19A, 19B, 19C, and 19D are manufacturing process diagrams of a printed wiring board according to a modification of the second embodiment of the present invention. FIGS.
20A, 20B, 20C, and 20D are plan views of a chip capacitor of a printed wiring board according to a third embodiment.
FIG. 21 is a plan view of a chip capacitor of the printed wiring board according to the third embodiment.
22A and 22B are plan views of a chip capacitor of a printed wiring board according to a modification of the third embodiment.
[Explanation of symbols]
20 chip capacitors
21 First electrode
22 Second electrode
23 Dielectric
23a Roughened surface
23b Polyimide membrane
26 Conductive paste
28a Electroless copper plating film
28b Electrolytic copper plating film
28 Composite metal membrane
30 core substrate
31 Core substrate
32 recess
36 Resin layer
37 recess
40 Interlayer resin insulation layer
46 Bahia Hall
50 Interlayer resin insulation layer
60 Bahia Hall
70 Solder resist layer
71U, 71D opening
72 Nickel plating layer
74 Gold plating layer
76 Solder bump
90 IC chip
92 Solder pads (IC chip side)
94 Daughter Board
95 Solder pad (Daughter board side)
96 Conductive connection pins
97 Conductive adhesive
98 fixed part
150 Interlayer resin insulation layer
158 Conductor circuit
160 Viahole
258 conductor circuit
260 Bahia Hall

Claims (16)

A printed wiring board formed by laminating a resin insulating layer and a conductor circuit on a core substrate,
A recess is formed in the core substrate, and a plurality of capacitors are accommodated in the recess.
On the surface of the electrode made of metallization of the capacitor, a conductive resin paste is applied,
A copper plating film is provided on the conductive resin paste,
Connected to the capacitor electrode by a via hole made of plating ,
A printed wiring board characterized in that a resin having a lower coefficient of thermal expansion than that of the core substrate and the resin insulating layer containing an inorganic filler is filled between a plurality of capacitors in the recess . The printed wiring board according to claim 1 , wherein a surface of the capacitor is roughened.   The printed wiring board according to claim 1, wherein a surface wettability improving process is performed on a surface of the capacitor. The resin layer, the printed wiring board according to any one of claims 1 to 3, characterized in that the formation of the through hole and drilled hole. Printed circuit board according to one of claims 1 to 4, characterized in that mounting the capacitor on the surface of the printed wiring board. 6. The printed wiring board according to claim 5 , wherein the capacitance of the chip capacitor on the surface is equal to or greater than the capacitance of the inner layer capacitor. 6. The printed wiring board according to claim 5 , wherein the inductance of the surface chip capacitor is equal to or greater than the inductance of the inner layer capacitor. As the capacitor, printed wiring board according to one of claims 1 to 7, characterized in that using a chip capacitor that is inside electrode is formed of the outer edge. As the capacitor, printed wiring board according to one of claims 1 to 8, characterized in that using a chip capacitor formed of the electrode in a matrix. As the capacitor, printed wiring board according to one of claims 1 to 9, the chip capacitor was plurality ligated characterized by using in for multi-piece. A method for producing a printed wiring board comprising at least the following steps (a) to (d):
(A) forming a recess in the core substrate;
(B) a step of placing a capacitor in which a copper plating film with a conductive resin paste on the applied conductive resin paste on the plurality of metallized electrode in the recess;
(C) filling the space between the plurality of capacitors with a resin having a lower coefficient of thermal expansion than the core substrate and the insulating layer ;
(D) A step of forming a resin layer on the capacitor and forming via holes reaching the electrodes of the capacitor by plating. 12. The method according to claim 11 , further comprising, after the step (b), applying a pressure from above to the top surfaces of the plurality of capacitors in the recess to align the heights of the top surfaces of the capacitors. Manufacturing method of printed wiring board. The method for manufacturing a printed wiring board according to claim 11 , further comprising a step of forming a through hole in the resin layer after the step (c) to form a through hole. A method for producing a printed wiring board comprising at least the following steps (a) to (e):
(A) forming a through hole in a resin material containing a resin as a core material;
(B) a step of attaching a resin material to the resin material in which the through holes are formed to form a core substrate having a recess;
(C) a step of placing a capacitor in which a copper plating film with a conductive resin paste on the applied conductive resin paste on the plurality of metallized electrodes in the recess of the core substrate;
(D) filling a resin having a lower coefficient of thermal expansion than the core substrate and the insulating layer between the plurality of capacitors;
(E) A step of forming a resin layer on the capacitor and forming a via hole reaching the electrode of the capacitor by plating. 15. The method according to claim 14 , further comprising: after the step (c), applying pressure from above to the upper surfaces of the plurality of capacitors in the recess to align the heights of the upper surfaces of the capacitors. Manufacturing method of printed wiring board. The method for manufacturing a printed wiring board according to claim 14 , further comprising a step of forming a through hole in the resin layer after the step (d).

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