JP4945842B2 - Printed wiring board and printed wiring board manufacturing method - Google Patents

Description

【０１０１】
Steam試験は、蒸気に当て湿度１００％に保った。また、ＨＡＳＴ試験では、相対湿度１００％、印加電圧１．３Ｖ、温度１２１℃で１００時間放置した。ＴＳ試験では、−１２５℃で３０分、５５℃で３０分放置する試験を１０００回線り返した。
【０１０２】
上記信頼性試験において、チップコンデンサを内蔵するプリント配線板においても、既存のコンデンサ表面実装形と同等の信頼性が達成できていることが分かった。また、上述したように、ＴＳ試験において、セラミックから成るコンデンサと、樹脂からなるコア基板及び層間樹脂絶縁層の熱膨張率の違いから、内部応力が発生しても、チップコンデンサの端子とバイアホールとの間に断線、チップコンデンサと層間樹脂絶縁層との間で剥離、層間樹脂絶縁層にクラックが発生せず、長期に渡り高い信頼性を達成できることが判明した。
【０１０３】
【発明の効果】
本願発明では、上述したようにプリント配線板内にコンデンサを配置するため、ＩＣチップとコンデンサとの距離が短くなり、ループインダクタンスを低減することができる。また、コア基板は、コンデンサを収容する第１のコア基板の上下に第２、第３のコア基板を積層してなるため、堅牢であり、セラミックからなり熱膨張率の小さいコンデンサを収容しても、コンデンサとコア基板との熱膨張率差による応力を層間樹脂絶縁層に与え導体回路にクラックが発生することがなく、高い信頼性を備えるプリント配線板を実現できる。また、コア基板は、表面を研磨して平坦化できるため、コア基板上層の層間樹脂絶縁層にうねりが生じず、層間樹脂絶縁層上に適正にバイアホール、導体回路を形成することができる。
【０１０４】
コンデンサの下部からも接続することが可能となるので、ループインダクタンスの距離を短くし、配設する自由度を増す構造であるといえる。
また、コア基板とコンデンサの間に樹脂が充填されているので、コンデンサなどが起因する応力が発生しても緩和されるし、マイグレーションの発生がない。そのために、コンデンサの電極とバイアホールの接続部への剥離や溶解などの影響がない。
そのために、信頼性試験を実施しても所望の性能を保つことができるのである。
また、コンデンサを銅によって被覆されている場合にも、マイグレーションの発生を防止することができる。
【図面の簡単な説明】
【図１】本発明の第１実施形態に係るプリント配線板の製造工程図である。
【図２】本発明の第１実施形態に係るプリント配線板の製造工程図である。
【図３】本発明の第１実施形態に係るプリント配線板の製造工程図である。
【図４】本発明の第１実施形態に係るプリント配線板の製造工程図である。
【図５】本発明の第１実施形態に係るプリント配線板の製造工程図である。
【図６】本発明の第１実施形態に係るプリント配線板の製造工程図である。
【図７】本発明の第１実施形態に係るプリント配線板の製造工程図である。
【図８】本発明の第１実施形態に係るプリント配線板の製造工程図である。
【図９】本発明の第１実施形態に係るプリント配線板の製造工程図である。
【図１０】本発明の第１実施形態に係るプリント配線板の製造工程図である。
【図１１】第１実施形態に係るプリント配線板の断面図である。
【図１２】図１１のプリント配線板の拡大断面図である。
【図１３】（Ａ）及び（Ｂ）は、第１実施形態のプリント配線板に収容されるチップコンデンサの断面図である。
【図１４】第１実施形態の改変例に係るプリント配線板の断面図である。
【図１５】ＩＣチップへの供給電圧と時間との変化を示すグラフである。
【図１６】第２実施形態に係るプリント配線板の断面図である。
【図１７】（Ａ）は第２実施形態のプリント配線板に収容されるチップコンデンサの断面図であり、（Ｂ）は、平面図である。
【図１８】（Ａ）及び（Ｂ）は、第１実施形態のプリント配線板に収容されるチップコンデンサの断面図である。
【図１９】（Ａ）及び（Ｂ）は、従来技術に係るプリント配線板のループインダクタンスの説明図である。
【符号の説明】
１０ プリント配線板
１１ 第１コア基板
１１Ａ 通孔
１２Ａ 通孔
１２Ｕ 第２コア基板
１２Ｄ 第３コア基板
１３Ｕ プリプレグ
１３Ｄ プリプレグ
１４ 樹脂充填剤
１５ 接着剤
２０ チップコンデンサ
２１ 第１電極
２２ 第２電極
２６ 導電性ペースト
３０ 積層コア基板
３１ 導体回路（コンフォマルマスク）
３１ａ 開口
３６ スルーホール
３７ 樹脂充填剤
５８ 導体回路
６０ バイアホール
７０ ソルダーレジスト
７６Ｕ 半田バンプ
７６Ｄ ＢＧＡ
８６ コンデンサ
９０ ＩＣチップ
９４ ドータボード
９７ 導電性接続ピン
１４４ 層間樹脂絶縁層
１５８ 導体回路
１６０ バイアホール
２５８ 導体回路
２６０ バイアホール[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a printed wiring board on which an electronic component such as an IC chip is placed, and more particularly to a printed wiring board having a capacitor built therein.
[0002]
[Prior art]
Usually, in the computer, the wiring distance between the power source and the IC chip is long, and the loop inductance of this wiring portion is very large. For this reason, the fluctuation of the IC drive voltage at the time of high-speed operation becomes large, which may cause an IC malfunction. It is also difficult to stabilize the power supply voltage. For this reason, a capacitor is mounted on the surface of the printed wiring board as an auxiliary to power supply.
[0003]
That is, the loop inductance that causes voltage fluctuation is the wiring length from the power source shown in FIG. 19A to the power source terminal 272P of the IC chip 270 via the power source line in the printed wiring board 300, and the ground terminal of the IC chip 270. It depends on the wiring length from 272E to the power supply through the ground wire in the printed wiring board 300 from the power supply. In addition, the loop inductance can be reduced by narrowing the distance between the power lines and the ground lines, for example, between the wirings through which currents flow in opposite directions.
For this reason, as shown in FIG. 19B, by mounting a chip capacitor 298 on the printed wiring board 300, the inside of the printed wiring board 300 connecting the IC chip 270 and the chip capacitor 292 serving as a power supply source. The loop inductance is reduced by shortening the wiring length between the power line and the grounding wire and reducing the wiring interval.
[0004]
[Problems to be solved by the invention]
However, the magnitude of the voltage drop causing the IC drive voltage fluctuation depends on the frequency. For this reason, as the driving frequency of the IC chip increases, the loop inductance cannot be reduced even if the chip capacitor is mounted on the surface as described above with reference to FIG. It became difficult to keep it down.
[0005]
For this reason, this inventor had the idea of accommodating a chip capacitor in a printed wiring board. As a technique for embedding a capacitor in a substrate, JP-A-6-326472, JP-A-7-263619, JP-A-10-256429, JP-A-11-45955, JP-A-11-126978, and JP-A-11-31868 are disclosed. Etc.
[0006]
Japanese Patent Application Laid-Open No. 6-326472 discloses a technique of embedding a capacitor in a resin substrate made of glass epoxy. With this configuration, it is possible to reduce power supply noise, eliminate the need for a space for mounting a chip capacitor, and reduce the size of the insulating substrate. Japanese Patent Application Laid-Open No. 7-263619 discloses a technique for embedding a capacitor in a substrate such as ceramic or alumina. With this configuration, by connecting between the power supply layer and the ground layer, the wiring length is shortened and the wiring inductance is reduced.
[0007]
[Problems to be solved by the invention]
However, the above-described technology cannot reduce the distance from the IC chip to the capacitor so much, and in the further high frequency region of the IC chip, the inductance cannot be reduced as currently required. In particular, in the resin-made multilayer build-up wiring board, due to the difference in thermal expansion coefficient between the ceramic capacitor and the resin core substrate and the interlayer resin insulation layer, the disconnection between the terminal of the chip capacitor and the via hole, Peeling occurred between the chip capacitor and the interlayer resin insulation layer, and cracks occurred in the interlayer resin insulation layer, and high reliability could not be achieved over a long period of time.
[0008]
The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a printed wiring board that can reduce loop inductance and has high reliability, and a method for manufacturing the same.
[0009]
  In order to solve the above-described problem, in claim 1, a printed wiring board is formed by laminating a resin insulating layer and a conductor circuit on a core substrate that accommodates a capacitor, and the core substrate is configured to accommodate the capacitor. The second and third core substrates are stacked above and below the first core substrate in which the holes are formed, and a pair of via holes are formed in the second and third core substrates,Forming a metal film on the electrode of the capacitor and connecting the first and second electrodes of the capacitor, respectively;One and the other of a pair of via holes;The metal film was formedBetween the first electrode and the second electrode of the capacitorBy platingThe technical feature is that each has an electrical connection.
[0010]
  According to the first aspect, since the capacitor is arranged in the printed wiring board, the distance between the IC chip and the capacitor is shortened, and the loop inductance can be reduced. In addition, the core substrate is formed by laminating the second and third core substrates on the top and bottom of the first core substrate that accommodates the capacitor. Therefore, the core substrate is robust and accommodates a capacitor made of ceramic and having a low coefficient of thermal expansion. However, stress due to the difference in thermal expansion coefficient between the capacitor and the core substrate is applied to the interlayer resin insulation layer, and the conductor circuit is not cracked, and a printed wiring board having high reliability can be realized. Moreover, since the surface of the core substrate can be polished and flattened, no undulation occurs in the interlayer resin insulation layer on the core substrate, and a via hole and a conductor circuit can be appropriately formed on the interlayer resin insulation layer.
  Furthermore, via holes are provided on both sides of the core substrate, so that the IC chip and the capacitor accommodated in the substrate can be connected to the power supply arranged on the external connection substrate and the capacitor accommodated in the substrate at the shortest distance. Can connect. For this reason, the voltage can be instantaneously compensated from the power source to the IC chip, and the IC drive voltage can be quickly stabilized.
  Further, electrical connection is made to the electrode of the chip capacitor formed with the metal film by a via hole formed by plating. Here, the electrode of the chip capacitor is made of metallization and has an uneven surface, but the surface is smoothed by the metal film, and a via hole is formed, so when a through hole is formed in the resin coated on the electrode The resin residue does not remain, and the connection reliability between the via hole and the electrode can be improved. Furthermore, since via holes are formed by plating on the plated electrodes, the connectivity between the electrodes and via holes is high, and disconnection between the electrodes and via holes may occur even when a heat cycle test is performed. Absent.
The metal film of the capacitor electrode is preferably provided with any one of copper, nickel, and a noble metal. This is because a layer of tin, zinc or the like in the built-in capacitor tends to induce migration at the connection portion with the via hole. Therefore, the occurrence of migration can also be prevented.
[0011]
It is desirable to fill the voids in the core substrate with resin. By eliminating the gap between the capacitor and the core substrate, the built-in capacitor is less likely to behave, and even if stress originating from the capacitor is generated, it can be relaxed by the filled resin. The resin also has an effect of reducing adhesion and migration between the capacitor and the core substrate.
[0012]
As the resin to be filled, a thermosetting resin, a photosensitive resin, a thermoplastic resin, or a composite thereof can be used. In addition to this, an adhesive resin sheet such as a prepreg may be sandwiched in advance and filled with a resin that exudes from the prepreg when the substrate is pressure-bonded.
[0013]
In addition, the surface of the chip capacitor can be roughened. As a result, the adhesion between the ceramic chip capacitor and the resin adhesive and resin filler is increased, and the adhesive and resin filler may be peeled off at the interface even when the heat cycle test is performed. Absent.
[0014]
According to the second aspect, the first, second, and third core substrates are made of the resin substrate in which the core material is impregnated with the resin, so that sufficient strength can be obtained.
[0015]
  In claim 3, since the conductive paste is applied to the surface of the capacitor electrode, the surface becomes completely flat. For this reason, when an opening is made in the second and third core substrates with a laser, no resin remains on the surface of the electrode, and the connection reliability between the electrode and the via hole formed by plating can be improved. .
[0016]
According to a fourth aspect of the present invention, a capacitor is provided on the surface in addition to the capacitor accommodated in the substrate. Since the capacitor is accommodated in the printed wiring board, the distance between the IC chip and the capacitor is shortened, the loop inductance can be reduced, and the power can be supplied instantaneously. Since the capacitor is disposed, a large-capacity capacitor can be attached, and a large amount of power can be easily supplied to the IC chip.
[0017]
According to the fifth aspect, since the capacitance of the capacitor on the surface is equal to or larger than the capacitance of the capacitor on the inner layer, there is no shortage of power supply in the high frequency region, and a desired operation of the IC chip is ensured.
[0018]
According to the sixth aspect of the present invention, since a capacitor having electrodes formed in a matrix is used, a large chip capacitor can be easily accommodated in the core substrate. As a result, the capacitance can be increased, and the electrical problem can be solved. Further, the capacitor becomes a core, and even after various thermal histories, the printed wiring board is hardly warped. Furthermore, since it is possible to route wiring from multiple electrodes, increasing the number of power lines and ground lines can reduce the inductance of the power lines and ground lines, thereby improving high frequency performance. It becomes possible. Furthermore, the capacitor electrode can be used as a through hole.
[0019]
  Claim7Then, electrical connection is made to the electrode of the chip capacitor formed with the metal film by a via hole formed by plating. Here, the electrode of the chip capacitor is made of metallization and has an uneven surface, but the surface is smoothed by the metal film, and a via hole is formed, so when a through hole is formed in the resin coated on the electrode The resin residue does not remain, and the connection reliability between the via hole and the electrode can be improved. Furthermore, since via holes are formed by plating on the plated electrodes, the connectivity between the electrodes and via holes is high, and disconnection between the electrodes and via holes may occur even when a heat cycle test is performed. Absent.
[0020]
The metal film of the capacitor electrode is preferably provided with any one of copper, nickel, and a noble metal. This is because a layer of tin, zinc or the like in the built-in capacitor tends to induce migration at the connection portion with the via hole. Therefore, the occurrence of migration can also be prevented.
[0021]
  Claim8In this case, at least a part of the electrode of the chip capacitor is accommodated in the exposed printed wiring board and electrically connected to the electrode exposed from the coating layer. At this time, it is desirable that the exposed metal is mainly composed of Cu. This is because the connection resistance can be reduced.
[0022]
  Claim11The method for producing a printed wiring board according to claim 1 comprises at least the following steps (a) to (c):
(A) a step of laminating the second and third core substrates above and below the first core substrate in which the capacitor is accommodated in the through hole with a resin plate impregnated with uncured resin interposed therebetween;
(B) forming an opening reaching the capacitor electrode with a laser in the second and third core substrates;
(C) A step of plating the opening to form a via hole.
[0023]
  Claim11In this printed wiring board manufacturing method, a chip capacitor can be accommodated in the core substrate, and a printed wiring board with reduced loop inductance can be provided.
[0024]
As the resin to be filled, a thermosetting resin, a photosensitive resin, a thermoplastic resin, or a composite thereof can be used. In addition to this, an adhesive resin sheet such as a prepreg may be sandwiched in advance and filled with a resin that exudes from the prepreg when the substrate is pressure-bonded.
[0025]
  Claim12The method for producing a printed wiring board comprises at least the following steps (a) to (e):
(A) a step of laminating the second and third core substrates above and below the first core substrate in which the capacitor is accommodated in the through hole with a resin plate impregnated with uncured resin interposed therebetween;
(B) forming an opening reaching the capacitor electrode with a laser in the second and third core substrates:
(C) plating the opening to form a via hole;
(D) applying a resin filler to the surfaces of the second and third core substrates;
(E) A step of polishing and smoothing the surfaces of the second and third core substrates.
[0026]
  Claim12In this printed wiring board manufacturing method, a chip capacitor can be accommodated in the core substrate, and a printed wiring board with reduced loop inductance can be provided. Also, since the surface of the core substrate is flattened by applying a resin filler and then flattened, there is no undulation in the interlayer resin insulation layer on the core substrate, and via holes and conductor circuits are properly formed on the interlayer resin insulation layer. Can be formed.
[0027]
  Claim13In the method of manufacturing a printed wiring board, the openings formed in the conductor circuits of the second and third core substrates are used as conformal masks in the step of forming the openings in the core substrate with a laser. Can be formed.
[0028]
In this invention, it is suitable to form an interlayer resin insulation layer using a thermosetting resin sheet. The thermosetting resin sheet contains a hardly soluble resin, soluble particles, a curing agent, and other components. Each will be described below.
[0029]
The thermosetting resin sheet used in the production method of the present invention is such that particles soluble in an acid or an oxidant (hereinafter referred to as soluble particles) are hardly soluble in an acid or oxidant (hereinafter referred to as a poorly soluble resin). It is distributed.
As used herein, the terms “poorly soluble” and “soluble” refer to those having a relatively fast dissolution rate as “soluble” for convenience when immersed in a solution of the same acid or oxidizing agent for the same time. A relatively slow dissolution rate is referred to as “slightly soluble” for convenience.
[0030]
Examples of the soluble particles include resin particles soluble in an acid or an oxidizing agent (hereinafter, soluble resin particles), inorganic particles soluble in an acid or an oxidizing agent (hereinafter, soluble inorganic particles), and a metal soluble in an acid or an oxidizing agent. Examples thereof include particles (hereinafter, soluble metal particles). These soluble particles may be used alone or in combination of two or more.
[0031]
The shape of the soluble particles is not particularly limited, and examples thereof include spherical shapes and crushed shapes. Moreover, it is desirable that the soluble particles have a uniform shape. This is because a roughened surface having unevenness with uniform roughness can be formed.
[0032]
The average particle size of the soluble particles is preferably 0.1 to 10 μm. If it is the range of this particle size, you may contain the thing of a 2 or more types of different particle size. That is, it contains soluble particles having an average particle diameter of 0.1 to 0.5 μm and soluble particles having an average particle diameter of 1 to 3 μm. Thereby, a more complicated roughened surface can be formed and it is excellent also in adhesiveness with a conductor circuit. In the present invention, the particle size of the soluble particles is the length of the longest part of the soluble particles.
[0033]
Examples of the soluble resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like, as long as the dissolution rate is higher than that of the hardly soluble resin when immersed in a solution made of an acid or an oxidizing agent. There is no particular limitation.
Specific examples of the soluble resin particles include, for example, an epoxy resin, a phenol resin, a polyimide resin, a polyphenylene resin, a polyolefin resin, a fluorine resin, and the like, and may be composed of one of these resins. And it may consist of a mixture of two or more resins.
[0034]
Moreover, as the soluble resin particles, resin particles made of rubber can be used. Examples of the rubber include polybutadiene rubber, epoxy-modified, urethane-modified, (meth) acrylonitrile-modified various modified polybutadiene rubber, carboxyl group-containing (meth) acrylonitrile-butadiene rubber, and the like. By using these rubbers, the soluble resin particles are easily dissolved in an acid or an oxidizing agent. That is, when soluble resin particles are dissolved using an acid, acids other than strong acids can be dissolved. When soluble resin particles are dissolved using an oxidizing agent, permanganese having a relatively low oxidizing power is used. Even acid salts can be dissolved. Even when chromic acid is used, it can be dissolved at a low concentration. Therefore, no acid or oxidant remains on the resin surface, and as described later, when a catalyst such as palladium chloride is applied after the roughened surface is formed, the catalyst is not applied or the catalyst is oxidized. There is nothing to do.
[0035]
Examples of the soluble inorganic particles include particles composed of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds, and silicon compounds.
[0036]
Examples of the aluminum compound include alumina and aluminum hydroxide. Examples of the calcium compound include calcium carbonate and calcium hydroxide. Examples of the potassium compound include potassium carbonate. Examples of the magnesium compound include magnesia, dolomite, basic magnesium carbonate and the like, and examples of the silicon compound include silica and zeolite. These may be used alone or in combination of two or more.
[0037]
Examples of the soluble metal particles include particles composed of at least one selected from the group consisting of copper, nickel, iron, zinc, lead, gold, silver, aluminum, magnesium, calcium, and silicon. Further, the surface layer of these soluble metal particles may be coated with a resin or the like in order to ensure insulation.
[0038]
When two or more kinds of the soluble particles are used in combination, the combination of the two kinds of soluble particles to be mixed is preferably a combination of resin particles and inorganic particles. Both of them have low electrical conductivity, so that the insulation of the resin film can be ensured, and the thermal expansion can be easily adjusted between the poorly soluble resin, and no crack occurs in the interlayer resin insulation layer made of the resin film. This is because no peeling occurs between the interlayer resin insulation layer and the conductor circuit.
[0039]
The poorly soluble resin is not particularly limited as long as it can maintain the shape of the roughened surface when the roughened surface is formed using an acid or an oxidizing agent in the interlayer resin insulation layer. For example, thermosetting Examples thereof include resins, thermoplastic resins, and composites thereof. Moreover, the photosensitive resin which provided photosensitivity to these resin may be sufficient.
[0040]
Specific examples of the hardly soluble resin include, for example, epoxy resins, phenol resins, phenoxy resins, polyimide resins, polyphenylene resins, polyolefin resins, fluororesins and the like. These resins may be used alone or in combination of two or more.
Furthermore, an epoxy resin having two or more epoxy groups in one molecule is more desirable. Not only can the aforementioned roughened surface be formed, but also has excellent heat resistance, etc., so that stress concentration does not occur in the metal layer even under heat cycle conditions, and peeling of the metal layer is unlikely to occur. Because.
[0041]
Examples of the epoxy resin include cresol novolac type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolac type epoxy resin, alkylphenol novolac type epoxy resin, biphenol F type epoxy resin, naphthalene type epoxy resin, Examples thereof include cyclopentadiene type epoxy resins, epoxidized products of condensates of phenols and aromatic aldehydes having a phenolic hydroxyl group, triglycidyl isocyanurate, and alicyclic epoxy resins. These may be used alone or in combination of two or more. Thereby, it will be excellent in heat resistance.
[0042]
In the resin film used in the present invention, it is desirable that the soluble particles are dispersed almost uniformly in the hardly soluble resin. A roughened surface having unevenness of uniform roughness can be formed, and even if a via or a through hole is formed in a resin film, adhesion of a metal layer of a conductor circuit formed thereon can be secured. Because. Moreover, you may use the resin film containing a soluble particle only in the surface layer part which forms a roughening surface. As a result, since the portion other than the surface layer portion of the resin film is not exposed to the acid or the oxidizing agent, the insulation between the conductor circuits via the interlayer resin insulation layer is reliably maintained.
[0043]
In the resin film, the blending amount of the soluble particles dispersed in the hardly soluble resin is preferably 3 to 40% by weight with respect to the resin film. When the blending amount of the soluble particles is less than 3% by weight, a roughened surface having desired irregularities may not be formed. When the blending amount exceeds 40% by weight, the soluble particles are dissolved using an acid or an oxidizing agent. In addition, the resin film is melted to the deep part of the resin film, and the insulation between the conductor circuits through the interlayer resin insulating layer made of the resin film cannot be maintained, which may cause a short circuit.
[0044]
The resin film preferably contains a curing agent, other components and the like in addition to the soluble particles and the hardly soluble resin.
Examples of the curing agent include imidazole curing agents, amine curing agents, guanidine curing agents, epoxy adducts of these curing agents, microcapsules of these curing agents, triphenylphosphine, and tetraphenylphosphorus. And organic phosphine compounds such as nium tetraphenylborate.
[0045]
The content of the curing agent is desirably 0.05 to 10% by weight with respect to the resin film. If it is less than 0.05% by weight, since the resin film is not sufficiently cured, the degree of penetration of the acid and the oxidant into the resin film increases, and the insulating properties of the resin film may be impaired. On the other hand, if it exceeds 10% by weight, an excessive curing agent component may denature the composition of the resin, which may lead to a decrease in reliability.
[0046]
Examples of the other components include fillers such as inorganic compounds or resins that do not affect the formation of the roughened surface. Examples of the inorganic compound include silica, alumina, and dolomite. Examples of the resin include polyimide resin, polyacrylic resin, polyamideimide resin, polyphenylene resin, melanin resin, and olefin resin. By containing these fillers, it is possible to improve the performance of the printed wiring board by matching the thermal expansion coefficient, improving heat resistance, and chemical resistance.
[0047]
Moreover, the said resin film may contain the solvent. Examples of the solvent include ketones such as acetone, methyl ethyl ketone, and cyclohexanone, and aromatic hydrocarbons such as ethyl acetate, butyl acetate, cellosolve acetate, toluene, and xylene. These may be used alone or in combination of two or more.
[0048]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
First, the configuration of the printed wiring board according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 11 shows a cross section of the package substrate 10, and FIG. 12 shows an enlarged part of FIG. 11 shows a state in which the IC chip 90 is mounted and attached to the daughter board 95 side.
[0049]
The package substrate 10 includes a chip capacitor 20, a laminated core substrate 30 that accommodates the chip capacitor 20, and interlayer resin insulating layers 144 and 244 constituting the build-up layers 80A and 80B. The laminated core substrate 30 includes a first core substrate 11 in which a through hole 11A for accommodating the capacitor 20 is formed, a second core substrate 12U laminated on the upper layer of the first core substrate 11 via a resin layer 13U, It comprises a third core substrate 12D laminated on the lower layer of the first core substrate 11 via a resin layer 13D. Via holes 60 and conductor circuits 58 connected to the electrodes 21 and 22 of the capacitor 20 are formed in the second core substrate 12U and the third core substrate 12D. The laminated core substrate 30 is formed with a through hole 36 that connects the built-up layer 80A and the built-up layer 80B. Via holes 160 and conductor circuits 158 are formed in the interlayer resin insulation layer 144 constituting the buildup layers 80A and 80B, and via holes 260 and conductor circuits 258 are formed in the interlayer resin insulation layer 244.
[0050]
A solder resist layer 70 is disposed above the interlayer resin insulation layer 244, and solder bumps 76 U are formed in the upper via hole 260 and the conductor circuit 258 through the opening 71 formed in the solder resist layer 70. The solder bumps 76U are connected to the pads 92 of the IC chip 90. On the other hand, a BGA 76D is formed in the lower via hole 260 and the conductor circuit 258, and is connected to the pad 96 of the daughter board 95 by the BGA 76D.
[0051]
As shown in FIG. 13A, the chip capacitor 20 includes a first electrode 21, a second electrode 22, and a dielectric 23 sandwiched between the first and second electrodes. A plurality of first conductive films 24 connected to the first electrode 21 side and a plurality of second conductive films 25 connected to the second electrode 22 side are arranged to face each other. The surface of the first electrode 21 and the second electrode is covered with a conductive paste 26.
[0052]
Here, the first electrode 21 and the second electrode 22 are made of Ni, Pb, or Ag metallization. The conductive paste 26 is made of a paste containing metal particles such as Cu, Ni, or Ag. Here, the particle diameter of the metal particles is preferably 0.1 to 10 μm, and particularly preferably 1 to 5 μm. The thickness of the conductive paste 26 is desirably 1 to 30 μm. If the thickness is less than 1 μm, unevenness on the electrode surface cannot be eliminated. On the other hand, if the thickness exceeds 30 μm, the effect is not particularly improved. Here, a thickness of 5 to 20 μm is most desirable. It is also possible to use a paste in which two or more types of particles having different diameters are blended, and to coat two or more types of different metal pastes.
[0053]
The electrodes 21 and 22 of the chip capacitor are made of metallization and have irregularities on the surface. For this reason, if the metal layer is used in a state where the metal layer is exposed, the resin may remain on the unevenness in the step of forming the opening 34 with a laser in the second core substrate 12U and the third core substrate 12D. At this time, a poor connection between the first and second electrodes 21 and 22 and the via hole 60 occurs due to the resin residue. In the present embodiment, the surface of the first and second electrodes 21 and 22 is smoothed by the conductive paste 26, and when the opening 34 covered on the electrode is drilled, no resin residue remains, and the via hole The connection reliability with the electrodes 21 and 22 when forming 60 can be improved.
[0054]
Further, a roughened layer is provided on the surface of the dielectric 23 made of ceramic of the chip capacitor 20. Therefore, the adhesion between the ceramic chip capacitor 20 and the resin adhesive 15 and the resin filler 14 is high, and the adhesive 15 and the resin filler 14 are peeled off at the interface even when the heat cycle test is performed. It does not occur. This roughened layer can be formed by polishing the surface of the chip capacitor 20 after firing, or by performing a roughening treatment before firing. In the first embodiment, the surface of the capacitor is roughened to improve the adhesion to the resin. Alternatively, a silane coupling treatment can be applied to the surface of the capacitor. Further, by forming a preimide film in advance, the surface wettability and the adhesion with the resin can be enhanced.
[0055]
On the other hand, as shown in FIG. 13B, it is also preferable to form a composite film 28 including an electroless plating film 28 a and an electrolytic plating film 28 b on the conductive paste 26. The thickness of the composite film 28 is desirably 0.1 to 10 μm, and optimally 1 to 5 μm. By forming the composite film 28, the surfaces of the first and second electrodes 21 and 22 are completely smooth, and when the opening 34 covered on the electrode is drilled, no resin residue remains, and a via hole is formed. The connection reliability with the electrodes 21 and 22 when forming 60 can be improved. Furthermore, since the via hole 60 is formed by copper plating on the electrodes 21 and 22 on which the copper composite film 28 is formed, the connectivity between the electrodes 21 and 22 and the via hole 60 is high, and a heat cycle test is performed. However, no disconnection occurs between the electrodes 21 and 22 and the via hole 60. It is also possible to form a single metal film instead of the composite film.
[0056]
In the package substrate 10 of this embodiment, since the chip capacitor 20 is disposed directly under the IC chip 90, the distance between the IC chip and the capacitor is shortened, and power can be instantaneously supplied to the IC chip side. . That is, the loop length that determines the loop inductance can be shortened.
[0057]
Further, a through hole 36 is provided between the chip capacitor 20 and the chip capacitor 20 so that the signal line does not pass through the chip capacitor 20. For this reason, it is possible to prevent reflection due to impedance discontinuity due to the high dielectric material generated when the capacitor is passed and propagation delay due to passage through the high dielectric material.
[0058]
An external substrate (daughter board) 94 connected to the back side of the printed wiring board and the first electrode 21 and the second electrode 22 of the capacitor 20 are via holes 60 provided in the second core substrate 12U on the IC chip side. And via holes 60 provided in the third core substrate 12D on the daughter board side. That is, since the terminals 21 and 22 of the capacitor 20 are directly connected to the IC chip 90 and the daughter board 95, the wiring length can be shortened.
[0059]
Next, a method for manufacturing the printed wiring board described above with reference to FIG. 11 will be described with reference to FIGS.
(1) First, a copper laminated substrate (second core substrate) 12U formed by laminating a 12 μm copper foil 31 on one side of a base material made of 0.06 mm thick BT (bismaleimide-triazine) or glass epoxy. Let it be a starting material (FIG. 1 (A)). Note that a base material impregnated with a reinforcing material such as FR4, FR5, or a glass epoxy resin can be used. In addition to this, a resin material having a low CTE may be used in order to match the coefficient of thermal expansion. In order to lower CTE, the resin may contain inorganic particles such as silica and alumina.
[0060]
(2) Etching is performed on the copper foil 31, and an opening 31a for forming a conformal mask is formed in a process described later. Thereafter, a thermosetting adhesive 15 such as epoxy for fixing the chip capacitor is applied to a predetermined position (FIG. 1B). The thermosetting adhesive 15 desirably has a smaller coefficient of thermal expansion than the core substrate.
[0061]
(3) The chip capacitor 20 described above with reference to FIG. 13A is attached to the thermosetting adhesive 15 and heated to cure the thermosetting adhesive 15 (FIG. 1C).
[0062]
(4) The first core substrate 11 in which the through-hole 11A for accommodating the chip capacitor 20 is formed, and the third core substrate 12D in which the opening 31a is formed in the copper foil 31 similarly to the second core substrate 12U. Are laminated through the prepregs 13U and 13D in which the openings 13A are formed (FIG. 2A). The first core substrate 11 is made of the same material as the second core substrate 12U and has a thickness of 0.4 mm. The third core substrate is formed in the same manner as the second core substrate 12U. The prepregs 13U and 13D are formed to have a thickness of 0.1 mm by impregnating a core material such as glass cloth with an epoxy resin. However, the prepreg contains a reinforcing material such as BT, phenol resin, or glass cloth in addition to epoxy. What is generally used with a printed wiring board can be used. A resin substrate that does not have a core material such as glass cloth can also be used. The core substrate could not be a ceramic or AIN substrate. This is because the substrate has poor external formability and cannot accommodate a capacitor, and even if it is filled with resin, voids are generated.
[0063]
(5) Resin filler that exudes from the prepregs 13U and 13D by pressing the laminated second core substrate 12U, first core substrate 11 and third core substrate 12D from both sides with stainless steel press plates 100A and 100B. Epoxy) 141Core substrate 1111A and the openings 13A of the prepregs 13U and 13D are filled. This pressurization is preferably performed under reduced pressure in order to prevent generation of bubbles in the core substrate. Thereafter, the laminated core substrate 30 that accommodates the chip capacitor 20 is completed by heating and curing (FIG. 2B).
[0064]
(6) A through-hole 33 serving as a through hole is drilled at a predetermined position of the laminated core substrate 30 (FIG. 2C).
[0065]
(7) Via holes reaching the first and second electrodes 21 and 22 of the chip capacitor 20 using the openings 31a formed in the copper foil 31 by a CO2 laser, YAG laser, excimer laser, or UV laser as a conformal mask. The opening 34 is drilled (FIG. 3A). When the opening 34 is formed, the conductive paste 26 is applied to the surfaces of the first and second electrodes 21 and 22 and the surfaces are smoothed as described above, so that the first and second electrodes 21 and 22 are formed. Resin residue does not remain on the surface.
[0066]
(8) The metal film 16 is formed in the surface layer of the laminated core substrate 30, the via hole non-through hole (opening) 34, and the through hole through hole 33 (FIG. 3B). For this purpose, a palladium catalyst is applied to the surface of the connection layer 40, and then the laminated core substrate 30 is immersed in the electroless plating solution to deposit the electroless copper plating film 16 uniformly. Although electroless plating is used here, a metal layer such as copper or nickel can be formed by sputtering. Sputtering is disadvantageous in terms of cost, but has an advantage that adhesion with the resin layer can be improved. In some cases, the electroless plating film may be formed after the sputtering. This is because, depending on the resin, it is effective for the case where the application of the catalyst is not stable, and the deposition with electroless plating is more stable when formed with an electroless plating film. The metal film 16 is desirably formed in a range of 0.1 to 3 mm. As described above, since resin does not remain on the surfaces of the first and second electrodes 21 and 22 of the chip capacitor 20, an appropriate connection is established to the first and second electrodes 21 and 22 by the electroless plating film 16. Can do.
[0067]
(9) Thereafter, a photosensitive dry film is attached to the surface of the metal film 16, a mask is placed, and exposure / development processing is performed to form a plating resist 17 having a predetermined pattern (FIG. 3C).
[0068]
(10) Then, the laminated core substrate 30 is immersed in the electrolytic plating solution, and an electric current is passed through the electroless plating film 16 to deposit the electrolytic copper plating film 18 (FIG. 4A).
[0069]
(11) After peeling the plating resist 17 with 5% KOH, the electroless plating film 16 and the copper foil 31 under the resist 17 are removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide, and the via hole 60, conductor circuit 58 and the through hole 36 are formed (FIG. 4B).
[0070]
(12) A roughening layer 58α, a roughening layer 60α, and a roughening layer 36α are provided on the surfaces of the conductor layers of the conductor circuit 58, the via hole 60, and the through hole 36. The roughening layer is applied by an oxidation (blackening) -reduction treatment, an electroless plating film such as an alloy made of Cu-Ni-P, or an etching treatment such as an etching solution made of a cupric complex and an organic acid salt. The roughened layer has Ra (average roughness height) = 0.01 to 5 μm. Particularly desirable is a range of 0.5 to 3 μm. Although the roughened layer is formed here, it is also possible to directly fill the resin and attach the resin film as described later without forming the roughened layer.
[0071]
(13) A resin filler having the following composition is prepared.
[Thermosetting resin (1)]
100 parts by weight of bisphenol F type epoxy monomer (manufactured by Yuka Shell, molecular weight 310, YL983U).
[Curing agent (2)]
6.5 parts by weight of imidazole curing agent (Shikoku Chemicals, 2E4MZ-CN).
[Inorganic particles (3)]
Silica (manufactured by Admatech, CRS 1101-CE, where the silica used is SiO with an average particle size of 1.6 μm and coated with a silane coupling agent on the surface)₂ The size of the spherical particles and the maximum particles is 170 parts by weight or less (thickness of 15 μm or less of the inner layer copper pattern described later). In 1st Embodiment, the inorganic particle added to a resin filler is 10-80 vol% as mentioned above, and is 50 vol% here.
By stirring and mixing 1.5 parts by weight of a leveling agent (manufactured by Sannopco, Perenol S4) to the bisphenol F type epoxy monomer, imidazole curing agent and silica, the viscosity of the mixture is 5-30 Pa. At 23 ± 1 ° C. Adjust to S. In the first embodiment, the viscosity is 5 Pa. What was adjusted to S is used.
[0072]
(14) The adjusted resin filler 37 is filled into the surface of the laminated core substrate 30 and the inside of the through hole 36 by printing (FIG. 5A). By filling the through hole 36 with the resin filler 39 adjusted in A above, the occurrence of cracks is prevented and the electrical connectivity and reliability are improved. Here, based on a conventional filler (thermosetting resin, thermoplastic resin, or resin composite thereof), an organic resin filler, an inorganic filler, a metal filler, etc. are blended to form a core substrate and an inner layer filler. Thermal expansion matching may be performed. At this time, the blending amount of the filler is desirably 10 to 80 vol%. The resin filler was semi-cured at 80 ° C. for 30 minutes. The reason for semi-curing is to facilitate polishing.
[0073]
(15) The surface of the conductor circuit 58 or the surface of the land 36a of the through hole 36 is obtained by subjecting one surface of the laminated core substrate 30 having undergone the processing of (13) above to belt sander polishing using belt polishing paper (manufactured by Sankyo Rikagaku) Polishing is performed so that the resin filler 39 does not remain. Next, buffing is performed to remove scratches caused by the belt sander polishing. This process is similarly performed on the other surface of the substrate. Then, the filled resin filler 37 is cured by heating (FIG. 5B). In the present embodiment, the second core substrate 12U and the third core substrate 12D are disposed on the surface of the laminated core substrate 30, which is robust, and the surface can be polished and smoothed. As a result, no undulation occurs in the interlayer resin insulation layer 144 formed in the process described later, and the conductor circuit 158 and the via hole 160 can be formed with high reliability.
[0074]
(16) Next, on both surfaces of the laminated core substrate 30 that has undergone the processing of (15) above, the surface of the lower conductor circuit 58 that has been flattened in the same manner as in (4) above, and the surface of the land 36a of the through hole 36 Are etched to form a roughened surface 58β and a roughened surface 38β on the surface of the lower conductor circuit 58 and the surface of the land 36a of the through hole 36 (FIG. 5C). Some etchants consist of a first cupric complex and an organic acid salt. The roughened surface can also be formed using electroless plating or oxidation-reduction treatment.
[0075]
(17) A pressure of 5 kg / cm while raising the temperature of a thermosetting resin sheet containing a soluble filler having a thickness of 50 μm to a temperature of 50 to 150 ° C. on both surfaces of the laminated core substrate 30 after the step (16).²Then, an interlayer resin insulation layer 144 is provided by vacuum compression lamination (FIG. 6A). The interlayer resin insulation layer may be a thermosetting resin, a resin made of a thermoplastic resin, or a resin in which a photosensitive group is substituted. Specific examples include resins used for printed wiring boards such as epoxy resins, polyphenol resins, and polyimide resins. Further, a resin having a low dielectric constant in the high frequency region may be used. The degree of vacuum during vacuum bonding of the resin is 10 mmHg. In addition, although the resin film was affixed here and the interlayer insulation layer was formed, you may form an interlayer insulation layer by apply | coating resin using a printing machine.
[0076]
(18) Next, the mask 45 in which the opening 45a is formed is placed on the interlayer resin insulating layer 144, and the opening 146 to be a via hole is formed (FIG. 6B). Here, carbonic acid (CO₂) A via hole opening 46 having a diameter of 80 μm is provided in the interlayer resin insulating layer 144 by a gas laser under the conditions of a beam diameter of 5 mm, a pulse width of 15 μsec, a mask hole diameter of 0.8 mm, and one shot.
[0077]
(19) Next, a roughened surface 144α of the interlayer resin insulation layer 144 is provided by dipping in an oxidizing agent such as chromic acid or permanganate (see FIG. 6C). The roughened surface 144α is preferably formed in the range of 0.1 to 5 μm. As an example, a roughened surface 144α of 2 to 3 μm is provided by dipping in a sodium permanganate solution 50 g / l at a temperature of 60 ° C. for 5 to 25 minutes. In addition to the above, plasma treatment is performed on the interlayer resin insulation layer 144 to roughen the surface layer of the interlayer resin insulation layer 144 to form a roughened surface 144α. In this case, argon gas is used as an inert gas, and plasma treatment is performed for 2 minutes under the conditions of power 200 W, gas pressure 0.6 Pa, temperature 70 ° C. (SV-4540, manufactured by Japan Vacuum Technology Co., Ltd.). To do.
[0078]
(20) A metal layer 52 that targets an alloy of Cu (or Ni, P, Pd, Co, W) by sputtering is formed on the surface layer of the interlayer resin insulating layer 144 (FIG. 7A). As the formation conditions, the pressure is 0.6 Pa, the temperature is 80 ° C., the power is 200 W, and the time is 5 minutes (plasma apparatus, Nippon Vacuum Technology Co., Ltd. SV-4540). Thereby, an alloy layer can be formed on the surface layer of the interlayer resin insulation layer 144. The thickness of the metal layer 52 at this time is 0.2 μm. The thickness of the metal layer 52 is preferably 0.1 to 2 μm. Other than sputtering, the plating layer may be formed without performing vapor deposition or sputtering. Or these composite_body | complexes may be sufficient.
[0079]
An example of plating will be described. The laminated core substrate 30 is conditioned and the catalyst is applied in an alkaline catalyst solution for 5 minutes. The laminated core substrate 30 is activated, and an electroless plating film 52 having a thickness of 0.6 μm is attached using a Rochelle salt type chemical copper plating bath.
Plating conditions for chemical copper plating:
CuSO_Four・ 5H₂O 10g / l
HCHO 8g / l
NaOH 5g / l
Rochelle salt 45g / l
Additive 30ml / l
Temperature 30 ℃
Plating time 18 minutes
[0080]
(21) A photosensitive film (dry film) having a thickness of 25 μm is pasted on the metal film 52, and a mask is placed thereon.², And developed with 0.8% sodium carbonate to provide a plating resist 54. Next, electrolytic plating is performed on the non-formation portion of the plating resist 54 on the electroless plating film 52 under the following conditions to form the electrolytic plating film 56 (FIG. 7B). The thickness of the electrolytic plating film 56 is preferably 5 to 20 μm.
[0081]
(Electrolytic plating aqueous solution)
Sulfuric acid 2.24 mol / l
Copper sulfate 0.26 mol / l
Additive 19.5 ml / l
[Electrolytic plating conditions]
Current density 1 A / dm²
65 minutes
Temperature 22 ± 2 ° C
[0082]
(22) Next, the plating resist 54 is peeled and removed in a NaOH solution of 50 g and 40 g / l. Thereafter, the electroless plating film 52 under the plating resist 54 is removed by etching using an aqueous sulfuric acid-hydrogen peroxide solution, and a conductor circuit 158 (including the via hole 160) is formed on the interlayer resin insulating layer 144. Thereafter, the surface of the conductor circuit 158 and the via hole 160 is subjected to a roughening process (FIG. 8A).
[0083]
(23) The steps (17) to (22) are repeated to form an interlayer resin insulation layer 244 including the via hole 260 and the conductor circuit 258 on the interlayer resin insulation layer 144 (FIG. 9A).
[0084]
(24) On the other hand, 46.67g of photosensitizing oligomer (molecular weight 4000) obtained by acrylating 50% of the epoxy group of 60 wt% cresol novolak type epoxy resin (manufactured by Nippon Kayaku) dissolved in DMDG, dissolved in methyl ethyl ketone. 15.0 g of bisphenol A type epoxy resin (produced by Yuka Shell, Epicoat 1001), 16 g of imidazole curing agent (product name: 2E4MZ-CN), polyacrylic monomer (photosensitive monomer) Nippon Kayaku Co., Ltd., R604) 3 g, also polyacrylic monomer (Kyoeisha Chemical Co., DPE6A) 1.5 g, and dispersion antifoaming agent (San Nopco, S-65) 0.71 g are mixed. 2 g of benzophenone (manufactured by Kanto Chemical) as a photoinitiator and 0.2 g of Michler ketone (manufactured by Kanto Chemical) as a photosensitizer are added, and the viscosity is 2.0 Pa · s at 25 ° C. A solder resist composition adjusted to 1 is obtained.
Viscosity is measured with a B-type viscometer (Tokyo Keiki, DVL-B type) at 60 rpm with rotor No. 4 and at 6 rpm with rotor No. 3.
[0085]
(25) The solder resist composition is applied to both sides of the package substrate obtained in the above (24) with a thickness of 20 μm. Next, after drying at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, a photomask film having a thickness of 5 mm on which a circular pattern (mask pattern) was drawn was placed in close contact, and 1000 mJ / cm²Expose with UV and develop DMTG. Further, heat treatment is performed at 80 ° C. for 1 hour, 100 ° C. for 1 hour, 120 ° C. for 1 hour, and 150 ° C. for 3 hours, and an opening 71 is formed in the solder pad portion (including the via hole and its land portion). A solder resist layer 70 having a thickness of 20 μm is formed (FIG. 9B). A solder pad for forming a solder bump for IC chip connection is preferably opened with an opening diameter of 100 to 170 μm. In addition, it is preferable that the solder pad on which the BGA / PGA is disposed for connecting the external terminal is opened with an opening diameter of 300 to 650 μm.
[0086]
(26) Then, nickel chloride 2.3 × 10^-1mol / l, sodium hypophosphite 2.8 × 10^-1mol / l, sodium citrate 1.6 × 10^-1A nickel plating layer 72 having a thickness of 5 μm is formed in the opening 71 by immersing in an electroless nickel plating solution of mol / l and pH = 4.5 for 20 minutes. After that, on the surface layer, potassium gold cyanide 7.6 × 10^-3mol / l, ammonium chloride 1.9 × 10^-1mol / l, sodium citrate 1.2 × 10^-1mol / l, sodium hypophosphite 1.7 × 10^-1A gold plating layer 74 having a thickness of 0.03 μm is formed on the nickel plating layer 72 by dipping in an electroless gold plating solution of mol / l for 7.5 minutes at 80 ° C. (FIG. 10A).
[0087]
(27) Then, a low melting point metal paste made of Sn / Ag (Sn / Ag / Cu or Sn / Sb) is filled into the opening 71 of the solder resist layer 70. Since this low melting point metal uses an alloy that does not contain Pb, it does not adversely affect the environment. The solder bumps 76U and BGA 76D are formed by reflowing the low melting point metal paste (FIG. 10B).
[0088]
The IC chip 90 is mounted by placing it on the solder bumps 76U of the completed package substrate 10 so that the pads 92 of the IC chip 90 correspond to the solder bumps 76U. The package substrate 10 on which the IC chip 90 is mounted is placed so as to correspond to the pads 96 on the daughter board 95 side, reflowed, and attached to the daughter board 95 (see FIG. 11). Here, the BGA 76D is formed on the connection side with the daughter board, but it is also possible to arrange solder bumps instead.
[0089]
Next, a printed wiring board according to a modification of the first embodiment of the present invention will be described with reference to FIG. The modified printed wiring board is substantially the same as that of the first embodiment described above. However, in the printed wiring board of the second modified example, the conductive pin 97 is provided and is formed so as to be connected to the daughter board via the conductive pin 97.
[0090]
In the first embodiment described above, only the chip capacitor 20 accommodated in the multilayer core substrate 30 is provided. However, in the modified example, large-capacity chip capacitors 86 are mounted on the front surface and the back surface.
[0091]
An IC chip consumes a large amount of power instantaneously and performs complicated arithmetic processing. Here, in order to supply large power to the IC chip side, in this embodiment, the printed circuit board is provided with a chip capacitor 20 for power supply and a chip capacitor 86. The effect of this chip capacitor will be described with reference to FIG.
[0092]
In FIG. 15, the vertical axis indicates the voltage supplied to the IC chip, and the horizontal axis indicates time. Here, an alternate long and two short dashes line C indicates a voltage fluctuation of a printed wiring board that does not include a power supply capacitor. When the power supply capacitor is not provided, the voltage is greatly attenuated. A broken line A indicates voltage fluctuation of a printed wiring board having a chip capacitor mounted on the surface. The voltage does not drop much as compared with the two-dot chain line C, but the loop length becomes long, so the rate-determining power supply cannot be sufficiently performed. That is, the voltage drops at the start of power supply. A two-dot chain line B indicates a voltage drop of the printed wiring board incorporating the chip capacitor described above with reference to FIG. Although the loop length can be shortened, the voltage fluctuates because a large-capacity chip capacitor cannot be accommodated in the laminated core substrate 30. Here, the solid line E indicates the voltage fluctuation of the printed wiring board of the modified example in which the chip capacitor 20 in the core substrate described above with reference to FIG. 14 and the large-capacity chip capacitor 86 are mounted on the surface. By providing the chip capacitor 20 in the vicinity of the IC chip and the chip capacitor 86 having a large capacity (and relatively large inductance), voltage fluctuation is minimized.
[0093]
Subsequently, the configuration of the printed wiring board according to the second embodiment of the present invention will be described with reference to FIGS. 16 and 17.
The configuration of the printed wiring board of the second embodiment is substantially the same as that of the first embodiment described above. However, the chip capacitors accommodated in the laminated core substrate 30 are different. 17A shows a plan view of the chip capacitor 120, and FIG. 17B shows a BB cross section of FIG. 17A. In the first embodiment described above, a plurality of small-capacity chip capacitors are accommodated in the core substrate. In the second embodiment, a large-capacity large-sized chip capacitor 120 is accommodated in the core substrate. Here, the chip capacitor 120 includes a plurality of first electrodes 121 and second electrodes 122, a dielectric 23, a first conductive film 24 connected to the first electrode 121, and a second electrode. The second conductive film 25 connected to the 122 side and the connection electrodes 127 on the upper and lower surfaces of the chip capacitor not connected to the first conductive film 24 and the second conductive film 25. The IC chip side and the daughter board side are connected via the electrode 127. As in the first embodiment, the conductive paste 26 is applied to the surfaces of the electrodes 121, 122, and 127 to smooth the surfaces.
[0094]
In the modified printed wiring board, since the large chip capacitor 20 is used, a chip capacitor having a large capacity can be used. Further, since the large chip capacitor 20 is used, the printed wiring board is not warped even when the heat cycle is repeated. Furthermore, since it is possible to route wiring from multiple electrodes, increasing the number of power lines and ground lines can reduce the inductance of the power lines and ground lines, thereby improving high frequency performance. It becomes possible. Further, the capacitor electrode 127 can be used as a through hole. In the second embodiment as well, it is preferable to mount a large-capacity capacitor on the surface as in the modification of the first embodiment.
[0095]
In the printed wiring boards of the first and second embodiments, the chip capacitor 20 is completely stripped of the coating layers (not shown) of the first and second electrodes 21 and 22 as shown in FIG. Thereafter, it can be covered with a copper plating film 29. The first and second electrodes 21 and 22 covered with the copper plating film 29 are electrically connected by via holes 60 made of copper plating. Here, the electrodes 21 and 22 of the chip capacitor are made of metallization and have irregularities on the surface. For this reason, if the metal layer is used in a state where the metal layer is exposed, the resin may remain on the unevenness in the step of forming the opening 34 with a laser in the second core substrate 12U and the third core substrate 12D. At this time, a poor connection between the first and second electrodes 21 and 22 and the via hole 60 occurs due to the resin residue. On the other hand, by covering with the copper plating film 29, the surfaces of the first and second electrodes 21 and 22 become smooth, and the openings 34 are formed in the second core substrate 12U and the third core substrate 12D with a laser. In this case, no resin residue remains and the connection reliability with the electrodes 21 and 22 when the via hole 60 is formed can be improved.
[0096]
Furthermore, since the via hole 60 is formed by plating on the electrodes 21 and 22 on which the copper plating film 29 is formed, the connectivity between the electrodes 21 and 22 and the via hole 60 is high, and even if a heat cycle test is performed, No disconnection occurs between the electrodes 21 and 22 and the via hole 60. There was no migration and no inconvenience at the capacitor via-hole connection.
[0097]
The copper plating film 29 is provided after the nickel / tin layer (coating layer) coated on the surface of the metal layer 26 at the manufacturing stage of the chip capacitor is peeled off at the stage of mounting on the printed wiring board. Alternatively, the copper plating film 29 can be directly coated on the metal layer 26 at the manufacturing stage of the chip capacitor 20. That is, in the second embodiment, as in the first embodiment, after providing an opening to the copper plating film 29 of the electrode with a laser, a desmear process or the like is performed, and the via hole is formed by copper plating. Therefore, even if an oxide film is formed on the surface of the copper plating film 29, the oxide film can be removed by the laser and desmear treatment, so that a proper connection can be established.
[0098]
Further, as shown in FIG. 18B, the first electrode 21 and the second electrode 22 made of metallization of the chip capacitor 20 are exposed and accommodated in the printed wiring board, and the exposed first electrode 21 and second electrode 22 are exposed. An electrical connection can also be made. At this time, it is desirable that the first electrode 21 and the second electrode 22 are mainly composed of Cu. This is because the connection resistance can be reduced.
[0099]
Here, with respect to the printed wiring board of the first embodiment, values obtained by measuring the inductance of the chip capacitor 20 embedded in the core substrate and the inductance of the chip capacitor mounted on the back surface (surface on the daughter board side) of the printed wiring board are as follows. Show.
In the case of a single capacitor
Embedded type 137pH
Back mounting type 287pH
When 8 capacitors are connected in parallel
Embedded type 60pH
Back mounting type 72pH
As described above, even when the capacitor is used alone, the inductance can be reduced by incorporating the chip capacitor even when they are connected in parallel to increase the capacitance.
[0100]
Next, the results of the reliability test will be described. Here, in the printed wiring board of the first embodiment, the change rate of the capacitance of one chip capacitor was measured.

[0101]
The steam test was kept at 100% humidity by exposure to steam. In the HAST test, the sample was left for 100 hours at a relative humidity of 100%, an applied voltage of 1.3 V, and a temperature of 121 ° C. In the TS test, a test that was allowed to stand at -125 ° C for 30 minutes and at 55 ° C for 30 minutes was repeated 1000 lines.
[0102]
In the above reliability test, it was found that a printed wiring board with a built-in chip capacitor can achieve the same reliability as the existing capacitor surface mount type. Further, as described above, in the TS test, even if internal stress occurs due to the difference in thermal expansion coefficient between the ceramic capacitor and the resin core substrate and the interlayer resin insulation layer, the chip capacitor terminals and via holes It was proved that high reliability can be achieved over a long period of time without disconnection, peeling between the chip capacitor and the interlayer resin insulation layer, and no crack in the interlayer resin insulation layer.
[0103]
【The invention's effect】
In the present invention, since the capacitor is disposed in the printed wiring board as described above, the distance between the IC chip and the capacitor is shortened, and the loop inductance can be reduced. In addition, the core substrate is formed by laminating the second and third core substrates on the top and bottom of the first core substrate that accommodates the capacitor. Therefore, the core substrate is robust and accommodates a capacitor made of ceramic and having a low coefficient of thermal expansion. However, stress due to the difference in thermal expansion coefficient between the capacitor and the core substrate is applied to the interlayer resin insulation layer, and the conductor circuit is not cracked, and a printed wiring board having high reliability can be realized. Moreover, since the surface of the core substrate can be polished and flattened, no undulation occurs in the interlayer resin insulation layer on the core substrate, and a via hole and a conductor circuit can be appropriately formed on the interlayer resin insulation layer.
[0104]
Since it is possible to connect from the lower part of the capacitor, it can be said that the distance of the loop inductance is shortened and the degree of freedom of arrangement is increased.
In addition, since the resin is filled between the core substrate and the capacitor, even if a stress caused by the capacitor or the like is generated, the stress is alleviated and no migration occurs. Therefore, there is no influence of peeling or dissolution on the connection portion between the capacitor electrode and the via hole.
Therefore, the desired performance can be maintained even if the reliability test is performed.
Also, migration can be prevented when the capacitor is covered with copper.
[Brief description of the drawings]
FIG. 1 is a manufacturing process diagram of a printed wiring board according to a first embodiment of the present invention.
FIG. 2 is a manufacturing process diagram of the printed wiring board according to the first embodiment of the present invention.
FIG. 3 is a manufacturing process diagram of the printed wiring board according to the first embodiment of the present invention.
FIG. 4 is a manufacturing process diagram of the printed wiring board according to the first embodiment of the present invention.
FIG. 5 is a manufacturing process diagram of the printed wiring board according to the first embodiment of the present invention.
FIG. 6 is a manufacturing process diagram of the printed wiring board according to the first embodiment of the present invention.
FIG. 7 is a manufacturing process diagram of the printed wiring board according to the first embodiment of the present invention.
FIG. 8 is a manufacturing process diagram of the printed wiring board according to the first embodiment of the present invention.
FIG. 9 is a manufacturing process diagram of the printed wiring board according to the first embodiment of the present invention.
FIG. 10 is a manufacturing process diagram of the printed wiring board according to the first embodiment of the present invention.
FIG. 11 is a cross-sectional view of the printed wiring board according to the first embodiment.
12 is an enlarged cross-sectional view of the printed wiring board of FIG.
13A and 13B are cross-sectional views of the chip capacitor accommodated in the printed wiring board according to the first embodiment.
FIG. 14 is a cross-sectional view of a printed wiring board according to a modification of the first embodiment.
FIG. 15 is a graph showing changes in supply voltage to IC chip and time.
FIG. 16 is a cross-sectional view of a printed wiring board according to a second embodiment.
17A is a cross-sectional view of a chip capacitor housed in a printed wiring board according to the second embodiment, and FIG. 17B is a plan view.
18A and 18B are cross-sectional views of the chip capacitor accommodated in the printed wiring board according to the first embodiment.
FIGS. 19A and 19B are explanatory diagrams of loop inductance of a printed wiring board according to the prior art. FIGS.
[Explanation of symbols]
10 Printed wiring board
11 First core substrate
11A through hole
12A through hole
12U 2nd core board
12D 3rd core substrate
13U prepreg
13D prepreg
14 Resin filler
15 Adhesive
20 chip capacitors
21 First electrode
22 Second electrode
26 Conductive paste
30 laminated core substrate
31 Conductor circuit (conformal mask)
31a opening
36 Through hole
37 Resin filler
58 Conductor circuit
60 Bahia Hall
70 Solder resist
76U solder bump
76D BGA
86 capacitors
90 IC chip
94 Daughter Board
97 Conductive connection pin
144 Interlayer resin insulation layer
158 Conductor circuit
160 Viahole
258 conductor circuit
260 Bahia Hall

Claims (13)

A printed wiring board formed by laminating a resin insulating layer and a conductor circuit on a core substrate that houses a capacitor,
The core substrate is formed by laminating second and third core substrates on the top and bottom of the first core substrate in which a through hole for accommodating the capacitor is formed,
Forming a pair of via holes in the second and third core substrates;
A metal film is formed on the capacitor electrode, and one and the other of the pair of via holes connected to the first and second electrodes of the capacitor, respectively, and the first electrode of the capacitor on which the metal film is formed A printed wiring board, wherein electrical connection is made between the first electrode and the second electrode by plating . It said first, second, third core substrate, printed wiring board according to claim 1, characterized by being impregnated core material. The electrodes of the capacitor, printed wiring board according to claim 1 or claim 2, characterized in that applying a conductive paste.   The printed wiring board according to claim 1, wherein a capacitor is mounted on a surface of the printed wiring board.   5. The printed wiring board according to claim 4, wherein a capacitance of the chip capacitor on the surface is equal to or greater than a capacitance of the inner layer chip capacitor. As the capacitor, printed wiring board according to one of claims 1 to 5, characterized in that using a chip capacitor having electrodes formed in a matrix. The printed wiring board according to claim 6 , wherein the metal film formed on the electrode of the capacitor is a plating film mainly made of copper. Wherein exposing the at least a portion of the coating layer of the capacitor electrodes, according to one of claims 1 to 5, characterized in that it took electrical connection by plating on the exposed electrodes from the covering layer Printed wiring board. The through hole is filled with a resin filler in a state where the capacitor is accommodated,
The third of said via holes formed in the core substrate, a printed wiring board according to one of claims 1-8, characterized in that through said resin filler is connected to the capacitor. The printed wiring board according to claim 9 , wherein the resin filler contains an inorganic filler. A method for producing a printed wiring board comprising at least the following steps (a) to (c):
(A) a step of laminating the second and third core substrates above and below the first core substrate in which the capacitor is accommodated in the through hole with a resin plate impregnated with uncured resin interposed therebetween;
(B) a step of forming openings respectively reaching the first and second electrodes of the capacitor with a laser in the second and third core substrates;
(C) Plating the opening to form via holes that connect to the first and second electrodes of the capacitor, respectively. A method for producing a printed wiring board comprising at least the following steps (a) to (e):
(A) a step of laminating the second and third core substrates above and below the first core substrate in which the capacitor is accommodated in the through hole with a resin plate impregnated with uncured resin interposed therebetween;
(B) A step of forming openings respectively reaching the first and second electrodes of the capacitor with a laser in the second and third core substrates:
(C) plating the opening to form via holes connected to the first and second electrodes of the capacitor;
(D) applying a resin filler to the surfaces of the second and third core substrates;
(E) A step of polishing and smoothing the surfaces of the second and third core substrates. In the step of forming an opening in the laser to the core substrate, the second, according to the third claim 11 or claim 12, characterized by using an opening formed in the conductor circuit of the core board as con follower circle mask Manufacturing method of printed wiring board.

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