JP4648230B2 - Wiring board manufacturing method - Google Patents

Description

  The present invention relates to a method of manufacturing a wiring board incorporating a ceramic chip.

  In recent years, semiconductor integrated circuit elements (IC chips) used for a CPU of a computer have been increased in speed and function, and accordingly, the number of terminals is increased and the pitch between terminals tends to be narrowed. In general, a large number of terminals are densely arranged on the bottom surface of an IC chip, and such a terminal group is connected to a terminal group on the motherboard side in the form of a flip chip. However, it is difficult to connect the IC chip directly on the mother board because there is a large difference in the pitch between the terminals on the IC chip side terminal group and the mother board side terminal group. For this reason, generally, a technique is adopted in which an IC chip is mounted on an IC chip mounting wiring board, and the IC chip mounting wiring board is mounted on a motherboard. As this type of IC chip mounting wiring board, for example, a core part is formed by embedding a ceramic chip in a core material made of a polymer material, and build-up layers are formed on the front and back surfaces of the core part. Conventionally proposed (see, for example, Patent Documents 1 and 2).

The conventional IC chip mounting wiring board is manufactured, for example, by the following procedure. First, a core material made of a polymer material having an accommodation hole portion that opens on both the core surface and the core back surface is prepared. At the same time, a ceramic chip for embedding in which a plurality of terminal electrodes are provided so as to protrude from the chip front surface and the chip back surface is prepared. Next, the taping process which affixes an adhesive tape on the core material back surface side is performed, and the core material back surface side opening of an accommodation hole part is sealed beforehand. And the ceramic chip for embedding is accommodated in an accommodation hole part, and the chip | tip back surface is affixed on the adhesive surface of an adhesive tape, and is temporarily fixed. Next, after the gap between the inner surface of the accommodation hole and the side surface of the embedding ceramic chip is filled with a resin filler, a fixing process is performed in which the gap is cured to fix the embedding ceramic chip to the core material. Thereafter, the build-up layer is formed by alternately forming an interlayer insulating layer mainly composed of a polymer material and a conductor layer on the front surface and the back surface of the core portion made of the core material and the embedded ceramic chip. Form. As a result, a desired IC chip mounting wiring board is obtained.
JP 2001-352141 A JP-A-2005-39243

  By the way, in the conventional manufacturing method, as shown in FIG. 14, in order to fix the embedding ceramic chip 204 to the core material 201, a gap between the inner surface 203 of the accommodation hole 202 and the side surface 205 of the embedding ceramic chip 204 is used. 206 is filled with a resin filler 207. However, since the ceramic chip 204 has thickness variation and warpage, and further, there is an error in the filling amount of the resin filler 207, so that it is flush with the surface of the ceramic chip 204 (so that the height coincides). ) It is difficult to embed the resin filler 207. Further, if the resin filler 207 covers the chip surface due to too much filling amount, problems such as build-up layer floating and delamination occur, and therefore the resin filler 207 is usually filled in a small amount. . Therefore, the height of the resin filler 207 in the gap 206 between the core material 201 (accommodating hole 202) and the ceramic chip 204 is lower than that of the core material 201 and the chip 204, and a recess 209 is formed in that portion. It will be. The influence of the concave portion 209 spreads to the surface of the buildup layer, resulting in a problem that the flatness is lowered and it is difficult to mount the IC chip.

  In addition, an error occurs in the filling amount of the resin filler 207 depending on temperature conditions, clogging of nozzles of the filling device, and the like. And the depth of the recessed part 209 will differ according to the filling amount. The thickness of the resin insulation layer for build-up formation varies depending on the depth of the recess 209 and the thickness of the ceramic chip 204.

  As shown in FIG. 15, for example, when the filling amount of the resin filler 207 is small and the recess 209 is formed deep and the ceramic chip 204 is thick, the resin insulating layer 210 formed on the ceramic chip 204 becomes thin. FIG. 16 shows a comparative example in which there is no recess due to the resin filler 207 and the ceramic chip 204 is equal to the thickness of the core material 201. As shown in FIGS. 15 and 16, when the via hole 211 is formed in the resin insulating layer 210 using a laser processing apparatus, the via hole 211 is formed in accordance with the thickness of the resin insulating layer 210 formed on the chip 204. The shape will be different. Further, when the resin insulating layer 210 on the ceramic chip 204 becomes thin, there arises a problem that chipping occurs at the location of the via hole 211 in the desmear process after the laser processing.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a method of manufacturing a wiring board that can improve the connection reliability with a semiconductor element and has a good product yield.

  And as a means (means 1) for solving the said subject, it has a core 1st main surface and a core 2nd main surface, and the accommodation hole opened in the said core 1st main surface and the said core 2nd main surface A core material preparation step of preparing a core material having a portion, and an embedded ceramic chip preparation step of preparing an embedded ceramic chip having a chip first main surface and a chip second main surface and having an internal conductor formed therein, A masking step in which a masking material is disposed in close contact with the core first main surface side to close the opening of the receiving hole, and the chip first main surface is directed to the same side as the core first main surface. And the ceramic chip for embedding is accommodated in the said accommodation hole part with the said chip 2nd main surface facing the same side as the said core 2nd main surface, In this state, the inner surface of the said accommodation hole part and the said ceramic chip for an embedding | Resin gap between side A fixing step of filling the embedded ceramic chip with the filler, a masking material removing step of removing the masking material after the fixing step, and a step of removing the masking material after the masking material removing step; An insulating layer forming step of forming a core-side insulating layer on one main surface and the chip first main surface; and a via forming step of forming a plurality of via holes and a plurality of via conductors in the core-side insulating layer; A build-up layer having a structure in which an interlayer insulating layer and a conductor layer are alternately stacked on the core-side insulating layer after the via formation step, and a plurality of connection terminals on which a semiconductor element can be surface-mounted on a surface layer portion There is a method for manufacturing a wiring board including a build-up layer forming step to be formed.

  Therefore, according to the manufacturing method of means 1, the resin filler is embedded in the gap between the inner surface of the receiving hole and the side surface of the ceramic chip for embedding in a state where the masking material is in close contact with the first main surface side of the core. The ceramic chip is fixed to the core material. At this time, the positions of the core first main surface, the chip first main surface, and the surface of the resin filler on the side in contact with the masking material are aligned and formed flat. Then, after the masking material is removed, a core-side insulating layer is formed on the core first main surface and the chip first main surface, and a build-up layer is further formed on the core-side insulating layer. That is, not the uneven surface (core second main surface and chip second main surface) due to the filling amount of the resin filler or the thickness of the chip, but the opposite surface (core) with relatively good flatness A buildup layer for mounting a semiconductor element is formed on the first main surface and the chip first main surface) side. In this way, since the unevenness on the surface of the buildup layer can be suppressed, the semiconductor element can be reliably mounted. In addition, since the thickness variation of the core-side insulating layer formed on the core first main surface and the chip first main surface is eliminated, uniform-shaped via holes and via conductors are formed in the core-side insulating layer. Can do. Therefore, the connection reliability with the semiconductor element can be improved, and a wiring board with a good product yield can be provided.

  In the manufacturing method of the above means 1, a cleaning and polishing step is performed after the masking material removing step and before the insulating layer forming step, and then polishing and then polishing the core first main surface and the chip first main surface. Is preferred. After removing the masking material, a part of the masking material (for example, an adhesive material) may remain on the core first main surface and the chip first main surface. This is because the material can be reliably removed.

Further, as another means (means 2) for solving the above-mentioned problem, the core has a first core main surface and a second core main surface, and is opened at the first core main surface and the second core main surface. A core material preparing step of preparing a core material having a receiving hole portion to be embedded, and an embedded ceramic chip for preparing an embedded ceramic chip having a chip first main surface and a chip second main surface and having an internal conductor formed therein A preparatory step, a masking step in which a masking material is disposed in close contact with the core first main surface side to close the opening of the accommodation hole, and the chip first main surface is the same as the core first main surface The ceramic chip for embedding is accommodated in the accommodating hole with the chip second main surface facing the same side as the core second main surface, and in this state, the core second main surface and the chip second film-like insulating resin material on the second main surface At the same time arranged to form a second core side insulating layer by heating under pressure, it fills the gap between the inner surface and the side surface of the embedded ceramic chip of the accommodation hole at a portion of the second core side insulating layer A second core side insulating layer forming step for fixing the embedded ceramic chip to the core material, a masking material removing step for removing the masking material after the second core side insulating layer forming step, and the masking material removing step A first core-side insulating layer forming step of forming a first core-side insulating layer on the core first main surface and the chip first main surface exposed through the first core-side insulating layer; A via forming step of forming via holes and a plurality of via conductors, and a structure in which an interlayer insulating layer and a conductor layer are alternately laminated on the first core side insulating layer after the via forming step; Semiconductor element There are provided methods for producing the wiring board, which comprises a buildup layer formation step of forming a buildup layer having a plurality of connection terminals that can be implemented.

  Therefore, according to the manufacturing method of the means 2, the second core side insulating layer is formed on the core second main surface and the chip second main surface while the masking material is in close contact with the core first main surface side. The embedding ceramic chip is fixed to the core material by filling the gap between the inner surface of the accommodation hole and the side surface of the embedding ceramic chip with a part of the second core side insulating layer. At this time, the positions of the partial surfaces of the core first main surface, the chip first main surface, and the second core-side insulating layer on the side in contact with the masking material are aligned and formed flat. Then, after the masking material is removed, a first core side insulating layer is formed on the core first main surface and the chip first main surface, and a buildup layer is further formed on the first core side insulating layer. Is done. That is, it is not the side with the irregularities due to the thickness of the chip (chip second main surface and core second main surface), but the opposite surface (core first main surface and chip first) with relatively good flatness. A build-up layer for mounting a semiconductor element is formed on the (1 main surface) side. In this case, unevenness on the surface of the buildup layer can be suppressed, and the semiconductor element can be reliably mounted. In addition, since the thickness variation of the core-side insulating layer formed on the core first main surface and the chip first main surface is eliminated, uniform-shaped via holes and via conductors are formed in the core-side insulating layer. Can do. Therefore, the connection reliability with the semiconductor element can be improved, and a wiring board with a good product yield can be provided. Moreover, since it is not necessary to use a resin filler like the wiring board of the means 1, manufacturing cost can be suppressed. Furthermore, the filling process of the resin filler using the filling apparatus can be omitted, and the manufacturing process can be simplified.

  In the manufacturing method of the above means 2, cleaning polishing in which the core first main surface and the chip first main surface are cleaned and then polished after the masking material removing step and before the first core-side insulating layer forming step. It is preferable to perform a process. After removing the masking material, a part of the masking material (for example, an adhesive material) may remain on the core first main surface and the chip first main surface. This is because the material can be reliably removed.

  The core material forms part of the core portion of the wiring board, and is formed in a flat plate shape having, for example, a core first main surface and a core second main surface located on the back side thereof. Such a core material has one or more housing holes for housing the embedding ceramic chip. The accommodation hole is a through hole that opens at the core first main surface and the core second main surface.

  Although the material which forms a core material is not specifically limited, A preferable core material is mainly formed of a polymer material. Specific examples of the polymer material for forming the core material include, for example, EP resin (epoxy resin), PI resin (polyimide resin), BT resin (bismaleimide / triazine resin), PPE resin (polyphenylene ether resin), etc. There is. In addition, composite materials of these resins and glass fibers (glass woven fabric or glass nonwoven fabric) or organic fibers such as polyamide fibers may be used.

  The ceramic chip for embedding is preferably a ceramic sintered body having a chip first main surface and a chip second main surface. As this ceramic sintered body, a sintered body of high-temperature fired ceramic such as alumina, aluminum nitride, boron nitride, silicon carbide, silicon nitride, etc. is preferably used, and also for borosilicate glass and lead borosilicate glass. A sintered body of low-temperature fired ceramic such as glass ceramic to which an inorganic ceramic filler such as alumina is added is preferably used. In this case, it is also preferable to use a sintered body of a dielectric ceramic such as barium titanate, lead titanate, or strontium titanate depending on the application. When a dielectric ceramic sintered body is used, a ceramic capacitor having a large capacitance can be easily realized.

  An internal conductor is formed inside the ceramic chip. The material for forming such an internal conductor is not particularly limited, but it is preferable to use a metal that can be sintered simultaneously with the ceramic, for example, nickel, molybdenum, tungsten, titanium, or the like. When a low-temperature fired ceramic sintered body is selected, copper, silver, or the like can be further used as a material for forming the internal conductor. The internal conductor may be a via conductor extending in the thickness direction of the ceramic sintered body or may be an inner conductor layer extending in the surface direction of the ceramic sintered body.

  Here, the ceramic chip for embedding may be a ceramic capacitor having a structure in which the first internal electrode layers and the second internal electrode layers are alternately stacked via ceramic dielectric layers. When the embedded ceramic chip having a function as a capacitor is used as described above, for example, the stray inductance can be reliably reduced by being disposed in the vicinity of the semiconductor element, so that the semiconductor element is stably operated. It becomes possible.

  The build-up layer constituting the wiring board has a structure in which interlayer insulating layers mainly composed of a polymer material and conductor layers are connected alternately. The build-up layer may be formed only on one side of the core part (that is, only on the core first main surface and the chip first main surface), and on both sides of the core part (that is, the core first main surface and the chip main surface). The first main surface of the chip, the second main surface of the core, and the second main surface of the chip) may be formed. For the build-up layer formed on the core first main surface and the chip first main surface, the semiconductor element mounting portion is set in a region corresponding to the ceramic chip on the surface. Since the semiconductor element can be mounted on such a semiconductor element mounting portion, the difference in thermal expansion coefficient from the semiconductor element can be reduced as compared with the case where the semiconductor element mounting portion is provided in the core material. Therefore, the structure can easily reduce the influence of thermal stress acting on the semiconductor element.

  Hereinafter, a method for manufacturing the wiring board will be described.

  In the core material preparation step, a plate-shaped core material having a core first main surface and a core second main surface and having a receiving hole portion opened in the core first main surface and the core second main surface is conventionally used. Prepared in advance using a known technique.

  Further, in the embedding ceramic chip preparation step, an embedding ceramic chip made of a ceramic sintered body having a chip first main surface and a chip second main surface and having an internal conductor formed in the ceramic sintered body is conventionally obtained. Prepared in advance using a known technique.

  In the subsequent masking step, the masking material is disposed so as to be in close contact with the core first main surface side to close the opening of the accommodation hole. It is preferable to use a peelable adhesive tape as the masking material. However, a masking material that does not have an adhesive layer can also be used if it can be brought into close contact with the core first main surface side.

  Thereafter, in the fixing step, the chip first main surface of the ceramic chip for embedding is directed to the same side as the core first main surface, and the chip second main surface is directed to the same side as the core second main surface to enter the receiving hole. Contains a ceramic chip for embedding. Here, when an adhesive tape is used as the masking material, an embedding ceramic chip is attached to the adhesive surface of the adhesive tape and temporarily fixed. In this state, the gap between the inner surface of the accommodation hole and the side surface of the embedding ceramic chip is filled with a resin filler made of a polymer material. As the resin filler, a thermosetting resin is suitable, and when this is used, heat treatment is performed after filling. As a result, the embedding ceramic chip is fixed in the accommodation hole by the cured resin filler. Instead of filling with the resin filler, the gap may be filled with a part of the second core-side insulating layer and fixed.

  Thereafter, in the masking material removal step, the masking material arranged on the core first main surface side so as to close the opening of the accommodation hole is removed.

  In the cleaning and polishing step, the core first main surface and the chip first main surface are cleaned with a solvent by acid degreasing and then polished. Polishing is performed using a conventionally known polishing apparatus (for example, a buff polishing apparatus, a lapping apparatus, etc.), and at that time, the core first main surface side is scraped off by about 1 μm to 5 μm, for example. In this step, it is preferable to perform solvent cleaning first and then perform polishing. This is because the removal of the adhesive and the flattening of the surface can be reliably performed in this order.

  In the insulating layer forming step, a core-side insulating layer is formed on the core first main surface and the chip first main surface exposed through the masking material removing step.

  A roughening step is preferably performed after the cleaning and polishing step and before the insulating layer forming step to roughen the surface of the metal layer on the plurality of terminal electrodes formed on the embedding ceramic chip. By roughening the metal layer, the adhesion of the core-side insulating layer can be enhanced. Further, when conductor layers are formed on the core first main surface and the second main surface of the core material, the conductor layer is roughened simultaneously with the metal layer roughening of the terminal electrode. Is preferred. The reason is that man-hours are reduced and productivity is improved as compared with the case of performing roughening separately.

  In the via forming step, a plurality of via holes and a plurality of via conductors are formed in the core-side insulating layer formed in the insulating layer forming step. In this via formation process, a plurality of via holes are formed by laser processing, and then desmear processing for removing smear in the plurality of via holes is performed, and then plating is performed to form filled via conductors in the plurality of via holes. preferable. If it does in this way, a favorable via conductor can be formed for connection with the fine conductor pattern formed in a buildup layer.

  In the subsequent buildup layer forming step, after the via forming step, a buildup layer is formed on the core first main surface and the chip first main surface based on a conventionally known technique.

  Moreover, as another means (means 3) for solving the said subject, it has a core 1st main surface and a core 2nd main surface, and it opens in the said core 1st main surface and the said core 2nd main surface. A core material having an accommodating hole portion, a chip first main surface and a chip second main surface, and an internal conductor is formed therein, and the chip first main surface faces the same side as the core first main surface. And an embedded ceramic chip housed in the housing hole with the second main surface of the chip facing the same side as the second core main surface, an inner surface of the housing hole, and the embedded ceramic chip A resin filler for fixing the embedding ceramic chip to the core material by filling a gap with a side surface, the core first main surface, the chip first main surface, and the core first main surface of the resin filler Disposed on the side exposed surface, at least the first chip main A core-side insulating layer in which a plurality of via holes and a plurality of via conductors are formed in a region corresponding to, and a structure in which an interlayer insulating layer and a conductor layer are alternately stacked. And a build-up layer having a plurality of connection terminals on which a semiconductor element can be surface-mounted on the surface layer portion, and the core first main surface side exposure of the core first main surface, the chip first main surface, and the resin filler There is a wiring board characterized in that the surfaces are at the same level, and the flatness of the core-side insulating layer is not less than 0 μm and not more than 30 μm.

  Therefore, according to the wiring substrate of means 3, since the flatness of the core-side insulating layer is increased, the unevenness on the surface of the buildup layer formed thereon can be suppressed, so that the semiconductor element can be mounted reliably. Can do. In addition, since the thickness variation of the core-side insulating layer formed on the core first main surface and the chip first main surface is eliminated, uniform-shaped via holes and via conductors are formed in the core-side insulating layer. Can do. Therefore, the connection reliability with the semiconductor element can be improved, and a wiring board with a good product yield can be provided.

  The thickness of the embedding ceramic chip is preferably equal to or less than the thickness of the core material. In this case, the thickness variation of the core-side insulating layer formed on the core second main surface and the chip second main surface can be suppressed.

[First Embodiment]

  Hereinafter, a first embodiment in which a ceramic chip built-in wiring board of the present invention is embodied will be described in detail with reference to the drawings.

  As shown in FIG. 1, a ceramic chip built-in wiring board 10 of this embodiment is a wiring board for mounting an IC chip, and includes a flat core material 11 made of glass epoxy, a ceramic capacitor 101, and resin insulation. Layers (core-side insulating layers) 33, 34, a buildup layer 31 formed on the resin insulating layer 33, and a buildup layer 32 formed on the resin insulating layer 34. Through-hole conductors 16 are formed at a plurality of locations in the core material 11. The through-hole conductor 16 connects and connects the upper surface 12 side and the lower surface 13 side of the core material 11. The inside of the through-hole conductor 16 is filled with a closing body 17 such as an epoxy resin. A conductor layer 41 made of copper is patterned on the upper surface 12 and the lower surface 13 of the core material 11, and each conductor layer 41 is electrically connected to the through-hole conductor 16. Furthermore, resin insulating layers (core-side insulating layers) 33 and 34 are formed on the upper surface 12 and the lower surface 13 of the core material 11 so as to cover the conductor layer 41.

  The buildup layer 31 formed on the upper surface 12 side of the core material 11 is formed by alternately laminating core first main surface side conductor layers 242 made of copper and resin insulating layers 35 (so-called interlayer insulating layers) made of epoxy resin. It has a structure. Terminal pads 44 are formed in an array at a plurality of locations on the surface of the resin insulation layer 35. The surface of the resin insulating layer 35 is almost entirely covered with a solder resist 37. An opening 46 for exposing the terminal pad 44 (connection terminal) is formed at a predetermined location of the solder resist 37. A plurality of solder bumps 45 are provided on the surface of the terminal pad 44. Each solder bump 45 is electrically connected to the surface connection terminal 22 of the IC chip 21 (semiconductor integrated circuit element). Each terminal pad 44 and each solder bump 45 are located in a region immediately above the ceramic capacitor 101 in the buildup layer 31, and this region becomes the semiconductor element mounting portion 23. A via conductor 43 is provided in the resin insulating layer 33, and a via conductor 47 is provided in the resin insulating layer 35. Most of these via conductors 43 and 47 are arranged coaxially, and the conductor layers 41 and 42 and the terminal pads 44 are electrically connected to each other through them.

  The buildup layer 32 formed on the lower surface 13 side of the core material 11 has substantially the same structure as the buildup layer 31 described above. That is, the buildup layer 32 has a structure in which the core second main surface side conductor layer 342 made of copper and the resin insulating layer 36 made of epoxy resin are alternately laminated. BGA pads 48 are formed in a lattice pattern at a plurality of locations on the lower surface of the resin insulating layer 36. The lower surface of the resin insulating layer 36 is almost entirely covered with a solder resist 38. An opening 40 for exposing the BGA pad 48 is formed at a predetermined portion of the solder resist 38. On the surface of the BGA pad 48, a plurality of solder bumps 49 are provided for electrical connection with a mother board (not shown). The wiring board 10 shown in FIG. 1 is mounted on a mother board (not shown) by each solder bump 49. A via conductor 50 is provided in the resin insulating layer 34, and a via conductor 51 is provided in the resin insulating layer 36. Most of these via conductors 50 and 51 are arranged coaxially, and the conductor layers 41 and 42 and the BGA pad 48 are electrically connected to each other through them.

  The core material 11 has a rectangular accommodation hole 91 in a plan view that opens at the center of the upper surface 12 and the center of the lower surface 13. That is, the accommodation hole 91 is a through hole. A ceramic capacitor 101 (embedded ceramic chip) shown in FIGS. 2, 3 and the like is housed in the housing hole 91 in an embedded state. The ceramic capacitor 101 has the chip first main surface 102 (the upper surface in FIGS. 1 and 2) facing the same side as the core first main surface 12 of the core material 11, and the chip second main surface 103 (FIGS. 1 and 2). Then, the lower surface is accommodated with the core material 11 facing the same side as the core second main surface 13. The ceramic capacitor 101 of this embodiment has a rectangular flat plate shape of 12.0 mm long × 12.0 mm wide × 0.75 mm thick. The thickness of the ceramic capacitor 101 is equal to or less than the thickness of the core material 11.

  Further, the gap 93 between the inner surface 92 of the accommodation hole 91 and the side surface 106 of the ceramic capacitor 101 is filled with a resin filler 95 made of a polymer material (thermosetting resin in this embodiment). The resin filler 95 has a function of fixing the ceramic capacitor 101 to the core material 11 and absorbing the deformation of the ceramic capacitor 101 and the core material 11 in the surface direction and the thickness direction by its own elastic deformation. . In the present embodiment, the upper end surface (exposed surface on the core first main surface 12 side) of the resin filler 95 is substantially the same as the core first main surface 12 of the core material 11 and the chip first main surface 102 of the ceramic capacitor 101. In addition, the lower end surface of the resin filler 95 is recessed above the core second main surface 13 of the core material 11 and the chip second main surface 103 of the ceramic capacitor 101.

  As shown in FIGS. 1 to 3, the ceramic capacitor 101 of this embodiment is a so-called via array type ceramic capacitor. The ceramic sintered body 104 constituting the ceramic capacitor 101 is a plate-like object having a chip first main surface 102 (upper surface) and a chip second main surface 103 (lower surface). The ceramic sintered body 104 has a structure in which first internal electrode layers 141 (internal conductors) and second internal electrode layers 142 (internal conductors) are alternately stacked via ceramic dielectric layers 105. The ceramic dielectric layer 105 is made of a sintered body of barium titanate, which is a kind of high dielectric constant ceramic, and functions as a dielectric (insulator) between the first internal electrode layer 141 and the second internal electrode layer 142. Each of the first internal electrode layer 141 and the second internal electrode layer 142 is a layer formed mainly of nickel, and is disposed every other layer inside the ceramic sintered body 104.

  A number of via holes 130 are formed in the ceramic sintered body 104. These via holes 130 penetrate the ceramic sintered body 104 in the thickness direction and are arranged in a lattice shape (array shape) over the entire surface. In each via hole 130, a plurality of via conductors 131 and 132 (internal conductors) penetrating between the upper surface 102 and the lower surface 103 of the ceramic sintered body 104 are formed using nickel as a main material. Each first via conductor 131 passes through each first internal electrode layer 141 and electrically connects them to each other. Each second via conductor 132 penetrates each second internal electrode layer 142 and electrically connects them to each other.

  On the upper surface 102 of the ceramic sintered body 104, a plurality of first external terminal electrodes 111 and 112 (terminal electrodes) are provided so as to project. A plurality of second external terminal electrodes 121 and 122 protrude from the lower surface 103 of the ceramic sintered body 104. The first external terminal electrodes 111 and 112 on the upper surface 102 side are electrically connected to the via conductor 43. On the other hand, the second external terminal electrodes 121 and 122 on the lower surface 103 side are connected to the via conductor 50, the conductor layer 42, the via conductor 51, the BGA pad 48, and the solder bump with respect to the electrode (contactor) included in the mother board (not shown). 49 is electrically connected. In addition, the substantially central portions of the bottom surfaces of the first external terminal electrodes 111 and 112 are directly connected to the end surfaces of the via conductors 131 and 132 on the top surface 102 side, and the substantially central portions of the bottom surfaces of the second external terminal electrodes 121 and 122. Are directly connected to the end surfaces of the via conductors 131 and 132 on the lower surface 103 side. Therefore, the external terminal electrodes 111 and 121 are electrically connected to the via conductor 131 and the first internal electrode layer 141, and the external terminal electrodes 112 and 122 are electrically connected to the via conductor 132 and the second internal electrode layer 142.

  The external terminal electrodes 111, 112, 121, and 122 have a layer structure in which a copper plating layer is formed on a metallized layer containing nickel as a main material. A copper plating layer consists of a metal softer than the metal which comprises a metallization layer, The surface is roughened. For this reason, the surfaces of the first external terminal electrodes 111 and 112 are rougher than the upper surface 102 of the ceramic sintered body 104. Similarly, the surfaces of the second external terminal electrodes 121 and 122 are also rougher than the lower surface 103 of the ceramic sintered body 104. Further, the external terminal electrodes 111, 112, 121, 122 when viewed from the direction perpendicular to the upper surface 102 (part thickness direction) are substantially circular (see FIG. 3).

  When energization is performed from the motherboard side via the second external terminal electrodes 121 and 122 and a voltage is applied between the first internal electrode layer 141 and the second internal electrode layer 142, for example, positive charges are applied to the first internal electrode layer 141. For example, negative charges are accumulated in the second internal electrode layer 142. As a result, the ceramic capacitor 101 functions as a capacitor. In the ceramic capacitor 101, the first via conductors 131 and the second via conductors 132 are alternately arranged adjacent to each other, and the directions of the currents flowing through the first via conductors 131 and the second via conductors 132 are opposite to each other. It is set to face. Thereby, the inductance component is reduced.

  Next, a method for manufacturing the ceramic chip built-in wiring board 10 of the present embodiment will be described.

  In the core material preparation step, the core material 11 is manufactured by a conventionally known method. In the embedding ceramic chip preparation step, the ceramic capacitor 101 is manufactured by a conventionally known method, and the core material 11 and the ceramic capacitor 101 are prepared in advance. deep.

  In the core material preparation step, the core material 11 is produced as follows. First, a copper clad laminate is prepared in which a copper foil having a thickness of 35 μm is attached to both surfaces of a base having a length of 400 mm × width of 400 mm × thickness of 0.80 mm. Next, drilling is performed on the copper-clad laminate using a drill, and a through hole for forming the through-hole conductor 16 is formed in advance at a predetermined position. Moreover, a copper-clad laminated board is drilled using a router, and the through-hole used as the accommodation hole part 91 is previously formed in the predetermined position (refer FIG. 4). In addition, the through-hole used as the accommodation hole part 91 is a hole with a substantially square cross section which has a side of 14.0 mm and a radius of 3 mm at four corners. And the through-hole conductor 16 is formed by performing electroless copper plating and electrolytic copper plating according to a conventionally well-known method. Next, after the paste which has an epoxy resin as a main component is printed in the cavity part of the through-hole conductor 16, the obstruction | occlusion body 17 is formed by hardening. Further, the copper foil on both sides of the copper clad laminate is etched to pattern the conductor layer 41 by, for example, a subtractive method. Specifically, after the electroless copper plating, electrolytic copper plating is performed using the electroless copper plating layer as a common electrode. Further, the dry film is laminated, and the dry film is exposed and developed to form a dry film in a predetermined pattern. In this state, unnecessary electrolytic copper plating layer, electroless copper plating layer and copper foil are removed by etching. Thereafter, the core material 11 is obtained by peeling the dry film.

  In the embedding ceramic chip preparation step, the ceramic capacitor 101 is manufactured as follows. That is, a ceramic green sheet is formed, and nickel paste for internal electrode layers is screen printed on the green sheet and dried. As a result, a first internal electrode portion that later becomes the first internal electrode layer 141 and a second internal electrode portion that becomes the second internal electrode layer 142 are formed. Next, the green sheets on which the first internal electrode portions are formed and the green sheets on which the second internal electrode portions are formed are alternately stacked, and each green sheet is integrated by applying a pressing force in the sheet stacking direction. To form a green sheet laminate.

  Further, a number of via holes 130 are formed through the green sheet laminate using a laser processing machine, and a via conductor nickel paste is filled into each via hole 130 using a paste press-fitting and filling device (not shown). Next, a paste is printed on the upper surface of the green sheet laminate, and metallized layers of the first external terminal electrodes 111 and 112 are formed so as to cover the upper end surfaces of the respective conductor portions on the upper surface side of the green sheet laminate. Further, a paste is printed on the lower surface of the green sheet laminate, and the metallized layers of the second external terminal electrodes 121 and 122 are formed so as to cover the lower end surfaces of the respective conductor portions on the lower surface side of the green sheet laminate.

  Thereafter, the green sheet laminate is dried to solidify the surface terminal part to some extent. Next, the green sheet laminate is degreased and fired at a predetermined temperature for a predetermined time. As a result, barium titanate and nickel in the paste are simultaneously sintered to form a ceramic sintered body 104.

  Next, electrolytic copper plating (thickness of about 10 μm) is performed on each external terminal electrode 111, 112, 121, 122 included in the obtained ceramic sintered body 104. As a result, a copper plating layer is formed on each external terminal electrode 111, 112, 121, 122, and the ceramic capacitor 101 is completed. In addition, since electroless copper plating is a little thick about 10 micrometers, the thickness of copper is securable even after passing through a later roughening process.

  As shown in FIG. 5, in the masking process, the peelable adhesive tape 152 as a masking material is disposed in close contact with the opening 96 on the core first main surface 12 side of the housing hole 91, and the housing hole portion The lower surface 13 side opening 96 of 91 is closed. The adhesive tape 152 is supported by a support base 151. In addition, the thickness of the base material of the adhesive tape 152 is 55 μm, and the thickness of the adhesive surface 153 is 25 μm. Further, the adhesive surface 153 is formed of a rubber adhesive.

  In the subsequent fixing step, the ceramic capacitor 101 is accommodated in the accommodation hole 91 using a mounting device (manufactured by Yamaha Motor Co., Ltd.). At this time, the ceramic capacitor 101 is affixed and temporarily fixed to the adhesive surface 153 of the adhesive tape 152. Here, when the chip is mounted (the state shown in FIG. 1), the chip first main surface 102 that is the upper surface is in close contact with the adhesive surface 153 in a state where the upper surface and the lower surface are reversed. . Similarly, the core material 11 is also in a state where the core first main surface 12 that is the upper surface when the chip is mounted faces downward.

  In this state, a filler 95 (NAMICS Co., Ltd.) made of a thermosetting resin is used in the gap 93 between the inner surface 92 of the accommodation hole 91 and the side surface 106 of the ceramic capacitor 101 using a dispenser device (manufactured by Asymtek). (See FIG. 6). Thereafter, when heat treatment is performed, the resin filler 95 is cured and the ceramic capacitor 101 is fixed in the accommodation hole 91. At this time, the positions of the surfaces of the core first main surface 12, the chip first main surface 102, and the resin filler 95 on the side in contact with the adhesive tape 152 are aligned and formed flat.

  Then, after fixing the ceramic capacitor 101, a masking material removing step is performed to peel off the adhesive tape 152 (see FIG. 7).

  Thereafter, in the cleaning and polishing step, the core first main surface 12 of the core material 11 and the chip first main surface 102 of the ceramic capacitor 101 are subjected to solvent cleaning by acidic degreasing and then polished, whereby the core first main surface 12 and The adhesive material (part of the adhesive surface 153) remaining after sticking to the chip first main surface 102 is removed.

  In the subsequent roughening step, the surface of the copper plating layer on the external terminal electrodes 111, 112, 121, 122 is roughened (CZ treatment). At the same time, the surface of the conductor layer 41 formed on the core first main surface 12 and the core second main surface 13 is also roughened. And if a roughening process is complete | finished, a washing process will be implemented. Moreover, you may perform a coupling process with respect to the core 1st main surface 12 and the core 2nd main surface 13 using a silane coupling agent (made by Shin-Etsu Chemical Co., Ltd.) as needed.

  Thereafter, in the core-side insulating layer forming step, the upper surface and the lower surface of the core material 11 and the ceramic capacitor 101 (core first main surface 12 and core second main surface 13, chip first main surface 102, and chip second main surface 103). The film-like insulating resin materials mainly composed of epoxy resin are arranged so as to overlap each other. Here, an insulating resin material having a thickness of about 45 μm is disposed on the core first main surface 12 and the chip first main surface 102 side. An insulating resin material having a thickness of about 60 μm is disposed on the core second main surface 13 and the chip second main surface 103 side in consideration of the presence of irregularities.

  Then, such a laminate is pressurized and heated under vacuum with a vacuum press hot press (not shown) to cure the film-like insulating resin material and to insulate the upper surface 12, 102 and the lower surface 13, 103 with resin insulation. Layers 33 and 34 are formed (see FIG. 8). Here, since the upper surface side (the core first main surface 12 and the chip first main surface 102 side) is a flat surface, the resin insulating layer 33 having a surface flatness of 0 μm to 30 μm is formed. On the other hand, since the lower surface side (the core second main surface 13 and the chip second main surface 103 side) has a recess, the flatness of the resin insulating layer 34 is worse than that of the resin insulating layer 33. Specifically, the ceramic capacitor 101 is thinner than the core material 11, the chip second main surface 103 is recessed from the core second main surface 13, and the surface of the resin filler 95 is also the core second main surface. It is recessed from the surface 13. Since the resin insulating layer 34 is formed by press-fitting the insulating resin material into the recessed portion, the flatness of the surface is lowered. In FIG. 8, the upper and lower surfaces of the core material 11 and the ceramic capacitor 101 in FIG. 7 are reversed (in a state where the chip is mounted).

  In the subsequent via formation step, a plurality of via holes 53 and a plurality of via conductors 43 are formed in the resin insulating layer 33 on the upper surface side, and a plurality of via holes 54 and a plurality of via conductors 50 are also formed in the resin insulating layer 34 on the lower surface side. (See FIG. 9). Specifically, a plurality of via holes 53 and 54 are formed in the resin insulating layers 33 and 34 by laser processing, and then a desmear process for removing smears in the via holes 53 and 54 is performed. Thereafter, plating is performed to form filled via conductors 43 and 50 in the via holes 53 and 54. Thereafter, patterning is performed according to a conventionally known method (for example, a subtractive method) to form the core first main surface side conductor layer 242 and the core second main surface side conductor layer 342. Here, since the surface of the chip second main surface 103 and the resin filler 95 is recessed from the core second main surface 13, the resin insulating layer 34 maintains good flatness like the resin insulating layer 33 side. Can not. Therefore, the via hole 54 and the via conductor 50 formed in the resin insulating layer 34 are formed to have a larger diameter than the via hole 53 and the via conductor 43 formed in the resin insulating layer 33. Thereby, the via conductor 50 and the external terminal electrodes 121 and 122 are reliably connected.

  Next, a buildup layer forming step is performed. In the buildup layer forming step, the buildup layer 31 is formed on the resin insulating layer 33 and the buildup layer 32 is formed on the resin insulating layer 34 based on a conventionally known method. Specifically, a photosensitive epoxy resin is deposited on the resin insulation layers 33 and 34, and exposure and development are performed, whereby a second layer of resin insulation having a blind hole at a position where the via conductor 47 is to be formed. Layers 35 and 36 are formed. Next, electrolytic copper plating is performed according to a conventionally known method (for example, a semi-additive method) to form a via conductor 47 in the blind hole, and a terminal pad 44 is formed on the second resin insulating layer 35. Then, a BGA pad 48 is formed on the second resin insulating layer 36. Next, solder resists 37 and 38 are formed by applying and curing a photosensitive epoxy resin on the second resin insulation layers 35 and 36. Next, exposure and development are performed with a predetermined mask placed, and the openings 40 and 46 are patterned in the solder resists 37 and 38. Further, solder bumps 45 are formed on the terminal pads 44 and solder bumps 49 are formed on the BGA pads 48. As a result, the wiring board 10 is completed.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) According to the ceramic chip built-in wiring substrate 10 of the present embodiment, there are uneven surfaces due to the filling amount of the resin filler 95 and the thickness of the ceramic capacitor 101 (the core second main surface 13 and the chip second main surface). The buildup layer 31 for mounting the IC chip 21 is formed not on the surface 103) side but on the opposite surface (core first main surface 12 and chip first main surface 102) with good flatness. In this way, since the unevenness on the surface of the buildup layer 31 can be suppressed, the IC chip 21 can be reliably mounted. Further, since the thickness variation of the core-side insulating layer 33 formed on the core first main surface 12 and the chip first main surface 102 is eliminated, the via-hole 53 and the via having a uniform shape are formed in the core-side insulating layer 33. A conductor 43 can be formed. From the above, the connection reliability with the IC chip 21 can be improved, and the product yield can be improved.

  (2) In this embodiment, since the cleaning and polishing step is performed after the masking material removing step, the adhesive material remaining on the core first main surface 12 and the chip first main surface 102 can be removed, and the external terminal The surface roughening process (CZ process) of the electrodes 111, 112, 121, 122 can be reliably performed.

  (3) In the present embodiment, in the roughening step, the surface of each conductor layer 41 is roughened simultaneously with the roughening of the surfaces of the external terminal electrodes 111, 112, 121, 122. As a result, since the area of the rough surface on the upper surface 12 and the lower surface 13 is increased, higher adhesion strength can be obtained between the resin insulating layers 33 and 34. Also, the metallized layer of the external terminal electrodes 111, 112, 121, 122 made of hard metal is not directly roughened, but a softer copper plating layer is formed and the surface is roughened. Therefore, a desired rough surface can be obtained relatively easily and reliably.

  (4) In the present embodiment, since the semiconductor element mounting portion 23 of the buildup layer 31 is located in the region directly above the ceramic capacitor 101, the semiconductor element mounting portion 23 is a ceramic having high rigidity and a low coefficient of thermal expansion. Supported by the capacitor 101. Therefore, in the semiconductor element mounting portion 23, the build-up layer 31 is not easily deformed, so that the IC chip 21 mounted on the semiconductor element mounting portion 23 can be supported more stably. Therefore, as the IC chip 21, a large IC chip of 10 mm square or more, which has a large influence of thermal stress due to a large amount of heat generation, or a low-k (low dielectric constant) IC chip can be used.

(5) Since the ceramic chip built-in wiring substrate 10 of the present embodiment includes the ceramic capacitor 101, good power can be supplied to the IC chip 21 by removing noise with the ceramic capacitor 101. In addition, since the IC chip 21 is mounted on the semiconductor element mounting portion 23, the IC chip 21 is disposed immediately above the ceramic capacitor 101. Thereby, the wiring (capacitor connection wiring) connecting the IC chip 21 and the ceramic capacitor 101 is shortened. Therefore, noise entering between the IC chip 21 and the ceramic capacitor 101 can be suppressed to be extremely small, and high reliability can be obtained without causing malfunctions such as malfunctions.
[Second Embodiment]

  Hereinafter, a second embodiment of the ceramic chip built-in wiring board according to the present invention will be described in detail with reference to the drawings.

  As shown in FIG. 10, in the ceramic chip built-in wiring substrate 10 of the present embodiment, a gap 93 between the inner surface 92 of the accommodation hole 91 and the side surface 106 of the ceramic capacitor 101 is filled with a part of the resin insulating layer 34. This is different from the first embodiment. Hereinafter, a manufacturing method of the ceramic chip built-in wiring board 10 will be described.

  Also in the present embodiment, the core material preparing step, the embedding ceramic chip preparing step, and the masking step are performed in the same manner as in the first embodiment. Thereafter, in the second core-side insulating layer forming step, the ceramic capacitor 101 is accommodated in the accommodating hole 91, and the ceramic capacitor 101 is temporarily fixed on the adhesive surface 153 of the adhesive tape 152 (see FIG. 5). Here, when the chip is mounted (the state shown in FIG. 10), the chip first main surface 102 that is the upper surface is in close contact with the adhesive surface 153 with the upper surface and the lower surface reversed. .

  In this state, a film-like insulating resin material mainly composed of an epoxy resin is arranged on the core second main surface 13 of the core material 11 and the chip second main surface 103 of the ceramic capacitor 101 so as to overlap each other. And pressurizing and heating under vacuum with a vacuum press hot press (not shown). Thereby, the film-like insulating resin material is cured to form the resin insulating layer 34 (second core side insulating layer), and the gap 93 between the inner surface 92 of the accommodation hole 91 and the side surface 106 of the ceramic capacitor 101 is resin-insulated. The ceramic capacitor 101 is fixed to the core material 11 by being filled with a part of the layer 34 (see FIG. 11). At this time, the core first main surface 12, the chip first main surface 102, and a part of the surface of the resin insulating layer 34 on the side in contact with the adhesive tape 152 are aligned and formed flat (on the same plane).

  Then, a masking material removing process for peeling the adhesive tape 152 is performed (see FIG. 12). Further, as in the first embodiment, a cleaning and polishing process for removing the adhesive material, and the external terminal electrodes 111, 112, 121, and 122 are performed. And a roughening step for roughening the surface.

  Thereafter, in the first core-side insulating layer forming step, a film-like insulating resin material mainly composed of epoxy resin is superimposed on the core first main surface 12 of the core material 11 and the chip first main surface 102 of the ceramic capacitor 101. Arrange like this. Then, the film-like insulating resin material is cured by pressurizing and heating under vacuum with a vacuum press and heat press (not shown) to form the resin insulating layer 33 (first core side insulating layer) (FIG. 13). reference).

  Thereafter, the via formation step and the buildup layer formation step are performed in the same manner as in the first embodiment, thereby completing the ceramic chip built-in wiring substrate 10 shown in FIG.

  According to the ceramic chip built-in wiring substrate 10 of the present embodiment manufactured as described above, on the side of the uneven surface (the core second main surface 13 and the chip second main surface 103) due to the thickness of the ceramic capacitor 101. The build-up layer 31 for mounting the IC chip 21 is formed on the opposite surfaces (core first main surface 12 and chip first main surface 102) with relatively good flatness. In this way, since the unevenness on the surface of the buildup layer 31 can be suppressed, the IC chip 21 can be reliably mounted. Further, since the thickness variation of the core-side insulating layer 33 formed on the core first main surface 12 and the chip first main surface 102 is eliminated, the via-hole 53 and the via having a uniform shape are formed in the core-side insulating layer 33. A conductor 43 can be formed. From the above, the connection reliability with the IC chip 21 can be improved, and the product yield can be improved.

  Moreover, in the ceramic chip built-in wiring substrate 10 of the present embodiment, since the resin filler 95 does not have to be used as in the first embodiment, the manufacturing cost can be reduced. Furthermore, since the filling process of the resin filler 95 using a dispenser can be omitted, the manufacturing process can be simplified.

  In addition, you may change each embodiment of this invention as follows.

  In the first embodiment, the resin filler 95 is filled into the gap 93 between the inner surface 92 of the accommodation hole 91 and the side surface 106 of the ceramic capacitor 101 in the core material 11 using a dispenser device. It is not limited to this. For example, the resin filler 95 may be filled into the gap 93 between the inner surface 92 of the accommodation hole 91 and the side surface 106 of the ceramic capacitor 101 by printing the resin filler 95 using a printing apparatus.

  In each of the above embodiments, the ceramic capacitor 101 is used as the embedded ceramic chip. However, a ceramic chip that does not have a capacitor function may be used instead.

  Next, the technical ideas grasped by the embodiment described above are listed below.

  (1) A core material that has a core first main surface and a core second main surface, and prepares a flat core material having an accommodation hole portion that opens at the core first main surface and the core second main surface. Preparation of an embedded ceramic chip comprising a preparation step and an embedded ceramic chip comprising a ceramic sintered body having a chip first main surface and a chip second main surface and having an internal conductor formed inside the ceramic sintered body A masking step in which a masking material is disposed in close contact with the core first main surface side to close the opening of the accommodation hole, and the chip first main surface is on the same side as the core first main surface. The ceramic chip for embedding is accommodated in the accommodating hole with the second main surface of the chip facing the same side as the second main surface of the core. In this state, the inner surface of the accommodating hole and the ceramic for embedding are accommodated. With the side of the chip It was exposed through a fixing step of filling the space with a resin filler and fixing the embedding ceramic chip to the core material, a masking material removal step of removing the masking material after the fixing step, and the masking material removal step. A cleaning and polishing step of polishing the core first main surface and the chip first main surface after solvent cleaning, and forming a core-side insulating layer on the core first main surface and the chip first main surface. An insulating layer forming step; a via forming step of forming a plurality of via holes and a plurality of via conductors in the core side insulating layer; and an interlayer insulating layer and a conductor layer on the core side insulating layer after the via forming step. And a build-up layer forming step of forming a build-up layer having a plurality of connection terminals on the surface layer part of which surface-mountable semiconductor integrated circuit elements can be formed. Method of manufacturing a Kkuchippu built-in wiring board.

  (2) In the above 1, the roughening step of roughening the surface of the metal layer on the plurality of external terminal electrodes formed on the embedding ceramic chip after the cleaning and polishing step and before the insulating layer forming step A method of manufacturing a wiring board with a built-in ceramic chip, wherein:

  (3) A flat core material having a core first main surface and a core second main surface, and having a receiving hole portion opened in the core first main surface and the core second main surface; An inner conductor is formed inside having a main surface and a chip second main surface, the chip first main surface is directed to the same side as the core first main surface, and the chip second main surface is the core second. The embedding ceramic chip is filled by filling a gap between the embedding ceramic chip housed in the housing hole portion in a state facing the main surface and the inner surface of the housing hole portion and the side surface of the embedding ceramic chip. A resin filler for fixing the chip to the core material, the core first main surface, the chip first main surface, and the core first main surface side exposed surface of the resin filler; Multiple via holes and multiple vias in the area corresponding to one main surface A core-side insulating layer on which a conductor is formed, and a plurality of layers that are formed on the core-side insulating layer and in which an interlayer insulating layer and a conductor layer are alternately stacked, and a semiconductor integrated circuit element can be surface-mounted on the surface layer portion The core first main surface, the chip first main surface and the core first main surface exposed surface of the resin filler are at the same level, and the core side insulating layer A flatness of the ceramic chip is 0 μm or more and 30 μm or less.

  (4) The wiring board with a built-in ceramic chip according to the above item 3, wherein a thickness of the embedding ceramic chip is equal to or less than a thickness of the core material.

1 is a schematic sectional view showing a wiring board according to a first embodiment embodying the present invention. 1 is a schematic cross-sectional view showing a ceramic capacitor according to a first embodiment. 1 is a schematic top view showing a ceramic capacitor according to a first embodiment. Explanatory drawing of the manufacturing method of the wiring board of 1st Embodiment. Explanatory drawing of the manufacturing method of the wiring board of 1st Embodiment. Explanatory drawing of the manufacturing method of the wiring board of 1st Embodiment. Explanatory drawing of the manufacturing method of the wiring board of 1st Embodiment. Explanatory drawing of the manufacturing method of the wiring board of 1st Embodiment. Explanatory drawing of the manufacturing method of the wiring board of 1st Embodiment. The schematic sectional drawing which shows the wiring board of 2nd Embodiment. Explanatory drawing of the manufacturing method of the wiring board of 2nd Embodiment. Explanatory drawing of the manufacturing method of the wiring board of 2nd Embodiment. Explanatory drawing of the manufacturing method of the wiring board of 2nd Embodiment. Explanatory drawing which shows the fixing method of the conventional ceramic chip. Explanatory drawing which shows the via | veer shape according to the thickness of the resin insulation layer. Explanatory drawing which shows the via | veer shape according to the thickness of the resin insulation layer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Ceramic chip built-in wiring board 11 as a wiring board ... Core material 12 ... Core 1st main surface 13 ... Core 2nd main surface 21 ... IC chip 31 as a semiconductor element ... Build-up layer 33 ... 1st core side insulating layer 34 ... second core side insulating layer 35 ... resin insulating layer 42 as interlayer insulating layer ... conductor layer 43 ... via conductor 44 ... terminal pad 53 as connection terminal ... via hole 91 ... receiving hole 92 ... inner surface of receiving hole 93 ... Gap 95 ... Resin filler 96 ... Opening 101 in receiving hole ... Ceramic capacitor 102 as ceramic chip for embedding ... Chip first main surface 103 ... Chip second main surface 106 ... Side surfaces 131, 132 of the embedding ceramic chip ... via conductor 141 as internal conductor ... first internal electrode layer 142 as internal conductor ... second internal electrode layer 152 as internal conductor ... as masking material Adhesive tape

Claims (3)

A core material preparing step of preparing a core material having a core first main surface and a core second main surface, and having an accommodation hole portion opened in the core first main surface and the core second main surface;
An embedded ceramic chip preparing step of preparing an embedded ceramic chip having a chip first main surface and a chip second main surface and having an internal conductor formed therein;
A masking step in which a masking material is disposed in close contact with the core first main surface side, and the opening of the accommodation hole is closed;
The ceramic chip for embedding is accommodated in the accommodation hole portion with the chip first main surface facing the same side as the core first main surface and the chip second main surface facing the same side as the core second main surface. In this state, a film-like insulating resin material is placed on the second core main surface and the second chip main surface and heated under pressure to form the second core-side insulating layer, and at the same time, the receiving hole A second core side insulating layer forming step of filling a gap between the inner surface of the portion and the side surface of the embedding ceramic chip with a part of the second core side insulating layer and fixing the embedding ceramic chip to the core material;
A masking material removing step of removing the masking material after the second core side insulating layer forming step;
A first core-side insulating layer forming step for forming a first core-side insulating layer on the core first main surface and the chip first main surface exposed through the masking material removing step;
A via forming step of forming a plurality of via holes and a plurality of via conductors in the first core side insulating layer;
Build-up having a structure in which an interlayer insulating layer and a conductor layer are alternately stacked on the first core side insulating layer after the via formation step, and a plurality of connection terminals on which a semiconductor element can be surface-mounted on the surface layer portion And a build-up layer forming step of forming a layer. After the masking material removing step and before the first core-side insulating layer forming step, a cleaning polishing step is performed in which the core first main surface and the chip first main surface are cleaned with a solvent and then polished. The manufacturing method of the wiring board of Claim 1 . In the via formation step, the plurality of via holes are formed by laser processing, and then desmear processing for removing smear in the plurality of via holes is performed, and then plating is performed to form filled via conductors in the plurality of via holes. The method for manufacturing a wiring board according to claim 1, wherein:

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