JP4668822B2 - Wiring board manufacturing method - Google Patents

Description

The present invention relates to a manufacturing method for a wiring board comprising an internal ceramic chip embedded in the core substrate, particularly relates to manufacturing method for a wiring board characterized by a formation method such as the via conductors .

  In recent years, semiconductor integrated circuit elements (IC chips) used for a CPU of a computer have been increased in speed and function, and accordingly, the number of terminals is increased and the pitch between terminals tends to be narrowed. In general, a large number of terminals are densely arranged on the bottom surface of an IC chip, and such a terminal group is connected to a terminal group on the motherboard side in the form of a flip chip. However, it is difficult to connect the IC chip directly on the mother board because there is a large difference in the pitch between the terminals on the IC chip side terminal group and the mother board side terminal group. For this reason, generally, a technique is adopted in which an IC chip is mounted on an IC chip mounting wiring board, and the IC chip mounting wiring board is mounted on a motherboard. As this type of IC chip mounting wiring board, for example, a core part is formed by embedding a ceramic chip in a core material made of a polymer material, and build-up layers are formed on the front and back surfaces of the core part. Conventionally proposed (see, for example, Patent Documents 1 and 2). A conventional method for manufacturing this type of wiring board will be described below with reference to FIG.

First, a core material 204 made of a polymer material having an accommodation hole 203 that opens on both the core first main surface 201 and the core second main surface 202 is prepared. At the same time, a ceramic chip 207 for embedding in which a plurality of terminal electrodes are provided on each of the chip first main surface 205 and the chip second main surface 206 is prepared. Next, the embedding ceramic chip 207 is accommodated in the accommodating hole 203 and the gap is filled with a resin filler 208 or the like, thereby fixing the embedding ceramic chip 207 to the core material 204. Here, the first main surface side insulating layer 221 is formed on the chip first main surface 205 side, and the second main surface side insulating layer 222 is formed on the chip second main surface 206 side. Thereafter, a through-hole hole 209 that penetrates the core material 204 and the like is formed, a first main surface side via hole 210 is formed in the first main surface side insulating layer 221, and a second main surface side insulating layer 222 is 2 The main surface side via hole 211 is formed. Next, by performing copper plating using a plating bath for through-hole plating, the through-hole conductor 212 is formed in the through-hole hole 209, and the conformal via conductor 213 is formed in the via holes 210 and 211. Form. Next, the hole filling material 214 is printed from the core first main surface 201 side to fill the cavity portion of the through-hole conductor 212 with the hole filling material 214. Then, after surface polishing as necessary, copper plating is performed using a plating bath similar to the plating bath for through-hole plating (so-called conformal plating bath). By this plating, the plating layer 223 is deposited on the surface layer portions on the core first main surface 201 side and the core second main surface 202 side. As a result, lid plating layers 215 are formed on both end surfaces of the through-hole conductor 212. Thereafter, a buildup layer is formed according to a conventional method to obtain a desired IC chip mounting wiring board.
JP 2001-352141 A JP-A-2005-39243

  By the way, in the above-described conventional manufacturing method, the hole filling material is formed in the recessed portions of the conformal via conductor 213 of the first main surface side insulating layer 221 and the conformal via conductor 213 of the second main surface side insulating layer 222. 214 is not filled. For this reason, a cavity is generated in the recess or foreign matter such as polishing dust is mixed, and the conformal via conductor 213 is covered with the plating layer 223 in this state.

  Therefore, in the conformal via conductor 213, connection failure is likely to occur. In addition, when thermal stress is applied, cracks and delamination may occur inside the conformal via conductor 213.

The present invention has been made in view of the above problems, its object is to provide a manufacturing method of a wiring board capable of improving the via connection reliability and vias thermal reliability.

  And as a means (means 1) for solving the above-mentioned problem, it has a core first main surface and a core second main surface, and is at least one of the core first main surface and the core second main surface. A core material having a receiving hole portion opened at the inside, a ceramic chip for embedding having a chip first main surface and a chip second main surface and having an internal conductor formed therein, and being housed and fixed in the housing hole portion, A core first main surface side insulating layer disposed on the core first main surface and the chip first main surface and having a first main surface side via hole formed therein, the core second main surface and the chip first A core second main surface side insulating layer disposed on two main surfaces and having a second main surface side via hole formed therein, and formed in the first main surface side via hole and electrically connected to the internal conductor Formed in the via hole on the second main surface side and electrically connected to the inner conductor. A through hole provided in a through hole for penetrating the second via conductor, the core material, the core first main surface side insulating layer, and the core second main surface side insulating layer in the thickness direction thereof. A conductor, a hole filling material filled in a cavity of the through-hole conductor, and a lid plating layer that closes an end surface of the through-hole conductor and the hole filling material, the first via conductor and the second via There is a wiring board characterized in that at least one of the conductors is a conformal via conductor having a depression, and the depression is filled with the hole filling material and closed with a via lid plating layer.

  Therefore, according to the means 1, the recessed portion of the conformal via conductor is filled with the hole filling material, and the recessed portion is further closed by the via lid plating layer. For this reason, it is possible to avoid the conventional problems such as the generation of a cavity in the hollow portion and the mixing of foreign matter, and the via connection reliability is improved. Further, even when thermal stress is applied, cracks and delamination are less likely to occur inside, and the via thermal reliability is improved.

  The core material forms part of the core portion of the wiring board, and is formed in a flat plate shape having, for example, a core first main surface and a core second main surface located on the back side thereof. Such a core material has one or more housing holes for housing the embedding ceramic chip. The accommodation hole may be a through hole that opens on both the core first main surface and the core second main surface, or a non-through hole that opens on the core first main surface or the core second main surface. It may be.

  Although the material which forms a core material is not specifically limited, A preferable core material is mainly formed of a polymer material. Specific examples of the polymer material for forming the core material include, for example, EP resin (epoxy resin), PI resin (polyimide resin), BT resin (bismaleimide / triazine resin), PPE resin (polyphenylene ether resin), etc. There is. In addition, composite materials of these resins and glass fibers (glass woven fabric or glass nonwoven fabric) or organic fibers such as polyamide fibers may be used.

  The embedding ceramic chip is preferably a ceramic sintered body having a chip first main surface and a chip second main surface, for example. As this ceramic sintered body, a sintered body of high-temperature fired ceramic such as alumina, aluminum nitride, boron nitride, silicon carbide, silicon nitride, etc. is preferably used, and also for borosilicate glass and lead borosilicate glass. A sintered body of low-temperature fired ceramic such as glass ceramic to which an inorganic ceramic filler such as alumina is added is preferably used. In this case, it is also preferable to use a sintered body of a dielectric ceramic such as barium titanate, lead titanate, or strontium titanate depending on the application. When a dielectric ceramic sintered body is used, a ceramic capacitor having a large capacitance can be easily realized. The embedded ceramic chip may not be a ceramic sintered body.

  The embedding ceramic chip is housed and fixed in the housing hole of the core material using, for example, an adhesive. In this case, the ceramic chip may be fixed in a state of being completely accommodated in the accommodation hole, or may be fixed in a state in which a part thereof is protruded from the inside of the accommodation hole.

  An internal conductor is formed inside the ceramic chip. The material for forming such an internal conductor is not particularly limited, but it is preferable to use a metal that can be sintered simultaneously with the ceramic, for example, nickel, molybdenum, tungsten, titanium, or the like. When a low-temperature fired ceramic sintered body is selected, copper, silver, or the like can be further used as a material for forming the internal conductor. The internal conductor may be a via conductor extending in the thickness direction of the ceramic sintered body or may be an inner conductor layer extending in the surface direction of the ceramic sintered body.

  Here, the ceramic chip for embedding may be a ceramic capacitor having a structure in which the first internal electrode layers and the second internal electrode layers are alternately stacked via ceramic dielectric layers. When the embedded ceramic chip having a function as a capacitor is used as described above, for example, the stray inductance can be reliably reduced by being disposed in the vicinity of the semiconductor integrated circuit element, so that the semiconductor integrated circuit element can be stabilized. It is possible to operate it automatically.

  The core first main surface side insulating layer is disposed on the core first main surface and the chip first main surface, and has one or more first main surface side via holes. Such a first main surface side via hole is formed in a corresponding region on the chip first main surface.

  The core second main surface side insulating layer is disposed on the core second main surface and the chip second main surface, and has one or more second main surface side via holes. . Such a second main surface side via hole is formed in a corresponding region on the chip second main surface.

  A first via conductor electrically connected to the internal conductor is formed in the first main surface side via hole, and a second via conductor also electrically connected to the internal conductor is formed in the second main surface side via hole. Is formed.

  At least one of the first via conductor and the second via conductor is a conformal via conductor having a recess. In this case, the first via conductor may be a conformal via conductor having a depression, and the second via conductor may be a filled via conductor having no depression. Alternatively, both the first via conductor and the second via conductor may be conformal via conductors having depressions. The former configuration is preferable in terms of cost in materials and processes. From the viewpoint of lowering the resistance, the latter configuration is preferable. A conformal via is a type of via in which a plating layer having a uniform thickness is formed along the shape of the via hole, and therefore the via hole is not completely filled with the plating layer and has a recess. Pointing. On the other hand, the filled via refers to a type of via that has a plating layer with a non-uniform thickness, the via hole is completely filled with the plating layer, and has no depression.

  In the core part constituted by the core material, the core first main surface side insulating layer, and the core second main surface side insulating layer, a through hole for penetrating the core part in the thickness direction is formed. Yes. A through-hole conductor is provided in the through-hole hole, and a hole filling material is filled in the cavity of the through-hole conductor.

  A first wiring laminated portion that has a structure in which an interlayer insulating layer having a via conductor is laminated and can support a semiconductor integrated circuit element may be disposed on the surface side of the core portion. Such a first wiring laminated portion is, for example, a so-called build-up layer having a structure in which an interlayer insulating layer and a conductor layer mainly composed of a polymer material are alternately connected and the conductor layers are connected by the via conductor. Also good.

  Further, a second wiring laminated portion that has a structure in which an interlayer insulating layer having a via conductor is laminated and can be supported by the mother board may be disposed on the back surface side of the core portion. Such a second wiring laminated portion is also a so-called build-up layer having a structure in which, for example, an interlayer insulating layer mainly composed of a polymer material and a conductor layer are alternately connected, and the conductor layers are connected by the via conductor. Also good.

And as another means (means 2) for solving the above-mentioned problem, it has a core first main surface and a core second main surface, and at least of the core first main surface and the core second main surface A core material having a receiving hole portion that is open at any one of the above, a ceramic chip for embedding that has a chip first main surface and a chip second main surface, has an internal conductor formed therein, and is housed and fixed in the housing hole portion. A core first main surface side insulating layer disposed on the core first main surface and the chip first main surface and having a first main surface side via hole formed thereon; the core second main surface; A core second main surface side insulating layer disposed on the chip second main surface and having a second main surface side via hole formed therein, and formed in the first main surface side via hole, electrically connected to the inner conductor A first via conductor connected to the second main surface side via hole and electrically connected to the inner conductor A second via conductor connected to the core material, the core first main surface side insulating layer and the core second main surface side insulating layer provided in a through-hole hole penetrating in the thickness direction. A hole conductor, a hole filling material filled in a cavity of the through hole conductor, and a lid plating layer that closes an end surface of the through hole conductor and the hole filling material, wherein the first via conductor has a recess. The second via conductor is a filled via conductor having no depression, and the depression is filled with the hole filling material and closed with a via lid plating layer. A method of manufacturing a wiring board, wherein a through hole forming step for forming the through hole, a drilling step for forming the first main surface side via hole and the second main surface side via hole, and electroless plating The Then, the through hole is plated by performing electroplating using a plating bath for through hole plating having a throwing power that generates a hollow portion at the center of the through hole conductor. The through hole conductor is formed, the first main surface side via hole is plated to form a conformal via conductor as the first via conductor, and the second main surface side via hole is plated. After the first plating step, and after the first plating step, the hole filling printing step for filling the hollow portion of the through-hole conductor and the hollow portion of the first via conductor with the hole filling material, and after the hole filling printing step, By performing electrolytic plating using a filled via plating bath having a slower throwing power than the plating bath for through-hole plating, the second via conductor There is a method for manufacturing a wiring board, including forming a filled via conductor and a second plating step of forming the lid plating layer and the via lid plating layer. In this case, a surface polishing step may be performed after the hole filling printing step and before the second plating step.

  Therefore, according to the manufacturing method of the means 2, by performing the first plating step, a through-hole conductor is formed, and a conformal via conductor as a first via conductor is formed in the first main surface side via hole, The second main surface side via hole is plated. When the subsequent hole filling printing process is performed, the hole filling material is filled in the cavity portion of the through-hole conductor, and the hole filling material is filled in the hollow portion of the first via conductor. Therefore, if plating is further performed thereafter, the via lid plating layer can be reliably formed on the surface of the hole filling material without causing problems such as generation of cavities and contamination with foreign matter. Therefore, the wiring board described in the means 1 can be reliably and easily manufactured.

  Hereinafter, the manufacturing method of the wiring board described in the means 2 will be described.

  In the preparation step, a core material that has a core first main surface and a core second main surface and has a receiving hole that opens at one of the core first main surface and the core second main surface is conventionally known. Prepared in advance by the above method. Moreover, a ceramic chip for embedding having a chip first main surface and a chip second main surface and having an internal conductor formed therein is prepared by a conventionally known technique and prepared in advance. And this ceramic chip is accommodated and fixed in the accommodation hole part of a core material. Thereafter, a core first main surface side insulating layer is formed on the core first main surface and the chip first main surface, and the core second main surface side insulating is formed on the core second main surface and chip second main surface. Form a layer.

  After the preparation step, a through hole forming step and a drilling step are performed. In the through hole forming step, a through hole is formed by, for example, drilling. In the drilling step, the first main surface side via hole and the second main surface side via hole are formed by, for example, laser processing.

  In the first plating step, plating is performed using a plating bath for through-hole plating to plate a predetermined portion. Here, the plating bath for through-hole plating refers to a plating bath that does not have a very strong throwing power (that is, ability to attach plating to a hole or groove). . Therefore, when this plating is performed, a through-hole conductor is formed in the through-hole hole, but a hollow portion is generated at the center thereof. In addition, when the first plating step is performed, the first main surface side via hole is plated to form a conformal via conductor as the first via conductor, and the second main surface side via hole is plated. Is done.

  In the subsequent hole-filling printing step, by performing printing using a conventionally known printing device or the like, the hollow portion of the through-hole conductor and the hollow portion of the first via conductor are filled with the hole-filling material. To eliminate. Therefore, the lid plating layer and the via lid plating layer can be easily formed.

  And it is good to perform a 2nd plating process after a hole-filling printing process. In the second plating step, specifically, plating is performed using a filled via plating bath. Here, the filled via plating bath refers to a plating bath having a stronger throwing power than a plating bath for through-hole plating. According to this plating, the filled via conductor as the second via conductor is formed, and the lid plating layer and the via lid plating layer are formed.

  In this case, it is preferable to perform the surface polishing step after the hole filling printing step and before the second plating step. According to this step, surplus hole filling material protruding or adhering to the surface is removed, and the plating layer on the surface layer is flattened. Therefore, the planarity of the wiring laminated part formed on the core part is improved, and the yield of the wiring board is also improved. The surface polishing step may be performed on at least one side of the core portion, but it is more preferable to perform the both sides.

[First Embodiment]

  A first embodiment that embodies a method for manufacturing a wiring board according to the present invention will be described below in detail with reference to FIGS.

  As shown in FIG. 1, the ceramic chip built-in wiring board 10 of the present embodiment is a wiring board for mounting an IC chip having a structure in which an embedded ceramic chip 101 is built. The core part 15 which comprises the wiring board 10 has the flat core material 11 which consists of glass epoxy.

  The core material 11 has a rectangular accommodation hole 92 in plan view. The accommodation hole 92 opens at the center of the core first main surface 12 (upper surface in FIG. 1) and the center of the core second main surface 13 (lower surface in FIG. 1). That is, the accommodation hole portion 92 is a through hole. The ceramic capacitor 101 (embedding ceramic chip) shown in FIG. 2 is housed in the housing hole 92 in a completely embedded state. The chip first main surface 102 (the upper surface in FIGS. 1 and 2) is directed to the same side as the core first main surface 12 of the core material 11. The chip second main surface 103 (the lower surface in FIGS. 1 and 2) is directed to the same side as the core second main surface 13 of the core material 11. The ceramic capacitor 101 of this embodiment has a rectangular flat plate shape of 12.0 mm long × 12.0 mm wide × 0.80 mm thick. The thickness of the ceramic capacitor 101 is substantially the same as or thinner than that of the core material 11. A gap between the inner surface of the accommodation hole 92 and the side surface 106 of the ceramic capacitor 101 is filled with a resin filler 95 made of a polymer material (thermosetting resin in this embodiment). The resin filler 95 has a function of fixing the ceramic capacitor 101 to the core material 11 and absorbing the deformation of the ceramic capacitor 101 and the core material 11 in the surface direction and the thickness direction by its own elastic deformation. .

  As shown in FIG. 2 and the like, the ceramic capacitor 101 of the present embodiment is a so-called via array type ceramic capacitor. The ceramic sintered body 104 constituting the ceramic capacitor 101 is a plate-like object having a chip first main surface 102 and a chip second main surface 103. The ceramic sintered body 104 has a structure in which first internal electrode layers 141 (internal conductors) and second internal electrode layers 142 (internal conductors) are alternately stacked via ceramic dielectric layers 105. The ceramic dielectric layer 105 is made of a sintered body of barium titanate, which is a kind of high dielectric constant ceramic, and functions as a dielectric (insulator) between the first internal electrode layer 141 and the second internal electrode layer 142. Each of the first internal electrode layer 141 and the second internal electrode layer 142 is a layer formed mainly of nickel, and is disposed every other layer inside the ceramic sintered body 104.

  A number of via holes 130 are formed in the ceramic sintered body 104. These via holes 130 penetrate the ceramic sintered body 104 in the thickness direction and are arranged in a lattice shape (array shape) over the entire surface. In each via hole 130, a plurality of via conductors 131 and 132 (internal conductors) penetrating between the chip first main surface 102 and the chip first main surface 103 of the ceramic sintered body 104 are formed using nickel as a main material. ing. The first via conductor 131 penetrates the plurality of first internal electrode layers 141 and electrically connects them to each other. The second via conductor 132 passes through the plurality of second internal electrode layers 142 and electrically connects them to each other.

  On the chip first main surface 102 of the ceramic sintered body 104, a plurality of first external terminal electrodes 111 and 112 (terminal electrodes) are projected. In addition, a plurality of second external terminal electrodes 121 and 122 project from the chip second main surface 103 of the ceramic sintered body 104. The first external terminal electrodes 111 and 112 on the chip first main surface 102 side are electrically connected to a conformal via conductor which is a first via conductor 51 described later. On the other hand, the second external terminal electrodes 121 and 122 on the chip second main surface 103 side are electrically connected to a filled via conductor which is a second via conductor 61 described later.

  As shown in FIG. 1, the core first main surface side insulating layer 33 constituting the core portion 15 is disposed on the core first main surface 12 and the chip first main surface 12 of the core material 11. Similarly, the core second main surface side insulating layer 34 constituting the core portion 15 is disposed on the core second main surface 13 and the chip second main surface 13 of the core material 11. Therefore, the ceramic capacitor 101 is completely embedded in the core portion 15.

  The core first main surface side insulating layer 33 is formed by using an organic resin material such as an epoxy resin as a main component, and has a plurality of first main surfaces in a region corresponding to the chip first main surface 13. A side via hole 56 is provided. In the present embodiment, the plurality of first main surface side via holes 56 have an opening diameter set to about 60 μm to 80 μm and are formed so as to expose the central portions of the first external terminal electrodes 111 and 112. In each first main surface side via hole 56, a conformal via conductor which is the first via conductor 51 is formed by copper plating. The bottom of the first via conductor 51 is joined to the center of the top surface of the first external terminal electrodes 111 and 112. The recess 60 of the first via conductor 51 is filled with the hole filling material 17, and a via lid plating layer 54 made of copper plating is formed on the upper end surface of the recess 60. As a result, the first via conductor 51 is blocked by the via lid plating layer 54.

  The core second main surface side insulating layer 34 is formed mainly of an organic resin material such as an epoxy resin, and has a plurality of second main surfaces in a region corresponding to the chip second main surface 13. A side via hole 66 is provided. In the present embodiment, the plurality of second main surface side via holes 66 have an opening diameter set to about 60 μm to 80 μm and are formed so as to expose the central portions of the second external terminal electrodes 121 and 122. In each second main surface side via hole 66, a filled via conductor which is the second via conductor 61 is formed by copper plating. The second via conductor 61 is joined to the center of the upper surface of the second external terminal electrodes 121 and 122 through the base layer 62.

  As shown in FIG. 1, a first wiring laminated portion 31 is laminated on the upper surface side of the core portion 15. The first wiring laminated portion 31 is made of an organic resin material such as an epoxy resin, for example, and includes a resin insulating layer 35 in which a plurality of via holes 71 are formed. Via conductors 72 made of copper plating are formed in the plurality of via holes 71 laid out in an array. These via conductors 72 are all filled via conductors, and their upper end surfaces function as terminal pads 44. The surface of the resin insulating layer 35 is almost entirely covered with a solder resist 37. An opening 46 for exposing the terminal pad 44 is formed at a predetermined position of the solder resist 37. A plurality of connection terminals 22 of the IC chip 21 (semiconductor integrated circuit element) can be bonded to these terminal pads 44, respectively.

  As shown in FIG. 1, the second wiring laminated portion 32 is laminated on the lower surface side of the core portion 15. The second wiring laminated portion 32 is made of an organic resin material such as epoxy resin, for example, and includes a resin insulating layer 36 in which a plurality of via holes 73 are formed. Via conductors 74 made of copper plating are formed in the plurality of via holes 73 laid out in an array. These via conductors 74 are all filled via conductors, and their lower end surfaces function as terminal pads 47. The surface of the resin insulating layer 36 is almost entirely covered with a solder resist 38. An opening 48 for exposing the terminal pad 47 is formed at a predetermined position of the solder resist 38. Solder balls 49 are joined to these terminal pads 47, respectively. Each solder ball 49 can be joined to a plurality of connection terminals (not shown) of the mother board 26.

  As shown in FIG. 1, at a plurality of locations in the core portion 15, a diameter of 300 μm that penetrates the core material 11, the core first main surface side insulating layer 33, and the core second main surface side insulating layer 34 in the thickness direction. A through-hole 18 for a certain degree is provided. In these through-hole holes 18, through-hole conductors 16 made of copper plating having a thickness of about 10 μm to 30 μm are formed. A hollow portion 19 (see FIGS. 1 and 5 and the like) at the center of the through-hole conductor 16 is completely filled with a hole filling material 17 that is a cured product of an epoxy resin containing a filler. The upper end surface and the lower end surface of the through-hole conductor 16 filled with the hole filling material 17 are flat, and a lid plating layer 41 made of copper plating having a thickness of about 10 μm to 40 μm is provided there. As a result, the upper end surface and the lower end surface of the through-hole conductor 16 are closed. Via conductors 72 and 74 are joined on the lid plating layer 41. The through-hole conductor 16 electrically connects the conductor of the first main surface side insulating layer 33 and the conductor of the core second main surface side insulating layer 34.

  When a voltage is applied between the first internal electrode layer 141 and the second internal electrode layer 142 by energization from the mother board 26 side, for example, positive charges are accumulated in the first internal electrode layer 141, and the second internal electrode layer 142 For example, negative charges accumulate. As a result, the ceramic capacitor 101 functions as a capacitor. In the ceramic capacitor 101, the first via conductors 131 and the second via conductors 132 are alternately arranged adjacent to each other, and the directions of the currents flowing through the first via conductors 131 and the second via conductors 132 are opposite to each other. It is set to face. Thereby, the inductance component is reduced.

  Next, a method for manufacturing the wiring board 10 of this embodiment will be described.

  In the core material preparation step, the core material 11 is manufactured by a conventionally known method. In the embedding ceramic chip preparation step, the ceramic capacitor 101 is manufactured by a conventionally known method, and the core material 11 and the ceramic capacitor 101 are prepared in advance. deep.

  In the core material preparation step, the core material 11 is produced as follows. First, a copper clad laminate is prepared in which a copper foil having a thickness of 35 μm is attached to both surfaces of a base having a length of 400 mm × width of 400 mm × thickness of 0.80 mm. In addition, the copper-clad laminate is perforated using a router, and a through hole that becomes the accommodation hole 92 is formed in advance at a predetermined position (see FIG. 3). In addition, the through-hole used as the accommodation hole 92 is a hole having a substantially square cross section having a side of 14.0 mm and a radius of 3 mm at four corners. And the through-hole conductor 16 is formed by performing electroless copper plating and electrolytic copper plating according to a conventionally well-known method. Furthermore, next, the copper foil on both surfaces of the copper clad laminate is etched and patterned to obtain the core material 11.

  In the embedding ceramic chip preparation step, the ceramic capacitor 101 is manufactured as follows. That is, a ceramic green sheet is formed, and nickel paste for internal electrode layers is screen printed on the green sheet and dried. As a result, a first internal electrode portion that later becomes the first internal electrode layer 141 and a second internal electrode portion that becomes the second internal electrode layer 142 are formed. Next, the green sheets on which the first internal electrode portions are formed and the green sheets on which the second internal electrode portions are formed are alternately stacked, and each green sheet is integrated by applying a pressing force in the sheet stacking direction. To form a green sheet laminate.

  Further, a number of via holes 130 are formed through the green sheet laminate using a laser processing machine, and a via conductor nickel paste is filled into each via hole 130 using a paste press-fitting and filling device (not shown). Next, a paste is printed on the upper surface of the green sheet laminate, and metallized layers of the first external terminal electrodes 111 and 112 are formed so as to cover the upper end surfaces of the respective conductor portions on the upper surface side of the green sheet laminate. Further, a paste is printed on the lower surface of the green sheet laminate, and the metallized layers of the second external terminal electrodes 121 and 122 are formed so as to cover the lower end surfaces of the respective conductor portions on the lower surface side of the green sheet laminate.

  Thereafter, the green sheet laminate is dried to solidify the surface terminal part to some extent. Next, the green sheet laminate is degreased and fired at a predetermined temperature for a predetermined time. As a result, barium titanate and nickel in the paste are simultaneously sintered to form a ceramic sintered body 104.

  Next, electrolytic copper plating (thickness of about 10 μm) is performed on each external terminal electrode 111, 112, 121, 122 included in the obtained ceramic sintered body 104. As a result, a copper plating layer is formed on each external terminal electrode 111, 112, 121, 122, and the ceramic capacitor 101 is completed.

  Next, the ceramic capacitor 101 is housed and fixed in the housing hole 92 of the core material 11. Specifically, the opening of the accommodation hole 92 is masked, and in this state, the ceramic capacitor 101 is mounted and temporarily fixed in the accommodation hole 92 using a mounting device. Next, the gap between the inner surface of the accommodation hole 92 and the side surface 106 of the ceramic capacitor 101 is filled with a filler 95 made of a thermosetting resin using a dispenser device, and this is thermally cured. Then, the masking is removed after heat curing.

  After performing the above preparation steps, the core first main surface side insulating layer 33 is formed on the core first main surface 12 and the chip first main surface 102, and the core second main surface 13 and the chip second The core second main surface side insulating layer 34 is formed on the main surface 103 (insulating layer forming step). Specifically, the procedure is as follows. That is, a film having a thickness of about 40 μm mainly composed of an epoxy resin on the core first main surface 12 and the chip first main surface 102 and on the core second main surface 13 and the chip second main surface 103. Insulating resin materials are placed one on top of the other. Then, this laminate is heated under pressure with a vacuum press-bonding hot press, and the film-like insulating resin material is pressure-bonded while thermosetting (see FIG. 3).

  Next, laser irradiation is performed using a conventionally known laser processing apparatus to form a first main surface side via hole 56 in the core first main surface side insulating layer 33, and the core second main surface side insulating layer 34 has a first surface. 2 The main surface side via hole 66 is formed (drilling step). Further, drilling is performed using a conventionally known drilling device, and through-hole holes 18 penetrating the core portion 15 are formed at a plurality of locations (through-hole forming step, see FIG. 4). In addition, a drilling step may be performed after the through-hole forming step, and the through-hole hole 18 may be formed by laser irradiation. Moreover, it is desirable to perform a desmear process for removing smear in the processed portion after the through hole forming process and the drilling process.

  In the subsequent first plating step, after electroless plating, plating using a plating bath for through-hole plating is performed, and copper plating 172 is applied to predetermined locations (see FIG. 5). In the present embodiment, Culex S (trade name) manufactured by EEJA is used as the plating bath (60 minutes, current value 50 to 100 A). Of course, this is only an example, and other plating baths for through-hole plating may be used. When this plating is performed, the through-hole conductor 16 is formed in the through-hole hole 18. At the same time, the first main surface side via hole 56 is plated to form a conformal via conductor as the first via conductor 51, and the second main surface side via hole 66 is plated to serve as the base layer 62. .

  In the subsequent hole filling printing step, the core portion 15 with the core first main surface side insulating layer 33 facing upward is set in a conventionally known printing apparatus, and the hole filling material 17 is printed. After printing, heat treatment is performed at 120 ° C. for 70 minutes, and further heat treatment is performed at 180 ° C. for 5 hours to thermally cure the hole filling material 17. After this step, the hole filling material 17 is filled in the hollow portion 19 of the through-hole conductor 16 and the hollow portion 60 of the first via conductor 51, and the hollow portion 19 and the hollow portion 60 disappear (see FIG. 6).

  Next, a surface polishing process is performed to polish the front and back surfaces of the core portion 15 using a conventionally known polishing apparatus, the excess hole filling material 171 protruding or adhering to the surface is removed, and plating on the surface layer is performed. The layer is slightly shaved and flattened.

In the subsequent second plating step, plating using a filled via plating bath is performed, and copper plating 173 is applied to a predetermined portion (see FIG. 7). In the present embodiment, Cubelight VF2 (trade name) manufactured by Ebara Eugelite Co., Ltd. is used as the plating bath (60 minutes, current value 50 to 100 A). Of course, this is only an example, and other filled via plating baths may be used. The filled via plating solution usually includes a leveler (plating inhibitor) such as an N-based polymer compound in order to promote plating growth inside the hole and suppress plating growth outside the hole. Yes. This makes it possible to adjust the throwing power, and it is usually preferable to have a throwing power of 80% or more. According to this plating, the filled via conductor which is the second via conductor 61 is formed, and the lid plating layer 41 and the via lid plating layer 54 are formed.
Further, in accordance with a conventionally known method (for example, a subtractive method), patterning by etching is performed to form the core first main surface side conductor layer 185 and the core second main surface side conductor layer 186, and then according to a conventionally known method. The first wiring laminated portion 31 and the second wiring laminated portion 32 are formed, and the desired wiring board 10 is completed. Specifically, the via conductor 47 is formed by depositing a photosensitive epoxy resin on the core first main surface side conductor layer 185 and the core second main surface side conductor layer 186, and performing exposure and development. The second resin insulation layers 35 and 36 having blind holes at the power positions are formed. Next, electrolytic copper plating is performed according to a conventionally known method (for example, a semi-additive method) to form a via conductor 47 inside the blind hole, and a terminal pad 44 is formed on the second resin insulating layer 35. Then, a BGA pad 48 is formed on the second resin insulating layer 36. Next, solder resists 37 and 38 are formed by applying and curing a photosensitive epoxy resin on the second resin insulation layers 35 and 36. Next, exposure and development are performed with a predetermined mask placed, and the openings 40 and 46 are patterned in the solder resists 37 and 38. Further, solder bumps 45 are formed on the terminal pads 44 and solder bumps 49 are formed on the BGA pads 48.

  Therefore, according to this embodiment, the following effects can be obtained.

  (1) In the wiring board 10 of the present embodiment, the first via conductor 51 is a conformal via conductor having the recessed portion 60, and the second via conductor 61 is a filled via conductor having no recessed portion 60. . And about the 1st via conductor 51, the hollow part 60 is further obstruct | occluded by the via cover plating layer 54 in the state with which the hollow part 60 was filled with the hole-filling material 17. FIG. For this reason, it is possible to avoid the conventional problems such as the generation of a cavity in the hollow portion 60 and the mixing of foreign matter, and the via connection reliability is improved. Further, even when thermal stress is applied, cracks and delamination are less likely to occur inside, and the via thermal reliability is improved.

  (2) Moreover, according to the manufacturing method of the wiring board 10 of this embodiment, the 1st plating process is performed, the through-hole conductor 16 is formed, and the 1st via conductor 56 is also made into the 1st main surface side via hole 56 collectively. The conformal via conductor 51 is formed, and the second main surface side via hole 66 is plated with a plating layer 172 serving as the base layer 62. When the subsequent hole filling printing process is performed, the hole filling material 17 is filled in the hollow portion 60 of the through-hole conductor 16 and the hole filling material 17 is filled in the hollow portion 60 of the first via conductor 51. Therefore, if plating is further performed thereafter, the via lid plating layer 54 can be reliably formed on the surface of the hole filling material 17 without causing problems such as generation of cavities and contamination with foreign matter. Therefore, the desired wiring board 10 shown in FIG. 1 can be reliably and easily manufactured. Further, since the number of man-hours does not increase compared with the conventional manufacturing method, an increase in manufacturing cost can be avoided.

(3) Moreover, in this embodiment, since the 2nd via conductor 61 arrange | positioned at the motherboard 26 side (in other words electric power feeding side) is a filled via conductor, there exists an advantage that the electrical resistance in that part is comparatively small. Therefore, the ceramic capacitor 101 can easily supply a large current.
[Second Embodiment]

Hereinafter, although not belonging to the present invention , a second embodiment embodying a method of manufacturing a wiring board as a reference example will be described in detail with reference to FIGS.

  In this embodiment, the steps up to the first plating step are performed in the same procedure as in the first embodiment, and the state shown in FIG. 8 is obtained.

  In the subsequent first plating step, after electroless plating, plating using a plating bath for through-hole plating is performed, and copper plating 172 is applied to predetermined locations (see FIG. 9). When this plating is performed, the through-hole conductor 16 is formed in the through-hole hole 18. At the same time, the first main surface side via hole 56 is plated to form a conformal via conductor which is the first via conductor 51. The second main surface side via hole 66 is plated to form a conformal via conductor which is the second via conductor 61. That is, in this embodiment, the type of via conductor formed in the second main surface side via hole 66 is different.

  In the subsequent hole filling printing step, the core portion 15 with the core first main surface side insulating layer 33 facing upward is set in a conventionally known printing apparatus, and the hole filling material 17 is printed. By this printing, the hole filling material 17 is filled into the hollow portion 19 of the through-hole conductor 16 and the hollow portion 60 of the first via conductor 51. Next, the core portion 15 is inverted and set in a printing apparatus, and the hole filling material 17 is printed. By this printing, the hole filling material 17 is filled in the recess 60 of the second via conductor 61. After printing, heat treatment is performed at 120 ° C. for 70 minutes, and further heat treatment is performed at 180 ° C. for 5 hours to thermally cure the hole filling material 17. Therefore, after passing through this step, the hollow portion 19 of the through-hole conductor 16, the hollow portion 60 of the first via conductor 51, and the hollow portion 60 of the second via conductor 61 are filled and disappear (see FIG. 9). .

  Next, a surface polishing step is performed to polish the upper and lower surfaces of the core portion 15 using a conventionally known polishing apparatus, the excess hole filling material 171 protruding or adhering to the surface is removed, and the plating on the surface layer is removed. The layer is slightly shaved and flattened.

  In the subsequent second plating step, plating using a filled via plating bath is performed, and copper plating 173 is applied to predetermined locations (see FIG. 10). According to this plating, the lid plating layer 41 and the via lid plating layers 54 and 164 are formed. Then, if the first wiring laminated portion 31 and the second wiring laminated portion 32 are formed according to a conventionally known method, a desired wiring board can be completed.

Even with the manufacturing method as described above, it is possible to achieve the same effects as the first embodiment. That is, an excellent wiring board capable of improving the via connection reliability and the via thermal reliability can be easily and reliably manufactured.
[Third Embodiment]

  A third embodiment that embodies the method for manufacturing a wiring board according to the present invention will be described below in detail with reference to FIGS.

  As shown in FIG. 11, in this embodiment, the structure of the core material 11 is different from that of the first embodiment. Specifically, the accommodation hole portion 92 opens only on the core first main surface 12. It is a hole.

  In the present embodiment, basically the same preparation steps as in the first embodiment are performed, but here the ceramic capacitor 101 is accommodated and fixed in the accommodating hole 92 of the core material 11 without performing masking. After the preparation step, the core first main surface side insulating layer 33 and the core second main surface side insulating layer 34 are formed, and then a through hole forming step and a drilling step are performed. As a result, as shown in FIG. 11, the through hole 18, the first main surface side via hole 56, and the second main surface side via hole 166 are formed in the core portion 15. The second main surface side via hole 166 formed in the present embodiment is deeper than that of the first embodiment because the bottom portion of the accommodation hole 92 is also penetrated.

  Thereafter, according to the manufacturing method of the first embodiment, the desired core portion 15 can be manufactured by performing the steps after the first plating step (see FIGS. 12, 13, and 14). Then, if the first wiring laminated portion 31 and the second wiring laminated portion 32 are formed according to a conventionally known method, a desired wiring board can be completed.

  Even with the manufacturing method as described above, it is possible to achieve the same effects as the first embodiment. That is, an excellent wiring board capable of improving the via connection reliability and the via thermal reliability can be easily and reliably manufactured.

  In addition, you may change each embodiment of this invention as follows.

  In each of the above embodiments, the ceramic capacitor 101 is used as the embedded ceramic chip. However, a ceramic chip having no capacitor function may be used instead.

1 is a schematic sectional view showing a wiring board according to a first embodiment embodying the present invention. 1 is a schematic cross-sectional view showing a ceramic capacitor according to a first embodiment. FIG. 3 is a schematic cross-sectional view for explaining the method for manufacturing the wiring board according to the first embodiment. The schematic sectional drawing for demonstrating the manufacturing method. The schematic sectional drawing for demonstrating the manufacturing method. The schematic sectional drawing for demonstrating the manufacturing method. The schematic sectional drawing for demonstrating the manufacturing method. The schematic sectional drawing for demonstrating the manufacturing method of the wiring board of 2nd Embodiment. The schematic sectional drawing for demonstrating the manufacturing method. The schematic sectional drawing for demonstrating the manufacturing method. The schematic sectional drawing for demonstrating the manufacturing method of the wiring board of 3rd Embodiment. The schematic sectional drawing for demonstrating the manufacturing method. The schematic sectional drawing for demonstrating the manufacturing method. The schematic sectional drawing for demonstrating the manufacturing method. The schematic sectional drawing for demonstrating the manufacturing method of the wiring board of another embodiment. The schematic sectional drawing for demonstrating the manufacturing method of the conventional wiring board.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Wiring board 11 ... Core material 12 ... Core 1st main surface 13 ... Core 2nd main surface 16 ... Through-hole conductor 17 ... Hole filling material 18 ... Hole for through-hole 19 ... Hollow part 33 ... Core 1st main surface side Insulating layer 34 ... Core second main surface side insulating layer 41 ... Lid plating layer 51 ... First via conductor 54, 164 ... Via lid plating layer 56 ... First main surface side via hole 60 ... Depression portion 61, 161 ... Second Via conductors 66, 166 ... second main surface side via hole 92 ... receiving hole portion 101 ... ceramic capacitor as embedded ceramic chip 102 ... chip first main surface 103 ... chip second main surface 131, 132 ... as inner conductor Via conductor 141... First internal electrode layer as an internal conductor 142... Second internal electrode layer as an internal conductor

Claims (2)

A core material having a core first main surface and a core second main surface, and having an accommodation hole opening in at least one of the core first main surface and the core second main surface;
An embedded ceramic chip having a chip first main surface and a chip second main surface, in which an internal conductor is formed, and is housed and fixed in the housing hole;
A core first main surface side insulating layer disposed on the core first main surface and the chip first main surface and having a first main surface side via hole formed thereon;
A core second main surface side insulating layer disposed on the core second main surface and the chip second main surface and having a second main surface side via hole formed thereon;
A first via conductor formed in the first main surface side via hole and electrically connected to the inner conductor;
A second via conductor formed in the second main surface side via hole and electrically connected to the inner conductor;
A through-hole conductor provided in a through-hole for passing through the core material, the core first main surface side insulating layer and the core second main surface side insulating layer in the thickness direction;
A hole filling material filled in the cavity of the through-hole conductor;
A lid plating layer that closes the end surface of the through-hole conductor and the hole filling material,
The first via conductor is a conformal via conductor having a depression, the second via conductor is a filled via conductor having no depression, the depression is filled with the hole filling material, and a via lid plating layer A method of manufacturing a wiring board characterized by being closed ,
A through hole forming step for forming the through hole,
A drilling step of forming the first main surface side via hole and the second main surface side via hole;
After performing electroless plating, by performing electrolytic plating using a plating bath for through-hole plating having a throwing power enough to generate a cavity in the center of the through-hole conductor, the through-hole hole is formed. The through hole conductor is formed by plating, the conformal via conductor as the first via conductor is formed by plating the first main surface side via hole, and the second main surface side via hole is formed. A first plating step of plating the substrate;
After the first plating step, a hole filling printing step of filling the hole filling material into the hollow portion of the through-hole conductor and the recess portion of the first via conductor;
After the hole filling printing process, by performing electrolytic plating using a plated via plating bath having a stronger throwing power than the plating bath for through-hole plating, the filled via conductor as the second via conductor is formed, A second plating step for forming the lid plating layer and the via lid plating layer;
A method for manufacturing a wiring board, comprising: The method for manufacturing a wiring board according to claim 1 , wherein a surface polishing step is performed after the hole filling printing step and before the second plating step.

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