JP4954824B2 - Wiring board with built-in components, capacitor for wiring board - Google Patents

Description

  The present invention relates to a component built-in wiring board having a structure in which a wiring laminated portion is formed on the surface of a core substrate, in which components such as capacitors are accommodated, and a wiring board built-in capacitor used for the component built-in wiring substrate Is.

  In recent years, semiconductor integrated circuit elements (IC chips) used as computer microprocessors and the like have become increasingly faster and more functional, with an accompanying increase in the number of terminals and a tendency to narrow the pitch between terminals. . In general, a large number of terminals are densely arranged on the bottom surface of an IC chip, and such a terminal group is connected to a terminal group on the motherboard side in the form of a flip chip. However, it is difficult to connect the IC chip directly on the mother board because there is a large difference in the pitch between the terminals on the IC chip side terminal group and the mother board side terminal group. For this reason, a method is generally employed in which a package is prepared by mounting an IC chip on an IC chip mounting wiring board, and the package is mounted on a motherboard. In a wiring board for mounting an IC chip constituting this type of package, it has been proposed to provide a capacitor (also referred to as a “capacitor”) in order to reduce switching noise of the IC chip and stabilize the power supply voltage. . As an example, a wiring board in which a chip-like capacitor is embedded in a core substrate made of a polymer material and a buildup layer is formed on the front surface and the back surface of the core substrate has been conventionally proposed (for example, see Patent Document 1). ).

  Specifically, in the wiring board described in Patent Document 1, a housing hole is formed that opens at the center of the upper surface of the core substrate and the center of the lower surface of the core substrate. Contains a via array type ceramic capacitor.

  FIG. 35 shows an example of a conventional via array type ceramic capacitor 201. A ceramic sintered body 202 constituting the ceramic capacitor 201 has a structure in which first internal electrode layers 204 and second internal electrode layers 205 are alternately stacked via ceramic dielectric layers 203. The ceramic dielectric layer 203 is made of a sintered body of barium titanate, which is a kind of high dielectric constant ceramic, and functions as a dielectric (insulator) between the first internal electrode layer 204 and the second internal electrode layer 205.

  In addition, a large number of via holes 206 are formed in the ceramic capacitor 201. These via holes 206 penetrate the ceramic capacitor 201 in the thickness direction and are arranged in a lattice shape (array shape) over the entire surface. In each via hole 206, a plurality of via conductors 207 and 208 that penetrate between the upper surface and the lower surface of the ceramic capacitor 201 are formed. Each first via conductor 207 penetrates each first internal electrode layer 204 and electrically connects them to each other. Each second via conductor 208 penetrates each second internal electrode layer 205 and electrically connects them to each other.

  The ceramic capacitor 201 configured as described above is manufactured by the following procedure, for example. That is, a nickel paste for internal electrode layers is screen-printed on a ceramic green sheet and dried. And the green sheet laminated body which integrated each green sheet is formed by laminating | stacking a some green sheet and providing a pressing force in a sheet | seat lamination direction. Further, a number of via holes 206 are formed through the green sheet laminate, and each via hole 206 is filled with a nickel paste for via conductors. Thereafter, the green sheet laminate is degreased and fired at a predetermined temperature for a predetermined time, whereby the ceramic capacitor 201 is formed.

Incidentally, in the conventional ceramic capacitor 201 shown in FIG. 35, it is confirmed by the Vickers test that residual stress is accumulated in the vicinity of the surface. That is, a compressive stress is applied in the direction (XY direction) perpendicular to the thickness direction (Z direction) of the ceramic capacitor 201, while a tensile stress is applied in the thickness direction. When such a ceramic capacitor 201 is embedded in the wiring board (see FIG. 36), the ceramic capacitor 201 is pulled in the Z direction due to the shrinkage of the buildup layer 209 formed so as to cover it. As a result, a crack 210 (see FIG. 36) is likely to occur near the surface of the ceramic capacitor 201 (specifically, near the via electrodes 211 and 212). For this reason, the reliability of a wiring board will fall.
Japanese Patent Laying-Open No. 2005-39243 (see FIG. 4 etc.)

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a wiring board with a built-in component that can prevent cracks by relieving stress generated in a state of being built in the wiring board. is there. Another object of the present invention is to provide a wiring board built-in capacitor suitable for the component built-in wiring board.

And as the means (section 1) for solving the above problems, has a core main surface and the core back surface, a core board having an accommodation hole which opens at least the core main surface, the component main surface, component present having the component back face and the component-side surface, and a resin mainly comprising the component main surface, having the component backside and on the stress relieving layer formed on the component side, said core main surface wherein a part article accommodated in the accommodation hole, the resin interlayer insulating layer and a conductor layer laminated with said core main surface and on the stress relaxing layer in a state in which a said component main surface toward the same side as the and a wiring laminated portion having a structure, the gap between the accommodation hole of the inner wall and the component side surfaces formed on the outer surface of the stress relieving layer in the core substrate, a resin filling portion for filling the gap arrangement there are component built-in wiring board, characterized in that it is.

  Therefore, according to the component built-in wiring board of the means 1, the stress relaxation layer formed on at least the component main surface of the component main body can relieve external stress applied to the surface of the component in a state where the component is built in the wiring board. It is possible to prevent the occurrence of cracks in the vicinity of the surface of the component body as in the prior art. Therefore, a component built-in wiring board having excellent reliability can be obtained. Further, since the stress relaxation layer relieves external stress, the wiring laminated portion laminated on the stress relaxing layer becomes difficult to be deformed. Therefore, when a semiconductor integrated circuit element is mounted on the surface of the wiring laminated portion, the semiconductor External stress applied to the integrated circuit element can also be relieved.

  The core substrate constituting the component-embedded wiring substrate is formed in a plate shape having, for example, a core main surface and a core back surface located on the opposite side, and has an accommodation hole for accommodating the component. The accommodation hole may be a non-through hole that opens only on the core main surface side, or may be a through hole that opens on both the core main surface side and the core back surface side. In addition, the component may be housed in the housing hole in a completely embedded state, or may be housed in the housing hole in a state in which a part protrudes from the opening of the housing hole.

  A material for forming the core substrate is not particularly limited, but a preferable core substrate is mainly formed of a polymer material. Specific examples of the polymer material for forming the core substrate include, for example, EP resin (epoxy resin), PI resin (polyimide resin), BT resin (bismaleimide / triazine resin), PPE resin (polyphenylene ether resin), etc. There is. In addition, composite materials of these resins and glass fibers (glass woven fabric or glass nonwoven fabric) or organic fibers such as polyamide fibers may be used.

  The component body constituting the component has a component main surface, a component back surface, and a component side surface. The shape of the component main body can be arbitrarily set. For example, it is preferable that the component main body has a plate shape in which the area of the component main surface is larger than the area of the component side surface. The shape of the component main body in plan view is preferably a polygonal shape in plan view having a plurality of sides. Examples of the polygonal shape in a plan view include a substantially rectangular shape in a plan view, a substantially triangular shape in a plan view, and a substantially hexagonal shape in a plan view, and in particular, a generally rectangular shape in a plan view. It is preferable. Here, the “substantially rectangular shape in plan view” does not mean only a complete rectangular shape in plan view but also includes a shape with chamfered corners and a shape in which a part of the side is curved. .

  Suitable components include a capacitor, a semiconductor integrated circuit element (IC chip), a MEMS (Micro Electro Mechanical Systems) element manufactured by a semiconductor manufacturing process, and the like. Here, “semiconductor integrated circuit element” refers to an element mainly used as a microprocessor of a computer or the like.

  Examples of suitable capacitors include a chip capacitor and a structure in which a plurality of internal electrode layers are stacked via a dielectric layer, and a plurality of vias in the capacitor connected to the plurality of internal electrode layers. Examples thereof include a capacitor having a conductor and a plurality of surface layer electrodes connected to at least an end portion on the capacitor main surface side of the plurality of via conductors in the capacitor. The capacitor is preferably a via array type capacitor in which the plurality of capacitor via conductors are arranged in an array as a whole. Such a structure is suitable for a capacitor with a built-in wiring board because it is easy to increase the capacity and reduce the size. In addition, with such a structure, the inductance of the capacitor can be reduced, and high-speed power supply for smoothing power fluctuations can be achieved.

  Examples of the dielectric layer constituting the capacitor include a ceramic dielectric layer constituting a ceramic capacitor. Examples of other dielectric layers constituting the capacitor include a resin dielectric layer and a dielectric layer made of a ceramic-resin composite material. As the ceramic dielectric layer, a sintered body of a high-temperature fired ceramic such as alumina, aluminum nitride, boron nitride, silicon carbide, silicon nitride, or the like is preferably used, and for borosilicate glass or lead borosilicate glass. A sintered body of low-temperature fired ceramic such as glass ceramic to which an inorganic ceramic filler such as alumina is added is preferably used. In this case, it is also preferable to use a sintered body of a dielectric ceramic such as barium titanate, lead titanate, or strontium titanate depending on the application. When a dielectric ceramic sintered body is used, a capacitor having a large capacitance can be easily realized. Further, as the resin dielectric layer, an epoxy resin, a resin such as tetrafluoroethylene resin (PTFE) containing an adhesive is preferably used. Furthermore, as the dielectric layer made of the ceramic-resin composite material, barium titanate, lead titanate, strontium titanate or the like is preferably used as the ceramic, and as the resin material, epoxy resin, phenol resin, urethane resin, Thermosetting resins such as silicone resin, polyimide resin, unsaturated polyester, thermoplastic resin such as polycarbonate resin, acrylic resin, polyacetal resin, polypropylene resin, and latex such as nitrile butadiene rubber, styrene butadiene rubber, and fluoro rubber are suitable. Used for.

  The internal electrode layer, the capacitor via conductor, and the surface electrode are not particularly limited. For example, when the dielectric layer is a ceramic dielectric layer, it is preferably a metallized conductor. The metallized conductor is formed by applying a conductive paste containing metal powder by a conventionally well-known method, for example, a metallized printing method, followed by baking. When the metallized conductor and the ceramic dielectric layer are formed by the co-firing method, the metal powder in the metallized conductor needs to have a melting point higher than the firing temperature of the ceramic dielectric layer. For example, when the ceramic dielectric layer is made of a so-called high-temperature fired ceramic (for example, alumina), the metal powder in the metallized conductor includes nickel (Ni), tungsten (W), molybdenum (Mo), manganese (Mn), etc. And their alloys can be selected. When the ceramic dielectric layer is made of a so-called low-temperature fired ceramic (for example, glass ceramic), copper (Cu) or silver (Ag) or an alloy thereof can be selected as the metal powder in the metallized conductor.

  The stress relaxation layer constituting the component can be appropriately selected in consideration of insulation, heat resistance, moisture resistance, and the like. Preferred examples of the polymer material for forming the stress relaxation layer include thermosetting resins such as epoxy resins, phenol resins, polyimide resins, silicone resins, urethane resins, polyolefin resins, polyamide resins, polycarbonate resins, acrylic resins, Examples thereof include thermoplastic resins such as polyacetal resin and polypropylene resin. In addition, a material obtained by adding an inorganic material to these resins may be used.

  Here, as a method of forming a stress relaxation layer on at least the component main surface, a method of forming a stress relaxation layer by laminating a resin film, a method of forming a stress relaxation layer by printing a varnish (varnish printing) ), A method of forming a stress relaxation layer by immersing components in a varnish tank (varnish dip), a method of forming a stress relaxation layer by printing a resin using a curtain coater, and a resin film using a vacuum press Examples include a method of forming a stress relaxation layer by thermocompression bonding.

  The stress relaxation layer is formed at least on the component main surface. Here, when the component main body has, for example, a substantially rectangular shape in plan view, that is, when there are four component side surfaces, the stress relaxation layer may be formed only on one component side surface. It may be formed on one or more component side surfaces. The stress relaxation layer may be formed only on the component main surface, or may be formed on all of the component main surface, the component back surface, and the component side surface. When the stress relaxation layer is formed on all of the component main surface, the component back surface, and the component side surface, not only the stress relaxation layer formed on the component main surface but also the stress relaxation layer formed on the component back surface Therefore, since the external stress applied in the planar direction of the component can be relieved, the occurrence of cracks in the component main body can be more reliably prevented. In addition, external stress applied in the thickness direction of the component can be relaxed by the stress relaxation layer formed on the side surface of the component. For this reason, generation | occurrence | production of the crack in a component main body can be prevented still more reliably.

  The reason why the stress relaxation layer is formed on “at least the component main surface” instead of “at least the component back surface” or “at least the component side surface” will be described below. That is, when it is desired to minimize the formation of the stress relaxation layer due to structural problems and cost problems, it is most effective to form the stress relaxation layer on the main part surface. More specifically, if the stress relaxation layer is formed on the component main surface, the external stress applied in the plane direction (XY direction) can be most effectively relaxed. Further, when a semiconductor integrated circuit element is mounted on the surface of the wiring laminated portion laminated on the stress relaxation layer, it can be expected that the external stress applied to the semiconductor integrated circuit element is relaxed.

  Here, the outer surface of the stress relaxation layer formed on the component main surface is preferably arranged in parallel with the component main surface. If it is not parallel to the component main surface, it is difficult to flatten the upper surface of the resin interlayer insulating layer in contact with the component main surface (the surface located on the side opposite to the component main surface in the resin interlayer insulating layer). Similarly, it is preferable that the outer surface of the stress relaxation layer formed on the component back surface is also arranged in parallel with the component back surface. If it is not parallel to the component back surface, the component main surface is inclined with respect to the core main surface, making it difficult to flatten the top surface of the resin interlayer insulating layer in contact with the component main surface. Moreover, it is preferable that the outer surface of the stress relaxation layer formed on the side surface of the component is arranged in parallel with the side surface of the component. If it is not parallel to the side surface of the component, the outer surface of the stress relaxation layer formed on the side surface of the component is inclined with respect to the inner wall surface of the housing hole, and the stress relaxation layer formed on the side surface of the component. There is a possibility that the gap between the outer surface of the container and the inner wall surface of the housing hole cannot be filled with the filler.

  In addition, the stress relaxation layer includes a contact surface that contacts the component body, an outer surface that is located on the opposite side of the contact surface, a plurality of conductor columns that conduct the contact surface side and the outer surface side, and A plurality of terminal pads arranged on the outer surface and connected to the plurality of conductor pillars may be provided. In this way, even if the component has a stress relaxation layer, the conductor portion of the component (for example, the internal electrode layer, the via conductor in the capacitor, the surface electrode, etc.) and the wiring laminated portion Can be reliably connected to each other through the conductor pillars and terminal pads included in the stress relaxation layer. Therefore, it is possible to obtain a component-embedded wiring board with even higher reliability.

  The stress relaxation layer is preferably thinner than the resin interlayer insulating layer. In this way, the component built-in wiring board is less likely to be thick. In addition, since the amount of deformation of the stress relaxation layer when external stress is applied is reduced by making the stress relaxation layer thinner, it is possible to prevent a decrease in dimensional stability of the wiring laminated portion laminated on the stress relaxation layer. Can do. Specifically, the thickness of the stress relaxation layer is preferably, for example, from 5 μm to 30 μm, and particularly preferably from 10 μm to 20 μm. If the thickness of the stress relaxation layer is less than 5 μm, external stress applied to the surface of the component cannot be sufficiently relaxed by the stress relaxation layer, so that it may not be possible to prevent the occurrence of cracks in the component body. . On the other hand, when the thickness of the stress relaxation layer is larger than 30 μm, the dimensional stability of the wiring laminated portion or the like is lowered.

  The wiring laminated portion constituting the component built-in wiring board has a structure in which a resin interlayer insulating layer mainly composed of a polymer material and a conductor layer are laminated. The wiring laminated portion is formed on the core main surface and the stress relaxation layer on the component main surface, and further on the core back surface and the component back surface (or on the component back surface). A laminated portion having the same structure as the wiring laminated portion may also be formed on the stress relaxation layer. If comprised in this way, it is not only the wiring lamination | stacking part formed on the core main surface and the stress relaxation layer on a component main surface, but the stress on a core back surface and a component back surface (or component back surface). Since an electric circuit can also be formed in the laminated portion formed on the relaxation layer, it is possible to further enhance the functionality of the component built-in wiring board.

  The resin interlayer insulating layer can be appropriately selected in consideration of insulation, heat resistance, moisture resistance, and the like. Preferred examples of the polymer material for forming the resin interlayer insulation layer include thermosetting resins such as epoxy resin, phenol resin, urethane resin, silicone resin, polyimide resin, polycarbonate resin, acrylic resin, polyacetal resin, polypropylene resin. And other thermoplastic resins. In addition, composite materials of these resins and organic fibers such as glass fibers (glass woven fabrics and glass nonwoven fabrics) and polyamide fibers, or three-dimensional network fluorine-based resin base materials such as continuous porous PTFE, epoxy resins, etc. A resin-resin composite material impregnated with a thermosetting resin may be used.

  In addition, when the said resin interlayer insulation layer is a thermosetting resin, it is preferable that the said stress relaxation layer is also a thermosetting resin. If it does in this way, components can be fixed by sticking a resin interlayer insulation layer and a stress relaxation layer simultaneously with formation of a resin interlayer insulation layer only by heating. This simplifies the process of assembling the components, so that the component built-in wiring board can be easily manufactured and the cost can be reduced.

  The stress relaxation layer may be formed of the same material as that of the resin interlayer insulating layer, or may be formed of a material different from that of the resin interlayer insulating layer. When the stress relaxation layer is formed of the same material as the resin interlayer insulation layer, it is not necessary to prepare a material different from that of the resin interlayer insulation layer when forming the stress relaxation layer. Therefore, since the material required for manufacturing the component built-in wiring board is reduced, the cost of the component built-in wiring board can be reduced. Further, since the component is fixed simultaneously with the formation of the resin interlayer insulating layer, the process for assembling the component is simplified. Therefore, the component built-in wiring board can be easily manufactured, and also in this case, the cost can be reduced. On the other hand, when the stress relaxation layer is formed of a material different from that of the resin interlayer insulating layer, the function of the stress relaxation layer can be specialized in the function of relaxing external stress applied to the surface of the component.

  The weight (wt%) per unit volume of the inorganic material contained in the stress relaxation layer is less than the weight (wt%) per unit volume of the inorganic material contained in the resin interlayer insulating layer, and the stress relaxation The volume ratio (vol%) occupied by the inorganic material in the layer is preferably smaller than the volume ratio (vol%) occupied by the inorganic material in the resin interlayer insulating layer. In this way, even when the stress relaxation layer is formed of the same resin material as the resin interlayer insulation layer, the weight per unit volume of the inorganic material contained in the stress relaxation layer and the inorganic material occupies the stress relaxation layer. By reducing the volume ratio, the stress relaxation layer becomes softer than the resin interlayer insulating layer. For this reason, the external stress applied to the component can be relaxed by the stress relaxation layer.

  Here, examples of the inorganic material include so-called inorganic fillers. Examples of the inorganic filler include inorganic compound fillers and metal fillers. Among these, examples of the inorganic compound filler include ceramic fillers made of calcium carbonate, silicon oxide, aluminum oxide, talc, aluminum nitride, barium sulfate, and the like. Moreover, the dielectric filler which consists of barium titanate, strontium titanate, lead titanate, lead zirconate titanate, etc. is mentioned. As these inorganic fillers, only 1 type may be used and 2 or more types may be used together. Further, the shape of the filler is not particularly limited, and examples thereof include an indefinite shape, a spherical shape, a fiber shape, and a plate shape. As these fillers, only one kind may be used, or two or more kinds may be used in combination.

  When the stress relaxation layer is formed of a material different from that of the resin interlayer insulating layer, the elastic modulus at room temperature of the stress relaxation layer is preferably smaller than the elastic modulus at room temperature of the resin interlayer insulating layer. . In this way, the stress relaxation layer becomes a layer that is easily deformed by a stress smaller than that of the resin interlayer insulating layer, and therefore, the external stress applied to the component can be reliably relaxed by the stress relaxation layer. Specifically, the stress relaxation layer preferably has an elastic modulus at room temperature of 0.01 GPa or more and 1 GPa or less. If the elastic modulus at room temperature is set to less than 0.01 GPa, the stress relaxation layer will be deformed too much even with a small stress, and the dimensional stability of the wiring laminated portion laminated on the stress relaxation layer will be reduced. End up. On the other hand, if the elastic modulus at room temperature is set to be greater than 1 GPa, the stress relaxation layer is hardly deformed, so that there is a possibility that external stress applied to the component by the stress relaxation layer cannot be reliably relaxed. In addition, as a method of measuring the elastic modulus at room temperature of the stress relaxation layer, for example, a method defined in JIS C6481 can be cited. The room temperature here is 25 ° C.

  Similarly, when the stress relaxation layer is formed of a material different from that of the resin interlayer insulation layer, the elongation at break of the stress relaxation layer at room temperature is larger than the elongation at break of the resin interlayer insulation layer at room temperature. It is preferable. In this way, since the stress relaxation layer has a lower yield stress than the resin interlayer insulation layer, the external stress applied to the component can be reliably relaxed by the stress relaxation layer. Specifically, the stress relaxation layer preferably has a breaking elongation at room temperature of 10% or more. If the elongation at break at room temperature is less than 10%, the yield stress is large, so that there is a possibility that the external stress applied to the component by the stress relaxation layer cannot be reliably relaxed. Here, the yield stress refers to a stress at a point (yield point) that changes from a region that undergoes elastic deformation to a region that undergoes plastic deformation. When an external stress exceeding the yield stress is applied, the stress relaxation layer functions to plastically deform and relax the external stress. Examples of the method for measuring the elongation at break of the stress relaxation layer at room temperature include those defined in JIS C6481.

  When the stress relaxation layer is formed of a material different from that of the resin interlayer insulation layer, the thermal expansion coefficient of the stress relaxation layer should be set as described above for the elastic modulus and elongation at break at room temperature. There is no particular limitation. This is because the thermal expansion coefficient of the stress relaxation layer has little influence on the stress relaxation effect when the elastic modulus at room temperature and the elongation at break of the stress relaxation layer are in the region of the above physical property values.

As another means for solving the problem of the present invention (unit 2), it has a core main surface and the core back surface, a core board that have a receiving hole which opens at least the core main surface a the accommodation capacitor wiring board built for that will be accommodated in the hole portion of the capacitor main surface, and having a capacitor back surface and the capacitor side surface, a plurality of internal electrode layers are stacked via the ceramic dielectric layer a capacitor present having a structure, a resin as a main component, the capacitor main surface, wherein a capacitor back surface and the capacitor side stress relaxation layer formed on an inner wall surface of the accommodation hole of the core substrate wiring board built capacitor, wherein the fixed to the core substrate by a resin filling portion for filling the gap between the outer surface of the stress relaxation layer formed on the capacitor side and That.

  Therefore, according to the means 2, the external stress applied to the surface of the wiring board built-in capacitor is relieved by the stress relaxation layer formed on at least the capacitor main surface of the capacitor body while the wiring board built-in capacitor is built in the wiring board. Therefore, it is possible to prevent the occurrence of cracks near the surface of the capacitor body as in the prior art.

[First Embodiment]

  Hereinafter, a first embodiment in which a component-embedded wiring board of the present invention is embodied will be described in detail with reference to the drawings.

  As shown in FIG. 1, a component built-in wiring board (hereinafter referred to as “wiring board”) 10 of this embodiment is a wiring board for mounting an IC chip. The wiring substrate 10 includes a substantially rectangular plate-shaped core substrate 11, a first buildup layer 31 (wiring laminated portion) formed on the core main surface 12 (upper surface in FIG. 1) of the core substrate 11, and the core substrate 11. The second buildup layer 32 is formed on the core back surface 13 (the lower surface in FIG. 1).

  The first buildup layer 31 formed on the core main surface 12 of the core substrate 11 includes two resin interlayer insulating layers 33 and 35 made of a thermosetting resin (epoxy resin), a conductor layer 42 made of copper, It has the structure which laminated | stacked alternately. In this embodiment, the thermal expansion coefficient of the resin interlayer insulation layers 33 and 35 is about 10 to 60 ppm / ° C. (specifically, about 40 ppm / ° C.). In addition, the thermal expansion coefficient of the resin interlayer insulation layers 33 and 35 says the average value of the measured value between 30 degreeC-glass transition temperature (Tg). In addition, terminal pads 44 are formed in an array at a plurality of locations on the surface of the second (uppermost) resin interlayer insulating layer 35 in the first buildup layer 31. Further, a solder resist 37 is laminated on the resin interlayer insulation layer 35 so as to almost entirely cover the resin interlayer insulation layer 35. An opening 46 for exposing the terminal pad 44 is formed at a predetermined position of the solder resist 37. A plurality of solder bumps 45 are provided on the surface of the terminal pad 44. Each solder bump 45 is electrically connected to the surface connection terminal 22 of the IC chip 21 having a rectangular flat plate shape. Note that an area including the terminal pads 44 and the solder bumps 45 is an IC chip mounting area 23 on which the IC chip 21 can be mounted. The IC chip mounting area 23 is set on the surface 39 of the first buildup layer 31. In addition, via conductors 43 and 47 are provided in the resin interlayer insulating layers 33 and 35, respectively. These via conductors 43 and 47 electrically connect the conductor layer 42 and the terminal pad 44 to each other.

  As shown in FIG. 1, the second buildup layer 32 formed on the core back surface 13 of the core substrate 11 has substantially the same structure as the first buildup layer 31 described above. That is, the second buildup layer 32 has a structure in which two resin interlayer insulating layers 34 and 36 made of a thermosetting resin (epoxy resin) and a conductor layer 42 are alternately laminated. The thermal expansion coefficients of the insulating layers 34 and 36 are about 10 to 60 ppm / ° C. (specifically, about 40 ppm / ° C.). BGA pads 48 electrically connected to the conductor layer 42 through via conductors 43 are formed in a lattice pattern at a plurality of positions on the lower surface of the second resin interlayer insulating layer 36 in the second buildup layer 32. Has been. A solder resist 38 that covers the resin interlayer insulation layer 36 substantially entirely is laminated on the lower surface of the resin interlayer insulation layer 36. An opening 40 for exposing the BGA pad 48 is formed at a predetermined portion of the solder resist 38. On the surface of the BGA pad 48, a plurality of solder bumps 49 are provided for electrical connection with a mother board (not shown). The wiring board 10 shown in FIG. 1 is mounted on a mother board (not shown) by each solder bump 49.

  As shown in FIG. 1, the core substrate 11 of the present embodiment has a substantially rectangular plate shape in plan view of 25 mm long × 25 mm wide × 1.0 mm thick. The core substrate 11 has a thermal expansion coefficient in the plane direction (XY direction) of about 10 to 30 ppm / ° C. (specifically, 18 ppm / ° C.). In addition, the thermal expansion coefficient of the core board | substrate 11 says the average value of the measured value between 0 degreeC-glass transition temperature (Tg). The core substrate 11 includes a base material 161 made of glass epoxy, a sub-base material 164 formed on an upper surface and a lower surface of the base material 161 and made of an epoxy resin to which an inorganic filler such as silica filler is added, and an upper surface of the base material 161. And a conductor layer 163 made of copper and formed on the lower surface. In the core substrate 11, a plurality of through-hole conductors 16 are formed so as to penetrate the core main surface 12, the core back surface 13, and the conductor layer 163. The through-hole conductor 16 connects and conducts the core main surface 12 side and the core back surface 13 side of the core substrate 11 and is electrically connected to the conductor layer 163. The inside of the through-hole conductor 16 is filled with a closing body 17 such as an epoxy resin. The upper end of the through-hole conductor 16 is electrically connected to a part of the conductor layer 42 on the surface of the resin interlayer insulating layer 33, and the lower end of the through-hole conductor 16 is on the lower surface of the resin interlayer insulating layer 34. It is electrically connected to a part of a certain conductor layer 42. Further, a conductor layer 41 made of copper is patterned on the core main surface 12 and the core back surface 13 of the core substrate 11, and each conductor layer 41 is electrically connected to the through-hole conductor 16. Furthermore, the core substrate 11 has one rectangular accommodation hole 90 in a plan view that opens at the center of the core main surface 12 and the center of the core back surface 13. That is, the accommodation hole 90 is a through hole.

  And in the accommodation hole part 90, the ceramic capacitor 101 (component) which is a capacitor | condenser for wiring board shown in FIGS. 2-4 etc. is accommodated in the embedded state. The ceramic capacitor 101 is accommodated with the capacitor main surface 102 facing the same side as the core main surface 12 of the core substrate 11. The ceramic capacitor 101 of the present embodiment has a substantially rectangular plate shape in plan view with a length of 10.0 mm × width of 10.0 mm × thickness of 0.8 mm. The ceramic capacitor 101 is arranged in a region immediately below the IC chip mounting region 23 in the core substrate 11. The area of the IC chip mounting region 23 (the area of the surface on which the surface connection terminals 22 are formed in the IC chip 21) is set to be smaller than the area of the capacitor main surface 102 of the ceramic capacitor 101. When viewed from the thickness direction of the ceramic capacitor 101, the IC chip mounting region 23 is located in the capacitor main surface 102 of the ceramic capacitor 101.

  As shown in FIGS. 1 to 4 and the like, the ceramic capacitor 101 of this embodiment is a so-called via array type ceramic capacitor. A ceramic sintered body 104 (component main body, capacitor main body) constituting the ceramic capacitor 101 has one capacitor main surface 102 (upper surface in FIG. 1) as a component main surface and one capacitor back surface 103 (FIG. 1) as a component back surface. , And a plate-like object having four capacitor side surfaces 106 which are component side surfaces. In the present embodiment, the thermal expansion coefficient of the ceramic sintered body 104 is less than 15 ppm / ° C., specifically about 6 to 13 ppm / ° C. The thermal expansion coefficient of the ceramic sintered body 104 refers to an average value of measured values between 30 ° C. and 250 ° C.

  The ceramic sintered body 104 has a structure in which power supply internal electrode layers 141 (internal electrode layers) and ground internal electrode layers 142 (internal electrode layers) are alternately stacked via ceramic dielectric layers 105. Yes. The ceramic dielectric layer 105 is made of a sintered body of barium titanate, which is a kind of high dielectric constant ceramic, and functions as a dielectric (insulator) between the power internal electrode layer 141 and the ground internal electrode layer 142. To do. Each of the power supply internal electrode layer 141 and the ground internal electrode layer 142 is a layer formed mainly of nickel, and is disposed in every other layer in the ceramic sintered body 104.

  As shown in FIGS. 1 to 4, a large number of via holes 130 are formed in the ceramic sintered body 104. These via holes 130 penetrate the ceramic sintered body 104 in the thickness direction and are arranged in a lattice shape (array shape) over the entire surface of the ceramic sintered body 104. In each via hole 130, a plurality of in-capacitor via conductors 131 and 132 that communicate between the capacitor main surface 102 and the capacitor back surface 103 of the ceramic sintered body 104 are formed using nickel as a main material. Each power supply capacitor internal via conductor 131 passes through each power supply internal electrode layer 141 and electrically connects them to each other. Each ground capacitor via conductor 132 passes through each ground internal electrode layer 142 and electrically connects them to each other. Each power source capacitor via conductor 131 and each ground capacitor inner via conductor 132 are arranged in an array as a whole. In the present embodiment, for convenience of explanation, the via conductors 131 and 132 in the capacitor are illustrated in 5 columns × 5 columns, but there are actually more columns.

  2 and the like, a plurality of main surface side power supply electrodes 111 (surface layer electrodes) and a plurality of main surface side ground electrodes 112 (surface layer electrodes) are formed on the capacitor main surface 102 of the ceramic sintered body 104. ) And protruding. Each main surface side ground electrode 112 is individually formed on the capacitor main surface 102, but may be formed integrally. The main surface side power supply electrode 111 is directly connected to the end surface of the plurality of power supply capacitor internal via conductors 131 on the capacitor main surface 102 side, and the main surface side ground electrode 112 is connected to the plurality of ground capacitor internal electrodes. The via conductor 132 is directly connected to the end surface on the capacitor main surface 102 side.

  Further, on the capacitor back surface 103 of the ceramic sintered body 104, a plurality of back surface side power supply electrodes 121 (surface layer electrodes) and a plurality of back surface side ground electrodes 122 (surface layer electrodes) are projected. Each back surface side ground electrode 122 is individually formed on the capacitor back surface 103, but may be formed integrally. The back surface side power supply electrode 121 is directly connected to the end surface of the plurality of power supply capacitor internal via conductors 131 on the capacitor back surface 103 side, and the back surface side ground electrode 122 is connected to the plurality of ground internal capacitor capacitor via conductors 132. Is directly connected to the end surface on the capacitor back surface 103 side. Therefore, the power supply electrodes 111 and 121 are electrically connected to the power supply capacitor internal via conductor 131 and the power supply internal electrode layer 141, and the ground electrodes 112 and 122 are connected to the ground capacitor internal via conductor 132 and the ground internal electrode layer 142. Is conducting.

  As shown in FIG. 1, the electrodes 111 and 112 on the capacitor main surface 102 side include the via conductor 47, the conductor layer 42, the via conductor 43, the terminal pad 44, the solder bump 45, and the surface connection terminal 22 of the IC chip 21. Is electrically connected to the IC chip 21 via On the other hand, the electrodes 121 and 122 on the capacitor back surface 103 side pass through via conductors 47, conductor layers 42, via conductors 43, BGA pads 48, and solder bumps 49 with respect to electrodes (contactors) of a mother board (not shown). Are electrically connected.

  As shown in FIG. 2 and the like, the electrodes 111, 112, 121, and 122 are made of nickel as a main material, and the surface is entirely covered with a copper plating layer (not shown). These electrodes 111, 112, 121, 122 and the via conductors 131, 132 in the capacitor are disposed immediately below the substantially central portion of the IC chip 21. In the present embodiment, the diameters of the electrodes 111, 112, 121, and 122 are set to about 500 μm, and the minimum pitch length is set to about 580 μm.

  For example, when energization is performed from the motherboard side via the electrodes 121 and 122 and a voltage is applied between the power supply internal electrode layer 141 and the ground internal electrode layer 142, for example, positive charges are accumulated in the power supply internal electrode layer 141. For example, negative charges accumulate in the ground internal electrode layer 142. As a result, the ceramic capacitor 101 functions as a capacitor.

  As shown in FIGS. 1 to 4 and the like, the ceramic capacitor 101 has a stress relaxation layer 151. Specifically, the stress relaxation layer 151 is formed on the one capacitor main surface 102, the one capacitor back surface 103, and the four capacitor side surfaces 106, respectively. Further, the thickness of the stress relaxation layer 151 formed on the capacitor main surface 102 and the capacitor back surface 103 is formed thinner than the resin interlayer insulating layers 33 to 36, and is set to 15 μm in this embodiment. Yes. Furthermore, the thickness of the stress relaxation layer 151 formed on the capacitor side surface 106 is set to 15 μm, which is the same as the thickness of the stress relaxation layer 151 formed on the capacitor main surface 102 and the capacitor back surface 103. A lowermost resin interlayer insulating layer 33 in the first buildup layer 31 is laminated on the stress relaxation layer 151 formed on the capacitor main surface 102, and the stress relaxation layer formed on the capacitor back surface 103. On top of 151, an uppermost resin interlayer insulation layer 34 in the second buildup layer 32 is laminated. Further, the core substrate 11 is located on the outer surface side of the stress relaxation layer 151 formed on the capacitor side surface 106.

  The stress relaxation layer 151 shown in FIGS. 1 to 4 and the like is mainly formed of a resin material made of a thermosetting resin. In this embodiment, the resin material is made of an epoxy resin, a phenol resin, and a polyolefin resin (elastomer component) (TLF-Y manufactured by Yodogawa Paper Mill). The elastic modulus at room temperature of the stress relaxation layer 151 is smaller than the elastic modulus at room temperature (7 GPa in the present embodiment) of the resin interlayer insulating layers 33 to 36, and is specifically set to 0.03 GPa. Furthermore, the elongation at break of the stress relaxation layer 151 at room temperature is larger than the elongation at break of the resin interlayer insulating layers 33 to 36 at room temperature (5% in the present embodiment), specifically 210%. ing. Further, the weight (wt%) per unit volume of the inorganic material contained in the stress relaxation layer 151 is less than the weight (wt%) per unit volume of the inorganic material contained in the resin interlayer insulating layers 33 to 36. In the embodiment, it is 0 wt%. Similarly, the volume ratio (vol%) occupied by the inorganic material in the stress relaxation layer 151 is also smaller than the volume ratio (vol%) occupied by the inorganic material in the resin interlayer insulating layers 33 to 36, and 0 vol% in this embodiment. It has become. That is, the stress relaxation layer 151 of this embodiment does not contain any inorganic material.

  As shown in FIG. 1 and the like, the gap between the inner wall surface 91 of the accommodation hole 90 in the core substrate 11 and the outer surface of the stress relaxation layer 151 formed on the capacitor side surface 106 of the ceramic capacitor 101 is high. It is filled with a resin filling portion 92 made of a molecular material (in this embodiment, a thermosetting resin such as epoxy). The resin filling portion 92 has a function of fixing the ceramic capacitor 101 to the core substrate 11.

  Next, a method for manufacturing the wiring board 10 of this embodiment will be described.

  In the core substrate preparation step, an intermediate product of the core substrate 11 is prepared by a conventionally known technique and prepared in advance.

  The intermediate product of the core substrate 11 is manufactured as follows. First, a copper clad laminate (see FIG. 5) in which a copper foil 162 is attached to both surfaces of a base material 161 having a length of 350 mm, a width of 375 mm, and a thickness of 0.6 mm is prepared. Next, the copper foil 162 on both sides of the copper-clad laminate is etched to pattern the conductor layer 163 by, for example, a subtractive method (see FIG. 6). Specifically, after the electroless copper plating, electrolytic copper plating is performed using the electroless copper plating layer as a common electrode. Further, the dry film is laminated, and the dry film is exposed and developed to form a dry film in a predetermined pattern. In this state, unnecessary electrolytic copper plating layer, electroless copper plating layer and copper foil 162 are removed by etching. Thereafter, the dry film is peeled off. Next, after roughening the upper and lower surfaces of the base material 161 and the conductor layer 163, an epoxy resin film (thickness of 80 μm) to which an inorganic filler has been added is attached to the upper and lower surfaces of the base material 161 by thermocompression bonding. Then, the sub-base material 164 is formed (see FIG. 7).

  Next, a conductor layer 41 (for example, 50 μm) is formed on the upper surface of the upper sub-base material 164 and the lower surface of the lower sub-base material 164, respectively. Specifically, after performing electroless copper plating on the upper surface of the upper sub-base material 164 and the lower surface of the lower sub-base material 164, an etching resist is formed, and then electrolytic copper plating is performed. Further, the etching resist is removed and soft etching is performed. Next, the laminated body composed of the base material 161 and the sub base material 164 is drilled using a router to form through holes to be the accommodation hole portions 90 at predetermined positions. (See FIG. 8). The intermediate product of the core substrate 11 is a multi-piece core substrate having a structure in which a plurality of regions to be the core substrate 11 are arranged vertically and horizontally along the plane direction.

  In the capacitor preparation step, the ceramic capacitor 101 is prepared by a conventionally known method and prepared in advance.

  The ceramic capacitor 101 is manufactured as follows. That is, a ceramic green sheet is formed, and nickel paste for internal electrode layers is screen printed on the green sheet and dried. As a result, a power internal electrode portion that will later become the power internal electrode layer 141 and a ground internal electrode portion that will be the ground internal electrode layer 142 are formed. Next, the green sheets with the power supply internal electrode portions and the green sheets with the ground internal electrode portions are alternately stacked, and each green sheet is integrated by applying a pressing force in the sheet stacking direction. To form a green sheet laminate.

  Further, a number of via holes 130 are formed through the green sheet laminate using a laser processing machine, and a via conductor nickel paste is filled into each via hole 130 using a paste press-fitting and filling device (not shown). Next, a paste is printed on the upper surface of the green sheet laminate, and the main surface side power supply electrode 111 and the main surface side ground electrode 112 so as to cover the upper end surface of each conductor portion on the upper surface side of the green sheet laminate. Form. Further, a paste is printed on the lower surface of the green sheet laminate, and the back-side power supply electrode 121 and the back-side ground electrode 122 are formed so as to cover the lower end surface of each conductor portion on the lower surface side of the green sheet laminate. .

  Thereafter, the green sheet laminate is dried to solidify the electrodes 111, 112, 121, and 122 to some extent. Next, the green sheet laminate is degreased and fired at a predetermined temperature for a predetermined time. As a result, barium titanate and nickel in the paste are simultaneously sintered to form a ceramic sintered body 104.

  Next, electroless copper plating (thickness of about 10 μm) is performed on each electrode 111, 112, 121, 122 included in the obtained ceramic sintered body 104. As a result, a copper plating layer is formed on each of the electrodes 111, 112, 121, 122, and the ceramic capacitor 101 is completed.

  In the subsequent stress relaxation layer forming step, after the capacitor main surface 102 of the completed ceramic capacitor 101 is roughened, a plurality of ceramic capacitors 101 are formed on the capacitor main surface 102 using a mounting device (manufactured by Yamaha Motor Co., Ltd.). Set it on a jig (not shown) in the above state. More specifically, a peelable adhesive tape 172 is disposed on the jig, and each ceramic capacitor 101 is affixed to the adhesive surface of the adhesive tape 172 and temporarily fixed (see FIG. 9). At this time, the ceramic capacitors 101 are spaced apart from each other along the adhesive surface in a state of being disposed in parallel with the adhesive surface of the adhesive tape 172.

  Next, a resin film 173 (thickness: 800 μm) that becomes a part of the uncured stress relaxation layer 151 is laminated on each ceramic capacitor 101 set in a jig (see FIGS. 10 and 11). At this time, a part of the resin film 173 is filled between the capacitor side surfaces 106 of the ceramic capacitors 101 adjacent to each other. Further, a part of the resin film 173 filled between the capacitor side surfaces 106 is filled between the adhesive tape 172 and the capacitor back surface 103 of the ceramic capacitor 101. It can be understood that the product in this state is an intermediate product of a capacitor board built-in capacitor assembly in which a plurality of product regions to be the ceramic capacitor 101 having the stress relaxation layer 151 are arranged vertically and horizontally along the plane direction. it can. At this point, the adhesive tape 172 is peeled off.

  Furthermore, using a mounting device (manufactured by Yamaha Motor Co., Ltd.), set the intermediate product of the capacitor assembly with built-in wiring board on a jig (not shown) with the capacitor back surface 103 of each ceramic capacitor 101 facing up. To do. More specifically, a peelable adhesive tape 175 is disposed on the jig, and the intermediate product of the wiring board built-in capacitor assembly is attached to the adhesive surface of the adhesive tape 175 and temporarily fixed ( (See FIG. 12).

  Next, a resin film 176 (thickness: 15 μm) that becomes a part of the uncured stress relaxation layer 151 is laminated on the intermediate product of the capacitor assembly for wiring board built in the jig (FIG. 12, FIG. 13). Thereafter, when heat treatment (curing) is performed for a predetermined time, the resin film 173 is cured at the same time, the resin film 176 is cured, and the resin film 173 and the resin film 176 become familiar with each other and become a stress relaxation layer 151 ( (See FIG. 13). It can be understood that the product in this state is a capacitor assembly 174 with a built-in wiring board in which a plurality of product regions to be the ceramic capacitor 101 having the stress relaxation layer 151 are arranged vertically and horizontally along the plane direction. Further, the wiring board built-in capacitor assembly 174 is divided using a laser processing machine. Specifically, the wiring board built-in capacitor aggregate 174 is divided into individual pieces by dividing the portion of the stress relaxation layer 151 filled between the capacitor side surfaces 106 of the ceramic capacitors 101 adjacent to each other (see the one-dot chain line in FIG. 13). Turn into. At that time, cutting is performed so that a stress relaxation layer 151 having a thickness of 15 μm is formed on each capacitor side surface 106. As a result, a large number of ceramic capacitors 101 each having the stress relaxation layer 151 formed on the capacitor main surface 102, the capacitor back surface 103, and the capacitor side surface 106 can be obtained simultaneously. At this time, the adhesive tape 175 is peeled off.

  In the subsequent housing step, the ceramic capacitors 101 are housed in the plurality of housing holes 90 using a mounting device (manufactured by Yamaha Motor Co., Ltd.) (see FIG. 14). At this time, the core back surface 13 side opening of each accommodation hole 90 is sealed with a peelable adhesive tape 171. The adhesive tape 171 is supported by a support base (not shown). The ceramic capacitor 101 is affixed and temporarily fixed to the adhesive surface of the adhesive tape 171.

  Thereafter, the resin filling portion 92 fills the gap between the inner wall surface 91 of the accommodation hole 90 and the outer surface of the stress relaxation layer 151 formed on the capacitor side surface 106 (see FIG. 15). Thereafter, when heat treatment is performed, the resin filling portion 92 is cured and the ceramic capacitor 101 is fixed to the core substrate 11. At this point, the adhesive tape 171 is peeled off.

  Next, the first buildup layer 31 is formed on the core main surface 12 and the second buildup layer 32 is formed on the core back surface 13 based on a conventionally known method. Specifically, a photosensitive epoxy resin is deposited on the core main surface 12 and the stress relaxation layer 151 formed on the capacitor main surface 102, and exposure and development are performed. (See FIG. 16). Further, a photosensitive epoxy resin is deposited on the core back surface 13 and the stress relaxation layer 151 formed on the capacitor back surface 103, and exposure and development are performed to form the resin interlayer insulating layer 34 (FIG. 16).

  Next, laser drilling is performed using a YAG laser or a carbon dioxide gas laser to form via holes 181 and 182 at positions where via conductors 47 are to be formed (see FIG. 17). Specifically, a via hole 181 passing through the resin interlayer insulating layer 33 and the stress relaxation layer 151 formed on the capacitor main surface 102 is formed, and the main surface side power supply electrode 111 and the main surface side ground electrode are formed. 112 is exposed. Similarly, a via hole 182 is formed through the resin interlayer insulating layer 34 and the stress relaxation layer 151 formed on the capacitor back surface 103 to expose the back side power supply electrode 121 and the back side ground electrode 122.

  Further, drilling is performed using a drill machine, and a through hole 191 that penetrates the core substrate 11 and the resin interlayer insulating layers 33 and 34 is formed in advance at a predetermined position (see FIG. 18). Then, after performing electroless copper plating on the resin interlayer insulating layers 33 and 34, the inner surfaces of the via holes 181 and 182 and the inner surfaces of the through holes 191, an etching resist is formed, and then electrolytic copper plating is performed. Further, the etching resist is removed and soft etching is performed. Thereby, the conductor layer 42 is patterned on the resin interlayer insulation layer 33 and the resin interlayer insulation layer 34 (see FIG. 19). At the same time, the through-hole conductor 16 is formed in the through hole 191, and the via conductor 47 is formed in each via hole 181, 182.

  Thereafter, a hole filling process is performed. Specifically, the cavity of the through-hole conductor 16 is filled with an insulating resin material (epoxy resin) to form the closing body 17 (see FIG. 20).

  Next, a photosensitive epoxy resin is deposited on the resin interlayer insulation layers 33 and 34, and exposure and development are performed, whereby the resin interlayer insulation layer having via holes 183 and 184 at positions where the via conductors 43 are to be formed. 35 and 36 are formed (see FIG. 20). Instead of depositing the photosensitive epoxy resin, an insulating resin or a liquid crystal polymer may be deposited. In this case, via holes 183 and 184 are formed at positions where the via conductors 43 are to be formed by a laser processing machine or the like. Next, electrolytic copper plating is performed according to a conventionally known method to form via conductors 43 in the via holes 183 and 184, and terminal pads 44 are formed on the resin interlayer insulating layer 35, and the resin interlayer insulating layer 36 is formed. A BGA pad 48 is formed thereon.

  Next, solder resists 37 and 38 are formed by applying and curing a photosensitive epoxy resin on the resin interlayer insulation layers 35 and 36. Next, exposure and development are performed with a predetermined mask placed, and the openings 40 and 46 are patterned in the solder resists 37 and 38. Further, solder bumps 45 are formed on the terminal pads 44 and solder bumps 49 are formed on the BGA pads 48. It can be understood that the product in this state is a multi-cavity wiring board in which a plurality of product regions to be the wiring board 10 are arranged vertically and horizontally along the plane direction. Furthermore, when the multi-cavity wiring board is divided, a large number of wiring boards 10 which are individual products can be obtained simultaneously.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) According to the wiring substrate 10 of the present embodiment, the ceramic capacitor 101 is built in the wiring substrate 10 by the stress relaxation layer 151 formed on the capacitor main surface 102, the capacitor back surface 103, and the capacitor side surface 106. The external stress applied to the surface of the ceramic capacitor 101 can be relaxed (specifically, when the ceramic capacitor 101 is built in the wiring board 10 and when the completed wiring board 10 is used). . Therefore, it is possible to prevent the occurrence of cracks 210 (see FIG. 36) near the surface of the ceramic capacitor 101 as in the prior art. Therefore, the wiring board 10 excellent in reliability can be obtained.

  (2) In this embodiment, the stress relaxation layer 151 is formed on all of the capacitor main surface 102, the capacitor back surface 103, and the capacitor side surface 106. As a result, not only the stress relaxation layer 151 formed on the capacitor main surface 102 but also the stress relaxation layer 151 formed on the capacitor back surface 103 can relieve external stress applied in the thickness direction of the ceramic capacitor 101. The occurrence of cracks in the ceramic sintered body 104 can be more reliably prevented. In addition, the external stress applied in the plane direction of the ceramic capacitor 101 can be relaxed by the stress relaxation layer 151 formed on the capacitor main surface 102 and the capacitor back surface 103, and the stress relaxation layer 151 formed on the capacitor side surface 106 can be used. External stress applied in the thickness direction of the ceramic capacitor 101 can also be relaxed. For this reason, generation | occurrence | production of the crack in the ceramic sintered compact 104 can be prevented much more reliably.

  (3) In this embodiment, since the ceramic capacitor 101 is disposed immediately below the IC chip 21 mounted in the IC chip mounting region 23, the electrical path between the ceramic capacitor 101 and the IC chip 21 is shortened, and the inductance component is reduced. Increase is prevented. Therefore, the switching noise of the IC chip 21 due to the ceramic capacitor 101 can be reliably reduced, and the power supply voltage can be reliably stabilized. In addition, since noise entering between the IC chip 21 and the ceramic capacitor 101 can be suppressed to a very low level, high reliability can be obtained without causing malfunction such as malfunction.

(4) In the present embodiment, since the stress relaxation layer 151 relieves external stress, the first buildup layer 31 stacked on the stress relaxation layer 151 is difficult to deform. The external stress applied to the IC chip 21 mounted on the board can also be relaxed. Therefore, the IC chip 21 is considered to be a large IC chip of 10 mm square or more, which has a large stress (strain) due to a difference in thermal expansion and is greatly affected by thermal stress, and has a large calorific value and severe thermal shock during use. A low-k (low dielectric constant) IC chip can be used.
[Second Embodiment]

  Hereinafter, a second embodiment in which the component built-in wiring board of the present invention is embodied will be described in detail with reference to the drawings. Here, the description will focus on the parts that are different from the first embodiment, and the common parts will not be described in place of the same member numbers.

  The wiring board 10 of the present embodiment is different from the ceramic capacitor 101 of the first embodiment in the configuration of the ceramic capacitor. That is, as shown in FIG. 21, the ceramic sintered bodies 104 constituting the ceramic capacitor 195 (component, capacitor for wiring board built-in) of this embodiment are formed on the capacitor main surface 102 and the capacitor back surface 103, respectively. The stress relaxation layer 152 is provided.

  The stress relaxation layer 152 has a contact surface 153 that contacts the ceramic sintered body 104 and an outer surface 154 that is located on the opposite side of the contact surface 153. The stress relaxation layer 152 is provided with a plurality of conductor columns 155 that penetrate the contact surface 153 side and the outer surface 154 side. A plurality of terminal pads 156 are disposed on the outer surface 154 of the stress relaxation layer 152. Each terminal pad 156 is electrically connected to the end surface of each conductor post 155 on the outer surface 154 side. Furthermore, in the stress relaxation layer 152 formed on the capacitor main surface 102, the end surface on the contact surface 153 side of each conductor column 155 is electrically connected to the main surface side power supply electrode 111 and the main surface side ground electrode 112. Has been. Further, in the stress relaxation layer 152 formed on the capacitor back surface 103, the end surface on the contact surface 153 side of each conductor column 155 is electrically connected to the back surface side power supply electrode 121 and the back surface side ground electrode 122. . As a result, the terminal pad 156 and the electrodes 111, 112, 121, 122 are conducted through the conductor pillar 155.

  Next, a method for manufacturing the wiring board 10 of this embodiment will be described.

  First, after performing the same preparatory steps (core substrate preparatory step and capacitor preparatory step) as in the first embodiment, a stress relaxation layer forming step is performed. In the stress relaxation layer forming step, after the capacitor main surface 102 and the capacitor back surface 103 of the completed ceramic capacitor 195 are roughened, a plurality of ceramic capacitors 195 are formed by using a mounting device (manufactured by Yamaha Motor Co., Ltd.). Set on a jig (not shown) with the surface 102 facing up. Next, a resin film 157 (thickness: 15 μm) to be the stress relaxation layer 152 is laminated on the capacitor main surface 102 of each ceramic capacitor 195 set in the jig (see FIG. 22). Further, using a mounting device (manufactured by Yamaha Motor Co., Ltd.), each ceramic capacitor 195 is set on a jig (not shown) with the capacitor back surface 103 facing upward. Next, a resin film 157 (thickness 15 μm) is laminated on the capacitor back surface 103 of each ceramic capacitor 195 set in a jig (see FIG. 22). Thereafter, heat treatment (curing) is performed for a predetermined time to cure each resin film 157.

  Next, laser drilling is performed using any one of a YAG laser, a carbon dioxide gas laser, and an excimer laser to form via holes 158 at positions where the conductor pillars 155 are to be formed (see FIG. 23). Specifically, a via hole 158 that penetrates the stress relaxation layer 152 formed on the capacitor main surface 102 is formed to expose the main surface side power supply electrode 111 and the main surface side ground electrode 112. Similarly, a via hole 158 penetrating the stress relaxation layer 152 formed on the capacitor back surface 103 is formed, and the back surface side power supply electrode 121 and the back surface side ground electrode 122 are exposed.

  Then, electrolytic copper plating is performed on the inner surface of the via hole 158 via the stress relaxation layer 152 to form the conductor pillar 155 on each of the electrodes 111, 112, 121, 122 (see FIG. 24). Alternatively, the conductive pillar 155 may be formed by printing a conductive paste such as a copper paste on each of the electrodes 111, 112, 121, and 122 and then drying it at a predetermined temperature for a predetermined time. Further, after performing electroless copper plating on the stress relaxation layer 152, an etching resist is formed, and then electrolytic copper plating is performed. Further, the etching resist is removed and soft etching is performed. Thereby, a plurality of terminal pads 156 are formed on the outer surface 154 of the stress relaxation layer 152, and the ceramic capacitor 195 having the stress relaxation layer 152 is completed. Each terminal pad 156 may be formed by sputtering.

  After that, if a housing process is performed so that the ceramic capacitor 101 is housed in the core substrate 11 prepared in the core substrate preparing process and the build-up layers 31 and 32 are formed based on a conventionally known technique, the wiring substrate 10 is obtained. Is completed.

  Therefore, according to the present embodiment, the conductor portions (electrodes 111 and 112) of the ceramic capacitor 101 and the conductor portions (via conductor 47 and conductor layer 42) in the lowermost resin interlayer insulating layer 33 in the first buildup layer 31. Can be reliably connected via the conductor portions (conductor pillars 155 and terminal pads 156) included in the stress relaxation layer 151 formed on the capacitor main surface 102. Similarly, the conductor portions (electrodes 121 and 122) of the ceramic capacitor 101 and the conductor portions (via conductor 47 and conductor layer 42) in the uppermost resin interlayer insulating layer 34 in the second buildup layer 32 are connected to the back surface of the capacitor. The stress relaxation layer 151 formed on the conductor 103 can be securely connected via the conductor portions (conductor pillars 155 and terminal pads 156). Therefore, it is possible to obtain the wiring board 10 with even higher reliability.

  In addition, you may change embodiment of this invention as follows.

  In the above embodiments, the stress relaxation layers 151 and 152 are mainly formed of a resin material made of a thermosetting resin (TLF-Y manufactured by Yodogawa Paper Mill). However, the stress relaxation layers 151 and 152 may be formed mainly of another resin material having an elastic modulus at room temperature of 0.01 GPa or more and 1 GPa or less and an elongation at break of 10% or more at room temperature.

  For example, the stress relaxation layers 151 and 152 may be formed mainly of a resin material made of epoxy resin and polyamide resin (KS-7003 manufactured by Hitachi Chemical Co., Ltd.). In this case, the elastic modulus at room temperature is 1 GPa, and the elongation at break at room temperature is 120%.

  In the second embodiment, the stress relaxation layer 152 is directly formed on the capacitor main surface 102 and the capacitor back surface 103 of the ceramic capacitor 195. However, the stress relaxation layer 152 may be formed separately from the ceramic capacitor 195, and the formed stress relaxation layer 152 may be adhered to the capacitor main surface 102 and the capacitor back surface 103.

  That is, a resin film 159 having a length of 10 mm × width of 10 mm × thickness of 15 μm is prepared (see FIG. 25). Next, laser drilling is performed using any one of a YAG laser, a carbon dioxide gas laser, and an excimer laser to form via holes 160 at positions where the conductor pillars 155 are to be formed (see FIG. 26). The via hole 160 may be formed by drilling using a microcomputer punch or a mechanical drill. Then, electrolytic copper plating is performed on the inner surface of the via hole 160 to form a conductor column 155 in each via hole 160 (see FIG. 27). Note that the conductive pillar 155 may be formed by printing a conductive paste such as a copper paste and then drying it at a predetermined temperature for a predetermined time. Further, after performing electroless copper plating on the stress relaxation layer 152, an etching resist is formed, and then electrolytic copper plating is performed. Further, the etching resist is removed and soft etching is performed. Thereby, a plurality of terminal pads 156 are formed on the outer surface 154 of the stress relaxation layer 152, and the stress relaxation layer 152 is completed (see FIG. 28). Each terminal pad 156 may be formed by sputtering. Thereafter, when the completed stress relaxation layer 152 is laminated on the capacitor main surface 102 and the capacitor back surface 103, the ceramic capacitor 195 having the stress relaxation layer 152 is completed.

  Further, the stress relaxation layer 152 may be formed by a method different from the above. That is, a copper clad laminate (see FIG. 29) in which a copper foil 222 is bonded to one side of a base 221 having a length of 10 mm, a width of 10 mm, and a thickness of 15 μm is prepared. Next, the copper foil 222 on one side of the copper-clad laminate is etched to pattern the terminal pads 156 by, for example, a subtractive method (see FIG. 30). Specifically, after the electroless copper plating, electrolytic copper plating is performed using the electroless copper plating layer as a common electrode. Further, the dry film is laminated, and the dry film is exposed and developed to form a dry film in a predetermined pattern. In this state, unnecessary electrolytic copper plating layer, electroless copper plating layer and copper foil 222 are removed by etching. Thereafter, the dry film is peeled off. Note that the terminal pad 156 may be patterned by performing a semi-additive method. Next, laser drilling is performed using any one of a YAG laser, a carbon dioxide laser, and an excimer laser to form via holes 223 at positions where the conductor pillars 155 are to be formed (see FIG. 31). The via hole 223 may be formed by drilling using a mechanical drill. Further, the via hole 223 may be formed before the terminal pad 156 is patterned. When electrolytic copper plating (or printing of conductive paste on the back surface of each terminal pad 156) is performed on the inner surface of the via hole 223, the conductive pillar 155 is formed in each via hole 223, and the stress relaxation layer 152 is formed. Is completed (see FIG. 28).

  In each of the above embodiments, the stress relaxation layers 151 and 152 are formed before the ceramic capacitor 101 is accommodated in the accommodation hole 90. However, the stress relaxation layers 151 and 152 may be formed after the ceramic capacitor 101 is accommodated in the accommodation hole 90. In this case, the stress relaxation layers 151 and 152 may be formed only on the capacitor main surface 102 (see FIG. 32), or may be formed on the core main surface 12 in addition to the capacitor main surface 102. It is also possible (see FIG. 33). Similarly, the stress relaxation layers 151 and 152 may be formed on the capacitor back surface 103 (see FIG. 32), or may be formed on the core back surface 13 in addition to the capacitor back surface 103 (see FIG. 32). 33).

  -Although the conductor pillar 155 with which the stress relaxation layer 152 of the said 2nd Embodiment is provided was a filled via (via of the form completely filled with copper plating) formed by electrolytic copper plating, it is formed by electrolytic copper plating. Conformal vias (vias that are not completely filled with copper plating) may be used.

  In the above embodiments, the ceramic capacitor 101 is housed in the core substrate 11. However, the ceramic capacitor 101 of each of the above embodiments may be accommodated in the buildup layer. In this way, the conduction path for electrically connecting the IC chip 21 and the ceramic capacitor 101 is shortened as compared with the case where the ceramic capacitor 101 is accommodated in the core substrate 11. As a result, an increase in the inductance component is prevented, so that the switching noise of the IC chip 21 can be reliably reduced by the ceramic capacitor 101 and the power supply voltage can be reliably stabilized. In addition, since noise entering between the IC chip 21 and the ceramic capacitor 101 can be suppressed to a very low level, high reliability can be obtained without causing malfunction such as malfunction. Since the ceramic capacitor 101 itself is thick, in FIG. 34, the build-up layer includes a first build-up layer 310 (wiring laminated portion) composed of more resin interlayer insulating layers (resin interlayer insulating layer 30) than in the above embodiments. ). In addition, you may accommodate the ceramic capacitor 101 of each said embodiment in the same 1st buildup layer 31 as each said embodiment.

  In each of the above embodiments, the gap between the inner wall surface 91 of the accommodation hole 90 and the outer surface of the stress relaxation layer 151 is filled using the resin filling portion 92 different from the resin interlayer insulating layer 33. However, the gap may be filled using part of the resin insulating layer 33. In this way, it is not necessary to prepare a material different from the resin interlayer insulating layer 33 when forming the resin filling portion. Therefore, since the material necessary for manufacturing the wiring board 10 is reduced, the cost of the wiring board 10 can be reduced.

  Next, the technical ideas grasped by the embodiment described above are listed below.

  (1) A core substrate having a core main surface and a core back surface and having an accommodation hole opening at least in the core main surface, a component main body having a component main surface, a component back surface, and a component side surface, and resin. And at least a stress relaxation layer formed on the component main surface, the component housed in the housing hole with the core main surface and the component main surface facing the same side, and a resin layer A wiring laminate having a structure in which an insulating layer and a conductor layer are laminated on the core main surface and the stress relaxation layer, and the wiring laminate on the stress relaxation layer formed on the component main surface. The lowermost resin interlayer insulation layer is laminated, and a solder resist covering the uppermost resin interlayer insulation layer is laminated on the uppermost resin interlayer insulation layer in the wiring laminate portion. Built-in wiring board.

  (2) A core substrate having a core main surface and a core back surface and having an accommodation hole opening at least in the core main surface, a component main body having a component main surface, a component back surface and a component side surface, and resin And having at least a stress relaxation layer formed on the component main surface and the component side surface, and accommodated in the accommodating hole portion with the core main surface and the component main surface facing the same side. An outer surface of a stress relaxation layer formed on the side surface of the component, comprising: a component; and a wiring laminated portion having a structure in which a resin interlayer insulating layer and a conductor layer are stacked on the core main surface and the stress relaxation layer The core substrate is disposed on the side, and a resin filling portion that fills the gap in the gap between the inner wall surface of the accommodation hole in the core substrate and the outer surface of the stress relaxation layer formed on the side surface of the component Inside a part characterized by being placed Wiring board.

1 is a schematic sectional view showing a wiring board according to a first embodiment embodying the present invention. Similarly, the schematic sectional drawing which shows a ceramic capacitor. Similarly, the schematic explanatory drawing for demonstrating the connection in the inner layer of a ceramic capacitor. Similarly, the schematic explanatory drawing for demonstrating the connection in the inner layer of a ceramic capacitor. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board. The schematic sectional drawing which shows the ceramic capacitor in 2nd Embodiment. Similarly, explanatory drawing of the manufacturing method of a ceramic capacitor. Similarly, explanatory drawing of the manufacturing method of a ceramic capacitor. Similarly, explanatory drawing of the manufacturing method of a ceramic capacitor. Explanatory drawing of the manufacturing method of the stress relaxation layer in other embodiment. Explanatory drawing of the manufacturing method of the stress relaxation layer in other embodiment. Explanatory drawing of the manufacturing method of the stress relaxation layer in other embodiment. Explanatory drawing of the manufacturing method of the stress relaxation layer in other embodiment. Explanatory drawing of the manufacturing method of the stress relaxation layer in other embodiment. Explanatory drawing of the manufacturing method of the stress relaxation layer in other embodiment. Explanatory drawing of the manufacturing method of the stress relaxation layer in other embodiment. Explanatory drawing of the manufacturing method of the wiring board in other embodiment. Explanatory drawing of the manufacturing method of the wiring board in other embodiment. The principal part sectional view showing the wiring board in other embodiments. The schematic sectional drawing which shows an example of the ceramic capacitor in a prior art. Similarly, the expanded sectional view which shows the crack of the surface vicinity of a ceramic capacitor.

Explanation of symbols

10 ... Wiring board with built-in components (wiring board)
DESCRIPTION OF SYMBOLS 11 ... Core board | substrate 12 ... Core main surface 13 ... Core back surface 31,310 ... 1st buildup layers 30, 33, 35 as wiring lamination | stacking part ... Resin interlayer insulation layer 42 ... Conductor layer 90 ... Accommodating hole part 101,195 ... Ceramic capacitor 102 as capacitor for component and wiring board built-in capacitor main surface 103 as component main surface ... Capacitor back surface 104 as component back surface ... Ceramic sintered body 105 as component body and capacitor body ... Ceramic dielectric layer 106 ... Capacitor side surface 111 as a component side surface ... Main surface side power supply electrode 112 as a surface layer electrode ... Main surface side ground electrode 121 as a surface layer electrode ... Back surface side power supply electrode 122 as a surface layer electrode ... Back surface side ground as a surface layer electrode Electrode 131... Power supply capacitor via conductor 132 as capacitor via conductor 132. Via capacitor conductor for ground 141 as via conductor in sensor ... Internal electrode layer for power supply 142 as internal electrode layer ... Internal electrode layers for ground 151, 152 as internal electrode layer ... Stress relaxation layer 153 ... Contact surface 154 ... Outside Surface 155 ... Conductor post 156 ... Terminal pad

Claims (16)

A core substrate having a core main surface and a core back surface and having an accommodation hole opening at least in the core main surface;
Component main component body having a component backside and parts side surfaces, and a resin mainly has the upper component main, the component on the back surface and the stress relaxation layer formed on the part sides, said core main A component housed in the housing hole with the surface and the component main surface facing the same side;
The resin interlayer insulating layer and a conductor layer and a wiring laminated portion having a laminated structure in said core main surface and the stress relaxation layer,
A resin filling portion that fills the gap is disposed in a gap between an inner wall surface of the accommodation hole in the core substrate and an outer surface of a stress relaxation layer formed on the side surface of the component. Wiring board with built-in components.   The weight per unit volume of the inorganic material contained in the stress relaxation layer is less than the weight per unit volume of the inorganic material contained in the resin interlayer insulation layer, and the proportion of the volume occupied by the inorganic material in the stress relaxation layer is 2. The component built-in wiring board according to claim 1, wherein the volume ratio of the inorganic material in the resin interlayer insulating layer is less than the volume ratio. The component built-in wiring board according to claim 1, wherein the resin filling portion that fills the gap includes a part of the resin interlayer insulating layer.   The stress relaxation layer includes a contact surface that contacts the component main body, an outer surface that is located on the opposite side of the contact surface, a plurality of conductor columns that conduct the contact surface side and the outer surface side, and the outer surface. 4. The component built-in wiring board according to claim 1, further comprising a plurality of terminal pads arranged on the top and connected to the plurality of conductor pillars. 5.   5. The component built-in wiring board according to claim 1, wherein an elastic modulus at room temperature of the stress relaxation layer is smaller than an elastic modulus at room temperature of the resin interlayer insulating layer.   6. The component built-in wiring board according to claim 1, wherein the stress relaxation layer has a breaking elongation rate at room temperature larger than a breaking elongation rate at room temperature of the resin interlayer insulating layer. .   The stress relaxation layer has an elastic modulus at room temperature of 0.01 GPa or more and 1 GPa or less, and an elongation at break of 10% or more at room temperature. Component built-in wiring board.   The component built-in wiring board according to claim 1, wherein the stress relaxation layer is thinner than the resin interlayer insulating layer.   The component built-in wiring board according to claim 1, wherein the stress relaxation layer has a thickness of 5 μm to 30 μm. The parts are
Having a structure in which a plurality of internal electrode layers are laminated via a ceramic dielectric layer;
A plurality of via conductors in the capacitor connected to the plurality of internal electrode layers;
A plurality of surface layer electrodes connected to at least an end of the component main surface in the plurality of via conductors in the capacitor, and a via array type ceramic in which the plurality of via conductors in the capacitor are arranged in an array as a whole. 10. The component built-in wiring board according to claim 1, wherein the wiring board is a capacitor. Have a core main surface and the core rear surface, and at least the core the housing wiring board built capacitor that will be accommodated in the hole portion of the substrate to have a housing opening portion which opens at the core main surface,
A capacitor body having a capacitor main surface, a capacitor back surface and a capacitor side surface, and having a structure in which a plurality of internal electrode layers are laminated via a ceramic dielectric layer, and a resin as a main component, on the capacitor main surface , the capacitor A stress relaxation layer formed on the back surface and the capacitor side surface ,
The core substrate is fixed to the core substrate by a resin filling portion that fills a gap between an inner wall surface of the accommodation hole portion and an outer surface of a stress relaxation layer formed on a side surface of the capacitor. Wiring board built-in capacitor. A wiring laminated portion having a structure in which a resin interlayer insulating layer and a conductor layer are laminated is formed on the core main surface and the stress relaxation layer, and the resin filling portion filling the gap is a part of the resin interlayer insulating layer. The wiring board built-in capacitor according to claim 11, comprising:   The stress relaxation layer includes a contact surface in contact with the capacitor main body, an outer surface located on the opposite side of the contact surface, a plurality of conductive columns for conducting the contact surface side and the outer surface side, and the outer surface. 13. The wiring board built-in capacitor according to claim 11, further comprising a plurality of terminal pads arranged on the top and connected to the plurality of conductor pillars.   The stress relaxation layer has an elastic modulus at room temperature of 0.01 GPa or more and 1 GPa or less, and an elongation at break of 10% or more at room temperature. Capacitor for wiring board.   15. The wiring board built-in capacitor according to claim 11, wherein a thickness of the stress relaxation layer is not less than 5 μm and not more than 30 μm. A plurality of via conductors in the capacitor connected to the plurality of internal electrode layers;
A plurality of surface layer electrodes connected to at least the capacitor main surface side end of the plurality of capacitor via conductors;
The wiring board built-in capacitor according to any one of claims 11 to 15, wherein the plurality of via conductors in the capacitor are arranged in an array as a whole.

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