JP5388677B2 - Capacitor, method for manufacturing the same, and wiring board - Google Patents

Description

  The present invention relates to a capacitor built in or mounted on a wiring board, and a wiring board with the capacitor built in or surface mounted.

  In recent years, semiconductor integrated circuit elements (IC chips) used as computer microprocessors and the like have become increasingly faster and more functional, with an accompanying increase in the number of terminals and a tendency to narrow the pitch between terminals. . In general, a large number of terminals are densely arranged on the bottom surface of an IC chip, and such a terminal group is connected to a terminal group on the motherboard side in the form of a flip chip. However, it is difficult to connect the IC chip directly on the mother board because there is a large difference in the pitch between the terminals on the IC chip side terminal group and the mother board side terminal group. For this reason, a method is generally employed in which a package is prepared by mounting an IC chip on an IC chip mounting wiring board, and the package is mounted on a motherboard. In a wiring board for mounting an IC chip constituting this type of package, it has been proposed to provide a capacitor (also referred to as a “capacitor”) in order to reduce switching noise of the IC chip and stabilize the power supply voltage. . As an example, a wiring board in which capacitors are embedded in a core substrate made of a polymer material and build-up layers are formed on the front surface and the back surface of the core substrate has been conventionally proposed (see, for example, Patent Document 1).

  Specifically, in the wiring board described in Patent Document 1, an accommodation hole opening at the upper surface and the lower surface is formed in the central portion of the core substrate, and a via array type ceramic capacitor is accommodated in the accommodation hole. ing.

  FIG. 16 shows an example of a conventional via array type ceramic capacitor 201. The ceramic capacitor 201 includes a capacitor forming layer portion 202 and a cover layer portion 203. The capacitor forming layer portion 202 has a structure in which the first internal electrodes 206 and the second internal electrodes 207 are alternately stacked via the ceramic dielectric layer 205. The ceramic dielectric layer 205 is made of a sintered body of barium titanate, which is a kind of high dielectric constant ceramic, and functions as a dielectric (insulator) between the first internal electrode 206 and the second internal electrode 207.

  The cover layer portion 203 is formed by laminating a plurality of ceramic dielectric layers 209 and is provided on the surface layer portion of the ceramic capacitor 201 so as to cover the capacitor forming layer portion 202. By providing this cover layer portion 203, the insulation, heat resistance, moisture resistance, etc. of the ceramic capacitor 201 are ensured.

  In addition, a large number of via holes 210 are formed in the ceramic capacitor 201. These via holes 210 penetrate the ceramic capacitor 201 in the thickness direction and are arranged in a lattice shape (array shape) over the entire surface. In each via hole 210, a plurality of via conductors 211 and 212 that penetrate between the upper surface and the lower surface of the ceramic capacitor 201 are formed. Each first via conductor 211 passes through each first internal electrode 206 and electrically connects them to each other. Each second via conductor 212 penetrates each second internal electrode 207 and electrically connects them to each other.

Japanese Patent Laying-Open No. 2005-39243 (FIG. 4 etc.)

  When the conventional ceramic capacitor 201 shown in FIG. 16 is built in a wiring board as in Patent Document 1, external stress is applied to the surface of the ceramic capacitor 201 due to resin curing shrinkage and thermal history (thermal expansion difference). It becomes like this. More specifically, since the ceramic capacitor 201 is covered with a thermosetting resin, a stress caused by a difference in thermal expansion is applied depending on the thermal history during manufacture and use. Note that the cover layer portion 203 of the ceramic capacitor 201 is formed only of the ceramic dielectric layer 209 and has relatively low toughness, so that a crack 215 (see FIG. 17) occurs in the outer peripheral portion of the cover layer portion 203. , Easy to progress. For this reason, there exists a possibility that the reliability of a wiring board may fall.

  The present invention has been made in view of the above problems, and a first object of the invention is to provide a capacitor capable of preventing cracks that occur when it is built in a wiring board and a method for manufacturing the same. A second object is to provide a suitable wiring board in which the capacitor is incorporated or surface-mounted.

And as means (means 1) for solving the above-mentioned problem, a plate-like capacitor body having a capacitor main surface and a capacitor back surface, and a plurality of via holes extending along the thickness direction of the capacitor body are formed. A capacitor comprising a plurality of via conductors in a capacitor, wherein the capacitor body is alternately laminated with a plurality of first dielectric layers and a plurality of internal electrodes electrically connected to the plurality of via conductors in the capacitor. And a second dielectric laminate portion disposed so as to be exposed on the capacitor main surface or the capacitor back surface of the capacitor body, and viewed from the thickness direction. Extending in the thickness direction of the second dielectric laminate portion and at least the outer peripheral portion of the second dielectric laminate portion and the capacitor main surface and the capacitor. Hole which opens at least one of the capacitors back surface is provided so as to surround the capacitor via conductors, within the bore, the dummy via conductors are not electrically connected to the internal electrodes are formed There is a capacitor characterized by.

  Therefore, according to the capacitor of means 1, since the outer peripheral portion of the second dielectric multilayer portion is provided with a hole portion extending along the thickness direction of the second dielectric multilayer portion, the dielectric portion is a hole portion. It becomes divided by and becomes discontinuous. As a result, cracks starting from the outer peripheral surface of the capacitor occur due to external stress applied to the capacitor surface when it is built into the wiring board, etc., and even if it progresses toward the capacitor center, it reaches the hole. This will prevent further progress.

  Here, as for the external dimension of a capacitor | condenser, it is preferable that a long side is 5 mm or more, for example. In this way, the external stress applied to the capacitor surface is increased, and cracks starting from the outer peripheral surface of the capacitor are likely to occur, so the problem of the present invention is likely to occur.

  The inner diameter of the via hole is not particularly limited, but is preferably 50 μm or more and 120 μm or less, for example. If the inner diameter of the via hole is less than 50 μm, the cross-sectional area of the via conductor in the capacitor formed in the via hole is reduced, so the resistance of the via conductor in the capacitor is increased and the overall resistance of the capacitor is reduced. It becomes difficult to do. In addition, when forming the via conductor in the capacitor, it becomes difficult to fill the via hole with the material for forming the via conductor, which may reduce the productivity. On the other hand, if the inner diameter of the via hole is larger than 120 μm, the via pitch must be set large, and there is a possibility that the wiring board side having fine wiring cannot be efficiently connected.

  Moreover, the inner diameter of the hole is not particularly limited, but is preferably 50 μm or more and 120 μm or less, for example. If the inner diameter of the hole is less than 50 μm, when forming a dummy via conductor to be described later in the hole, it becomes difficult to fill the hole with the via conductor forming material, which may reduce the productivity. . On the contrary, if the inner diameter of the hole is larger than 120 μm, there is a possibility that a large number of holes cannot be arranged with respect to the outer peripheral part of the second dielectric laminated part having a small area. Note that the inner diameter of the hole may be set larger or smaller than the inner diameter of the via hole. Further, the inner diameter of the hole may be set equal to the inner diameter of the via hole. If the inner diameter of the hole portion is equal to the inner diameter of the via hole, the hole portion and the via hole can be formed under the same conditions, which is convenient for manufacturing. Further, the depth of the hole is not particularly limited, but may be equal to, for example, the thickness of the second dielectric laminate or may be smaller than the thickness of the second dielectric laminate.

In addition, in order to make a crack reach a hole part reliably, it is preferable that there are many said hole parts. Specifically, the number (density) of holes in the outer peripheral portion of the second dielectric laminate is preferably, for example, 5 or more and 25 or less per 1 mm ² . If the number is less than 5 per 1 mm ² , cracks cannot be reliably reached at the hole. On the other hand, when the number is larger than 25 per 1 mm ² , it becomes difficult to fill the hole with the via conductor forming material when forming the dummy via conductor, which may reduce the productivity.

  A dummy via conductor that is not electrically connected to the internal electrode is preferably formed in the hole. If it does in this way, the toughness in the 2nd dielectric laminated part of a capacitor body will improve with a dummy via conductor. Thereby, generation | occurrence | production of the crack resulting from an above-described external stress can be suppressed reliably.

  Here, the dummy via conductor is preferably formed using the same material as the via conductor in the capacitor. In this way, it is not necessary to prepare a dedicated material for the dummy via conductor separately from the material for the via conductor in the capacitor. Therefore, since the material required for manufacturing the capacitor is reduced, the cost of the capacitor can be reduced. Moreover, since the dummy via conductor can be fired simultaneously under the same conditions (temperature, time) as the via conductor in the capacitor, the manufacturing cost can be suppressed.

  When the plurality of holes are formed in the outer peripheral portion of the second dielectric stacked portion, the plurality of holes are annularly arranged in a plurality of rows as viewed from the thickness direction of the second dielectric stacked portion. May be arranged. The plurality of hole portions are arranged in parallel with the four sides constituting the outer peripheral portion of the second dielectric multilayer portion, and the four corner portions (each of which constitutes the outer peripheral portion of the second dielectric multilayer portion). It is preferable to be arranged at the side connection portion. Furthermore, it is preferable that the plurality of hole portions are arranged continuously and at an equal pitch with no gaps. When it does in this way, the probability that the above-mentioned crack will reach a hole becomes high. Thereby, the progress of cracks can be reliably prevented in the outer peripheral portion of the second dielectric laminate portion. In addition, when a some hole part is arrange | positioned cyclically | annularly and in several rows, it is preferable that a some hole part is arrange | positioned in zigzag form. In this way, even if the crack passes between the plurality of holes constituting the outer row, the crack surely reaches the hole in the inner row. As a result, the progress of cracks can be more reliably prevented at the outer peripheral portion of the second dielectric laminate.

  Further, the hole portion penetrates the first dielectric laminate portion and the second dielectric laminate portion in the thickness direction, and is opened on both the capacitor main surface and the capacitor back surface of the capacitor body. Also good. In such a case, the probability that the crack reaches the hole becomes high regardless of which of the first dielectric laminated portion and the second dielectric laminated portion propagates. Thereby, the progress of cracks can be prevented in both the outer peripheral portion of the first dielectric multilayer portion and the outer peripheral portion of the second dielectric multilayer portion.

  Further, the capacitor body has a substantially rectangular plate shape having four sides when viewed from the thickness direction, and the hole portion is at least one of the four sides in the outer peripheral portion of the second dielectric multilayer portion. It may be formed in a slit shape extending in parallel with one side. When it does in this way, when the above-mentioned crack progresses to the 2nd dielectric lamination part, the probability that a crack will reach a hole becomes high. Thereby, the progress of cracks can be more reliably prevented at the outer peripheral portion of the second dielectric laminate portion.

  Further, it is preferable that the second dielectric laminated portion is formed by alternately laminating a plurality of second dielectric layers and dummy electrode layers not electrically connected to the plurality of capacitor via conductors. In this case, the dummy electrode layer is laminated between the plurality of second dielectric layers. The dummy electrode layer is preferably an electrode having a large area, and may be, for example, a solid pattern arranged with a clearance around the via conductor in the capacitor. If it does in this way, the toughness in the 2nd dielectric laminated part of a capacitor body can be raised. Thereby, generation | occurrence | production of the crack resulting from an above-described external stress can be suppressed more reliably.

  The second dielectric layer is preferably thicker than the first dielectric layer. In this way, it is possible to sufficiently ensure the strength of the second dielectric laminated portion. The thickness of the second dielectric layer may be equal to the thickness of the first dielectric layer. In this case, since each dielectric layer can be formed using a sheet material having the same thickness, the manufacturing cost can be reduced.

  The dummy electrode layer is preferably formed using the same material as the internal electrode. In this way, it is not necessary to prepare a dedicated material for the dummy electrode layer separately from the material for the internal electrode. Therefore, since the material required for manufacturing the capacitor is reduced, the cost of the capacitor can be reduced. Moreover, since the dummy electrode layer can be co-fired under the same conditions (temperature and time) as the internal electrode, the manufacturing cost can be reduced.

  The thickness of the dummy electrode layer is preferably equal to or greater than the thickness of the internal electrode. In this way, it is possible to sufficiently ensure the strength of the second dielectric multilayer portion, and to reliably prevent cracks occurring at the outer peripheral portion of the second dielectric multilayer portion.

  The capacitor preferably includes a plurality of terminal electrodes arranged on the capacitor main surface and connected to at least a capacitor main surface side end of the plurality of via conductors in the capacitor. When the terminal electrode is provided in this way, the connection with the conductor in the wiring board can be reliably performed.

  Examples of the first dielectric layer and the second dielectric layer include a ceramic dielectric layer, a resin dielectric layer, and a dielectric layer made of a ceramic-resin composite material. As the ceramic dielectric layer, a sintered body of dielectric ceramic such as barium titanate, lead titanate, strontium titanate is preferably used. It becomes easy to realize a large capacitor. Further, as the other ceramic dielectric layer, a sintered body of a high-temperature fired ceramic such as alumina, aluminum nitride, boron nitride, silicon carbide, silicon nitride or the like is preferably used, and borosilicate glass or borosilicate. A sintered body of low-temperature fired ceramic such as glass ceramic obtained by adding an inorganic ceramic filler such as alumina to lead glass is preferably used. Further, as the resin dielectric layer, an epoxy resin, a resin such as tetrafluoroethylene resin (PTFE) containing an adhesive is preferably used. Furthermore, as the dielectric layer made of the ceramic-resin composite material, barium titanate, lead titanate, strontium titanate or the like is preferably used as the ceramic, and as the resin material, epoxy resin, phenol resin, urethane resin, Thermosetting resins such as silicone resin, polyimide resin, unsaturated polyester, thermoplastic resin such as polycarbonate resin, acrylic resin, polyacetal resin, polypropylene resin, and latex such as nitrile butadiene rubber, styrene butadiene rubber, and fluoro rubber are suitable. Used for.

  The via conductor in the capacitor, the internal electrode, the dummy via conductor, the dummy electrode layer, and the terminal electrode are not particularly limited. For example, when the first dielectric layer and the second dielectric layer are ceramic dielectric layers. Is preferably a metallized conductor. The metallized conductor is formed by applying a conductive paste containing metal powder by a conventionally well-known method, for example, a metallized printing method, followed by baking. When the metallized conductor and the ceramic dielectric layer are formed by the co-firing method, the metal powder in the metallized conductor needs to have a melting point higher than the firing temperature of the ceramic dielectric layer. For example, when the ceramic dielectric layer is made of a so-called high-temperature fired ceramic (for example, alumina or the like), nickel (Ni), tungsten (W), molybdenum (Mo), manganese (Mn), or the like is used as the metal powder in the metallized conductor. And their alloys can be selected. When the ceramic dielectric layer is made of a so-called low-temperature fired ceramic (for example, glass ceramic), copper (Cu) or silver (Ag) or an alloy thereof can be selected as the metal powder in the metallized conductor.

  Further, as another means (means 2) for solving the above-mentioned problem, there is a wiring board incorporating the capacitor described in means 1 above.

  Therefore, according to the wiring board of the above means 2, since the outer peripheral portion of the second dielectric multilayer portion is provided with the hole extending along the thickness direction of the second dielectric multilayer portion, the dielectric portion Is cut by the hole and becomes discontinuous. As a result, a crack starting from the outer peripheral surface of the capacitor is generated in the step of incorporating the capacitor, and even if it progresses toward the center of the capacitor, it does not progress further by reaching the hole. As a result, the reliability of the wiring board is improved. If no dummy via conductor is formed in the hole, the resin in contact with the capacitor main surface or the capacitor back surface enters the hole, so that the fixing strength of the capacitor is improved and the reliability of the wiring board is further improved. .

  The wiring board preferably includes a core substrate having an accommodation hole for accommodating the capacitor of the means 1, and a wiring laminated portion formed on the upper surface and the lower surface of the core substrate. A material for forming the core substrate is not particularly limited, but a preferable core substrate is mainly formed of a polymer material. Specific examples of the polymer material for forming the core substrate include, for example, EP resin (epoxy resin), PI resin (polyimide resin), BT resin (bismaleimide / triazine resin), PPE resin (polyphenylene ether resin), etc. There is. In addition, composite materials of these resins and glass fibers (glass woven fabric or glass nonwoven fabric) or organic fibers such as polyamide fibers may be used.

  In addition, as another means (means 3) for solving the above-described problem, a wiring board having a substrate main surface and the capacitor described in the means 1 being surface-mounted by a flip chip method on the substrate main surface. There is.

  Therefore, according to the wiring board of the above means 3, since the outer peripheral portion of the second dielectric laminated portion is provided with the hole extending along the thickness direction of the second dielectric laminated portion, the dielectric portion Is cut by the hole and becomes discontinuous. As a result, cracks starting from the outer peripheral surface of the capacitor are generated in the surface mounting process of the capacitor, and even if the crack progresses toward the center of the capacitor, it does not progress further by reaching the hole. As a result, the reliability of the wiring board is improved.

  In the wiring board, a gap between the main surface of the board and the capacitor may be sealed with a resin material. In the sealing process of the resin material, even when tensile stress due to thermosetting shrinkage acts on the capacitor, it is possible to prevent the occurrence of cracks in the outer peripheral portion of the second dielectric laminated portion.

  Further, as another means (means 4) for solving the above-mentioned problem, there is provided a method of manufacturing the capacitor according to the means 1, wherein the first green sheet of ceramic used as the first dielectric laminated portion is The via holes are formed in the green sheet laminate by laminating and integrating a ceramic second green sheet to be the second dielectric laminate to produce a green sheet laminate and laser processing. And a hole filling step for forming the hole portion, a via filling step for filling a via conductor forming material in at least the via hole of the via hole and the hole portion, and a temperature at which the ceramic can be sintered. And a firing step of firing the first green sheet, the second green sheet, and the via conductor forming material by heating the green sheet laminate. There is a method of manufacturing the capacitor that.

  Therefore, according to the manufacturing method of the means 4, since the hole portion is formed in the hole making step, the dielectric portion is divided by the hole portion and becomes discontinuous. As a result, when the completed capacitor is built in the wiring board, cracks starting from the outer peripheral surface of the capacitor are generated due to the external stress described above, and reach the hole even if the crack propagates toward the center of the capacitor. This will prevent further progress. In the drilling process, the via hole and the hole are formed simultaneously. Thereby, since the manufacturing time of the capacitor is not so long, the manufacturing cost can be suppressed. In the via filling step, the via hole is preferably filled with the via conductor forming material that becomes the via conductor in the capacitor, and at the same time, the hole is filled with the via conductor forming material that becomes the dummy via conductor. In this way, the manufacturing time of the capacitor is further shortened.

  In the laminating step, the second green sheet is laminated on both the first surface side and the second surface side of the first green sheet, and the hole forming step includes forming the via hole in the green sheet laminated body. Via hole forming step for forming the first hole portion forming step for forming the hole portion in the second green sheet laminated on the first surface side of the first green sheet, after the first hole portion forming step, It is preferable to include a second hole forming step of forming the hole in the second green sheet laminated on the second surface side of the first green sheet in a state where the green sheet laminate is turned over. In this way, the hole is not formed in the state of a thin and easily deformable green sheet, but is formed in a state of a green sheet laminate that is difficult to deform by being laminated. Formation of the part becomes easy.

1 is a schematic cross-sectional view showing a wiring board according to an embodiment of the present invention. The schematic sectional drawing which shows a ceramic capacitor. The schematic explanatory drawing for demonstrating the connection of an internal electrode and the via conductor in a capacitor | condenser in a capacitor | condenser formation layer part. The schematic explanatory drawing for demonstrating the connection of an internal electrode and the via conductor in a capacitor | condenser in a capacitor | condenser formation layer part. Schematic explanatory drawing which shows the relationship between a dummy electrode layer and a dummy via conductor in a cover layer part. Schematic explanatory drawing which shows the relationship between a dummy electrode layer and a dummy via conductor in the cover layer part of other embodiment. Schematic explanatory drawing which shows the relationship between a dummy electrode layer and a dummy via conductor in the cover layer part of other embodiment. Schematic explanatory drawing which shows the relationship between a dummy electrode layer and a dummy via conductor in the cover layer part of other embodiment. The schematic sectional drawing which shows the ceramic capacitor of other embodiment. The schematic sectional drawing which shows the ceramic capacitor of other embodiment. The schematic sectional drawing which shows the wiring board of other embodiment. The schematic sectional drawing which shows the wiring board of other embodiment. The principal part sectional view showing the wiring board of other embodiments. The principal part sectional view showing the wiring board of other embodiments. The principal part sectional view showing the ceramic capacitor of other embodiments. The schematic sectional drawing which shows an example of the conventional ceramic capacitor. The expanded sectional view which shows the crack of the cover layer part in the conventional ceramic capacitor.

  Hereinafter, an embodiment embodying the present invention will be described in detail with reference to the drawings.

  As shown in FIG. 1, the wiring board 10 of this embodiment is a wiring board for mounting an IC chip. The wiring substrate 10 is formed on a substantially rectangular plate-shaped core substrate 11, a first buildup layer 31 (wiring laminated portion) formed on the upper surface 12 of the core substrate 11, and a lower surface 13 of the core substrate 11. It consists of the second buildup layer 32 (wiring laminated portion).

  The core substrate 11 of the present embodiment has a substantially rectangular plate shape in plan view of 25 mm length × 25 mm width × 1.0 mm thickness. Through-hole conductors 16 are formed at a plurality of locations on the core substrate 11. The through-hole conductor 16 connects and connects the upper surface 12 side and the lower surface 13 side of the core substrate 11. The inside of the through-hole conductor 16 is filled with a closing body 17 such as an epoxy resin. A conductor layer 41 made of copper is patterned on the upper surface 12 and the lower surface 13 of the core substrate 11, and each conductor layer 41 is electrically connected to the through-hole conductor 16.

  As shown in FIG. 1, the first buildup layer 31 is formed by alternately laminating two resin interlayer insulation layers 33 and 35 made of thermosetting resin (epoxy resin) and a conductor layer 42 made of copper. It has the structure. Terminal pads 44 are formed in an array at a plurality of locations on the surface of the second resin interlayer insulation layer 35. Further, the surface of the resin interlayer insulating layer 35 is almost entirely covered with a solder resist 37. An opening 46 for exposing the terminal pad 44 is formed at a predetermined position of the solder resist 37. A plurality of solder bumps 45 are provided on the surface of the terminal pad 44. Each solder bump 45 is electrically connected to the surface connection terminal 22 of the IC chip 21 having a rectangular flat plate shape. Note that an area including the terminal pads 44 and the solder bumps 45 is an IC chip mounting area 23 on which the IC chip 21 can be mounted. The IC chip mounting area 23 is set on the surface of the first buildup layer 31. In addition, via conductors 43 and 47 are provided in the resin interlayer insulating layers 33 and 35, respectively. These via conductors 43 and 47 electrically connect the conductor layer 42 and the terminal pad 44 to each other.

  As shown in FIG. 1, the second buildup layer 32 has substantially the same structure as the first buildup layer 31 described above. That is, the second buildup layer 32 has a structure in which two resin interlayer insulating layers 34 and 36 made of thermosetting resin (epoxy resin) and conductor layers 42 are alternately laminated. BGA pads 48 electrically connected to the conductor layer 42 through via conductors 47 are formed in an array at a plurality of locations on the lower surface of the second resin interlayer insulation layer 36. The lower surface of the resin interlayer insulating layer 36 is almost entirely covered with a solder resist 38. An opening 40 for exposing the BGA pad 48 is formed at a predetermined portion of the solder resist 38. On the surface of the BGA pad 48, a plurality of solder bumps 49 are provided for electrical connection with a mother board (not shown). The wiring board 10 shown in FIG. 1 is mounted on a mother board (not shown) by each solder bump 49.

  The core substrate 11 has a receiving hole 91 that is rectangular in a plan view and opens at the center of the upper surface 12 and the center of the lower surface 13. That is, the accommodation hole 91 is a through hole. The ceramic capacitor 101 is housed in the housing hole 91 in an embedded state. The ceramic capacitor 101 of this embodiment has a rectangular flat plate shape of 15.0 mm long × 15.0 mm wide × 0.8 mm thick. Further, the gap between the inner surface of the accommodation hole 91 and the capacitor side surface 106 of the ceramic capacitor 101 is filled with a filler 92 made of a polymer material (thermosetting resin in this embodiment). The filler 92 has a function of fixing the ceramic capacitor 101 to the core substrate 11 and absorbing the deformation of the ceramic capacitor 101 and the core substrate 11 in the surface direction and the thickness direction by its own elastic deformation.

  The ceramic capacitor 101 is arranged in a region immediately below the IC chip mounting region 23 in the core substrate 11. The area of the IC chip mounting region 23 (the area of the surface on which the surface connection terminals 22 are formed in the IC chip 21) is set to be smaller than the area of the capacitor main surface 102 of the ceramic capacitor 101. When viewed from the thickness direction of the ceramic capacitor 101, the IC chip mounting region 23 is located in the capacitor main surface 102 of the ceramic capacitor 101.

  As shown in FIGS. 1 and 2, the ceramic capacitor 101 of this embodiment is a so-called via array type capacitor. The ceramic sintered body 104 (capacitor main body) constituting the ceramic capacitor 101 includes one capacitor main surface 102 (upper surface in FIG. 1), one capacitor rear surface 103 (lower surface in FIG. 1), and four capacitor side surfaces 106. And has a substantially rectangular plate shape having four sides 110 when viewed from the thickness direction.

  The ceramic sintered body 104 includes a capacitor formation layer portion 107 (first dielectric laminate portion), an upper cover layer portion 108 (second dielectric laminate portion) that covers the upper surface of the capacitor formation layer portion 107, and a capacitor formation layer. A lower cover layer portion 109 (second dielectric laminate portion) covering the lower surface of the portion 107. The capacitor forming layer portion 107 has a structure in which a plurality of ceramic dielectric layers 105 (first dielectric layers) and a plurality of internal electrodes 141 and 142 are alternately stacked. The internal electrodes formed on the capacitor forming layer portion 107 are the power supply internal electrode 141 and the ground internal electrode 142, and the power supply internal electrode 141 and the ground internal electrode 142 are alternately arranged via the ceramic dielectric layer 105. Are arranged in layers. The ceramic dielectric layer 105 is made of a sintered body of barium titanate, which is a kind of high dielectric constant ceramic, and functions as a dielectric (insulator) between the power supply internal electrode 141 and the ground internal electrode 142. The power supply internal electrode 141 and the ground internal electrode 142 are both conductors formed mainly of nickel.

  As shown in FIGS. 2 to 5, a large number of via holes 130 (inner diameter of about 100 μm) are formed in the ceramic sintered body 104. These via holes 130 extend along the thickness direction of the ceramic sintered body 104 and penetrate the ceramic sintered body 104, and are arranged in a lattice shape (array shape) over the entire surface. In the present embodiment, for convenience of explanation, the via holes 130 are illustrated as 4 rows × 4 rows, but there are actually more rows. In each via hole 130, a plurality of in-capacitor via conductors 131 and 132 that communicate between the capacitor main surface 102 and the capacitor back surface 103 of the ceramic sintered body 104 are formed using nickel as a main material. That is, the in-capacitor via conductors 131 and 132 are formed using the same material as the plurality of internal electrodes 141 and 142. Each power supply capacitor via conductor 131 passes through each power supply internal electrode 141 and electrically connects them to each other (see FIGS. 2 and 3). Each ground-capacitor via conductor 132 passes through each ground internal electrode 142 and is electrically connected to each other (see FIGS. 2 and 4).

  As shown in FIGS. 1 and 2, the cover layer portions 108 and 109 are arranged so as to be exposed at the surface layer portion of the ceramic sintered body 104. More specifically, the upper cover layer portion 108 is disposed so as to be exposed at the capacitor main surface 102, and the lower cover layer portion 109 is disposed so as to be exposed at the capacitor back surface 103. Each of the cover layer portions 108 and 109 alternately includes a plurality of ceramic dielectric layers 153 (second dielectric layers) and large-area dummy electrode layers 154 that are not electrically connected to the via conductors 131 and 132 in the capacitor. It has a laminated structure. The dummy electrode layer 154 is formed of the same material (a metal material mainly composed of nickel) as the internal electrodes 141 and 142 in the capacitor formation layer portion 107, and has a thickness greater than the thickness of the internal electrodes 141 and 142. Is formed. The dummy electrode layer 154 is formed to be a solid pattern having a clearance 155 (circular blanking pattern) around the via conductors 131 and 132 in the capacitor (see FIG. 5). Further, the ceramic dielectric layer 153 is formed of the same material (specifically, barium titanate) as the ceramic dielectric layer 105 in the capacitor forming layer portion 107 and is formed thicker than the ceramic dielectric layer 105. .

As shown in FIGS. 2 and 5, a large number of holes 161 (with an inner diameter of about 80 μm) are formed in the outer peripheral portions of the cover layer portions 108 and 109 when the ceramic sintered body 104 is viewed from the thickness direction. Is formed. That is, the inner diameter of the hole 161 of this embodiment is set smaller than the inner diameter of the via hole 130. Each hole 161 is provided so as to surround all the in-capacitor via conductors 131 and 132, and is arranged in a rectangular ring shape when viewed from the thickness direction of the cover layer portions 108 and 109. More specifically, each hole 161 is arranged in parallel with the four sides 110 on the outer periphery of the cover layer portions 108 and 109, and the four corners of the cover layer portions 108 and 109 (the connection of each side 110). Part). And each hole 161 is arrange | positioned continuously and at equal pitch, and without a gap | interval, and has comprised the cyclic | annular form as a whole. Accordingly, the number (density) of the hole portions 161 in the outer peripheral portions of the cover layer portions 108 and 109 is 25 per 1 mm ^{2 in} this embodiment. The hole 161 formed in the upper cover layer portion 108 extends along the thickness direction of the cover layer portion 108, penetrates the cover layer portion 108, and opens at the capacitor main surface 102. On the other hand, the hole 161 formed in the lower cover layer portion 109 extends along the thickness direction of the cover layer portion 109, penetrates the cover layer portion 109, and opens at the capacitor back surface 103. That is, since the depth of the hole 161 is equal to the thickness of the cover layer portions 108 and 109, each hole 161 does not penetrate the corresponding portion in the capacitor forming layer portion 107.

  As shown in FIGS. 2 and 5, a plurality of dummy via conductors 162 that are not electrically connected to the internal electrodes 141 and 142 are formed using nickel as a main material in each hole 161. That is, the dummy via conductor 162 is formed using the same material as the internal electrodes 141 and 142 and the capacitor via conductors 131 and 132. The height of the dummy via conductor 162 is equal to the depth of the hole 161.

  1 and 2, on the capacitor main surface 102 of the ceramic sintered body 104, a plurality of main surface side power supply electrodes 111 (terminal electrodes) and a plurality of main surface side ground electrodes 112 are provided. (Terminal electrode) is projected. Each main surface side ground electrode 112 is individually formed on the capacitor main surface 102, but may be formed integrally. The main surface side power supply electrode 111 is directly connected to the end surface of the plurality of power supply capacitor internal via conductors 131 on the capacitor main surface 102 side, and the main surface side ground electrode 112 is connected to the plurality of ground capacitor internal electrodes. The via conductor 132 is directly connected to the end surface on the capacitor main surface 102 side.

  Further, on the capacitor back surface 103 of the ceramic sintered body 104, a plurality of back surface side power supply electrodes 121 (terminal electrodes) and a plurality of back surface side ground electrodes 122 (terminal electrodes) are projected. Each back surface side ground electrode 122 is individually formed on the capacitor back surface 103, but may be formed integrally. The back surface side power supply electrode 121 is directly connected to the end surface of the plurality of power supply capacitor internal via conductors 131 on the capacitor back surface 103 side, and the back surface side ground electrode 122 is connected to the plurality of ground internal capacitor capacitor via conductors 132. Is directly connected to the end surface on the capacitor back surface 103 side. Therefore, the power supply electrodes 111 and 121 are electrically connected to the power supply capacitor inner via conductor 131 and the power supply inner electrode 141, and the ground electrodes 112 and 122 are electrically connected to the ground capacitor inner via conductor 132 and the ground internal electrode 142. doing.

  As shown in FIG. 1, the electrodes 111 and 112 on the capacitor main surface 102 side include the via conductor 43, the conductor layer 42, the via conductor 47, the terminal pad 44, the solder bump 45, and the surface connection terminal 22 of the IC chip 21. And is electrically connected to the IC chip 21. On the other hand, the electrodes 121 and 122 on the capacitor back surface 103 side are connected to electrodes (contactors) of a mother board (not shown) via via conductors 43, conductor layers 42, via conductors 47, BGA pads 48 and solder bumps 49. Are electrically connected.

  As shown in FIG. 2, the electrodes 111, 112, 121, and 122 are made of nickel as a main material, and the surface is entirely covered with a copper plating layer (not shown). The electrodes 111, 112, 121, 122 and the via conductors 131, 132 in the capacitor are disposed directly below the central portion of the IC chip 21. In the present embodiment, the diameters of the electrodes 111, 112, 121, and 122 are set to about 500 μm.

  For example, when energization is performed from the mother board side through the electrodes 121 and 122 and a voltage is applied between the power supply internal electrode 141 and the ground internal electrode 142, for example, positive charges are accumulated in the power supply internal electrode 141, For example, negative charges accumulate in the internal electrode 142. As a result, the ceramic capacitor 101 functions as a capacitor. In the ceramic capacitor 101, the via-conductor 131 for power supply capacitor and the via-conductor 132 for ground capacitor are alternately arranged adjacent to each other, and the via-conductor 131 for power-supply capacitor and the via-conductor 132 for ground capacitor are connected to each other. The directions of the flowing currents are set to be opposite to each other. Thereby, the inductance component is reduced.

  The ceramic capacitor 101 of this embodiment is manufactured as follows. That is, a ceramic first green sheet having a thickness of about 7 μm is formed, and a ceramic second green sheet having a thickness of about 30 μm is formed. Then, the internal electrode nickel paste is screen-printed on the first green sheet and dried. As a result, a power internal electrode portion that will later become the power internal electrode 141 and a ground internal electrode portion that will be the ground internal electrode 142 are formed. Moreover, the nickel paste for dummy electrode layers is screen-printed on the second green sheet and dried. As a result, a dummy electrode layer portion to be the dummy electrode layer 154 later is formed.

  Next, the first green sheet on which the internal electrode portion for power supply is formed and the first green sheet on which the internal electrode portion for ground is formed are alternately stacked, and a portion that will later become the capacitor forming layer portion 107 is formed. Next, the second green sheet is laminated on the first surface side of the first green sheet (that is, the upper surface of the portion that becomes the capacitor forming layer portion 107), and the portion that later becomes the upper cover layer portion 108 is formed. Also, the second green sheet is laminated on the second surface side of the first green sheet (that is, the lower surface of the portion that becomes the capacitor forming layer portion 107), and the portion that becomes the lower cover layer portion 109 later is formed. Then, by applying a pressing force in the sheet stacking direction, the green sheets are integrated to form a green sheet stack (lamination step).

  Next, by performing laser processing using a laser processing machine, a large number of via holes 130 and holes 161 are formed through the green sheet laminate (hole forming step). More specifically, first, a plurality of via holes 130 are formed in the green sheet laminate (via hole forming step). Next, a plurality of holes 161 are formed in a portion to be the upper cover layer part 108 in the green sheet laminate (first hole part forming step). Further, after the first hole portion forming step, a plurality of hole portions 161 are formed in a portion that becomes the lower cover layer portion 109 in a state where the green sheet laminated body is turned over (second hole portion forming step). In the first hole portion forming step and the second hole portion forming step, laser processing is performed in a state where the number of shots is reduced as compared with the via hole forming step. Further, the same number of holes 161 are formed in each of the first hole forming process and the second hole forming process.

  Next, using a paste press-fitting and filling device (not shown), each via hole 130 and each hole 161 are filled with via conductor nickel paste (via conductor forming material) (via filling step). Next, a nickel paste for terminal electrodes is printed on the upper surface of the green sheet laminate, and terminal electrode portions are formed so as to cover the upper end surfaces of the respective conductor portions on the upper surface side of the green sheet laminate. Further, a nickel paste for terminal electrodes is printed on the lower surface of the green sheet laminate, and the terminal electrode portion is formed so as to cover the lower end surface of each conductor portion on the lower surface side of the green sheet laminate.

  Thereafter, the green sheet laminate is dried to solidify each terminal electrode part to some extent. Next, the green sheet laminate is degreased and further fired at a predetermined temperature for a predetermined time in a reducing atmosphere (firing step). The firing temperature at this time is set to 1300 ° C., which is the temperature at which barium titanate can be sintered. As a result, the barium titanate in the first green sheet and the second green sheet is sintered to form the ceramic sintered body 104. At the same time, nickel in the internal electrode portion for power supply and the internal electrode for ground sinters to become internal electrodes 141 and 142, nickel in the dummy electrode layer portion sinters to become dummy electrode layer 154, and terminal electrode portion The nickel inside is sintered to become electrodes 111, 112, 121, 122. Also, the nickel in the via conductor nickel paste sinters into capacitor via conductors 131 and 132 and dummy via conductor 162.

  Next, electrolytic copper plating (thickness of about 15 μm) is performed on each of the electrodes 111, 112, 121, and 122 included in the obtained ceramic sintered body 104. As a result, a copper plating layer is formed on each of the electrodes 111, 112, 121, 122, and the ceramic capacitor 101 is completed.

  When the ceramic capacitor 101 is built in the wiring substrate 10, first, the core substrate 11 having the accommodation hole portion 91 is prepared and prepared by a conventionally known method. Then, the ceramic capacitor 101 is accommodated in the accommodation hole portion 91 of the core substrate 11, and a filler 92 made of a thermosetting resin is placed in the gap between the inner surface of the accommodation hole portion 91 and the capacitor side surface 106 of the ceramic capacitor 101. Fill. Thereafter, when heat treatment is performed, the filler 92 is cured and the ceramic capacitor 101 is fixed in the accommodation hole 91.

  Further, the first buildup layer 31 is formed on the upper surface 12 of the core substrate 11 and the capacitor main surface 102 of the ceramic capacitor 101 based on a conventionally known technique, and the lower surface 13 of the core substrate 11 and the capacitor of the ceramic capacitor 101 are also formed. A second buildup layer 32 is formed on the back surface 103. As a result, the wiring substrate 10 including the core substrate 11 and the buildup layers 31 and 32 is completed.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) In this embodiment, in the step of incorporating the ceramic capacitor 101, for example, when the ceramic capacitor 101 is fixed in the accommodation hole 91 of the core substrate 11 with the filler 92, the filler 92 is cured by heat treatment. Shrink. Further, when the build-up layers 31 and 32 are laminated on the upper surface 12 and the lower surface 13 of the core substrate 11, the film-like insulating resin material that becomes the resin interlayer insulating layers 33 to 36 is cured by applying pressure and heat treatment. Then shrink. In these cases, external stress is applied to the surface of the ceramic capacitor 101.

  Therefore, in the ceramic capacitor 101 of the present embodiment, the hole 161 is provided in the outer peripheral portion of the cover layer portions 108 and 109. For this reason, the dielectric portion (the portion of the ceramic dielectric layer 153) is divided by the hole 161 and becomes discontinuous. As a result, a crack 215 (see FIG. 17) starting from the outer peripheral surface of the ceramic capacitor 101 is generated due to external stress applied to the capacitor surface when incorporated in the wiring board 10, and the crack 215 is formed in the center direction of the ceramic capacitor 101. Even if it progresses, it does not progress any more by reaching the hole 161.

  (2) In the present embodiment, the dummy via conductor 162 is formed in the hole 161. For this reason, the toughness in the cover layer portions 108 and 109 of the ceramic sintered body 104 is improved by the dummy via conductor 162. Moreover, since the dummy electrode layer 154 having a large area is formed in the cover layer portions 108 and 109, the toughness in the cover layer portions 108 and 109 is further improved. Thereby, generation | occurrence | production of the above-mentioned crack 215 can be suppressed reliably.

  (3) In this embodiment, since the ceramic capacitor 101 is disposed immediately below the IC chip 21 mounted in the IC chip mounting area 23, the wiring connecting the ceramic capacitor 101 and the IC chip 21 is shortened, and the wiring inductance is reduced. Increase in ingredients is prevented. Therefore, the switching noise of the IC chip 21 due to the ceramic capacitor 101 can be reliably reduced, and the power supply voltage can be reliably stabilized. In addition, since noise entering between the IC chip 21 and the ceramic capacitor 101 can be suppressed to a very low level, high reliability can be obtained without causing malfunction such as malfunction.

  (4) In this embodiment, since the IC chip mounting area 23 is located in the area directly above the ceramic capacitor 101, the IC chip 21 mounted in the IC chip mounting area 23 has high rigidity and a thermal expansion coefficient. Supported by a small ceramic capacitor 101. Therefore, in the IC chip mounting area 23, the first buildup layer 31 is not easily deformed, so that the IC chip 21 mounted in the IC chip mounting area 23 can be supported more stably.

  In addition, you may change this embodiment as follows.

  In the ceramic capacitor 101 of the above embodiment, the holes 161 are arranged in a ring and in a row when viewed from the thickness direction of the cover layer portions 108 and 109, but the present invention is not limited to this. For example, like the ceramic capacitor 301 shown in FIG. 6, the holes 161 may be arranged in an annular shape and in two rows when viewed from the thickness direction of the cover layer portions 108 and 109. In this way, the probability that the crack 215 (see FIG. 17) reaches the hole 161 is increased. Thereby, the progress of the crack 215 can be reliably prevented at the outer peripheral portions of the cover layer portions 108 and 109.

  Furthermore, as shown in FIG. 6, the holes 161 may be arranged in a staggered manner. In this way, even if the crack 215 passes between the plurality of holes 161 constituting the outer row, the crack 215 reliably reaches the holes 161 in the inner row. As a result, the progress of the crack 215 can be prevented more reliably at the outer peripheral portions of the cover layer portions 108 and 109.

  In the ceramic capacitor 101 of the above embodiment, the holes 161 (and the dummy via conductors 162) are arranged at an equal pitch, but the present invention is not limited to this. For example, like the ceramic capacitor 351 shown in FIG. 8, more hole portions 161 (and dummy via conductors 162) are arranged in the corner portions 352 of the cover layer portions 108 and 109 than in the above embodiment, and the corner portions 352 are arranged. The pitch of the holes 161 arranged may be smaller than the pitch of the holes 161 arranged parallel to the four sides 110. Further, the hole 161 arranged in the corner 352 may be set deeper than the hole 161 arranged in parallel with the four sides 110. Further, the inner diameter of the hole 161 arranged at the corner 352 may be set larger than the inner diameter of the hole 161 arranged in parallel with the four sides 110. As described above, the dummy via conductor 162 further improves the toughness of the corner portion 352 where stress is likely to concentrate. Thereby, generation | occurrence | production of the above-mentioned crack 215 can be suppressed reliably.

  In the ceramic capacitor 101 of the above-described embodiment, a large number of holes 161 are provided in a region that becomes the outer peripheral portion of the cover layer portions 108 and 109 so as to surround the via conductors 131 and 132 in the capacitor. It is not limited. For example, as in the ceramic capacitor 311 shown in FIG. 7, holes 163 formed in the shape of slits extending in parallel with the four sides 110 in the outer peripheral portions of the cover layer portions 108 and 109 are connected to the via conductors 131 and 132 in the capacitor. A dummy via conductor 164 may be formed in the hole 163 so as to surround the hole. In this way, when the above-described crack 215 progresses to the cover layer portions 108 and 109, the probability that the crack 215 reaches the hole portion 163 is increased. Thereby, the progress of the crack 215 can be more reliably prevented at the outer peripheral portions of the cover layer portions 108 and 109.

  In the ceramic capacitor 101 of the above embodiment, the hole 161 that penetrates only the cover layer portion 108 in the thickness direction and the hole 161 that penetrates only the cover layer portion 109 in the thickness direction are provided. It is not limited to this. For example, as in a ceramic capacitor 321 shown in FIG. 9, a hole 165 that penetrates the capacitor forming layer portion 107 and the cover layer portions 108 and 109 in the thickness direction and opens at both the capacitor main surface 102 and the capacitor back surface 103 is formed. The dummy via conductor 166 may be formed in the hole 165. In this way, the probability that the crack 215 reaches the hole 165 is increased regardless of which of the capacitor forming layer portion 107 and the cover layer portions 108 and 109 propagates. Thereby, the crack 215 can be prevented from progressing in both the outer peripheral portion of the capacitor forming layer portion 107 and the outer peripheral portions of the cover layer portions 108 and 109.

  In the ceramic capacitor 101 of the above embodiment, the height of the dummy via conductor 162 is equal to the depth of the hole 161, but the present invention is not limited to this. For example, like the ceramic capacitor 361 shown in FIG. 13, the height of the dummy via conductor 362 may be smaller than the depth of the hole 161. In this way, a part of the resin interlayer insulating layer 33 in contact with the capacitor main surface 102 and a part of the resin interlayer insulating layer 34 in contact with the capacitor back surface 103 enter the hole 161, so that the ceramic capacitor 361 and The bonding strength with the buildup layers 31 and 32 is improved, and as a result, the reliability of the wiring board 10 is improved. Further, like the ceramic capacitor 363 shown in FIG. 14, the height of the dummy via conductor 364 may be larger than the depth of the hole 161. In this way, the protruding portion of the dummy via conductor 364 from the capacitor main surface 102 bites into the resin interlayer insulating layer 33, or the protruding portion of the dummy via conductor 364 from the capacitor back surface 103 bites into the resin interlayer insulating layer 34. Will come to do. As a result, the bonding strength between the ceramic capacitor 363 and the buildup layers 31 and 32 is improved, and as a result, the reliability of the wiring board 10 is improved.

  In the ceramic capacitor 101 of the above embodiment, the depth of the hole 161 is equal to the thickness of the cover layer portions 108 and 109, but the present invention is not limited to this. For example, like the ceramic capacitor 371 shown in FIG. 15, the depth of the hole 167 is smaller than the thickness of the cover layer portions 108 and 109 (specifically, equal to the thickness of the ceramic dielectric layer 153 for two layers). In addition, the dummy via conductor 168 may be formed in the hole 167. That is, the dummy via conductor 168 may not be electrically connected to the internal electrodes 141 and 142 by not forming the hole portion 167 in the capacitor forming layer portion 107. In this way, the area of the internal electrodes 141 and 142 can be increased by bringing the outer peripheral portions of the internal electrodes 141 and 142 close to the vicinity of the capacitor side surface 106, so that the capacity of the ceramic capacitor 371 can be increased. Can do.

  The cover layer portions 108 and 109 in the above embodiment have a structure in which a plurality of ceramic dielectric layers 153 and dummy electrode layers 154 are alternately stacked. However, the dummy electrode layer 154 may be omitted, and the cover layer portions 108 and 109 may be configured only by the ceramic dielectric layer 153.

  In the above embodiment, the ceramic dielectric layer 153 of the cover layer portions 108 and 109 is formed thicker than the ceramic dielectric layer 105 of the capacitor forming layer portion 107, and the dummy electrode layer 154 of the cover layer portions 108 and 109 is formed of the capacitor. It was formed thicker than the internal electrodes 141 and 142 of the layer portion 107. However, the thickness of the ceramic dielectric layer 153 may be set equal to the thickness of the ceramic dielectric layer 105, and the thickness of the dummy electrode layer 154 may be set equal to the thickness of the internal electrodes 141 and 142. In this way, since the ceramic sintered body 104 can be fired by laminating green sheets having the same thickness, the manufacturing cost can be suppressed. Further, since the arrangement interval of the dummy electrode layers 154 is shortened in the cover layer portions 108 and 109, the occurrence of the cracks 215 can be reliably prevented.

  In the ceramic capacitor 101 of the above embodiment, the cover layer portion 108 is provided on the capacitor main surface 102 side of the ceramic sintered body 104 and the cover layer portion 109 is provided on the capacitor back surface 103 side of the ceramic sintered body 104. It was. However, the cover layer portions 108 and 109 may be provided only on the capacitor main surface 102 side, or may be provided only on the capacitor back surface 103 side.

  In the ceramic capacitor 101 of the above embodiment, the terminal electrodes (electrodes 111, 112, 121, 122) are formed on both the capacitor main surface 102 and the capacitor back surface 103, but the present invention is not limited to this. For example, like the ceramic capacitor 331 shown in FIG. 10, the terminal electrodes (electrodes 111 and 112) may be formed only on the capacitor main surface 102 side.

  In the wiring substrate 10 of the above-described embodiment, the ceramic capacitor 101 is built in the accommodation hole portion 91 opened at the upper surface 12 and the lower surface 13 of the core substrate 11, but is not limited thereto. For example, the accommodation hole 91 may be a bottomed recess (non-through hole) that opens only on the upper surface 12 of the core substrate 11, and the ceramic capacitor 101 may be incorporated therein.

  In the above embodiment, the package form of the wiring board 10 is BGA (ball grid array), but is not limited to BGA, and may be, for example, PGA (pin grid array), LGA (land grid array), or the like. .

  In the above embodiment, the ceramic capacitor 101 is built in the wiring board 10. However, the ceramic capacitor 101 may be surface-mounted on the main surface of the wiring board 10. FIG. 11 shows a specific example thereof. In the wiring substrate 341 of FIG. 11, the ceramic capacitor 101 is surface-mounted on the main surface 342 of the substrate by a flip chip method. In the wiring board 341, when the ceramic capacitor 101 is surface-mounted using solder, a compressive stress is applied to the vicinity of the surface layer of the ceramic capacitor 101 due to a difference in thermal expansion between the wiring board 341 and the ceramic capacitor 101. In the ceramic capacitor 101, the dummy electrode layer 154 having a large area is formed in the cover layer portions 108 and 109, and its toughness is sufficiently ensured. For this reason, in the cover layer portions 108 and 109, the occurrence of cracks starting from the outer peripheral surface of the ceramic capacitor 101 is avoided. Even if a crack is generated and propagated, the crack stops at the hole 161, and the crack does not propagate to the inner capacitor forming layer 107.

  Further, as in the wiring board 343 of FIG. 12, the gap between the substrate main surface 344 and the ceramic capacitor 101 may be sealed with an underfill material 345 (resin material). In the wiring substrate 343, in the sealing process with the underfill material 345, tensile stress due to thermosetting shrinkage of the underfill material 345 acts on the ceramic capacitor 101. In the ceramic capacitor 101, the dummy electrode layer 154 having a large area is formed in the cover layer portions 108 and 109, and its toughness is sufficiently ensured. For this reason, in the cover layer portions 108 and 109, it is possible to avoid the occurrence of cracks starting from the outer peripheral surface of the ceramic capacitor 101. Even if a crack occurs, the crack stops in the hole 161 and does not propagate to the inner capacitor forming layer 107.

  -In the manufacturing method of the said embodiment, after forming the several hole part 161 in the site | part used as the upper cover layer part 108 in a green sheet laminated body, in a state where the green sheet laminated body was turned over, a lower cover layer part The plurality of hole portions 161 are formed in the portion to be 109, but may be changed to the following method, for example. That is, a laminate of the first green sheet to be the capacitor forming layer portion 107 and a laminate of the second green sheet to be the cover layer portions 108 and 109 are separately formed, and a plurality of laminates are formed with respect to the laminate of the second green sheet. The hole 161 is formed. Thereafter, the laminate of the first green sheets and the laminate of the second green sheets are joined to form a green sheet laminate.

  Next, in addition to the technical ideas described in the claims, the technical ideas grasped by the embodiment described above are listed below.

  (1) A capacitor comprising a plate-like capacitor body having a capacitor main surface and a capacitor back surface, and a plurality of in-capacitor via conductors formed in a plurality of via holes extending along the thickness direction of the capacitor body. The capacitor body includes a plurality of first dielectric layers and a plurality of first dielectric layers alternately stacked with a plurality of internal electrodes electrically connected to the plurality of via conductors in the capacitors; and the capacitors A second dielectric multilayer portion disposed so as to be exposed at the capacitor main surface or the capacitor back surface of the main body, and at least an outer peripheral portion of the second dielectric multilayer portion as viewed from the thickness direction. A hole extending in the thickness direction of the second dielectric laminate portion and opening in at least one of the capacitor main surface and the capacitor back surface. A dummy via conductor provided so as to surround the via conductor in the capacitor and not electrically connected to the internal electrode is formed in the hole portion using the same material as the via conductor in the capacitor. Capacitor.

  (2) In the technical idea (1), the depth of the hole is equal to the thickness of the second dielectric laminated portion.

  (3) In the technical idea (2), the depth of the hole is smaller than the thickness of the second dielectric laminated portion.

  (4) A capacitor comprising a plate-like capacitor body having a capacitor main surface and a capacitor back surface, and a plurality of in-capacitor via conductors formed in a plurality of via holes extending along the thickness direction of the capacitor body. The capacitor body includes a plurality of first dielectric layers and a plurality of first dielectric layers formed by alternately stacking a plurality of internal electrodes electrically connected to the plurality of via conductors in the capacitors; The second dielectric layer and the dummy electrode layers not electrically connected to the plurality of via conductors in the capacitor are alternately laminated, and are exposed on the capacitor main surface or the capacitor back surface of the capacitor body. The dummy electrode layer is formed using the same material as that of the internal electrode, and the second dielectric layer is viewed from the thickness direction. A hole extending in the thickness direction of the second dielectric multilayer portion and opening in at least one of the capacitor main surface and the capacitor back surface in a region that is at least an outer peripheral portion of the electric conductor multilayer portion, A capacitor characterized by being provided so as to surround the inner via conductor.

  (5) In the technical idea (4), the thickness of the dummy electrode layer is equal to or greater than the thickness of the internal electrode.

DESCRIPTION OF SYMBOLS 10,341,343 ... Wiring board 101,301,311,321,331,351,361,363 ... Ceramic capacitor 102 as a capacitor ... Capacitor main surface 103 ... Capacitor back surface 104 ... Ceramic sintered body 105 as a capacitor body ... Ceramic dielectric layer 107 as the first dielectric layer ... Capacitor forming layer portion 108, 109 as the first dielectric laminate portion Cover layer portion 110 as the second dielectric laminate portion ... Side 130 ... Via hole 131 ... Capacitor Power supply capacitor inner via conductor 132 as inner via conductor ... Ground capacitor inner via conductor 141 as capacitor via conductor 141 ... Power supply inner electrode 142 as inner electrode ... Ground inner electrode 153 as inner electrode ... Second dielectric Ceramic dielectric layer 154 as a body layer ... dummy electrode layer 61,163,165,167 ... hole 162,164,166,168,362,364 ... dummy via conductors 342, 344 ... substrate main surface

Claims (9)

A plate-shaped capacitor body having a capacitor main surface and a capacitor back surface;
A capacitor comprising a plurality of via conductors in a capacitor formed in a plurality of via holes extending along the thickness direction of the capacitor body,
The capacitor body is
A plurality of first dielectric layers and a plurality of first electrodes laminated alternately with a plurality of internal electrodes electrically connected to the plurality of via conductors in the capacitor;
And a second dielectric laminate portion disposed so as to be exposed at the capacitor main surface or the capacitor back surface of the capacitor body,
Extending along the thickness direction of the second dielectric laminate portion to at least one of the capacitor main surface and the capacitor back surface in a region that is at least the outer peripheral portion of the second dielectric laminate portion when viewed from the thickness direction A hole opening to surround the via conductor in the capacitor ,
A capacitor, wherein a dummy via conductor not electrically connected to the internal electrode is formed in the hole . The plurality of holes are formed in an outer peripheral portion of the second dielectric multilayer portion, and are arranged annularly and in a plurality of rows as viewed from the thickness direction of the second dielectric multilayer portion. The capacitor according to claim 1 . The hole portion penetrates the first dielectric laminate portion and the second dielectric laminate portion in the thickness direction, and is opened on both the capacitor main surface and the capacitor back surface of the capacitor body. The capacitor according to claim 1 or 2 , characterized in that The capacitor body has a substantially rectangular plate shape having four sides when viewed from the thickness direction,
2. The capacitor according to claim 1 , wherein the hole is formed in a slit shape extending in parallel with at least one of the four sides in the outer peripheral portion of the second dielectric multilayer portion. . The second dielectric laminated portion is formed by alternately laminating a plurality of second dielectric layers and dummy electrode layers not electrically connected to the plurality of via conductors in the capacitor. Item 5. The capacitor according to any one of Items 1 to 4 . A wiring board incorporating the capacitor according to any one of claims 1 to 5 . Has a substrate main surface, a wiring substrate on which surface-mounted capacitor according at flip chip method in any one of claims 1 to 5 on the substrate main surface. A method for manufacturing a capacitor according to any one of claims 1 to 5 ,
A laminating step of stacking and integrating a ceramic first green sheet to be the first dielectric laminate and a ceramic second green sheet to be the second dielectric laminate to produce a green sheet laminate;
A hole forming step for forming the via hole and the hole portion in the green sheet laminate by performing laser processing;
A via filling step of filling a via conductor forming material into at least the via hole of the via hole and the hole portion;
And a firing step of firing the first green sheet, the second green sheet, and the via conductor forming material by heating the green sheet laminate to a temperature at which the ceramic can be sintered. Manufacturing method. In the laminating step, the second green sheet is laminated on both the first surface side and the second surface side of the first green sheet,
The hole forming step includes a via hole forming step of forming the via hole in the green sheet laminate, and a first portion of forming the hole in the second green sheet laminated on the first surface side of the first green sheet. After the hole forming step and the first hole forming step, the hole is formed in the second green sheet laminated on the second surface side of the first green sheet with the green sheet laminate turned upside down. The method for manufacturing a capacitor according to claim 8 , further comprising a second hole portion forming step.

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