JP2007258545A - Wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board capable of stably supplying power to a semiconductor element. <P>SOLUTION: A core member 11 of the wiring board 10 has a housing hole 91 opened on a core first main surface 12 and a core second main surface 13, and a ceramic capacitor 101 is housed in the housing hole 91. A build-up layer 31 for supporting an IC chip 21 is formed on the core first main surface 12, and a build-up layer 32 to be connected to a mother board 60 is formed on the core second main surface 13. A through hole conductor 16 is formed in a hole 15 for a through hole of the core 11. Via conductors 131, 132 each having a cross sectional area larger than the cross sectional area of the through hole conductor 16 are formed in the ceramic capacitor 101. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a wiring board incorporating a ceramic chip.

  In recent years, semiconductor integrated circuit elements (IC chips) used for a CPU of a computer have been increased in speed and function, and accordingly, the number of terminals is increased and the pitch between terminals tends to be narrowed. In general, a large number of terminals are densely arranged on the bottom surface of an IC chip, and such a terminal group is connected to a terminal group on the motherboard side in the form of a flip chip. However, it is difficult to connect the IC chip directly on the mother board because there is a large difference in the pitch between the terminals on the IC chip side terminal group and the mother board side terminal group. For this reason, generally, a technique is adopted in which an IC chip is mounted on an IC chip mounting wiring board, and the IC chip mounting wiring board is mounted on a motherboard. As this type of IC chip mounting wiring board, for example, a core part is formed by embedding a ceramic chip in a core material made of a polymer material, and build-up layers are formed on the front and back surfaces of the core part. Conventionally proposed (see, for example, Patent Documents 1 and 2).

  FIG. 13 shows a conventional IC chip mounting wiring board 200. The IC chip mounting wiring substrate 200 includes a flat core material 201 made of glass epoxy, a buildup layer 202 formed on the upper surface of the core material 201, and a build formed on the lower surface of the core material 201. And an up layer 203. The core material 201 has a housing hole 205 that opens at the upper surface and the lower surface, and the ceramic chip 206 is housed and fixed in the housing hole 205.

  The buildup layer 202 has a structure in which resin insulation layers (so-called interlayer insulation layers) 207 and 208 made of epoxy resin and conductor layers 209 made of copper are alternately laminated. An IC chip 210 (semiconductor integrated circuit element) is mounted. Similarly, the build-up layer 203 has a structure in which the resin insulating layers 211 and 212 and the conductor layers 213 are alternately stacked, and is connected to the mother board 214 via the build-up layer 203.

  A number of through-hole conductors 216 having a diameter of about 300 μm are formed in the core material 201 so that the upper and lower surfaces communicate with each other. The inside of the through-hole conductor 216 is filled with a closing body 217 such as an epoxy resin. The through-hole conductor 216 is connected to the conductor layers 209 and 213 of the buildup layers 202 and 203. Then, a current is supplied to the IC chip 210 from the mother board 214 side through the conductor layers 209 and 213 and the through-hole conductor 216.

A plurality of via conductors 220 having a diameter of about 100 μm are formed in the ceramic chip 206 so that the upper and lower surfaces communicate with each other. The via conductor 220 of the ceramic chip 206 is also connected to the conductor layers 209 and 213 of the buildup layers 202 and 203. Then, a current is supplied from the mother board 214 side to the IC chip 210 through the conductor layers 209 and 213 and the via conductor 220.
JP 2002-100870 A JP-A-2005-39243

  By the way, the through-hole conductor 216 of the core material 201 is formed by performing copper plating. On the other hand, the via conductor 220 of the ceramic chip 206 is formed using a metal material suitable for metallization that can be sintered simultaneously with the ceramic, such as nickel. That is, the via conductor 220 of the ceramic chip 206 is formed using nickel, which has higher electrical resistance than copper. The via conductor 220 has a smaller diameter than the through-hole conductor 216 and a cross-sectional area smaller than that of the through-hole conductor 216. Accordingly, the wiring through the via conductor 220 of the ceramic chip 206 has a higher resistance value than the wiring through the through-hole conductor 216 of the core material 201. For this reason, there is a concern that the power supply to the IC chip 210 may vary. If the power supply to the IC chip 210 varies, the circuit operation becomes unstable, and the performance of the IC chip 210 deteriorates.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a wiring board capable of stably supplying power to a semiconductor element.

  A means (means 1) for solving the above-mentioned problems has a core first main surface and a core second main surface, and is open at least in any one of the core first main surface and the core second main surface. A core material having an accommodating hole portion, a through-hole conductor formed in a through-hole for passing through the core material in the thickness direction, and a chip first main surface and a chip second main surface. In-chip via conductors are formed, and a ceramic chip for embedding accommodated and fixed in the accommodating hole and a first interlayer insulating layer having a via conductor in the first insulating layer are laminated on the first main surface of the core. A structure in which a first wiring stacked portion capable of supporting a semiconductor element and a second interlayer insulating layer having a via conductor in a second insulating layer are stacked on the second main surface of the core. And a second wiring stack that can be supported by the mother board With the door, the cross-sectional area of the chip via conductor, and its gist the wiring board being greater than the cross-sectional area of the through-hole conductors.

  Therefore, according to the wiring substrate of means 1, since the cross-sectional area of the via conductor in the chip is larger than the cross-sectional area of the through-hole conductor, a sufficient current can be supplied to the semiconductor element via the via conductor in the chip. As a result, variations in power supply are easily eliminated, the semiconductor element can be stably operated, and the performance of the semiconductor element can be sufficiently exhibited.

  Another means (means 2) for solving the above-described problem has a core first main surface and a core second main surface, and is at least one of the core first main surface and the core second main surface. A core material having a receiving hole portion that opens, a through-hole conductor formed in a through-hole for passing through the core material in the thickness direction, a chip first main surface and a chip second main surface. An embedded via-chip conductor is formed inside the embedded ceramic chip accommodated and fixed in the accommodating hole, and a first interlayer insulating layer having a first insulating-layer via conductor is formed on the first main surface of the core. A first wiring laminated portion capable of supporting a semiconductor element and a second interlayer insulating layer having a via conductor in the second insulating layer are laminated on the second main surface of the core. Second wiring having the above structure and capable of being supported by the mother board A chip first main surface side electrode disposed on the chip first main surface and a position corresponding to the position of the chip first main surface side electrode on the chip second main surface. A chip second main surface side electrode, and a chip via conductor group comprising a plurality of chip via conductors arranged in parallel between the chip first main surface side electrode and the chip second main surface side electrode. The wiring board is characterized in that the chip first main surface side electrode and the chip second main surface side electrode are connected to end portions of the in-chip via conductor group.

  Therefore, according to the wiring board of the means 2, in the embedded ceramic chip, an in-chip via conductor group composed of a plurality of in-chip via conductors is provided between the chip first main surface side electrode and the chip second main surface side electrode. Therefore, a sufficient current can be supplied to the semiconductor element via the via conductor group in the chip. As a result, variations in power supply are easily eliminated, the semiconductor element can be stably operated, and the performance of the semiconductor element can be sufficiently exhibited.

  The cross-sectional area of the in-chip via conductor group is preferably larger than the cross-sectional area of the through-hole conductor. If it does in this way, sufficient electric current can be supplied to a semiconductor element via the via conductor in the chip.

  The resistance value per unit length of the in-chip via conductor may be smaller than the resistance value per unit length of the through-hole conductor. In this way, since the amount of current flowing through the in-chip via conductor can be increased as compared with the through-hole conductor, a sufficient amount of current can be ensured to be supplied to the semiconductor element via the in-chip via conductor.

  The maximum diameter of the in-chip via conductor may be 120 μm or more and 200 μm or less. In the conventional embedded ceramic chip, since the maximum diameter of the via conductor in the chip is about 100 μm, it is difficult to supply a sufficient current to the semiconductor element. On the other hand, the supply current to the semiconductor element can be sufficiently ensured by setting the maximum diameter of the via conductor in the chip to 120 μm or larger, which is larger than the conventional one, as in the wiring board of the present invention. Further, if the maximum diameter of the in-chip via conductor is increased more than necessary, it may be difficult to form the in-chip via conductor, but the problem can be avoided by setting it to 200 μm or less.

  The specific resistance of the metal used for the in-chip via conductor is preferably higher than the specific resistance of the metal used for the through-hole conductor. This is because, when the specific resistance of the via conductor in the chip is increased, it becomes difficult for the current to flow, and the problem of the present invention is likely to occur, so that the significance of adopting the configuration of the present invention is increased.

  The core material forms part of the core portion of the wiring board, and is formed in a flat plate shape having, for example, a core first main surface and a core second main surface located on the back side thereof. Such a core material has one or more housing holes for housing the embedding ceramic chip. The accommodation hole may be a through hole that opens on both the core first main surface and the core second main surface, or a non-through hole that opens on the core first main surface or the core second main surface. It may be. The accommodating recess may be large enough to completely accommodate the embedding ceramic chip, or may be large enough to be accommodated in a state in which a part thereof is protruded.

  Although the material which forms the said core material is not specifically limited, A preferable core material is mainly formed of a polymer material. Specific examples of the polymer material for forming the core material include, for example, EP resin (epoxy resin), PI resin (polyimide resin), BT resin (bismaleimide / triazine resin), PPE resin (polyphenylene ether resin), etc. There is. In addition, composite materials of these resins and glass fibers (glass woven fabric or glass nonwoven fabric) or organic fibers such as polyamide fibers may be used.

  As the embedding ceramic chip, for example, a flat ceramic sintered body having a chip first main surface and a chip second main surface is suitable. As this ceramic sintered body, a sintered body of a high-temperature fired ceramic such as alumina, aluminum nitride, boron nitride, silicon carbide, silicon nitride, etc. is preferably used, and also for borosilicate glass or lead borosilicate glass. A sintered body of low-temperature fired ceramic such as glass ceramic to which an inorganic ceramic filler such as alumina is added is preferably used. In this case, it is also preferable to use a sintered body of a dielectric ceramic such as barium titanate, lead titanate, or strontium titanate depending on the application. When a dielectric ceramic sintered body is used, a ceramic capacitor having a large capacitance can be easily realized.

  The material for forming the in-chip via conductor is not particularly limited, but it is preferable to use a metal that can be sintered at the same time as the ceramic, for example, nickel, molybdenum, tungsten, titanium, or the like. When a low-temperature fired ceramic sintered body is selected, copper, silver, or the like can be further used as a material for forming the via conductor.

  On the chip first main surface of the ceramic chip for embedding, a plurality of chip first main surface side electrodes made of a metallized layer electrically connected to the via conductor in the chip are arranged. Similarly, on the chip second main surface of the ceramic chip for embedding, a plurality of chip second main surface side electrodes made of a metallized layer that is electrically connected to the via conductor in the chip are arranged. Since the plurality of electrodes can be sintered simultaneously with the ceramic, they are formed using a metal material suitable for metallization, such as nickel, molybdenum, tungsten, titanium, or the like.

  Here, the ceramic chip for embedding may be a ceramic capacitor having a structure in which the first internal electrode layers and the second internal electrode layers are alternately stacked via ceramic dielectric layers. When the embedded ceramic chip having a function as a capacitor is used as described above, for example, the stray inductance can be reliably reduced by being disposed in the vicinity of the semiconductor element, so that the semiconductor element is stably operated. It becomes possible.

  The first wiring laminated portion constituting the wiring substrate has a structure in which a first interlayer insulating layer having a via conductor in the first insulating layer is laminated on the first main surface of the core, and supports a semiconductor integrated circuit element. To do. The second wiring laminated portion has a structure in which a second interlayer insulating layer having a via conductor in the second insulating layer is laminated on the second core main surface, and is supported by a mother board. The first wiring laminated portion and the second interlayer insulating layer preferably include a build-up layer formed by alternately laminating an interlayer insulating layer mainly composed of a polymer material and a conductor layer. The first insulating layer via conductor formed in the first interlayer insulating layer and the second insulating layer via conductor formed in the second wiring laminated portion may be conformal vias or filled vias. However, filled vias are preferable from the viewpoint of reducing resistance. Conformal via means that a plating layer with a uniform thickness is formed along the shape of the via hole, and therefore the via hole is not completely filled with the plating layer, and a type of via having a depression is used. pointing. On the other hand, a filled via refers to a type of via that has a plating layer with a non-uniform thickness, the via hole is completely filled with the plating layer, and has no depression.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

  As shown in FIG. 1, a ceramic chip built-in wiring board 10 according to the present embodiment is a wiring board for mounting an IC chip, and includes a substantially rectangular plate-shaped core material 11 made of glass epoxy and a core of the core material 11. Formed on the build-up layer 31 (first wiring laminated portion) formed on the first main surface 12 (upper surface in FIG. 1) and the core second main surface 13 (lower surface in FIG. 1) of the core material 11 And the buildup layer 32 (second wiring laminated portion). Through holes 15 penetrating in the thickness direction are formed at a plurality of locations in the core material 11, and an outer diameter is 300 μm and a thickness is 20 μm by applying copper plating to the inner surface of the through hole 15. Through-hole conductors 16 are formed. The through-hole conductor 16 connects and connects the upper surface 12 side and the lower surface 13 side of the core material 11. Note that the inside of the through-hole conductor 16 is filled with a closing body 17 made of an insulating material (for example, an epoxy resin containing a silica filler). A conductor layer 41 made of copper is patterned on the upper surface 12 and the lower surface 13 of the core material 11, and each conductor layer 41 is electrically connected to the through-hole conductor 16.

  The buildup layer 31 formed on the upper surface 12 of the core material 11 is formed by alternately laminating two resin insulating layers 33 and 35 (first interlayer insulating layer) made of epoxy resin and a conductor layer 42 made of copper. It has the structure. Terminal pads 44 are formed in an array at a plurality of locations on the surface of the resin insulation layer 35. The surface of the resin insulating layer 35 is almost entirely covered with a solder resist 37. An opening 46 for exposing the terminal pad 44 is formed at a predetermined position of the solder resist 37. The terminal pad 44 is electrically connected to the IC chip 21 (semiconductor integrated circuit element) through a plurality of solder bumps 45.

  A plurality of via holes 51 and via conductors 52 are provided in the resin insulating layer 33, and a plurality of via holes 55 and via conductors 56 are provided in the resin insulating layer 35. The via holes 51 and 55 of the resin insulating layers 33 and 35 are formed in a bowl shape by laser processing. The via holes 51 and 55 have a diameter on the large diameter side of about 100 μm and a diameter on the small diameter side of about 70 μm. By filling the via holes 51 and 55 with copper, filled via conductors 52 and 56 are formed therein. In the present embodiment, most of the via conductors 52 and 56 (via conductors in the first insulating layer) are arranged coaxially, and the conductor layers 41 and 42 and the terminal pads 44 are electrically connected to each other through them. It is connected.

  The buildup layer 32 formed on the lower surface 13 of the core material 11 has substantially the same structure as the buildup layer 31 described above. That is, the buildup layer 32 has a structure in which two resin insulating layers 34 and 36 (second interlayer insulating layer) made of an epoxy resin and the conductor layer 42 are alternately stacked. BGA pads 48 that are electrically connected to the conductor layer 42 via via conductors 56 (second in-layer via conductors) are formed in a lattice pattern at a plurality of locations on the lower surface of the resin insulating layer 36. . The lower surface of the resin insulating layer 36 is almost entirely covered with a solder resist 38. An opening 40 for exposing the BGA pad 48 is formed at a predetermined portion of the solder resist 38. On the surface of the BGA pad 48, a plurality of solder bumps 49 are provided for electrical connection with the mother board 60 (mother board). The wiring board 10 is mounted on the mother board 60 by the solder bumps 49.

  The core material 11 has a rectangular accommodation hole 91 in a plan view that opens at the center of the upper surface 12 and the center of the lower surface 13. That is, the accommodation hole 91 is a through hole. A ceramic capacitor 101 (embedded ceramic chip) shown in FIGS. 2, 3 and the like is housed in the housing hole 91 in an embedded state. The ceramic capacitor 101 has the chip first main surface 102 (the upper surface in FIGS. 1 and 2) facing the same side as the core first main surface 12 of the core material 11, and the chip second main surface 103 (FIGS. 1 and 2). Then, the lower surface is accommodated with the core material 11 facing the same side as the core second main surface 13. The ceramic capacitor 101 of this embodiment has a rectangular flat plate shape of 12.0 mm long × 12.0 mm wide × 0.80 mm thick. Further, the gap between the inner surface of the accommodation hole 91 and the side surface 106 of the ceramic capacitor 101 is filled with a filler 92 made of a polymer material (thermosetting resin in the present embodiment). The filler 92 has a function of fixing the ceramic capacitor 101 to the core material 11 and absorbing the deformation of the ceramic capacitor 101 and the core material 11 in the surface direction and the thickness direction by its own elastic deformation.

  As shown in FIGS. 1 to 3, the ceramic capacitor 101 of this embodiment is a so-called via array type ceramic capacitor. The ceramic sintered body 104 constituting the ceramic capacitor 101 is a plate-like object having a chip first main surface 102 (upper surface) and a chip second main surface 103 (lower surface). The ceramic sintered body 104 has a structure in which the first internal electrode layers 141 and the second internal electrode layers 142 are alternately stacked via the ceramic dielectric layer 105. The ceramic dielectric layer 105 is made of a sintered body of barium titanate, which is a kind of high dielectric constant ceramic, and functions as a dielectric (insulator) between the first internal electrode layer 141 and the second internal electrode layer 142. Each of the first internal electrode layer 141 and the second internal electrode layer 142 is a layer formed mainly of nickel, and is disposed every other layer inside the ceramic sintered body 104.

  A number of via holes 130 are formed in the ceramic sintered body 104. These via holes 130 penetrate the ceramic sintered body 104 in the thickness direction and are arranged in a lattice shape (array shape) over the entire surface. In each via hole 130, a plurality of via conductors 131 and 132 penetrating between the upper surface 102 and the lower surface 103 of the ceramic sintered body 104 are formed using nickel as a main material. Each first via conductor 131 passes through each first internal electrode layer 141 and electrically connects them to each other. Each second via conductor 132 penetrates each second internal electrode layer 142 and electrically connects them to each other.

  A plurality of first external terminal electrodes 111 and 112 (chip first main surface side electrodes) protrude from the upper surface 102 of the ceramic sintered body 104. On the lower surface 103 of the ceramic sintered body 104, a plurality of second external terminal electrodes 121 and 122 (chip second main surface side electrodes) are projected. The first external terminal electrodes 111 and 112 on the upper surface 102 side are electrically connected to the connection terminals of the IC chip 21 via the via conductor 52, the conductor layer 42, the via conductor 56, the terminal pad 44 and the solder bump 45. Connected. On the other hand, the second external terminal electrodes 121 and 122 on the lower surface 103 side are connected to the vias 52, the conductor layers 42, the via conductors 56, the BGA pads 48, and the solder bumps 49 with respect to the electrodes (contacts) of the mother board 60. It is electrically connected via. In addition, the substantially central portions of the bottom surfaces of the first external terminal electrodes 111 and 112 are directly connected to the end surfaces of the via conductors 131 and 132 on the top surface 102 side, and the substantially central portions of the bottom surfaces of the second external terminal electrodes 121 and 122. Are directly connected to the end surfaces of the via conductors 131 and 132 on the lower surface 103 side. Therefore, the external terminal electrodes 111 and 121 are electrically connected to the via conductor 131 and the first internal electrode layer 141, and the external terminal electrodes 112 and 122 are electrically connected to the via conductor 132 and the second internal electrode layer 142.

  The external terminal electrodes 111, 112, 121, and 122 have a layer structure in which a copper plating layer is formed on a metallized layer containing nickel as a main material. A copper plating layer consists of a metal softer than the metal which comprises a metallization layer, The surface is roughened. For this reason, the surfaces of the first external terminal electrodes 111 and 112 are rougher than the upper surface 102 of the ceramic sintered body 104. Similarly, the surfaces of the second external terminal electrodes 121 and 122 are also rougher than the lower surface 103 of the ceramic sintered body 104. Further, the external terminal electrodes 111, 112, 121, 122 when viewed from the direction perpendicular to the upper surface 102 (part thickness direction) are substantially circular (see FIG. 3). In the present embodiment, the diameter of the external terminal electrodes 111, 112, 121, 122 is set to about 500 μm.

In this embodiment, the via conductors 131 and 132 in the ceramic capacitor 101 contain 30 vol% barium titanate component (BT) with respect to nickel (Ni) as a main material, and the specific resistance is 13.0 ×. 10 ⁶ (Ω · cm). That is, the via conductors 131 and 132 have a higher specific resistance than copper (the specific resistance is 1.7 × 10 ⁶ (Ω · cm)) constituting the through-hole conductor 16 of the core material 11, and thus the via conductors 131 and 132 are more than the through-hole conductor 16. It is difficult to pass electricity.

Here, the resistance value R is
R = ε × L / S
It can be expressed as Note that ε is a specific resistance, L is a length, and S is a cross-sectional area.

For this reason, the via conductors 131 and 132 of the present embodiment are formed so that the cross-sectional area S is larger than the cross-sectional area of the through-hole conductor 16 with a diameter of 150 μm larger than that of the conventional one (see FIG. 4). Here, the cross-sectional areas of the via conductors 131 and 132 and the through-hole conductor 16 are cross-sectional areas when the via conductors 131 and 132 and the through-hole conductor 16 are cut along a plane parallel to the chip first main surface 12. Specifically, since the through-hole conductor 16 has an outer diameter of 300 μm and a thickness of 20 μm (an annular cross-sectional shape), its cross-sectional area is 17.6 × 10 ⁻³ (= 0.15 × 0). .15 × 3.14−0.13 × 0.13 × 3.14) mm ² . On the other hand, the cross-sectional areas of the via conductors 131 and 132 are 17.7 × 10 ⁻³ (= 0.075 × 0.075 × 3.14) mm ² . Incidentally, since the conventional via conductor 220 (see FIG. 13) has a diameter of 100 μm and a cross-sectional area of 7.9 × 10 ⁻³ mm ² , the via conductors 131 and 132 of this embodiment have 2 A current that is twice or more can flow.

  In the wiring board 10 configured as described above, when energization is performed from the mother board 60 side through the second external terminal electrodes 121 and 122 and a voltage is applied between the first internal electrode layer 141 and the second internal electrode layer 142, the first internal For example, positive charges are accumulated in the electrode layer 141, and negative charges are accumulated in the second internal electrode layer 142, for example. As a result, the ceramic capacitor 101 functions as a capacitor. In the ceramic capacitor 101, the first via conductors 131 and the second via conductors 132 are alternately arranged adjacent to each other, and the directions of the currents flowing through the first via conductors 131 and the second via conductors 132 are opposite to each other. It is set to face. Thereby, the inductance component is reduced. In addition, current is supplied to the IC chip 21 through the via conductors 131 and 132, and current is supplied to the IC chip 21 through the through-hole conductor 16, whereby the IC chip 21 operates.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) In the wiring board 10 of the present embodiment, the via conductors 131 and 132 have a low resistance value by making the cross-sectional area of the via conductors 131 and 132 in the ceramic capacitor 101 larger than the cross-sectional area of the through-hole conductor 16. Therefore, a sufficient amount of current flowing through the via conductors 131 and 132 can be secured. As a result, variations in power supply are easily eliminated, the IC chip 21 can be stably operated, and the performance of the IC chip 21 can be fully exhibited.

  (2) In the wiring board 10 of this embodiment, filled via conductors 52 and 56 made of copper are formed on the resin insulating layers 33, 34, 35, and 36 of the buildup layers 31 and 32. Since the filled via conductors 52 and 56 can be reduced in resistance as compared with the conformal via conductor, a current necessary for the operation of the IC chip 21 can be stably passed.

(3) Since the wiring substrate 10 of the present embodiment includes the ceramic capacitor 101, good power can be supplied to the IC chip 21 by removing noise with the ceramic capacitor 101. Moreover, since the IC chip 21 is disposed directly above the ceramic capacitor 101, the wiring (capacitor connection wiring) connecting the IC chip 21 and the ceramic capacitor 101 is shortened. Therefore, noise entering between the IC chip 21 and the ceramic capacitor 101 can be suppressed to be extremely small, and high reliability can be obtained without causing malfunctions such as malfunctions.
[Second Embodiment]

  Hereinafter, a second embodiment of the wiring board according to the present invention will be described with reference to the drawings.

As shown in FIGS. 5 and 6, the wiring substrate 10 of the present embodiment is different from the first embodiment in the configuration of the ceramic capacitor 101. That is, in the ceramic capacitor 101 of this embodiment, a via conductor in which three via conductors 131 are arranged in parallel between the first external terminal electrode 111 and the second external terminal electrode 121 arranged to face the electrode 111. A group 134 is formed. Further, a via conductor group 135 in which three via conductors 132 are arranged in parallel is formed between the first external terminal electrode 112 and the second external terminal electrode 122 arranged to face the electrode 112. Each of the via conductors 131 and 132 constituting the via conductor groups 134 and 135 has a diameter of 100 μm. Therefore, the cross-sectional area of the via conductor groups 134 and 135 is 23.6 × 10 ⁻³ (= 3 × 0.05 × 0.05 × 3.14) mm ² , and the cross-sectional area of the conventional via conductor (7 .9 × 10 ⁻³ mm ² ). By increasing the cross-sectional area of the via conductor groups 134 and 135 in this way, a sufficient current can be supplied to the IC chip 21 via the via conductor groups 134 and 135. As a result, variations in power supply are easily eliminated, the IC chip 21 can be stably operated, and the performance of the IC chip 21 can be fully exhibited.
[Third Embodiment]

Hereinafter, a third embodiment of the wiring board according to the present invention will be described with reference to the drawings. As shown in FIG. 7, in the wiring substrate 10 of this embodiment, a low-temperature fired ceramic (a ceramic that can be fired simultaneously with a relatively low melting point high-conductivity metal material mainly composed of Cu is used as a material for forming the ceramic capacitor 101. ) And copper is used as a material for forming the via conductors 131 and 132 in the ceramic capacitor 101. That is, the via conductors 131 and 132 are made of the same material as the through-hole conductor 16 and have a specific resistance of 1.7 × 10 ⁶ (Ω · cm). The via conductors 131 and 132 have a diameter of 150 μm and a cross-sectional area of 17.7 × 10 ⁻³ mm ² as in the first embodiment. Therefore, the cross-sectional area of the via conductors 131 and 132 is larger than that of the through-hole conductor 16, and the resistance value per unit length of the via conductors 131 and 132 is smaller than the resistance value per unit length of the through-hole conductor 16. Furthermore, in the wiring board 10 of the present embodiment, via holes 51 and 55 and via conductors 52 and 56 larger than those of the first embodiment are formed in the region corresponding to the chip second main surface 103 in the buildup layer 32 on the lower surface side. Is forming. With this configuration, the resistance value of the wiring through the via conductors 131 and 132 of the ceramic capacitor 101 can be reduced more than the resistance value of the wiring through the through-hole conductor 16, so that the IC is connected via the via conductors 131 and 132. A sufficient current can be supplied to the chip 21. As a result, variations in power supply are easily eliminated, the IC chip 21 can be stably operated, and the performance of the IC chip 21 can be fully exhibited. Instead of the low-temperature fired ceramic, a glass ceramic obtained by adding 40 to 60 parts by weight of an inorganic ceramic filler such as alumina to borosilicate glass or lead borosilicate glass can be used as a forming material.
[Fourth Embodiment]

  A fourth embodiment embodying the wiring board of the present invention will be described below with reference to the drawings. As shown in FIG. 8, in the wiring substrate 10 of the present embodiment, the accommodation hole 91 is a bottomed recess (non-through hole) that opens only on the upper surface 12 of the core material 11, and the ceramic capacitor 101 has the same configuration as that of the first embodiment. In the present embodiment, the resin insulating layer 34 of the buildup layer 32 is entirely in contact with the lower surface 13 of the core material 11. The resin insulating layer 34 and the ceramic capacitor 101 are electrically connected to each other via a plurality of via conductors 58 that penetrate the bottom surface of the housing hole 91 and the lower surface 13 of the core material 11. The insides of these via conductors 58 are filled with a conductor paste. In this wiring board 10 as well, the same effects as those in the first embodiment can be obtained.

  In addition, you may change embodiment of this invention as follows.

  In the second embodiment, via conductor groups 134 and 135 including three via conductors 131 and 132 arranged in parallel between the first external terminal electrodes 111 and 112 and the second external electrodes 121 and 122 are provided. However, the number and arrangement of the via conductors 131 and 132 in the via conductor groups 134 and 135 can be changed as appropriate. Specific examples of the via conductor group are shown in FIGS. That is, in the via conductor group in FIG. 9, two via conductors 131 are provided, and in the via conductor group in FIG. 10, three via conductors 131 are provided. Further, in the via conductor group in FIG. 11, four via conductors 131 are provided, and in the via conductor group in FIG. 12, five via conductors 131 are provided. Thus, by providing a via conductor group including a plurality of via conductors 131, the cross-sectional area can be sufficiently increased. Here, as shown in FIGS. 10 to 12, the via conductors 131 are preferably arranged uniformly with respect to the external terminal electrodes. That is, by arranging the plurality of via conductors 131 so as to be point-symmetric with respect to the center of the external terminal electrode, a wide cross-sectional area of the via conductor 131 can be ensured, and as a result, the cross-sectional area of the via conductor group can be increased. Can be large enough. In addition, the connection strength between the via conductor 131 and the external terminal electrodes 111 and 121 can be sufficiently secured.

  In the above embodiment, the ceramic capacitor 101 is used as the ceramic chip for embedding, but a ceramic chip having no capacitor function may be used instead.

  In the above embodiment, the package form of the wiring board 10 is BGA (ball grid array), but is not limited to BGA, and may be, for example, PGA (pin grid array), LGA (land grid array), or the like. .

  Next, in addition to the technical ideas described in the claims, the technical ideas grasped by the respective embodiments described above are listed below.

  (1) A flat core material having a core first main surface and a core second main surface, and having a receiving hole portion opened at the core first main surface and the core second main surface, and the core material A through-hole conductor formed in a through-hole hole penetrating in the thickness direction, a chip first main surface and a chip second main surface, and an in-chip via conductor formed therein, An embedded ceramic chip housed and fixed in the first insulating layer, and a first interlayer insulating layer having a via conductor in the first insulating layer stacked on the core first main surface and the chip first main surface, A first wiring laminated portion capable of supporting a semiconductor integrated circuit element and a second interlayer insulating layer having a via conductor in the second insulating layer are laminated on the core second main surface and the chip second main surface. A second wiring laminated portion having a structure that can be supported by the mother board; Provided, the wiring board sectional area of the chip via conductor, and greater than the cross-sectional area of the through-hole conductors.

  (2) A flat core material having a core first main surface and a core second main surface, and having an accommodation hole opening at the core first main surface and the core second main surface, and the core material A through-hole conductor formed in a through-hole hole penetrating in the thickness direction, a chip first main surface and a chip second main surface, and an in-chip via conductor formed therein, An embedded ceramic chip housed and fixed in the first insulating layer, and a first interlayer insulating layer having a via conductor in the first insulating layer stacked on the core first main surface and the chip first main surface, A first wiring laminated portion capable of supporting a semiconductor integrated circuit element and a second interlayer insulating layer having a via conductor in the second insulating layer are formed on the core second main surface and the chip second main surface. Second wiring stack having a stacked structure and capable of being supported by a mother board A chip first main surface side electrode disposed on the chip first main surface, and a chip disposed on the chip second main surface corresponding to the position of the chip first main surface side electrode. A second main surface side electrode, and an in-chip via conductor group composed of a plurality of in-chip via conductors arranged in parallel between the chip first main surface side electrode and the chip second main surface side electrode, The wiring substrate, wherein the chip first main surface side electrode and the chip second main surface side electrode are connected to end portions of the in-chip via conductor group.

  (3) The wiring board according to 1 or 2, wherein the metal used for the in-chip via conductor is nickel and the metal used for the through-hole conductor is copper.

  (4) The wiring board according to any one of 1 to 3, wherein the first insulating layer via conductor and the second insulating layer via conductor are filled via conductors.

1 is a schematic sectional view showing a wiring board according to a first embodiment embodying the present invention. 1 is a schematic cross-sectional view showing a ceramic capacitor according to a first embodiment. 1 is a schematic top view showing a ceramic capacitor according to a first embodiment. Sectional drawing which shows a through-hole conductor and a via conductor. The schematic sectional drawing which shows the wiring board of 2nd Embodiment. The schematic top view which shows the ceramic capacitor of 2nd Embodiment. The schematic sectional drawing which shows the wiring board of 3rd Embodiment. The schematic sectional drawing which shows the wiring board of 4th Embodiment. Explanatory drawing which shows the layout of the via conductor group of another embodiment. Explanatory drawing which shows the layout of the via conductor group of another embodiment. Explanatory drawing which shows the layout of the via conductor group of another embodiment. Explanatory drawing which shows the layout of the via conductor group of another embodiment. The schematic sectional drawing which shows the conventional wiring board.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Wiring board 11 ... Core material 12 ... Upper surface as 1st core main surface 13 ... Lower surface as 2nd core 2nd main surface 15 ... Inside hole for through holes 16 ... Through-hole conductor 21 ... IC chip as a semiconductor element 31 ... Build-up layers 33, 35 as the first wiring laminate 33 ... First interlayer insulation layer 32 ... Build-up layers 34, 36 as the second interconnection laminate ... Second interlayer insulation layers 52, 56 ... Via conductors in the insulation layer 60 DESCRIPTION OF SYMBOLS ... Mother board as mother board 91 ... Accommodating hole 101 ... Ceramic capacitor as embedding ceramic chip 102 ... Upper surface as chip first main surface 103 ... Lower surface as chip second main surface 111, 112 ... Chip first main surface First external terminal electrodes 121 and 122 as side electrodes Second external terminal electrodes 131 and 132 as chip second main surface side electrodes Vias in the chip Via conductors as conductors 134, 135... Via conductor groups as via conductor groups in the chip

Claims (6)

A core material having a core first main surface and a core second main surface, and having an accommodation hole opening in at least one of the core first main surface and the core second main surface;
A through-hole conductor formed in a through-hole hole penetrating the core material in the thickness direction;
An embedded ceramic chip having a chip first main surface and a chip second main surface, in which a via conductor in the chip is formed, and is housed and fixed in the housing hole;
A first wiring laminated portion having a structure in which a first interlayer insulating layer having a via conductor in the first insulating layer is laminated on the core first main surface, and capable of supporting a semiconductor element;
A second wiring laminated portion having a structure in which a second interlayer insulating layer having a via conductor in the second insulating layer is laminated on the second main surface of the core and capable of being supported by a mother board. A wiring board, wherein a cross-sectional area of the via conductor in the chip is larger than a cross-sectional area of the through-hole conductor. A core material having a core first main surface and a core second main surface, and having an accommodation hole opening in at least one of the core first main surface and the core second main surface;
A through-hole conductor formed in a through-hole hole penetrating the core material in the thickness direction;
An embedded ceramic chip having a chip first main surface and a chip second main surface, in which a via conductor in the chip is formed, and is housed and fixed in the housing hole;
A first wiring laminated portion having a structure in which a first interlayer insulating layer having a via conductor in the first insulating layer is laminated on the core first main surface, and capable of supporting a semiconductor element;
A second wiring laminated portion having a structure in which a second interlayer insulating layer having a via conductor in the second insulating layer is laminated on the second main surface of the core and capable of being supported by a mother board. ,
A chip first main surface side electrode disposed on the chip first main surface, and a chip second main surface disposed on the chip second main surface corresponding to the position of the chip first main surface side electrode. A chip-side via conductor group including a plurality of via conductors in a chip arranged in parallel between the chip first main surface side electrode and the chip second main surface side electrode; A wiring board, wherein the chip first main surface side electrode and the chip second main surface side electrode are connected to an end portion of a conductor group.   The wiring board according to claim 2, wherein a cross-sectional area of the in-chip via conductor group is larger than a cross-sectional area of the through-hole conductor.   4. The wiring board according to claim 1, wherein a resistance value per unit length of the in-chip via conductor is smaller than a resistance value per unit length of the through-hole conductor. 5. .   5. The wiring board according to claim 1, wherein a maximum diameter of the in-chip via conductor is 120 μm or more and 200 μm or less. 6. The wiring board according to claim 1, wherein a specific resistance of the metal used for the via conductor in the chip is higher than a specific resistance of the metal used for the through-hole conductor.

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