JP4907274B2 - Wiring board, capacitor - Google Patents

Description

  The present invention has a structure in which a capacitor mainly composed of ceramic or the like is embedded in a substrate core, and further, a wiring laminated portion is formed on the surface thereof, and a wiring substrate on which a semiconductor integrated circuit element is mounted, and The present invention relates to a capacitor used for a wiring board.

  In recent years, semiconductor integrated circuit elements (IC chips) used in computer microprocessors and chip sets have become increasingly faster and more functional, with an accompanying increase in the number of terminals and a decrease in the pitch between terminals. There is a tendency. In general, a large number of terminals are densely arranged on the bottom surface of an IC chip, and such a terminal group is connected to a terminal group on the motherboard side in the form of a flip chip. However, it is difficult to connect the IC chip directly on the mother board because there is a large difference in the pitch between the terminals on the IC chip side terminal group and the mother board side terminal group. For this reason, a method is generally employed in which a package is prepared by mounting an IC chip on an IC chip mounting wiring board, and the package is mounted on a motherboard.

By the way, there is a demand for downsizing, multi-functionality, and cost reduction for this type of package. Therefore, as the IC chip mounting wiring board constituting the package, for example, a core part is configured by embedding a chip-like ceramic capacitor in a core substrate made of a polymer material, and build-up layers are formed on the front and back surfaces of the core part. In the past, there has been proposed (see, for example, Patent Document 1). The advantage of this configuration is that by incorporating a capacitor that has been surface-mounted on a conventional package, the degree of freedom of the core surface can be increased, and the space can be reduced and the space can be reduced. Alternatively, it is possible to increase the functionality by surface-mounting other electronic components such as resistors in a vacant space.
JP-A-2005-39243 JP 2002-43754 A

  However, when a package structure in which a resistor or the like is surface-mounted in a vacant space is adopted, a new component mounting space is required for the surface layer portion of the package. Therefore, even if multifunctionalization can be achieved, it has been difficult to achieve further downsizing. Further, in the manufacture of such a package, the process of mounting the resistor cannot be omitted, and this has been an obstacle to cost reduction.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a wiring board suitable for miniaturization and cost reduction, although it is easy to achieve multiple functions. Another object of the present invention is to provide a capacitor suitable for use in the above excellent wiring board.

And means for solving the above problems (means 1) include a substrate core having a core main surface and a core back surface, a capacitor main surface and a capacitor back surface, and a first internal electrode layer via a dielectric layer. A capacitor function unit having a structure in which second internal electrode layers are alternately stacked; and a capacitor housed in the substrate core with the core main surface and the capacitor main surface facing the same side; A wiring laminate portion having a structure in which an interlayer insulating layer and a conductor layer are alternately laminated on the core main surface and the capacitor main surface, and the capacitor function as viewed from the capacitor main surface direction in the capacitor. A circuit unit including a resistor and a capacitor that is electrically connected to the resistor is formed in a region outside the unit, and the first internal electrode layer and the second internal electrode layer are electrostatically There is a wiring board, characterized by being arranged in a state unaffected on.

  Therefore, according to the wiring board of the means 1, since the resistor is formed in the capacitor itself, for example, different potentials can be set in the same capacitor. Therefore, compared to the conventional structure in which the resistor is mounted on the surface portion of the wiring board, it is easy to achieve multi-function. Further, since it is not necessary to newly set a component mounting space for the resistor in the surface layer portion of the wiring board, it is difficult to be restricted by further miniaturization, and is suitable for the entire miniaturization. Furthermore, since the resistor mounting process can be omitted, it is suitable for cost reduction.

  Here, the wiring board of the means 1 is a device for mounting a semiconductor integrated circuit element which is a mounted object. An example of the “semiconductor integrated circuit element” is a semiconductor integrated circuit element that is used as a microprocessor of a computer or the like and has one or more processor cores. This semiconductor integrated circuit element is, for example, flip-chip mounted on the semiconductor integrated circuit element mounting region. Note that the number of processor cores may be two or three or more. Another example of the semiconductor integrated circuit element is one used as a controller for performing high-speed data processing. Specific examples of the function as the controller include a memory controller, a multiprocessing controller, a bus controller, a video controller, and the like, and an image processing chip and a chip set correspond to this. Here, as an example of the chip set, there is a chip set that plays a central role of a mother board, is composed of a north bridge and a south bridge, and has functions as various controllers. Further, the “semiconductor integrated circuit element mounting region” refers to a region where terminal pad groups are arranged on the surface of the wiring laminated portion.

  The board core constituting the wiring board forms part of the core portion of the wiring board, and is formed in a plate shape having a core main surface and a core back surface located on the opposite side, for example. Such a substrate core may have an accommodation hole for accommodating a capacitor. The accommodation hole may be a non-through hole that opens only on the core main surface, or may be a through hole that opens on both the core main surface and the core back surface. The capacitor may be completely embedded in the accommodation hole, or may be embedded with a part of the capacitor protruding.

  The material for forming the substrate core is not particularly limited, but a preferable substrate core is formed mainly of a polymer material. Specific examples of the polymer material for forming the substrate core include, for example, EP resin (epoxy resin), PI resin (polyimide resin), BT resin (bismaleimide / triazine resin), PPE resin (polyphenylene ether resin), etc. There is. In addition, composite materials of these resins and glass fibers (glass woven fabric or glass nonwoven fabric) or organic fibers such as polyamide fibers may be used.

  The capacitor constituting the wiring board has a capacitor main surface and a capacitor back surface, and has a structure in which first internal electrode layers and second internal electrode layers are alternately stacked via dielectric layers. . As a material for forming the dielectric layer, resin, ceramic, or the like can be selected, but it is particularly preferable to use a ceramic sintered body. That is, as a more preferable capacitor, a ceramic capacitor having a capacitor main surface and a capacitor back surface, and a structure in which first internal electrode layers and second internal electrode layers are alternately stacked via a ceramic dielectric layer Can be mentioned. The ceramic capacitor here includes a capacitor in which a thin film is formed of a ceramic material on a substrate (a substrate not limited to a ceramic).

  The capacitor is accommodated in the substrate core with the core main surface and the capacitor main surface facing the same side. That is, the capacitor is used in a state of being built in the substrate core. The capacitor is arranged in a region corresponding to the semiconductor integrated circuit element mounting region in the core substrate. The capacitor is fixed by a filler made of a polymer material, for example, while being accommodated in the substrate core.

  An example of a suitable capacitor is a via array type capacitor. That is, the capacitor includes a plurality of power supply via conductors that connect the first internal electrode layers, a plurality of ground via conductors that connect the second internal electrode layers, and ends of the plurality of power supply via conductors. A plurality of power supply electrode conductors and a plurality of ground via conductors are arranged in an array. It is preferable to arrange | position. More specifically, the plurality of power supply via conductors and the plurality of ground via conductors are preferably arranged in an array as a whole when viewed from the capacitor thickness direction. With this configuration, it is easy to reduce the size of the capacitor as a whole, and it is also easy to reduce the size of the entire wiring board. In addition, high capacitance can be easily achieved despite being small, and more stable power supply can be achieved.

  The capacitor has one capacitor function part or a plurality of capacitor function parts electrically independent from each other. The capacitor function part refers to a region including the first internal electrode layer and the second internal electrode layer. There may be two such capacitor function units, or three or more, but it is preferable that there are as many as the processor cores. With this configuration, all the capacitor function units can be electrically connected to all the processor cores, respectively.

  The distance between the adjacent capacitor function units is not particularly limited, but is preferably such that they do not interfere with each other electrostatically, and specifically 50 μm or more. In particular, it is preferable that a distance equal to or larger than the capacitor via pitch (ground-power supply pitch) is secured.

  When the dielectric layer constituting the capacitor is a ceramic dielectric layer, for example, a sintered body of high-temperature fired ceramic such as alumina, aluminum nitride, boron nitride, silicon carbide, silicon nitride, etc. is preferably used. A sintered body of low-temperature fired ceramic such as glass ceramic obtained by adding an inorganic ceramic filler such as alumina to acid glass or lead borosilicate glass is preferably used. In this case, it is also preferable to use a sintered body of a dielectric ceramic such as barium titanate, lead titanate, or strontium titanate depending on the application. When a dielectric ceramic sintered body is used, a ceramic capacitor having a large capacitance can be easily realized.

  A material for forming the first internal electrode layer and the second internal electrode layer is not particularly limited, but it is preferable to use a metal that can be sintered simultaneously with the ceramic, for example, nickel, molybdenum, tungsten, titanium, or the like. When a sintered body of low-temperature fired ceramic is selected, copper, silver, or the like can be further used as a material for forming the first internal electrode layer and the second internal electrode layer.

  The capacitor is formed with one or more resistors in order to achieve multiple functions. Such a resistor is not a resistor formed separately from the capacitor, but one formed integrally with the capacitor. The use of the resistor is not particularly limited, but one example is a use as a so-called termination resistor.

  For example, the resistor is formed on at least one of the capacitor main surface and the capacitor back surface of the capacitor. Since the resistor formed in such a position is exposed on the outer surface of the capacitor, it is advantageous in that the resistance value can be finely adjusted by performing trimming or the like after the formation. The resistor may be formed only on the capacitor main surface, may be formed only on the capacitor back surface, or may be formed on both the capacitor main surface and the capacitor back surface. The advantages of the configuration in which the resistor is formed on both are as follows. That is, when the resistor is electrically independent from the capacitor function part, according to this configuration, the resistor can be mounted twice as much as the conventional structure in which the resistor is surface-mounted on the wiring board surface layer part. In addition, the degree of freedom in circuit formation is increased.

  The resistor (surface-side resistance pattern) formed on the capacitor main surface can be formed of any conductive material, and in particular, the power supply electrode terminal and the ground electrode terminal on the capacitor main surface. It is preferable that they are made of the same material. The reason for this is that an increase in the number of man-hours can be prevented because the power electrode terminal and the ground electrode terminal can be formed at the same time.

Further, the resistor (back surface side resistance pattern) formed on the back surface of the capacitor can be formed of any material having conductivity, and in particular, the power electrode terminal and the ground electrode terminal on the back surface of the capacitor. It is preferable that they are made of the same material. The reason for this is that an increase in the number of man-hours can be prevented because the power electrode terminal and the ground electrode terminal can be formed at the same time.
Note that if a back side resistance pattern, which is a resistor, is formed only on the back side of the capacitor, not on the top side of the capacitor, the space on the front side of the capacitor can be effectively used for forming a conductor for supplying power. Further, the resistor in the wiring board is usually disposed on the core back surface side rather than the core main surface side (that is, the semiconductor integrated circuit element mounting side) of the core substrate. Therefore, it is not necessary to change the design rule as in the case where the surface side resistance pattern is adopted, and therefore the burden of circuit design is reduced. In the case of adopting such a structure, a through-hole conductor that penetrates the core substrate side is provided, a resistance pattern on the back surface side is connected thereto, and the semiconductor integrated circuit element is connected via the through-hole conductor and the conductor layer in the wiring laminated portion. What is necessary is just to make an electrical connection with the side.

  Alternatively, the resistor may be an inner layer resistance pattern formed inside the capacitor. The inner layer resistance pattern can be formed of any material having conductivity, but is preferably formed of the same material as the first internal electrode layer and the second internal electrode layer. The reason for this is that an increase in the number of steps can be prevented because the first internal electrode layer and the second internal electrode layer can be formed at the same time. In addition, since the first internal electrode layer and the second internal electrode layer are thinner than the power supply electrode terminal and the ground electrode terminal, there is an advantage that a small and high resistance resistor can be easily formed.

  In addition, the resistor may be a via resistor formed inside the capacitor. That is, the resistor is not limited to the one extending in the planar direction of the capacitor, and may be one extending in the thickness direction of the capacitor. When there is such a via resistance, for example, a plurality of resistors arranged via a dielectric layer can be connected to function as one resistor. The via resistance is preferably formed of the same material as the plurality of power supply via conductors and the plurality of ground via conductors. The reason is that the number of man-hours can be prevented from being increased because the plurality of power supply via conductors and the plurality of ground via conductors can be formed together.

  The shape of the front surface side resistance pattern, the back surface side resistance pattern, and the inner layer resistance pattern is not particularly limited, but it is advantageous to use a linear pattern in order to achieve a desired resistance value in a limited narrow space. It is. That is, with such a shape, the resistance value per unit length can be increased, so that a pattern with a relatively small area is sufficient and a large space is not required. In other words, the use of a linear pattern is preferable in order to realize downsizing of the capacitor, and hence downsizing of the entire wiring board. The linear pattern may be linear or curved, but for example, it is more preferable that the linear pattern meanders. The line width of the linear pattern is preferably made as narrow as possible and smaller than the diameters of the power supply via conductor and the ground via conductor. Therefore, for example, if the diameters of the power supply via conductor and the ground via conductor are about 100 μm to 200 μm, the line width of the linear pattern is set to about 10 μm to 100 μm.

  The resistor can be arranged at an arbitrary position in the capacitor, but is preferably arranged in a region outside the capacitor function part configured to include the first internal electrode layer and the second internal electrode layer. The reason is that such a position makes it easier to secure a space for forming a resistor. In addition, the risk of having an electrical influence on the capacitor is small as compared with the case where the resistor is disposed in the region inside the capacitor function unit.

  The capacitor may be formed with a passive element other than a resistor, for example, one or two or more capacitors in order to increase the functionality. Such a capacitor is not a capacitor formed separately from the capacitor, but a capacitor formed integrally with the capacitor. Such a capacitor is preferably arranged in a state where it is not electrostatically affected by the first internal electrode layer and the second internal electrode layer constituting the capacitor function unit.

  For example, the capacitor may be formed on at least one of the capacitor main surface and the capacitor back surface. Since the capacitor formed at such a position is exposed on the outer surface of the capacitor, it is advantageous in that the capacitance value can be finely adjusted by performing trimming after the formation.

  Alternatively, the capacitor may be formed inside the capacitor. Such a capacitor can be formed of any material having conductivity, but is preferably formed of the same material as the first internal electrode layer and the second internal electrode layer. The reason for this is that an increase in the number of steps can be prevented because the first internal electrode layer and the second internal electrode layer can be formed at the same time.

  The circuit unit may be configured by electrically connecting the capacitor to a resistor. That is, by combining the capacitor and the resistor, a predetermined function can be given and multifunctionalization can be achieved. An example of a suitable circuit unit is a filter circuit, for example. More specifically, a band-pass filter circuit that allows passage of only a predetermined frequency band, such as a high-pass filter circuit, a low-pass filter circuit, and a middle-pass filter circuit, can be given.

  The wiring laminated portion constituting the wiring board has a structure in which interlayer insulating layers mainly composed of a polymer material and conductor layers are alternately laminated. The wiring laminated portion includes a plurality of power supply conductor portions that are electrically independent from each other, and the plurality of capacitor function portions are electrically connected to the plurality of processor cores via the plurality of power supply conductor portions, respectively. It is preferable that they are connected. Although there is a large difference in the pitch between terminals between the terminal group on the semiconductor integrated circuit element side and the terminal group on the capacitor side, the processor core and the capacitor function can be provided via a plurality of power supply conductors by providing a wiring laminated portion. Can be connected individually and easily. In addition, the wiring laminated portion (first wiring laminated portion) is formed only on the core main surface and the capacitor main surface, but the interlayer insulating layer and the conductor layer are alternately laminated on the core back surface and the capacitor back surface. A second wiring laminated portion having the above structure may be further formed. With such a configuration, since an electric circuit can be formed not only in the first wiring laminated portion but also in the second wiring laminated portion, further multi-functionalization of the wiring board can be achieved.

  In addition, as for the wiring laminated portion (first wiring laminated portion) formed on the core main surface and the capacitor main surface, a semiconductor on which a semiconductor integrated circuit element having one or a plurality of processor cores can be mounted. An integrated circuit element mounting area may be set. A semiconductor integrated circuit element can be mounted in such a semiconductor integrated circuit element mounting region. The area of the semiconductor integrated circuit element mounting region is set to be equal to or smaller than the area of the capacitor main surface of the capacitor, and the semiconductor integrated circuit element mounting region has a thickness direction of the capacitor. It is preferable that the capacitor is located within the capacitor main surface of the capacitor. According to this configuration, the semiconductor integrated circuit element mounting region is located in the region immediately above the capacitor, so that the semiconductor integrated circuit element mounted in the semiconductor integrated circuit element mounting region is supported by the capacitor. In this case, it is preferable to use a ceramic capacitor having high rigidity and a small coefficient of thermal expansion. Therefore, in the semiconductor integrated circuit element mounting region, the wiring laminated portion is hardly deformed, so that the semiconductor integrated circuit element mounted in the semiconductor integrated circuit element mounting region can be supported more stably. The area of the semiconductor integrated circuit element mounting region may be set to be larger than the area of the capacitor main surface of the capacitor. However, in order to stably support the semiconductor integrated circuit element, the area of the capacitor main surface is preferably set to 50% or more of the semiconductor integrated circuit element mounting region.

In addition, as another means (means 2) for solving the problem of the present invention, the first internal electrode layer and the second internal electrode layer have a capacitor main surface and a capacitor back surface, and a dielectric layer is interposed therebetween. A capacitor function part having a structure in which the layers are alternately stacked , and a resistor and a capacitor electrically connected to the resistor in a region outside the capacitor function part when viewed from the capacitor main surface direction. There is a capacitor characterized in that a circuit portion to be configured is arranged in a state where it is not electrostatically affected by the first internal electrode layer and the second internal electrode layer .

  Therefore, since the resistor is formed in the capacitor of the means 2, it is possible to set different potentials in the same capacitor, for example. Therefore, compared to the conventional structure in which the resistor is mounted on the surface portion of the wiring board, it is easy to achieve multi-function. Further, since it is not necessary to newly set a component mounting space for the resistor in the surface layer portion of the wiring board, it is difficult to be restricted by further miniaturization, and is suitable for the entire miniaturization. Furthermore, since the resistor mounting process can be omitted, it is suitable for cost reduction.

  The capacitor includes a plurality of power via conductors for conducting the first internal electrode layers, a plurality of ground via conductors for conducting the second internal electrode layers, and ends of the plurality of power via conductors. And the ground electrode terminals located at the ends of the plurality of ground via conductors, and the plurality of power via conductors and the plurality of ground via conductors are arranged in an array. It is preferable that they are arranged.

  The resistor may be formed on at least one of the capacitor main surface and the capacitor back surface. The resistor on the capacitor main surface is preferably a surface-side resistance pattern formed of the same material as the power supply electrode terminal and the ground electrode terminal. It is preferable that the resistor on the back surface of the capacitor is a back surface side resistance pattern formed of the same material as the power supply electrode terminal and the ground electrode terminal. The resistor inside the capacitor is preferably an inner layer resistor pattern formed of the same material as the first internal electrode layer and the second internal electrode layer inside the capacitor. The resistor may be a via resistor formed of the same material as the plurality of power supply via conductors and the plurality of ground via conductors inside the capacitor.

  From the viewpoint of reducing the area of the pattern, the front-side resistance pattern, the back-side resistance pattern, or the inner-layer resistance pattern may be a linear pattern, particularly a meandering linear pattern. In addition, from the viewpoint of ease of securing a resistor forming space, the resistor is disposed in a region outside the capacitor function unit including the first internal electrode layer and the second internal electrode layer. It is good to have.

  The capacitor may be formed with a capacitor that is electrically connected to the resistor. In addition, a circuit unit such as a filter circuit may be configured by the capacitor and the resistor. Further, an inductor such as a coil may be formed in addition to the capacitor and the resistor. It is also possible to configure a circuit unit such as a transmission circuit by connecting capacitors and resistors other than resistors and inductors to each other.

[First Embodiment]

  Hereinafter, a first embodiment in which a wiring board of the present invention is embodied will be described in detail with reference to the drawings.

  As shown in FIG. 1, a wiring board 10 of this embodiment is a wiring board for mounting an IC chip, and is a substantially rectangular plate-like board core 11 made of glass epoxy, and an upper surface 12 (core The first buildup layer 31 (wiring laminated portion) formed on the main surface) and the second buildup layer 32 formed on the lower surface 13 (core back surface) of the substrate core 11. Through-hole conductors 16 are formed at a plurality of locations in the substrate core 11. The through-hole conductor 16 connects and connects the upper surface 12 side and the lower surface 13 side of the substrate core 11. The inside of the through-hole conductor 16 is filled with a closing body 17 such as an epoxy resin. In addition, a conductor layer 41 made of copper is patterned on the upper surface 12 and the lower surface 13 of the substrate core 11, and each conductor layer 41 is electrically connected to the through-hole conductor 16.

  The first buildup layer 31 formed on the upper surface 12 of the substrate core 11 includes two resin insulation layers 33 and 35 (so-called interlayer insulation layers) made of epoxy resin and conductor layers 42 made of copper alternately. It has a laminated structure. In the present embodiment, the thermal expansion coefficient of the first buildup layer 31 is about 30 to 40 ppm / ° C., specifically about 35 ppm / ° C. In addition, the thermal expansion coefficient of the 1st buildup layer 31 says the average value of the measured value between 30 degreeC-glass transition temperature (Tg). A part of the conductor layer 42 on the surface of the first resin insulating layer 33 is electrically connected to the upper end of the through-hole conductor 16. Terminal pads 44 are formed in an array at a plurality of locations on the surface of the second resin insulating layer 35. The surface of the resin insulating layer 35 is almost entirely covered with a solder resist 37. An opening 46 for exposing the terminal pad 44 is formed at a predetermined position of the solder resist 37. A plurality of solder bumps 45 are provided on the surface of the terminal pad 44. Each solder bump 45 is electrically connected to the surface connection terminal 22 of the IC chip 21 (semiconductor integrated circuit element). The IC chip 21 has a rectangular flat plate shape and has two processor cores 24 and 25. The IC chip 21 of this embodiment is made of silicon having a thermal expansion coefficient of about 3.5 ppm / ° C. Each terminal pad 44 and each solder bump 45 are located in a region immediately above the ceramic capacitor 101 in the first buildup layer 31, and this region is an IC chip mounting region 23 (semiconductor integrated circuit element mounting region). ) The IC chip mounting area 23 is set on the surface 39 of the first buildup layer 31. Further, via conductors 43 and 47 are provided in the resin insulation layers 33 and 35, respectively. Most of these via conductors 43 and 47 are arranged coaxially, and the conductor layers 41 and 42 and the terminal pads 44 are electrically connected to each other through them.

  As shown in FIG. 1, the second buildup layer 32 formed on the lower surface 13 of the substrate core 11 has substantially the same structure as the first buildup layer 31 described above. That is, the second buildup layer 32 has a thermal expansion coefficient of about 30 to 40 ppm / ° C., and the two resin insulation layers 34 and 36 (so-called interlayer insulation layers) made of epoxy resin and the conductor layers 42 are alternately arranged. It has a laminated structure. A part of the conductor layer 42 on the lower surface of the first resin insulating layer 34 is electrically connected to the lower end of the through-hole conductor 16. BGA pads 48 that are electrically connected to the conductor layer 42 via via conductors 43 are formed in a lattice pattern at a plurality of locations on the lower surface of the second resin insulating layer 36. The lower surface of the resin insulating layer 36 is almost entirely covered with a solder resist 38. An opening 40 for exposing the BGA pad 48 is formed at a predetermined portion of the solder resist 38. On the surface of the BGA pad 48, a plurality of solder bumps 49 are provided for electrical connection with a mother board (not shown). The wiring board 10 shown in FIG. 1 is mounted on a mother board (not shown) by each solder bump 49.

  The substrate core 11 has a thermal expansion coefficient in the plane direction (XY direction) of about 10 to 15 ppm / ° C. In addition, the thermal expansion coefficient of the substrate core 11 means an average value of measured values between 0 ° C. and the glass transition temperature (Tg). The substrate core 11 has one rectangular accommodation hole 90 in a plan view that opens at the center of the upper surface 12 and the center of the lower surface 13. That is, the accommodation hole 90 is a through hole. The ceramic capacitor 101 shown in FIGS. 2 to 5 and the like is housed in the housing hole 90 in an embedded state. The ceramic capacitor 101 is accommodated with the upper surface 102 (capacitor main surface) facing the same side as the upper surface 12 of the substrate core 11. The ceramic capacitor 101 of this embodiment has a rectangular flat plate shape of 6.0 mm long × 12.0 mm wide × 0.8 mm thick. In addition, it is preferable that the thickness of the ceramic capacitor 101 is 0.2 mm or more and 1.0 mm or less. If the thickness is less than 0.2 mm, the stress at the time of bonding the IC chip 21 onto the IC chip mounting region 23 cannot be reduced by the ceramic capacitor 101, which is insufficient as a support. On the other hand, if it is larger than 1.0 mm, the wiring board 10 becomes thick. More preferably, the thickness of the ceramic capacitor 101 is 0.4 mm or more and 0.8 mm or less. The ceramic capacitor 101 is arranged in a region immediately below the IC chip mounting region 23 in the substrate core 11. The area of the IC chip mounting region 23 (the area of the region where the terminal pads 44 are formed in the first buildup layer 31) is set to be smaller than the area of the upper surface 102 of the ceramic capacitor 101. When viewed from the thickness direction of the ceramic capacitor 101, the IC chip mounting region 23 is located in the upper surface 102 of the ceramic capacitor 101.

  As shown in FIG. 1, the gap between the inner surface of the accommodation hole 90 and the side surface 106 of the ceramic capacitor 101 is filled with a filler 92 made of a polymer material (in this embodiment, a thermosetting resin such as epoxy). ing. The filler 92 has a function of fixing the ceramic capacitor 101 to the substrate core 11 and absorbing the deformation of the ceramic capacitor 101 and the substrate core 11 in the surface direction and the thickness direction by its own elastic deformation. The ceramic capacitor 101 has a substantially square shape in plan view, and has a taper of C0.6 at the four corners. Thereby, when the filler 92 is deformed due to a temperature change, the stress concentration on the corners of the ceramic capacitor 101 can be alleviated, and the occurrence of cracks in the filler 92 can be prevented.

  As shown in FIGS. 1 to 5, the ceramic capacitor 101 of this embodiment is a so-called via array type ceramic capacitor. The ceramic sintered body 104 constituting the ceramic capacitor 101 preferably has a thermal expansion coefficient that is an intermediate value between the thermal expansion coefficient of the IC chip 21 and the thermal expansion coefficients of the build-up layers 31 and 32. It is preferable that the value is close to the thermal expansion coefficient. In this embodiment, the thermal expansion coefficient of the ceramic sintered body 104 is about 8 to 12 ppm / ° C., specifically about 9.5 ppm / ° C. The thermal expansion coefficient of the ceramic sintered body 104 refers to an average value of measured values between 30 ° C. and 250 ° C. The ceramic sintered body 104 is a plate-like object having an upper surface 102 and a lower surface 103 (capacitor back surface). The resin insulating layer 33 constituting the first buildup layer 31 is formed on the upper surface 102 of the ceramic sintered body 104, and the second buildup layer is formed on the lower surface 103 of the ceramic sintered body 104. The resin insulating layer 34 constituting 32 is formed. The ceramic sintered body 104 has a structure in which the first internal electrode layers 141 and the second internal electrode layers 142 are alternately stacked via the ceramic dielectric layer 105. The ceramic dielectric layer 105 is made of a sintered body of barium titanate, which is a kind of high dielectric constant ceramic, and functions as a dielectric (insulator) between the first internal electrode layer 141 and the second internal electrode layer 142. Each of the first internal electrode layer 141 and the second internal electrode layer 142 is a layer formed mainly of nickel, and is disposed every other layer inside the ceramic sintered body 104.

  As shown in FIGS. 2 to 5, the ceramic capacitor 101 has two capacitor function units 107 and 108. A common ceramic dielectric layer 105 is used for both capacitor function units 107 and 108. Further, when viewed from the thickness direction of the ceramic capacitor 101, the processor core 24 of the IC chip 21 is located in the upper surface of the capacitor function unit 107, and the IC chip 21 in the upper surface of the capacitor function unit 108. The processor core 25 is located.

  A large number of via holes 130 are formed in the capacitor function unit 107. These via holes 130 penetrate the capacitor function part 107 in the thickness direction, and are arranged in a grid pattern (array form) over the entire surface of the capacitor function part 107. In each via hole 130, a plurality of via conductors 131 and 132 that communicate between the upper surface 102 and the lower surface 103 of the ceramic sintered body 104 in the capacitor function unit 107 are formed using nickel as a main material. Each first power supply via conductor 131 passes through each first internal electrode layer 141 and electrically connects them to each other. Each first ground via conductor 132 passes through each second internal electrode layer 142 and electrically connects them to each other. Here, as shown in FIG. 3, a clearance hole 141a is formed in the first internal electrode layer 141 in a region through which the first ground via conductor 132 penetrates, and the first internal electrode layer 141 and the first ground electrode are formed. The via conductor 132 is electrically insulated. Similarly, as shown in FIG. 4, a clearance hole 142a is formed in the second internal electrode layer 142 in a region through which the first power supply via conductor 131 passes, and the second internal electrode layer 142 and the first power supply The electrical via conductor 131 is electrically insulated.

  The first power supply via conductors 131 and the first ground via conductors 132 are arranged in an array as a whole. For convenience of explanation, the via conductors 131 and 132 are illustrated in 3 rows × 3 rows (or 5 rows × 5 rows), but there are actually more rows.

  2 to 5, a plurality of first power electrode terminals 111 and a plurality of first ground electrode terminals 112 project on the upper surface 102 of the ceramic sintered body 104 in the capacitor function unit 107. It is installed. A plurality of first power supply electrode terminals 121 and a plurality of first ground electrode terminals 122 project from the lower surface 103 of the ceramic sintered body 104 in the capacitor function unit 107. The electrode terminals 111 and 112 on the upper surface 102 side are electrically connected to the via conductor 47. On the other hand, the electrode terminals 121 and 122 on the lower surface 103 side are connected to electrodes (contactors) of a mother board (not shown) through via conductors 47, conductor layers 42, via conductors 43, BGA pads 48 and solder bumps 49. Are electrically connected. Further, the substantially center portions of the bottom surfaces of the electrode terminals 111 and 112 are directly connected to the end surfaces of the via conductors 131 and 132 on the upper surface 102 side, and the substantially center portions of the bottom surfaces of the electrode terminals 121 and 122 are connected to the via conductors 131 and 132, respectively. It is directly connected to the end surface on the lower surface 103 side in 132. Therefore, the power supply electrode terminals 111 and 121 are electrically connected to the first power supply via conductor 131 and the first internal electrode layer 141, and the ground electrode terminals 112 and 122 are connected to the first ground via conductor 132 and the second internal electrode. Conductive to layer 142.

  Similarly, a large number of via holes 130 are also formed in the capacitor function unit 108 shown in FIGS. In each via hole 130, a plurality of via conductors 133 and 134 that communicate between the upper surface 102 and the lower surface 103 of the ceramic sintered body 104 in the capacitor function unit 108 are formed using nickel as a main material. Each of the second power supply via conductors 133 passes through each of the first internal electrode layers 141 and electrically connects them to each other. Each second ground via conductor 134 passes through each second internal electrode layer 142 and electrically connects them to each other. Each second power supply via conductor 133 and each second ground via conductor 134 are arranged in an array as a whole. For convenience of explanation, the via conductors 133 and 134 are illustrated as 3 rows × 3 rows (or 5 rows × 5 rows), but there are actually more rows.

  A plurality of second power electrode terminals 113 and a plurality of second ground electrode terminals 114 project from the upper surface 102 of the ceramic sintered body 104 in the capacitor function unit 108. A plurality of second power electrode terminals 123 and a plurality of second ground electrode terminals 124 project from the lower surface 103 of the ceramic sintered body 104 in the capacitor function unit 108. The electrode terminals 113 and 114 on the upper surface 102 side are electrically connected to the via conductor 47. On the other hand, the electrode terminals 123 and 124 on the lower surface 103 side are connected to electrodes (contactors) of a mother board (not shown) via via conductors 47, conductor layers 42, via conductors 43, BGA pads 48 and solder bumps 49. Are electrically connected. Further, the substantially center portion of the bottom surface of the electrode terminals 113 and 114 is directly connected to the end surface on the upper surface 102 side of the via conductors 133 and 134, and the substantially center portion of the bottom surface of the electrode terminals 123 and 124 is connected to the via conductor 133, 134. It is directly connected to the end surface on the lower surface 103 side in 134. Therefore, the power supply electrode terminals 113 and 123 are electrically connected to the second power supply via conductor 133 and the first internal electrode layer 141, and the ground electrode terminals 114 and 124 are connected to the second ground via conductor 134 and the second internal electrode. Conductive to layer 142.

  As shown in FIG. 2, the electrode terminals 111, 112, 113, 114 are formed using nickel as a main material, and the surface is entirely covered with a copper plating layer (not shown). Similarly, the electrode terminals 121, 122, 123, and 124 are also made of nickel as a main material, and the surface is covered with a copper plating layer (not shown). In the present embodiment, the diameters of the electrode terminals 111 to 114 and 121 to 124 are set to about 500 μm, and the minimum pitch length is set to about 580 μm.

  When energization is performed from the motherboard side via the electrode terminals 121 and 122 (or the electrode terminals 123 and 124) and a voltage is applied between the first internal electrode layer 141 and the second internal electrode layer 142, the first internal electrode layer 141 is applied. For example, positive charges are accumulated, and for example, negative charges are accumulated in the second internal electrode layer 142. As a result, the ceramic capacitor 101 functions as a capacitor. In the capacitor function unit 107, the first power supply via conductors 131 and the first ground via conductors 132 are alternately arranged adjacent to each other, and the first power supply via conductors 131 and the first ground via conductors 132 are arranged. The directions of the currents flowing through are set to be opposite to each other. Similarly, in the capacitor function unit 108, the second power supply via conductors 133 and the second ground via conductors 134 are alternately disposed adjacent to each other, and the second power supply via conductor 133 and the second ground via conductor are arranged. The directions of currents flowing through 134 are set to be opposite to each other. Thereby, the inductance component is reduced.

  As shown in FIG. 1, a part of each first power supply via conductor 131 includes a first power supply electrode terminal 111 and a first power supply conductor portion 171 (power supply conductor portion included in the first buildup layer 31. And the surface connection terminal 22 of the IC chip 21 are electrically connected to the processor core 24 of the IC chip 21. Part of each first ground via conductor 132 is connected to the processor core via the first ground electrode terminal 112, the first ground conductor portion 172 included in the first buildup layer 31, and the surface connection terminal 22. 24 is electrically connected. As a result, power can be supplied from the capacitor function unit 107 to the processor core 24. The first power supply conductor portion 171 and the first ground conductor portion 172 are conductor portions including the via conductor 47, the conductor layer 42, the via conductor 43, the terminal pad 44, and the solder bump 45.

  Similarly, a part of each second power supply via conductor 133 includes a second power supply electrode terminal 113, a second power supply conductor portion 173 (power supply conductor portion) included in the first buildup layer 31, and an IC chip. It is electrically connected to the processor core 25 of the IC chip 21 via the surface connection terminal 22 of the 21. A part of each second ground via conductor 134 is connected to the processor core via the second ground electrode terminal 114, the second ground conductor portion 174 included in the first buildup layer 31, and the surface connection terminal 22. 25 is electrically connected. As a result, power can be supplied from the capacitor function unit 108 to the processor core 25. The second power conductor portion 173 and the second ground conductor portion 174 are conductor portions including the via conductor 47, the conductor layer 42, the via conductor 43, the terminal pad 44, and the solder bump 45. The second power supply conductor 173 is electrically independent of the first power supply conductor 171, and the second ground conductor 174 is electrically independent of the first ground conductor 172.

  Therefore, in the wiring board 10 of this embodiment, an independent power supply system is set for each of the processor cores 24 and 25. Therefore, the capacitor function units 107 and 108 are electrically independent from each other. Therefore, the electrical path in the ceramic capacitor 101 is divided into a first electrical path that connects the capacitor function unit 107 and the processor core 24 and a second electrical path that connects the capacitor function unit 108 and the processor core 25. The insulating portions (ceramic dielectric layer 105) of the capacitor function portions 107 and 108 are physically integrated with each other, but the conductor portions of the capacitor function portions 107 and 108 are separated from each other. Are physically independent.

  Further, as shown in FIGS. 1, 5, etc., the ceramic capacitor 101 constituting the wiring substrate 10 of the present embodiment includes a surface-side resistance pattern 301 as a resistor. Here, the surface-side resistance pattern 301 is disposed on the upper surface 102 (capacitor main surface) of the ceramic capacitor 101 in a region outside the capacitor function units 107 and 108. The surface-side resistance pattern 301 is a linear pattern, and the line width is set to be smaller than the diameter (about 150 μm) of each via conductor 131 to 134 (specifically, 50 μm to 60 μm). ing. In the present embodiment, one end of the surface-side resistance pattern 301 is connected to the end of the second power supply via conductor 133, but may be connected to another via conductor 131, 132, 134 depending on the application, or The via conductors 131 to 134 may not be connected at all. The surface-side resistance pattern 301 is formed using nickel as a main material, and the surface is covered with a copper plating layer (not shown). That is, the surface-side resistance pattern 301 of this embodiment is formed of the same material as the electrode terminals 111 to 114 on the upper surface 102 (capacitor main surface).

  Note that, as in the modification shown in FIG. 6, the surface-side resistance pattern 302 that is a resistor may be formed of a curved linear pattern.

  Next, a method for manufacturing the wiring board 10 of this embodiment will be described.

  In the preparation step, the substrate core 11 and the ceramic capacitor 101 are respectively prepared by a conventionally known technique and prepared in advance.

  The substrate core 11 is manufactured as follows. First, a copper clad laminate is prepared in which a copper foil having a thickness of 35 μm is attached to both surfaces of a base material having a length of 400 mm × width of 400 mm × thickness of 0.8 mm. In addition, it is preferable that the thickness of a base material is 0.2 mm or more and 1.0 mm or less. Next, the copper-clad laminate is drilled using a router, and a through hole that becomes the accommodation hole 90 is formed in advance at a predetermined position (see FIG. 7). In addition, the through-hole used as the accommodation hole part 90 is a hole of 14.0 mm in length x 30.0 mm in width | variety, and a cross-sectional substantially rectangular shape which has a radius of 1.5 mm in four corners. And the copper foil of both surfaces of a copper clad laminated board is etched, and the conductor layer 41 is patterned by the subtractive method, for example. Specifically, after the electroless copper plating, electrolytic copper plating is performed using the electroless copper plating layer as a common electrode. Further, the dry film is laminated, and the dry film is exposed and developed to form a dry film in a predetermined pattern. In this state, unnecessary electrolytic copper plating layer, electroless copper plating layer and copper foil are removed by etching. Thereafter, the substrate core 11 is obtained by peeling the dry film.

  The ceramic capacitor 101 is manufactured as follows. That is, a ceramic green sheet is formed, and nickel paste for internal electrode layers is screen printed on the green sheet and dried. As a result, a first internal electrode portion that later becomes the first internal electrode layer 141 and a second internal electrode portion that becomes the second internal electrode layer 142 are formed. Next, the green sheets on which the first internal electrode portions are formed and the green sheets on which the second internal electrode portions are formed are alternately stacked, and each green sheet is integrated by applying a pressing force in the sheet stacking direction. To form a green sheet laminate.

  Further, a number of via holes 130 are formed through the green sheet laminate using a laser processing machine, and a via conductor nickel paste is filled into each via hole 130 using a paste press-fitting and filling device (not shown). Next, an electrode terminal forming paste is printed on the upper surface of the green sheet laminate, and the first power supply electrode terminal 111 and the first ground are formed so as to cover the upper end surface of each conductor portion on the upper surface side of the green sheet laminate. An electrode terminal 112, a second power electrode terminal 113, and a second ground electrode terminal 114 are formed. In addition, the paste is printed on the lower surface of the green sheet laminate, and the first power electrode terminal 121, the first ground electrode terminal 122, and the lower surface of each conductor portion are covered on the lower surface side of the green sheet laminate. A second power electrode terminal 123 and a second ground electrode terminal 124 are formed. In this step, the electrode surface forming paste is printed at a predetermined position to form the linear surface-side resistance pattern 301 together.

  Thereafter, the green sheet laminate is dried to solidify the surface terminal part to some extent. Next, the green sheet laminate is degreased and fired at a predetermined temperature for a predetermined time. As a result, barium titanate and nickel in the paste are simultaneously sintered to form a ceramic sintered body 104.

  Next, electroless copper plating (thickness of about 10 μm) is performed on each of the electrode terminals 111 to 114 and 121 to 124 and the surface side resistance pattern 301 included in the obtained ceramic sintered body 104. As a result, a copper plating layer is formed on each of the electrode terminals 111 to 114, 121 to 124, and the ceramic capacitor 101 is completed. Note that the resistance value may be finely adjusted by trimming the surface-side resistance pattern 301 as necessary. As a specific method, for example, the resistance value can be increased by gradually removing the surface-side resistance pattern 301 by laser processing.

  In the subsequent fixing step, the ceramic capacitor 101 is accommodated in the accommodation hole 90 using a mounting device (manufactured by Yamaha Motor Co., Ltd.) (see FIG. 8). At this time, the opening on the lower surface 13 side of the accommodation hole 90 is sealed with a peelable adhesive tape 152. The adhesive tape 152 is supported by a support base 151. Each ceramic capacitor 101 is affixed and temporarily fixed to the adhesive surface 153 of the adhesive tape 152.

  In this state, a filler 92 (manufactured by NAMICS Co., Ltd.) made of a thermosetting resin is used in the gap between the inner surface of the accommodation hole 90 and the side surface 106 of the ceramic capacitor 101 using a dispenser device (manufactured by Asymtek). Fill material). Thereafter, when heat treatment is performed, the filler 92 is cured and the ceramic capacitor 101 is fixed in the accommodation hole 90. At this time, the adhesive tape 152 is peeled off (see FIG. 9).

  Thereafter, a buildup layer forming step is performed. In the buildup layer forming step, the first buildup layer 31 is formed on the upper surface 12 and the upper surface 102 and the second buildup layer 32 is formed on the lower surface 13 and the lower surface 103 based on a conventionally known method. . Specifically, a photosensitive epoxy resin is applied to the upper surface 12 and the upper surface 102, and a photosensitive epoxy resin is applied to the lower surface 13 and the lower surface 103, and exposure and development are performed, whereby the via conductor 47 is formed. First resin insulation layers 33 and 34 having blind holes are formed at positions to be formed. Further, laser drilling is performed using a YAG laser or a carbon dioxide gas laser, and through holes penetrating the substrate core 11 and the resin insulating layers 33 and 34 are formed in advance at predetermined positions. And after forming the through-hole conductor 16 by performing electroless copper plating and electrolytic copper plating according to a conventionally well-known method, the closure body 17 is filled and formed in the through-hole conductor 16. Next, electrolytic copper plating is performed according to a conventionally known method (for example, a semi-additive method) to form a via conductor 47 inside the blind hole, and a second layer is formed on the first resin insulation layers 33 and 34. The conductor layer 42 is formed.

  Next, a photosensitive epoxy resin is deposited on the first resin insulation layers 33 and 34, and exposure and development are performed, whereby a second layer having a blind hole at a position where the via conductor 43 is to be formed. Resin insulation layers 35 and 36 are formed. Next, electrolytic copper plating is performed in accordance with a conventionally known method to form a via conductor 43 in the blind hole, and a terminal pad 44 is formed on the second resin insulating layer 35, and a second layer resin is formed. A BGA pad 48 is formed on the insulating layer 36.

  Next, solder resists 37 and 38 are formed by applying and curing a photosensitive epoxy resin on the second resin insulation layers 35 and 36. Next, exposure and development are performed with a predetermined mask placed, and the openings 40 and 46 are patterned in the solder resists 37 and 38. Further, solder bumps 45 are formed on the terminal pads 44 and solder bumps 49 are formed on the BGA pads 48. As a result, the wiring substrate 10 including the substrate core 11 and the buildup layers 31 and 32 is completed.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) In this embodiment, since the surface side resistance pattern 301 which is a resistor is formed in the ceramic capacitor 101 itself, for example, different potentials can be set in the same capacitor 101. Therefore, compared to the conventional structure in which the resistor is mounted on the surface layer portion of the wiring board, it is easy to achieve multi-functionality and high functionality. Further, since it is not necessary to newly set a component mounting space for the resistor in the surface layer portion of the wiring board, the wiring board 10 is less susceptible to restrictions on further downsizing and is structurally suitable for overall downsizing. be able to. Furthermore, since the resistor mounting step can be omitted, an increase in the number of man-hours can be avoided, and the wiring board 10 suitable for cost reduction and short delivery time can be obtained. In addition, according to the present embodiment, since the resistor is integrally formed with the ceramic capacitor 101 itself, the reliability is surely improved as compared with the conventional structure in which the resistor is joined by soldering or the like. Can do.

  (2) According to the wiring board 10 of this embodiment, the power supply system of the two processor cores 24 and 25 cannot be shared, and even when a different power supply system should be set for each of the processor cores 24 and 25. Since the two capacitor function units 107 and 108 can be electrically connected to the two processor cores 24 and 25, respectively, the individual processor cores 24 and 25 can be sufficiently operated. Therefore, when the multi-core microprocessor structure as in this embodiment is adopted, the merit can be maximized.

  (3) In this embodiment, since the IC chip mounting area 23 of the IC chip 21 is located in the area directly above the ceramic capacitor 101, the IC chip 21 mounted in the IC chip mounting area 23 is highly rigid. It is supported by the ceramic capacitor 101 having a small coefficient of thermal expansion. Therefore, in the IC chip mounting area 23, the first buildup layer 31 is not easily deformed, so that the IC chip 21 mounted in the IC chip mounting area 23 can be supported more stably. Therefore, it is possible to prevent the IC chip 21 from cracking and poor connection due to large thermal stress. Therefore, as the IC chip 21, a large IC chip of 10 mm square or more, which is greatly affected by thermal stress and has a large calorific value and severe thermal shock during use, or a low-k (low dielectric constant) IC which is considered to be brittle. A chip can be used.

  Furthermore, since the ceramic capacitor 101 of the present embodiment has two capacitor function units 107 and 108, good power supply is performed to the processor cores 24 and 25 by removing noise in each of the capacitor function units 107 and 108. be able to. In addition, the processor cores 24 and 25 are arranged directly above the capacitor function units 107 and 108, respectively. As a result, the conduction path (capacitor connection wiring) that electrically connects the processor cores 24 and 25 and the capacitor function units 107 and 108 is minimized. Therefore, it is possible to smoothly supply power to the processor cores 24 and 25. In addition, since noise entering between the IC chip 21 and the ceramic capacitor 101 can be suppressed to a very low level, high reliability can be obtained without causing malfunction such as malfunction.

  (4) In the paragraph [0063] of JP-A-2002-43754, a technique for embedding a plurality of chip capacitors in a substrate core is disclosed. However, in order to embed a plurality of chip capacitors, it is necessary to provide the same number of receiving holes 90 as the chip capacitors in the substrate core 11, so that it is difficult to manufacture the substrate core 11 and thus the wiring substrate 10. In addition, even if there are a plurality of chip capacitors, it is difficult to achieve high functionality by stabilizing the power source or the like. Furthermore, since the area of the upper surface of the chip capacitor is considerably smaller than the IC chip mounting area 23, the chip capacitor cannot function as a support for the IC chip 21. As a result, since the thermal expansion coefficients cannot be matched between the IC chip 21 and the wiring substrate 10, a large thermal stress acts on the IC chip 21, and the IC chip 21 is likely to be cracked or poorly connected.

  On the other hand, in the present embodiment, since one ceramic capacitor 101 is used instead of a plurality of chip capacitors, it is only necessary to provide one accommodation hole 90 in the substrate core 11. Therefore, since the process for assembling the ceramic capacitor 101 is simplified, the wiring board 10 can be easily manufactured and the cost can be reduced. Further, since the via array type ceramic capacitor 101 having a large capacitance is used instead of a simple chip capacitor, it is easy to achieve high functionality. Furthermore, in this embodiment, the area of the IC chip mounting region 23 is set to be smaller than the area of the upper surface 102 of the ceramic capacitor 101. In other words, the ceramic capacitor 101 having a larger area than the IC chip mounting region 23 is used. Moreover, the IC chip mounting region 23 is located in the upper surface 102 of the ceramic capacitor 101 when viewed from the thickness direction. Therefore, one ceramic capacitor 101 can function as a support for the IC chip 21. Therefore, it is possible to prevent the IC chip 21 from cracking and poor connection due to large thermal stress.

  (5) For example, it is conceivable to use a chip capacitor instead of the ceramic capacitor 101 and dispose the chip capacitor on the back side of the IC chip 21 in the wiring substrate 10 (the surface side of the second buildup layer 32). In this case, the inductance of the chip capacitor is 7.2 pH, and the inductance of the electrical path connecting the chip capacitor and the IC chip 21 is 2.8 pH, so the total inductance is 10.0 pH, which is relatively large.

  On the other hand, in this embodiment, the ceramic capacitor 101 having a lower inductance (1.2 pH) than the chip capacitor is used. In addition, since the ceramic capacitor 101 is embedded in the substrate core 11, the electrical path connecting the ceramic capacitor 101 and the IC chip 21 is shorter than the electrical path connecting the chip capacitor and the IC chip 21. For this reason, the inductance of the electrical path is also reduced to 0.6 pH. As a result, since the total inductance is 1.8 pH, the inductance component can be reduced as compared with the case where a chip capacitor is used. As a result, it is possible to supply power smoothly and suppress the generation of noise.

  (6) In the capacitor function unit 107 of this embodiment, a plurality of first power supply via conductors 131 and a plurality of first ground via conductors 132 are arranged in an array as a whole. Similarly, in the capacitor function unit 108 of the present embodiment, a plurality of second power supply via conductors 133 and a plurality of second ground via conductors 134 are arranged in an array as a whole. That is, the ceramic capacitor 101 including the capacitor function units 107 and 108 is a via array type capacitor. For this reason, it is easy to reduce the size of the ceramic capacitor 101 itself, and it is also easy to reduce the size of the entire wiring board 10. In addition, high capacitance can be easily achieved despite being small, and more stable power supply can be achieved.

(7) The ceramic capacitor 101 of the present embodiment may be modified as follows. For example, in the modification shown in FIG. 10, a back-side resistance pattern 311 made of a linear pattern as a resistor is formed on the lower surface 103 (capacitor back surface). In another modification shown in FIG. 11, a back-side resistance pattern 312 composed of a meandering linear pattern is formed on the lower surface 103. Moreover, these back surface side resistance patterns 311 and 312 are formed of nickel as a main material, and the surface is covered with a copper plating layer (not shown), and are formed of the same material as the electrode terminals 121 to 124.
[Second Embodiment]

  Hereinafter, a second embodiment in which the wiring board of the present invention is embodied will be described in detail with reference to FIGS.

  The ceramic capacitor 101 of the present embodiment shown in FIGS. 12 to 14 is different from the first embodiment in that a resistor and a capacitor 400 are provided therein. In this ceramic capacitor 101, an inner layer resistance pattern 321 as a resistor is formed at the interface between the first ceramic dielectric layer 105 and the second ceramic dielectric layer 105 (see FIG. 13). The inner layer resistance pattern 321 is formed of the same material as the first internal electrode layer 141 and the second internal electrode layer 142. Although the inner layer resistance pattern 321 is shown in FIG. 13 as a linear pattern, it may be a meandering linear pattern. Via conductors 420 are arranged at positions where both end portions of the inner layer resistance pattern 321 are located, and the exposed end portions of the via conductors 420 are used as the terminals T2 and T3, respectively.

  Similarly, at the interface between the first ceramic dielectric layer 105 and the second ceramic dielectric layer 105, the first electrode 401 constituting the capacitor 400 is formed next to the inner layer resistance pattern 321. (See FIG. 13). The first electrode 401 is also formed of the same material as the first internal electrode layer 141 and the second internal electrode layer 142. The first electrode 401 is a rectangular conductor pattern, and has a circular clearance hole 404 at a substantially central portion thereof.

  A second electrode 402 constituting the capacitor 400 is formed at a position immediately below the first electrode 401 at the interface between the second ceramic dielectric layer 105 and the third ceramic dielectric layer 105. (See FIG. 14). The second electrode 402 is also formed of the same material as the first internal electrode layer 141 and the second internal electrode layer 142. The second electrode 402 is a rectangular conductor pattern, and a via conductor 420 is connected to the upper surface side thereof. The via conductor 420 is disposed so as to penetrate the clearance hole 404, and the end exposed at the upper surface 12 is used as the terminal T1.

  The inner layer resistance pattern 321 and the capacitor 400 are electrically connected to each other, and a filter circuit 405 as a circuit unit is configured inside the ceramic capacitor 101 by this connection. For example, if a connection mode as shown in FIG. 15 is adopted, the filter circuit 405 can function as a so-called low-pass filter circuit. If the connection mode as shown in FIG. 16 is adopted, the filter circuit 405 can function as a so-called high-pass filter circuit.

As described above, according to the present embodiment, as a result of the filter function being imparted to the capacitor 101, it is possible to achieve multiple functions. Therefore, noise can be reduced by configuring the wiring board 10 using the capacitor 101 with the filter circuit 405.
[Third Embodiment]

  Hereinafter, a third embodiment in which the wiring board of the present invention is embodied will be described in detail with reference to FIGS.

  In the ceramic capacitor 101 of this embodiment shown in FIGS. 17 and 18, inner layer resistance patterns 321 are formed at a plurality of interfaces in the ceramic dielectric layer 105. These inner layer resistance patterns 321 are arranged in the inner region of the first internal electrode layer 141 or the second internal electrode layer 142, but are located in the clearance hole 404 in order to avoid connection with them. ing. The inner layer resistance patterns 321 are connected in series by a via conductor 420, and one large resistor is formed by this connection.

Even when the capacitor 101 having such a configuration is used, the multi-function, size reduction, and cost reduction of the wiring board 10 can be achieved as in the first embodiment.
[Fourth Embodiment]

  Hereinafter, a fourth embodiment in which the wiring board of the present invention is embodied will be described in detail with reference to FIG.

  In the ceramic dielectric layer 105 of the ceramic capacitor 101 of this embodiment shown in FIG. 19, via resistors 323 as resistors are formed at a plurality of locations. These via resistors 323 have, for example, a smaller diameter (about 50 μmφ to 80 μmφ) than the via conductor 420 in the above embodiment. For this reason, although it is formed of the same material as the via conductors 131 to 134 like the via conductor 420, it functions as a resistor. The plurality of via resistors 323 may be connected in series or may be connected via an inner layer resistor pattern 321.

Even when the capacitor 101 having such a configuration is used, the multi-function, size reduction, and cost reduction of the wiring board 10 can be achieved as in the first embodiment.
[Fifth Embodiment]

  Hereinafter, a fifth embodiment embodying the wiring board of the present invention will be described in detail with reference to FIG.

  The ceramic capacitor 101 of the present embodiment shown in FIG. 20 has a plurality of surface-side resistance patterns 301 and a plurality of inner-layer resistance patterns 321 on the upper surface 12 side, which are connected in series via via conductors 420. Has been. Further, the ceramic capacitor 101 has a plurality of inner layer resistance patterns 322 on the lower surface 13 side, which are connected in series via via conductors 420.

  Even when the capacitor 101 having such a configuration is used, the multi-function, size reduction, and cost reduction of the wiring board 10 can be achieved as in the first embodiment.

  In addition, you may change each embodiment of this invention as follows.

  -The accommodation hole 90 of each said embodiment was a through-hole part opened in the upper surface 12 and the lower surface 13. As shown in FIG. However, the housing hole 90 may be a bottomed recess (non-through hole) that opens only on the upper surface 12 of the substrate core 11.

  A wiring pattern (inner layer pattern) may be formed in the substrate core 11 of each of the above embodiments. With this configuration, a more complicated electric circuit can be formed in the wiring board 10, so that the wiring board 10 can be further enhanced in function. The substrate core 11 may be formed by laminating a thin insulating layer on the core.

  As shown in FIGS. 21 to 23, a firing resistor pattern 161 as a resistor may be formed on the upper surface 102 of the ceramic capacitor 101 or the like. For example, the firing resistor pattern 161 electrically connects the first power supply electrode terminal 111 (second power supply electrode terminal 113) and the other first power supply electrode terminal 111 (second power supply electrode terminal 113). ing. The fired resistance pattern 161 is made of a ceramic having a resistance value higher than that of the material constituting the power supply electrode terminals 111 and 113, the first internal electrode layer 141, the second internal electrode layer 142, and the like. The firing resistance pattern 161 is formed, for example, by applying a ceramic paste to the upper surface 102 side after the ceramic capacitor 101 is completed, firing it for a predetermined time, removing unnecessary portions, and adjusting the resistance value.

  With this configuration, for example, different potentials can be set in the ceramic capacitor 101, and it becomes easy to enhance the functionality of the wiring board 10. If the resistor 161 is not formed in the ceramic capacitor 101, the resistor 161 is embedded in the substrate core 11 at a location different from the ceramic capacitor 101, or the resistor 161 is provided on the buildup layers 31 and 32 side. There must be.

  In the above-described embodiment, the present invention is embodied for the capacitor 101 including the plurality of capacitor function units 107 and 108. However, the present invention may be embodied for a component including only one capacitor function unit.

  Next, the technical ideas grasped by the embodiment described above are listed below.

  (1) A substrate core having a core main surface and a core back surface, a capacitor main surface and a capacitor back surface, and first internal electrode layers and second internal electrode layers are alternately stacked via ceramic dielectric layers. A ceramic capacitor accommodated in the substrate core with the core main surface and the capacitor main surface facing the same side, an interlayer insulating layer and a conductor layer, the core main surface and the capacitor A wiring board comprising: a wiring laminated portion having a structure of alternately laminating on a main surface, wherein a resistor is formed on the ceramic capacitor.

  (2) A substrate core having a core main surface and a core back surface, a capacitor main surface and a capacitor back surface, and first internal electrode layers and second internal electrode layers are alternately stacked via ceramic dielectric layers. A ceramic capacitor embedded in the substrate core in a state where the core main surface and the capacitor main surface are directed to the same side; A semiconductor integrated circuit device having a structure in which an interlayer insulating layer and a conductor layer are alternately laminated on the core main surface and the capacitor main surface, and on which a semiconductor integrated circuit device having a plurality of processor cores can be mounted A wiring connection portion in which a mounting area is set, a resistor is formed on the ceramic capacitor, and the ceramic capacitor is disposed on the core substrate. Wherein arranged in the region corresponding to the semiconductor integrated circuit element mounting area, a wiring substrate on which the plurality of capacitor function units, characterized in that each of said plurality of processor cores are electrically connectable.

1 is a schematic sectional view showing a wiring board according to a first embodiment embodying the present invention. 1 is a schematic cross-sectional view showing a ceramic capacitor according to a first embodiment. Schematic explanatory drawing for demonstrating the connection in the inner layer of the ceramic capacitor of 1st Embodiment. Schematic explanatory drawing for demonstrating the connection in the inner layer of the ceramic capacitor of 1st Embodiment. The schematic plan view for demonstrating the mode of the upper surface of the ceramic capacitor of 1st Embodiment. The schematic plan view for demonstrating the mode of the upper surface of the ceramic capacitor in the example of a change of 1st Embodiment. Explanatory drawing of the manufacturing method of the wiring board of 1st Embodiment. Explanatory drawing of the manufacturing method of the wiring board of 1st Embodiment. Explanatory drawing of the manufacturing method of the wiring board of 1st Embodiment. The schematic bottom view for demonstrating the mode of the lower surface of the ceramic capacitor in the example of a change of 1st Embodiment. Similarly, the schematic bottom view for demonstrating the mode of the lower surface of a ceramic capacitor. The schematic sectional drawing which shows the ceramic capacitor of 2nd Embodiment. Schematic explanatory drawing for demonstrating the connection in the inner layer of the ceramic capacitor of 2nd Embodiment. Schematic explanatory drawing for demonstrating the connection in the inner layer of the ceramic capacitor of 2nd Embodiment. Schematic for demonstrating the circuit part which the ceramic capacitor of 2nd Embodiment comprises. Schematic for demonstrating the circuit part which the ceramic capacitor of 2nd Embodiment comprises. The schematic sectional drawing which shows the ceramic capacitor of 3rd Embodiment. Schematic explanatory drawing for demonstrating the connection in the inner layer of the ceramic capacitor of 3rd Embodiment. The schematic sectional drawing which shows the ceramic capacitor of 4th Embodiment. The schematic sectional drawing which shows the ceramic capacitor of 5th Embodiment. The schematic plan view which shows the mode of the resistor vicinity in the ceramic capacitor of other embodiment. Similarly, the schematic sectional drawing which shows the mode of a resistor vicinity. Similarly, the schematic sectional drawing which shows the mode of a resistor vicinity.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Wiring board 11 ... Board core 12 ... Upper surface 13 as a core main surface ... Lower surface 21 as a core back surface ... IC chip 23 as a semiconductor integrated circuit element ... IC chip mounting area 24, 25 as a semiconductor integrated circuit element mounting area ... Processor core 31... (First) first buildup layer 32 as a wiring laminate portion (second) second buildup layers 33, 34, 35, and 36 as a wiring laminate portion Resin insulation as an interlayer insulating layer Layer 42 ... Conductor layers 51 and 52 ... IC chip mounting area 101 as a semiconductor integrated circuit element mounting area ... Ceramic capacitor 102 as a capacitor ... Upper surface 103 as a capacitor main surface ... Lower surface 105 as a capacitor back surface ... Dielectric layer Ceramic dielectric layers 107, 108 ... capacitor functional part 141 ... first internal electrode layer 142 ... second internal electrode layer 61... Firing resistance pattern 171 as a resistor. First power source conductor portion 173 as a power source conductor portion. Second power source conductor portions 301 and 302 as a power source conductor portion. Surface-side resistance pattern 311 as a resistor. , 312 ... back side resistance patterns 321 and 322 as resistors, inner layer resistance patterns 323 as resistors, via resistances 400 as resistors, capacitors 405 ... circuit part

Claims (24)

A substrate core having a core main surface and a core back surface;
A capacitor functional portion having a capacitor main surface and a capacitor back surface, and having a structure in which first internal electrode layers and second internal electrode layers are alternately stacked via a dielectric layer; A capacitor housed in the substrate core with the capacitor main surface facing the same side;
A wiring laminated portion having a structure in which an interlayer insulating layer and a conductor layer are alternately laminated on the core main surface and the capacitor main surface ;
In the capacitor, a circuit unit including a resistor and a capacitor electrically connected to the resistor in a region outside the capacitor function unit when viewed from the capacitor main surface direction includes the first internal The wiring board, wherein the wiring board is disposed in a state where it is not electrostatically affected by the electrode layer and the second internal electrode layer . The capacitor is
A plurality of power supply via conductors for conducting the first internal electrode layers;
A plurality of ground via conductors for conducting the second internal electrode layers;
A power electrode terminal located at an end of the plurality of power via conductors;
A ground electrode terminal positioned at an end of each of the plurality of ground via conductors, wherein the plurality of power supply via conductors and the plurality of ground via conductors are arranged in an array. The wiring board according to claim 1. The wiring laminated portion is a first wiring laminated portion,
The wiring board according to claim 1, further comprising a second wiring laminated portion having a structure in which an interlayer insulating layer and a conductor layer are alternately laminated on the core back surface and the capacitor back surface.   4. The wiring substrate according to claim 1, wherein the resistor is formed on at least one of the capacitor main surface and the capacitor back surface of the capacitor. 5.   4. The wiring according to claim 2, wherein the resistor is a surface-side resistor pattern formed of the same material as the power electrode terminal and the ground electrode terminal on the capacitor main surface. substrate.   4. The wiring board according to claim 2, wherein the resistor is a back side resistance pattern formed of the same material as the power supply electrode terminal and the ground electrode terminal on the back side of the capacitor. 5. .   4. The resistor according to claim 1, wherein the resistor is an inner layer resistance pattern formed of the same material as that of the first internal electrode layer and the second internal electrode layer inside the capacitor. The wiring board according to item.   4. The resistor according to claim 2, wherein the resistor is a via resistor formed of the same material as the plurality of power supply via conductors and the plurality of ground via conductors inside the capacitor. Wiring board.   The wiring board according to claim 5, wherein the front-side resistance pattern, the back-side resistance pattern, or the inner-layer resistance pattern is a linear pattern.   The wiring board according to claim 5, wherein the front-side resistance pattern, the back-side resistance pattern, or the inner-layer resistance pattern is a meandering linear pattern. The said capacitor | condenser which comprises the said circuit part has a structure where the 1st electrode and the 2nd electrode were laminated | stacked and arranged via the said dielectric material layer, The any one of Claim 1 thru | or 10 characterized by the above-mentioned. Wiring board. The capacitor constituting the circuit unit has a structure in which a first electrode and a second electrode are stacked via the dielectric layer, and a first via conductor connected to the first electrode; A second via conductor connected to the second electrode, wherein an end portion of the first via conductor and an end portion of the second via conductor are respectively exposed at the capacitor main surface. wiring board according to any one of claims 1 to 10.   The wiring board according to claim 12, wherein the circuit unit is a filter circuit. A capacitor functional unit having a capacitor main surface and a capacitor back surface, and having a structure in which the first internal electrode layers and the second internal electrode layers are alternately stacked via a dielectric layer ;
A circuit unit including a resistor and a capacitor electrically connected to the resistor in a region outside the capacitor function unit when viewed from the capacitor main surface direction includes the first internal electrode layer and the capacitor A capacitor, wherein the capacitor is disposed in a state where it is not electrostatically affected by the second internal electrode layer . A plurality of power supply via conductors for conducting the first internal electrode layers;
A plurality of ground via conductors for conducting the second internal electrode layers;
A power electrode terminal located at an end of the plurality of power via conductors;
A ground electrode terminal positioned at an end of each of the plurality of ground via conductors, wherein the plurality of power supply via conductors and the plurality of ground via conductors are arranged in an array. The capacitor according to claim 14.   16. The capacitor according to claim 14, wherein the resistor is formed on at least one of the capacitor main surface and the capacitor back surface.   The capacitor according to claim 15, wherein the resistor is a surface-side resistor pattern formed of the same material as the power supply electrode terminal and the ground electrode terminal on the capacitor main surface.   16. The capacitor according to claim 14, wherein the resistor is an inner layer resistance pattern formed of the same material as the first internal electrode layer and the second internal electrode layer inside the capacitor.   The capacitor according to claim 15, wherein the resistor is a via resistor formed of the same material as the plurality of power supply via conductors and the plurality of ground via conductors inside the capacitor.   The capacitor according to claim 17 or 18, wherein the surface side resistance pattern or the inner layer resistance pattern is a linear pattern.   The capacitor according to claim 17 or 18, wherein the surface side resistance pattern or the inner layer resistance pattern is a meandering linear pattern. The said capacitor | condenser which comprises the said circuit part has a structure where the 1st electrode and the 2nd electrode were laminated | stacked via the said dielectric material layer, The any one of Claims 14 thru | or 21 characterized by the above-mentioned. Capacitor. The capacitor constituting the circuit unit has a structure in which a first electrode and a second electrode are stacked via the dielectric layer, and a first via conductor connected to the first electrode; A second via conductor connected to the second electrode, wherein an end portion of the first via conductor and an end portion of the second via conductor are respectively exposed at the capacitor main surface. The capacitor according to any one of claims 14 to 21 .   The capacitor according to claim 23, wherein the circuit unit is a filter circuit.

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