JP2008270776A - Wiring board having built-in component and manufacturing method thereof, and capacitor to be built in wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reliable wiring board having built-in components. <P>SOLUTION: The wiring board 10 has a core substrate 11, a ceramic capacitor 101, and a wiring laminated section 31. On the core substrate 11, a storage hole section 90 is formed. The ceramic capacitor 101 has a resin coating layer 151 coating a capacitor main surface 102 and a capacitor side 106. One portion 33a of an interlayer insulation layer 33 composing the wiring laminated section 31 fills up a clearance between an inner-wall surface 91 of the storage hole section 90 and the surface of the resin coating layer 151 coating the capacitor side 106 to fix the ceramic capacitor 101 onto the core substrate 11, thus reducing the clearance between the storage hole section 90 and the ceramic capacitor 101. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention has a structure in which a wiring laminated portion is formed on the surface of a core substrate, and includes a component built-in wiring substrate in which components such as capacitors are accommodated, a manufacturing method thereof, and a wiring substrate used for the component built-in wiring substrate It relates to a built-in capacitor.

  In recent years, semiconductor integrated circuit elements (IC chips) used as computer microprocessors and the like have become increasingly faster and more functional, with an accompanying increase in the number of terminals and a tendency to narrow the pitch between terminals. . In general, a large number of terminals are densely arranged on the bottom surface of an IC chip, and such a terminal group is connected to a terminal group on the motherboard side in the form of a flip chip. However, it is difficult to connect the IC chip directly on the mother board because there is a large difference in the pitch between the terminals on the IC chip side terminal group and the mother board side terminal group. For this reason, a method is generally employed in which a package is prepared by mounting an IC chip on an IC chip mounting wiring board, and the package is mounted on a motherboard. In a wiring board for mounting an IC chip constituting this type of package, it has been proposed to provide a capacitor (also referred to as a “capacitor”) in order to reduce switching noise of the IC chip and stabilize the power supply voltage. . As an example, a wiring board in which a chip-like capacitor is embedded in a core substrate made of a polymer material and a buildup layer is formed on the front surface and the back surface of the core substrate has been conventionally proposed (for example, see Patent Document 1). ).

One example of the conventional method for manufacturing a wiring board will be described below. First, a core substrate 204 made of a polymer material having an accommodation hole 203 that opens on both the core main surface 201 and the core back surface 202 is prepared (see FIG. 22). In addition, a capacitor 208 (see FIGS. 23 and 24) is prepared in which a plurality of surface layer electrodes 207 project from the capacitor main surface 205 and the capacitor back surface 206, respectively. Next, a taping step of attaching the adhesive tape 209 to the core back surface 202 side is performed, and the opening of the housing hole 203 on the core back surface 202 side is sealed in advance. And the accommodation process which accommodates the capacitor | condenser 208 in the accommodation hole part 203 is performed, the capacitor | condenser back surface 206 is affixed on the adhesive surface of the adhesive tape 209, and is temporarily fixed (refer FIG. 23). Next, a fixing step of filling the gap A1 between the inner wall surface of the accommodation hole 203 and the side surface of the capacitor 208 with a part of the resin insulating layer 210 in contact with the core main surface 201 is performed to fix the capacitor 208 (see FIG. 24). ). Thereafter, a buildup layer is formed by alternately forming a resin insulating layer mainly composed of a polymer material and a conductor layer on the core main surface 201 and the core back surface 202 of the core substrate 204. As a result, a desired wiring board is obtained.
Japanese Patent Laying-Open No. 2005-39243 (see FIG. 4)

  By the way, a general wiring board is obtained by dividing a multi-piece wiring board having a structure in which a plurality of product regions to be wiring boards are arranged vertically and horizontally along a plane direction. However, when the number of wiring boards obtained by the multi-cavity wiring board (the number of wirings) is increased, the number of receiving holes 203 is also increased, so that the volume to be filled with a part of the resin insulating layer 210 is also increased. Therefore, even if the resin insulating layer 210 is formed on the core main surface 201, it becomes difficult to sufficiently fill the gap A1 with a part of the resin insulating layer 210, and voids are likely to occur. Therefore, cracks are likely to occur between the capacitor 208 and the core substrate 204 (or build-up layer) starting from the void, and the reliability of the wiring board may be reduced.

  In order to completely fill the gap A1, the resin insulating layer 210 needs to be thickened. In recent years, thinning of the wiring board has been demanded. However, increasing the thickness of the resin insulating layer 210 is not preferable because it leads to thickening of the wiring board. Further, when forming the buildup layer, via holes are formed in the resin insulating layer 210 by laser to expose the surface layer electrodes 207 projecting from the capacitor main surface 205 through the resin insulating layer 210. However, when the resin insulating layer 210 is thick as described above, it is difficult to adjust the laser output when forming the via hole, and thus the surface electrode 207 may not be exposed. In this case, even if the via conductor is formed in the via hole, the capacitor 208 and the buildup layer cannot be electrically connected, and the reliability of the wiring board is lowered.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a component built-in wiring board excellent in reliability and a manufacturing method thereof. Another object of the present invention is to provide a wiring board built-in capacitor suitable for the component built-in wiring board.

  As means for solving the above problems (means 1), a core substrate having a core main surface and a core back surface and having an accommodation hole opening at least in the core main surface, a component main surface, and a component back surface And a resin coating layer that covers at least the component side surface, the core main surface and the component main surface are directed to the same side, and the inner wall surface of the receiving hole and the component side surface A component laminated in the accommodating hole, and a wiring laminated portion having a structure in which an interlayer insulating layer and a conductor layer are laminated on the core main surface and the component main surface, The component is fixed by filling a gap between an inner wall surface of the housing hole and a surface of the resin coating layer covering the side surface of the component with a part of an interlayer insulating layer in contact with the core main surface. There is a wiring board with built-in components.

  Therefore, according to the component built-in wiring board of means 1, since the gap formed between the housing hole and the component is reduced by covering the component with the resin coating layer, a large amount of interlayer is formed between the housing hole and the component. It is not necessary to fill the insulating layer. As a result, the gap can be sufficiently filled with a portion of the interlayer insulating layer without increasing the thickness of the interlayer insulating layer in contact with the main surface of the core, so that generation of voids and the like can be prevented. Therefore, a component built-in wiring board having excellent reliability can be obtained.

  The core substrate constituting the component-embedded wiring substrate is formed in a plate shape having, for example, a core main surface and a core back surface located on the opposite side, and has an accommodation hole for accommodating the component. The accommodation hole may be a non-through hole that opens only on the core main surface side, or may be a through hole that opens on both the core main surface side and the core back surface side. In addition, the component may be housed in the housing hole in a completely embedded state, or may be housed in the housing hole in a state in which a part protrudes from the opening of the housing hole.

  A material for forming the core substrate is not particularly limited, but a preferable core substrate is mainly formed of a polymer material. Specific examples of the polymer material for forming the core substrate include, for example, EP resin (epoxy resin), PI resin (polyimide resin), BT resin (bismaleimide / triazine resin), PPE resin (polyphenylene ether resin), etc. There is. In addition, composite materials of these resins and glass fibers (glass woven fabric or glass nonwoven fabric) or organic fibers such as polyamide fibers may be used.

  The components constituting the component-embedded wiring board have a component main surface, a component back surface, and a component side surface. The shape of the component can be arbitrarily set. For example, it is preferable that the component has a plate shape in which the area of the component main surface is larger than the area of the component side surface. In this way, when the component is accommodated in the accommodation hole, the distance between the inner wall surface of the accommodation hole and the side surface of the component is reduced, so that the resin coating layer covering the side surface of the component does not need to be so thick. Further, the shape of the component in plan view is preferably a polygonal shape in plan view having a plurality of sides. Examples of the polygonal shape in a plan view include a substantially rectangular shape in a plan view, a substantially triangular shape in a plan view, and a substantially hexagonal shape in a plan view, and in particular, a generally rectangular shape in a plan view. It is preferable. Here, the “substantially rectangular shape in plan view” does not mean only a complete rectangular shape in plan view but also includes a shape with chamfered corners and a shape in which a part of the side is curved. .

  Suitable components include a capacitor, a semiconductor integrated circuit element (IC chip), a MEMS (Micro Electro Mechanical Systems) element manufactured by a semiconductor manufacturing process, and the like. Here, “semiconductor integrated circuit element” refers to an element mainly used as a microprocessor of a computer or the like.

  Examples of suitable capacitors include a chip capacitor and a structure in which a plurality of internal electrode layers are stacked via a dielectric layer, and a plurality of vias in the capacitor connected to the plurality of internal electrode layers. Examples thereof include a capacitor having a conductor and a plurality of surface layer electrodes connected to at least an end portion on the component main surface side of the plurality of via conductors in the capacitor. The capacitor is preferably a via array type capacitor in which the plurality of capacitor via conductors are arranged in an array as a whole. With such a structure, the inductance of the capacitor can be reduced, and high-speed power supply for noise absorption and power supply fluctuation smoothing can be performed. In addition, it is easy to reduce the size of the entire capacitor, and it is also easy to reduce the size of the entire component-embedded wiring board. Moreover, a high electrostatic capacity is easily achieved for a small amount, and a more stable power supply can be achieved.

  Examples of the dielectric layer constituting the capacitor include a ceramic dielectric layer, a resin dielectric layer, and a dielectric layer made of a ceramic-resin composite material. As the ceramic dielectric layer, a sintered body of a high-temperature fired ceramic such as alumina, aluminum nitride, boron nitride, silicon carbide, silicon nitride, or the like is preferably used, and for borosilicate glass or lead borosilicate glass. A sintered body of low-temperature fired ceramic such as glass ceramic to which an inorganic ceramic filler such as alumina is added is preferably used. In this case, it is also preferable to use a sintered body of a dielectric ceramic such as barium titanate, lead titanate, or strontium titanate depending on the application. When a dielectric ceramic sintered body is used, a capacitor having a large capacitance can be easily realized. Further, as the resin dielectric layer, an epoxy resin, a resin such as tetrafluoroethylene resin (PTFE) containing an adhesive is preferably used. Furthermore, as the dielectric layer made of the ceramic-resin composite material, barium titanate, lead titanate, strontium titanate or the like is preferably used as the ceramic, and as the resin material, epoxy resin, phenol resin, urethane resin, Thermosetting resins such as silicone resin, polyimide resin, unsaturated polyester, thermoplastic resin such as polycarbonate resin, acrylic resin, polyacetal resin, polypropylene resin, and latex such as nitrile butadiene rubber, styrene butadiene rubber, and fluoro rubber are suitable. Used for.

  The internal electrode layer, the capacitor via conductor, and the surface electrode are not particularly limited. For example, when the dielectric layer is a ceramic dielectric layer, it is preferably a metallized conductor. The metallized conductor is formed by applying a conductive paste containing metal powder by a conventionally well-known method, for example, a metallized printing method, followed by baking. When the metallized conductor and the ceramic dielectric layer are formed by the co-firing method, the metal powder in the metallized conductor needs to have a melting point higher than the firing temperature of the ceramic dielectric layer. For example, when the ceramic dielectric layer is made of a so-called high-temperature fired ceramic (for example, alumina or the like), nickel (Ni), tungsten (W), molybdenum (Mo), manganese (Mn), or the like is used as the metal powder in the metallized conductor. And their alloys can be selected. When the ceramic dielectric layer is made of a so-called low-temperature fired ceramic (for example, glass ceramic), copper (Cu) or silver (Ag) or an alloy thereof can be selected as the metal powder in the metallized conductor.

  The resin coating layer constituting the component can be appropriately selected in consideration of insulation, heat resistance, moisture resistance, and the like. Preferred examples of the polymer material for forming the resin coating layer include thermosetting resins such as epoxy resins, phenol resins, urethane resins, silicone resins, polyimide resins, polycarbonate resins, acrylic resins, polyacetal resins, polypropylene resins, etc. And other thermoplastic resins. In addition, a material obtained by adding a glass filler to these resins may be used.

  Here, the thickness of the resin coating layer is preferably, for example, 200 μm or more and 800 μm or less, and particularly preferably about 500 μm. If the thickness of the resin coating layer is less than 200 μm, the gap generated between the housing hole and the part does not become so small, so a large amount of interlayer insulation layer must be filled between the housing hole and the part. I will have to. On the other hand, when the thickness of the resin coating layer is larger than 800 μm, the component becomes too large, and there is a possibility that the component cannot be accommodated in the accommodation hole.

  The resin coating layer covers at least the side of the component. Here, when the component has, for example, a substantially rectangular shape in plan view, that is, when there are four component side surfaces, the resin coating layer may cover only one component side surface, or two or more The side of the part may be covered. In addition, the resin coating layer may cover only the component side surface, or may cover only the component main surface and the component side surface, while not covering the component back surface, or the component back surface and the component. While covering the side surface, the component main surface may not be covered, or all of the component main surface, the component back surface, and the component side surface may be covered. In particular, the resin coating layer preferably covers the component main surface and the component side surface, but does not cover the component back surface. If the surface covered by the resin coating layer is only the side surface of the component, the space (gap) generated between the housing hole and the component is not so small, so the amount of the interlayer insulating layer filled in the housing hole is small. It will increase. On the other hand, if the resin coating layer covers even the back surface of the component, the space described above becomes small, but the component may move unless the resin coating layer is set in a cured state.

  Here, the surface of the resin coating layer covering the component main surface is preferably arranged in parallel with the component main surface. If it is not parallel to the component main surface, it is difficult to flatten the upper surface of the interlayer insulating layer in contact with the component main surface (the surface located on the side opposite to the component main surface in the interlayer insulating layer). Similarly, it is preferable that the surface of the resin coating layer covering the back surface of the component is also arranged in parallel with the back surface of the component. If it is not parallel to the component back surface, the component main surface is inclined with respect to the core main surface, making it difficult to flatten the upper surface of the interlayer insulating layer in contact with the component main surface. Moreover, it is preferable that the surface of the resin coating layer which covers a component side surface is arrange | positioned in parallel with a component side surface. If the surface of the resin coating layer covering the component side surface is not parallel to the side surface of the component, the surface of the resin coating layer covering the component side surface is inclined with respect to the inner wall surface of the housing hole portion. There is a possibility that a part of the interlayer insulating layer cannot be filled well in the gap with the inner wall surface.

  In addition, the wiring lamination part which comprises the said component built-in wiring board has the structure which laminated | stacked the interlayer insulation layer and conductor layer which mainly consist of polymer materials. In addition, although the wiring laminated portion is formed only on the core main surface and the component main surface, a laminated portion having the same structure as the wiring laminated portion may be formed on the core back surface and the component back surface. Good. With this configuration, an electric circuit can be formed not only in the wiring laminated portion formed on the core main surface and the component main surface, but also in the laminated portion formed on the core back surface and the component back surface. It is possible to further increase the functionality of the substrate.

  The interlayer insulating layer can be appropriately selected in consideration of insulation, heat resistance, moisture resistance, and the like. Preferred examples of the polymer material for forming the interlayer insulating layer include thermosetting resins such as epoxy resin, phenol resin, urethane resin, silicone resin, polyimide resin, polycarbonate resin, acrylic resin, polyacetal resin, polypropylene resin, etc. And other thermoplastic resins. In addition, composite materials of these resins and organic fibers such as glass fibers (glass woven fabrics and glass nonwoven fabrics) and polyamide fibers, or three-dimensional network fluorine-based resin base materials such as continuous porous PTFE, epoxy resins, etc. A resin-resin composite material impregnated with a thermosetting resin may be used.

  In addition, when the said interlayer insulation layer is a thermosetting resin, it is preferable that the said resin coating layer is also a thermosetting resin. If it does in this way, components can be fixed by making an interlayer insulation layer and a resin coating layer closely_contact | adhere simultaneously with formation of an interlayer insulation layer only by heating. This simplifies the process of assembling the components, so that the component built-in wiring board can be easily manufactured and the cost can be reduced.

  The resin coating layer may be formed of the same material as the interlayer insulating layer, or may be formed of a material different from the interlayer insulating layer, but is formed of the same material as the interlayer insulating layer. It is preferred that In this way, it is not necessary to prepare a material different from the interlayer insulating layer when forming the resin coating layer. Therefore, since the material necessary for manufacturing the wiring board is reduced, the cost of the wiring board can be reduced. In addition, since the components are fixed simultaneously with the formation of the interlayer insulating layer, the process for assembling the components is simplified. Therefore, the wiring board can be easily manufactured, and in this case, the cost can be reduced. Furthermore, since it becomes easy to integrate an interlayer insulation layer and a resin coating layer, components can be fixed more reliably.

  Furthermore, when the component built-in wiring board has the configuration of means 1, the resin coating layer is preferably formed of a material having the same thermal expansion coefficient as that of the interlayer insulating layer. This makes it difficult for a difference in thermal expansion coefficient to occur between the resin coating layer and the interlayer insulating layer, thereby preventing the occurrence of delamination between the two. Therefore, the reliability of the component built-in wiring board is further increased.

  Here, the “thermal expansion coefficient” means a thermal expansion coefficient in a direction (XY direction) perpendicular to the thickness direction (Z direction), and TMA (thermomechanical analysis) between 0 ° C. and 100 ° C. Means the value measured in the apparatus) (hereinafter the same). “TMA” refers to thermomechanical analysis, such as that defined in JPCA-BU01.

  Further, as another means (means 2) for solving the problems of the present invention, it has a capacitor main surface, a capacitor back surface, and a capacitor side surface, and a plurality of internal electrode layers are laminated via a dielectric layer. There is a wiring board built-in capacitor having a structure, wherein at least a side surface of the capacitor is covered with an uncured resin coating layer.

  Therefore, according to the means 2, a wiring board built-in capacitor suitable for the component built-in wiring board of the means 1 can be provided.

  In addition, since the resin coating layer is in an uncured state, the component covered with the resin coating layer is accommodated in the accommodation hole portion, and the interlayer insulating layer is interposed in the gap between the inner wall surface of the accommodation hole portion and the resin coating layer covering the side surface of the component. When filling a part, the resin coating layer becomes familiar with the interlayer insulating layer and is easily bonded.

  In addition, as an uncured state, the state which is not hardened at all, a semi-hardened state, etc. are mentioned, However, It is good in a semi-hardened state (for example, B stage). If the resin coating layer is not cured at all, it becomes difficult to handle a component covered with the resin coating layer. Further, since the resin coating layer is easily deformed, even if a component covered with the resin coating layer is accommodated in the accommodation hole portion, the gap between the inner wall surface of the accommodation hole portion and the resin coating layer covering the side surface of the component is kept between the interlayer insulating layers. There is a possibility that the object of the present invention, which is sufficiently filled with a part of the area, cannot be achieved.

  A method (means 3) suitable for producing the component built-in wiring board of means 1 is the method for producing a component built-in wiring board according to means 1, wherein a core substrate preparing step of preparing the core board is provided. A component preparing step of preparing a component having at least a side surface of the component covered with a resin coating layer; and a housing step of housing the component in the housing hole of the core substrate after the core substrate preparing step and the component preparing step. And after the housing step, the interlayer insulating layer is laminated on the core main surface and the component main surface, and the core main body is interposed in a gap between the inner wall surface of the housing hole and the resin coating layer covering the component side surface. And a fixing step of fixing the component by curing the interlayer insulating layer in contact with the core main surface after filling a part of the interlayer insulating layer in contact with the surface. is there.

  Therefore, according to the manufacturing method of the means 3, the gap generated between the housing hole and the component is reduced by performing the housing process of housing the component covered with the resin coating layer in the housing hole. For this reason, in the fixing step, it is not necessary to fill a large amount of interlayer insulating layer in the gap between the inner wall surface of the accommodation hole and the resin coating layer covering the side surface of the component. As a result, it is possible to sufficiently fill the gap with a part of the interlayer insulating layer without increasing the thickness of the interlayer insulating layer in contact with the main surface of the core, thereby preventing generation of voids and the like. Therefore, a component built-in wiring board having excellent reliability can be obtained.

  Hereinafter, a manufacturing method of the component built-in wiring board will be described.

  In the component preparation step, the component described in the means 1 is prepared by a conventionally known method and prepared in advance. The component preparation step includes a resin coating layer forming step of forming at least a resin coating layer that covers the side surface of the component. Here, examples of the method for forming the resin coating layer include a method for forming the resin coating layer by applying a resin, a method for forming the resin coating layer by applying a resin sheet, and the like. The component prepared in the component preparation step is such that the component main surface and the component side surface are covered by the resin coating layer, while the component back surface is not covered by the resin coating layer, The component main surface, the component back surface, and the component side surface may be covered with the resin coating layer, and the resin coating layer may be in a cured state.

  In the subsequent accommodating step, the component is accommodated in the accommodating hole of the core substrate. In the subsequent fixing step, the interlayer insulating layer is laminated on the core main surface and the component main surface, and the core main surface is formed in a gap between the inner wall surface of the housing hole and the resin coating layer covering the component side surface. After filling a part of the insulative interlayer insulating layer, the interlayer insulating layer in contact with the core main surface is cured to fix the component. If the resin coating layer is in an uncured state, the resin coating layer becomes easy to adhere to and adhere to the interlayer insulating layer, and the component is securely fixed. As a result, the component built-in wiring board is completed. When the interlayer insulating layer is a thermosetting resin, the step of curing the resin includes heating the uncured interlayer insulating layer.

  Hereinafter, an embodiment embodying a component built-in wiring board of the present invention will be described in detail with reference to the drawings.

  As shown in FIG. 1, a component built-in wiring board (hereinafter referred to as “wiring board”) 10 of this embodiment is a wiring board for mounting an IC chip. The wiring substrate 10 includes a substantially rectangular plate-shaped core substrate 11, a first buildup layer 31 (wiring laminated portion) formed on the core main surface 12 (upper surface in FIG. 1) of the core substrate 11, and the core substrate 11. The second buildup layer 32 is formed on the core back surface 13 (the lower surface in FIG. 1).

  The first buildup layer 31 formed on the core main surface 12 of the core substrate 11 is composed of two resin insulating layers 33 and 35 (so-called interlayer insulating layer) made of thermosetting resin (epoxy resin) and copper. The conductive layers 42 are alternately laminated. In this embodiment, the thermal expansion coefficients of the resin insulating layers 33 and 35 are about 10 to 60 ppm / ° C. (specifically, about 20 ppm / ° C.). In addition, the thermal expansion coefficient of the resin insulating layers 33 and 35 means an average value of measured values between 30 ° C. and the glass transition temperature (Tg). In addition, terminal pads 44 are formed in an array at a plurality of locations on the surface of the second resin insulating layer 35. Further, the surface of the resin insulating layer 35 is almost entirely covered with a solder resist 37. An opening 46 for exposing the terminal pad 44 is formed at a predetermined position of the solder resist 37. A plurality of solder bumps 45 are provided on the surface of the terminal pad 44. Each solder bump 45 is electrically connected to the surface connection terminal 22 of the IC chip 21 having a rectangular flat plate shape. Note that an area including the terminal pads 44 and the solder bumps 45 is an IC chip mounting area 23 on which the IC chip 21 can be mounted. The IC chip mounting area 23 is set on the surface 39 of the first buildup layer 31. Further, via conductors 43 and 47 are provided in the resin insulation layers 33 and 35, respectively. These via conductors 43 and 47 electrically connect the conductor layer 42 and the terminal pad 44 to each other.

  As shown in FIG. 1, the second buildup layer 32 formed on the core back surface 13 of the core substrate 11 has substantially the same structure as the first buildup layer 31 described above. That is, the second buildup layer 32 has a structure in which two resin insulation layers 34 and 36 made of a thermosetting resin (epoxy resin) and a conductor layer 42 are alternately laminated. The thermal expansion coefficients of 34 and 36 are about 10 to 60 ppm / ° C. (specifically, about 20 ppm / ° C.). BGA pads 48 that are electrically connected to the conductor layer 42 via via conductors 43 are formed in a lattice pattern at a plurality of locations on the lower surface of the second resin insulating layer 36. The lower surface of the resin insulating layer 36 is almost entirely covered with a solder resist 38. An opening 40 for exposing the BGA pad 48 is formed at a predetermined portion of the solder resist 38. On the surface of the BGA pad 48, a plurality of solder bumps 49 are provided for electrical connection with a mother board (not shown). The wiring board 10 shown in FIG. 1 is mounted on a mother board (not shown) by each solder bump 49.

  As shown in FIG. 1, the core substrate 11 of the present embodiment has a substantially rectangular plate shape in plan view of 25 mm long × 25 mm wide × 1.0 mm thick. The core substrate 11 has a thermal expansion coefficient in the plane direction (XY direction) of about 10 to 30 ppm / ° C. (specifically, 18 ppm / ° C.). In addition, the thermal expansion coefficient of the core board | substrate 11 says the average value of the measured value between 0 degreeC-glass transition temperature (Tg). The core substrate 11 includes a base material 161 made of glass epoxy, a sub-base material 164 formed on an upper surface and a lower surface of the base material 161 and made of an epoxy resin to which an inorganic filler such as silica filler is added, and an upper surface of the base material 161. And a conductor layer 163 made of copper and formed on the lower surface. In the core substrate 11, a plurality of through-hole conductors 16 are formed so as to penetrate the core main surface 12, the core back surface 13, and the conductor layer 163. The through-hole conductor 16 connects and conducts the core main surface 12 side and the core back surface 13 side of the core substrate 11 and is electrically connected to the conductor layer 163. The inside of the through-hole conductor 16 is filled with a closing body 17 such as an epoxy resin. The upper end of the through-hole conductor 16 is electrically connected to a part of the conductor layer 42 on the surface of the resin insulating layer 33, and the lower end of the through-hole conductor 16 is a conductor on the lower surface of the resin insulating layer 34. A part of the layer 42 is electrically connected. Further, a conductor layer 41 made of copper is patterned on the core main surface 12 and the core back surface 13 of the core substrate 11, and each conductor layer 41 is electrically connected to the through-hole conductor 16. Furthermore, the core substrate 11 has one rectangular accommodation hole 90 in a plan view that opens at the center of the core main surface 12 and the center of the core back surface 13. That is, the accommodation hole 90 is a through hole.

  And in the accommodation hole part 90, the ceramic capacitor 101 (component) which is a capacitor | condenser for wiring board shown in FIGS. 2-4 etc. is accommodated in the embedded state. The ceramic capacitor 101 is accommodated with the capacitor main surface 102 facing the same side as the core main surface 12 of the core substrate 11 and the inner wall surface 91 of the accommodation hole 90 and the capacitor side surface 106 facing each other. Yes. The ceramic capacitor 101 of the present embodiment has a substantially rectangular plate shape in plan view with a length of 10.0 mm × width of 10.0 mm × thickness of 0.8 mm. The ceramic capacitor 101 is arranged in a region immediately below the IC chip mounting region 23 in the core substrate 11. The area of the IC chip mounting region 23 (the area of the surface on which the surface connection terminals 22 are formed in the IC chip 21) is set to be smaller than the area of the capacitor main surface 102 of the ceramic capacitor 101. When viewed from the thickness direction of the ceramic capacitor 101, the IC chip mounting region 23 is located in the capacitor main surface 102 of the ceramic capacitor 101.

  As shown in FIGS. 1 to 4 and the like, the ceramic capacitor 101 of this embodiment is a so-called via array type capacitor. The ceramic sintered body 104 constituting the ceramic capacitor 101 includes one capacitor main surface 102 (upper surface in FIG. 1) as a component main surface, one capacitor back surface 103 (lower surface in FIG. 1) as a component back surface, and a component. A plate-like object having four capacitor side surfaces 106 as side surfaces. In this embodiment, the thermal expansion coefficient of the ceramic sintered body 104 is less than 15 ppm / ° C., specifically about 12 to 13 ppm / ° C. The thermal expansion coefficient of the ceramic sintered body 104 refers to an average value of measured values between 30 ° C. and 250 ° C.

  In the ceramic sintered body 104, the power supply internal electrode layer 141 (internal electrode layer) and the ground internal electrode layer 142 (internal electrode layer) are alternately stacked via the ceramic dielectric layer 105 (dielectric layer). It has a structure. The ceramic dielectric layer 105 is made of a sintered body of barium titanate, which is a kind of high dielectric constant ceramic, and functions as a dielectric (insulator) between the power internal electrode layer 141 and the ground internal electrode layer 142. To do. Each of the power supply internal electrode layer 141 and the ground internal electrode layer 142 is a layer formed mainly of nickel, and is disposed in every other layer in the ceramic sintered body 104.

  As shown in FIGS. 1 to 4, a large number of via holes 130 are formed in the ceramic sintered body 104. These via holes 130 penetrate the ceramic sintered body 104 in the thickness direction and are arranged in a lattice shape (array shape) over the entire surface of the ceramic sintered body 104. In each via hole 130, a plurality of in-capacitor via conductors 131 and 132 that communicate between the capacitor main surface 102 and the capacitor back surface 103 of the ceramic sintered body 104 are formed using nickel as a main material. Each power supply capacitor internal via conductor 131 passes through each power supply internal electrode layer 141 and electrically connects them to each other. Each ground capacitor via conductor 132 passes through each ground internal electrode layer 142 and electrically connects them to each other. Each power source capacitor via conductor 131 and each ground capacitor inner via conductor 132 are arranged in an array as a whole. In the present embodiment, for convenience of explanation, the via conductors 131 and 132 in the capacitor are illustrated in 5 columns × 5 columns, but there are actually more columns.

  2 and the like, a plurality of main surface side power supply electrodes 111 (surface layer electrodes) and a plurality of main surface side ground electrodes 112 (surface layer electrodes) are formed on the capacitor main surface 102 of the ceramic sintered body 104. ) And protruding. Each main surface side ground electrode 112 is individually formed on the capacitor main surface 102, but may be formed integrally. The main surface side power supply electrode 111 is directly connected to the end surface of the plurality of power supply capacitor internal via conductors 131 on the capacitor main surface 102 side, and the main surface side ground electrode 112 is connected to the plurality of ground capacitor internal electrodes. The via conductor 132 is directly connected to the end surface on the capacitor main surface 102 side.

  Further, on the capacitor back surface 103 of the ceramic sintered body 104, a plurality of back surface side power supply electrodes 121 (surface layer electrodes) and a plurality of back surface side ground electrodes 122 (surface layer electrodes) are projected. Each back surface side ground electrode 122 is individually formed on the capacitor back surface 103, but may be formed integrally. The back surface side power supply electrode 121 is directly connected to the end surface on the capacitor back surface 103 side of the plurality of power supply capacitor internal via conductors 131, and the back surface side ground electrode 122 is connected to the plurality of ground capacitor internal via conductors 132. Is directly connected to the end surface on the capacitor back surface 103 side. Therefore, the power supply electrodes 111 and 121 are electrically connected to the power supply capacitor internal via conductor 131 and the power supply internal electrode layer 141, and the ground electrodes 112 and 122 are connected to the ground capacitor internal via conductor 132 and the ground internal electrode layer 142. Is conducting.

  As shown in FIG. 1, the electrodes 111 and 112 on the capacitor main surface 102 side include the via conductor 47, the conductor layer 42, the via conductor 43, the terminal pad 44, the solder bump 45, and the surface connection terminal 22 of the IC chip 21. Is electrically connected to the IC chip 21 via On the other hand, the electrodes 121 and 122 on the capacitor back surface 103 side pass through via conductors 47, conductor layers 42, via conductors 43, BGA pads 48, and solder bumps 49 with respect to electrodes (contactors) of a mother board (not shown). Are electrically connected.

  As shown in FIG. 2 and the like, the electrodes 111, 112, 121, and 122 are made of nickel as a main material, and the surface is entirely covered with a copper plating layer (not shown). These electrodes 111, 112, 121, 122 and the via conductors 131, 132 in the capacitor are disposed immediately below the substantially central portion of the IC chip 21. In the present embodiment, the diameters of the electrodes 111, 112, 121, and 122 are set to about 500 μm, and the minimum pitch length is set to about 580 μm.

  For example, when energization is performed from the motherboard side via the electrodes 121 and 122 and a voltage is applied between the power supply internal electrode layer 141 and the ground internal electrode layer 142, for example, positive charges are accumulated in the power supply internal electrode layer 141. For example, negative charges accumulate in the ground internal electrode layer 142. As a result, the ceramic capacitor 101 functions as a capacitor. In the ceramic capacitor 101, the via-conductor 131 for power supply capacitor and the via-conductor 132 for ground capacitor are alternately arranged adjacent to each other, and the via-conductor 131 for power-supply capacitor and the via-conductor 132 for ground capacitor are connected to each other. The directions of the flowing currents are set to be opposite to each other. Thereby, the inductance component is reduced.

  As shown in FIGS. 1 to 4 and the like, the ceramic sintered body 104 is covered with a resin coating layer 151. Specifically, the resin coating layer 151 covers the entire capacitor main surface 102 and the entire four capacitor side surfaces 106. On the other hand, the resin coating layer 151 does not completely cover the capacitor back surface 103, and the back side power supply electrode 121 and the back side ground electrode 122 are exposed. The thickness of the resin coating layer 151 that covers the capacitor main surface 102 and the capacitor side surface 106 is set to 500 μm. The resin coating layer 151 is formed of the same material as the resin insulation layer 33 (that is, an epoxy resin that is a thermosetting resin). Thereby, the thermal expansion coefficient of the resin coating layer 151 is also the same value as the thermal expansion coefficient of the resin insulating layer 33, specifically, about 10 to 60 ppm / ° C. (specifically, about 20 ppm / ° C.). Is set to Further, the thermal expansion coefficient of the resin coating layer 151 is set to a value larger than the thermal expansion coefficient of the ceramic sintered body 104.

  As shown in FIG. 1 and the like, the gap between the inner wall surface 91 of the accommodation hole 90 and the surface of the resin coating layer 151 covering the capacitor side surface 106 of the ceramic capacitor 101 is the resin insulation that is in contact with the core main surface 12. It is filled with a resin filling portion 33 a which is a part of the layer 33. The resin filling portion 33 a has a function of fixing the ceramic capacitor 101 to the core substrate 11. The ceramic capacitor 101 has a substantially square shape in plan view, and has chamfered portions with chamfering dimensions of 0.55 mm or more (in this embodiment, chamfering dimensions of 0.6 mm) at the four corners. Thereby, when the resin filling portion 33a is deformed due to a temperature change, stress concentration on the corner portion of the ceramic capacitor 101 can be alleviated, so that the occurrence of cracks in the resin filling portion 33a can be prevented.

  Next, a method for manufacturing the wiring board 10 of this embodiment will be described.

  In the core substrate preparation step, an intermediate product of the core substrate 11 is prepared by a conventionally known technique and prepared in advance.

  The intermediate product of the core substrate 11 is manufactured as follows. First, a copper clad laminate (see FIG. 5) in which a copper foil 162 is attached to both surfaces of a base material 161 having a length of 350 mm, a width of 375 mm, and a thickness of 0.6 mm is prepared. Next, the copper foil 162 on both sides of the copper-clad laminate is etched to pattern the conductor layer 163 by, for example, a subtractive method (see FIG. 6). Specifically, after the electroless copper plating, electrolytic copper plating is performed using the electroless copper plating layer as a common electrode. Further, the dry film is laminated, and the dry film is exposed and developed to form a dry film in a predetermined pattern. In this state, unnecessary electrolytic copper plating layer, electroless copper plating layer and copper foil 162 are removed by etching. Thereafter, the dry film is peeled off. Next, after roughening the upper and lower surfaces of the base material 161 and the conductor layer 163, an epoxy resin film (thickness of 80 μm) to which an inorganic filler has been added is attached to the upper and lower surfaces of the base material 161 by thermocompression bonding. Then, the sub-base material 164 is formed (see FIG. 7).

  Next, the conductor layer 41 (for example, 50 μm) is patterned on the upper surface of the upper sub-base material 164 and the lower surface of the lower sub-base material 164, respectively. Specifically, after performing electroless copper plating on the upper surface of the upper sub-base material 164 and the lower surface of the lower sub-base material 164, an etching resist is formed, and then electrolytic copper plating is performed. Further, the etching resist is removed and soft etching is performed. Next, the laminated body composed of the base material 161 and the sub base material 164 is drilled using a router to form through holes to be the accommodation hole portions 90 at predetermined positions. (See FIG. 8). The intermediate product of the core substrate 11 is a multi-piece core substrate having a structure in which a plurality of regions to be the core substrate 11 are arranged vertically and horizontally along the plane direction.

  In the component preparation step (capacitor preparation step), the ceramic capacitor 101 is prepared by a conventionally known method and prepared in advance.

  The ceramic capacitor 101 is manufactured as follows. That is, a ceramic green sheet is formed, and nickel paste for internal electrode layers is screen printed on the green sheet and dried. As a result, a power internal electrode portion that will later become the power internal electrode layer 141 and a ground internal electrode portion that will be the ground internal electrode layer 142 are formed. Next, the green sheets with the power supply internal electrode portions and the green sheets with the ground internal electrode portions are alternately stacked, and each green sheet is integrated by applying a pressing force in the sheet stacking direction. To form a green sheet laminate.

  Further, a number of via holes 130 are formed through the green sheet laminate using a laser processing machine, and a via conductor nickel paste is filled into each via hole 130 using a paste press-fitting and filling device (not shown). Next, a paste is printed on the upper surface of the green sheet laminate, and the main surface side power supply electrode 111 and the main surface side ground electrode 112 so as to cover the upper end surface of each conductor portion on the upper surface side of the green sheet laminate. Form. Further, a paste is printed on the lower surface of the green sheet laminate, and the back-side power supply electrode 121 and the back-side ground electrode 122 are formed so as to cover the lower end surface of each conductor portion on the lower surface side of the green sheet laminate. .

  Thereafter, the green sheet laminate is dried to solidify the electrodes 111, 112, 121, and 122 to some extent. Next, the green sheet laminate is degreased and fired at a predetermined temperature for a predetermined time. As a result, barium titanate and nickel in the paste are simultaneously sintered to form a ceramic sintered body 104.

  Next, electroless copper plating (thickness of about 10 μm) is performed on each electrode 111, 112, 121, 122 included in the obtained ceramic sintered body 104. As a result, a copper plating layer is formed on each of the electrodes 111, 112, 121, 122, and the ceramic capacitor 101 is completed.

  In the subsequent capacitor placement process, after roughening the capacitor main surface 102 of the completed ceramic capacitor 101, a plurality of ceramic capacitors 101 are placed with the capacitor main surface 102 facing upward using a mounting device (manufactured by Yamaha Motor Co., Ltd.). In this state, it is set on a jig (not shown). More specifically, a peelable adhesive tape 172 (base material) is disposed on the jig, and each ceramic capacitor 101 is affixed to the adhesive surface (release surface) of the adhesive tape 172 and temporarily fixed. (See FIG. 9). At this time, the ceramic capacitors 101 are spaced apart from each other along the adhesive surface in a state of being disposed in parallel with the adhesive surface of the adhesive tape 172.

  In the subsequent resin filling step, an epoxy resin film 173 (thickness 400 μm) that is an uncured resin coating layer 151 is laminated on each ceramic capacitor 101 set in a jig (see FIGS. 10 and 11). At this time, a part of the epoxy resin film 173 is filled between the capacitor side surfaces 106 of the ceramic capacitors 101 adjacent to each other. In this state, it can be understood that the wiring board built-in capacitor assembly 174 is obtained by arranging a plurality of product regions to be the ceramic capacitor 101 having the resin coating layer 151 vertically and horizontally along the plane direction. Further, the wiring board built-in capacitor assembly 174 is divided using a laser processing machine. Specifically, the wiring board built-in capacitor assembly 174 is divided into pieces by dividing the resin coating layer 151 portion (see the one-dot chain line in FIG. 11) filled between the capacitor side surfaces 106 of the ceramic capacitors 101 adjacent to each other. Turn into. At that time, cutting is performed so that a resin coating layer 151 having a thickness of 500 μm is formed on each capacitor side surface 106. As a result, a large number of ceramic capacitors 101 in which the capacitor main surface 102 and the capacitor side surface 106 are covered with the resin coating layer 151 while the capacitor back surface 103 is not covered with the resin coating layer 151 are obtained simultaneously. At this point, the adhesive tape 172 is peeled off.

  In the subsequent housing step, the ceramic capacitors 101 are respectively housed in the plurality of housing holes 90 using a mounting device (manufactured by Yamaha Motor Co., Ltd.) (see FIG. 12). At this time, the core back surface 13 side opening of each accommodation hole 90 is sealed with a peelable adhesive tape 171. The adhesive tape 171 is supported by a support base (not shown). The ceramic capacitor 101 is affixed and temporarily fixed to the adhesive surface of the adhesive tape 171.

  Next, the first buildup layer 31 is formed on the core main surface 12 and the second buildup layer 32 is formed on the core back surface 13 based on a conventionally known method. Specifically, a fixing process is first performed. That is, a photosensitive epoxy resin is deposited on the core main surface 12 and the capacitor main surface 102, and exposure and development are performed to form the resin insulating layer 33 (see FIG. 13). In place of depositing the photosensitive epoxy resin, an insulating resin or a liquid crystal polymer (LCP) may be deposited. At the same time, a gap between the inner wall surface 91 of the accommodation hole 90 and the surface of the resin coating layer 151 covering the capacitor side surface 106 is filled with the resin filling portion 33a which is a part of the resin insulating layer 33. Thereafter, when heat treatment is performed, the resin insulating layer 33 (resin filling portion 33 a) and the resin coating layer 151 are cured, and the ceramic capacitor 101 is fixed to the core substrate 11. At this point, the adhesive tape 171 is peeled off.

  Next, a photosensitive epoxy resin is applied to the core back surface 13 and the capacitor back surface 103, and exposure and development are performed to form the resin insulating layer 34 (see FIG. 14). Instead of depositing the photosensitive epoxy resin, an insulating resin or a liquid crystal polymer may be deposited. In the subsequent exposure process, laser drilling is performed using a YAG laser or a carbon dioxide gas laser to form via holes 181 and 182 at positions where via conductors 47 are to be formed (see FIG. 15). Specifically, a via hole 181 passing through the resin insulating layer 33 and the resin coating layer 151 covering the capacitor main surface 102 is formed to expose the main surface side power supply electrode 111 and the main surface side ground electrode 112. . Similarly, a via hole 182 penetrating the resin insulating layer 34 is formed, and the back surface side power supply electrode 121 and the back surface side ground electrode 122 are exposed.

  Further, drilling is performed using a drill machine, and a through hole 191 that penetrates the core substrate 11 and the resin insulating layers 33 and 34 is formed in advance at a predetermined position (see FIG. 16). Then, after electroless copper plating is performed on the resin insulating layers 33 and 34, the inner surfaces of the via holes 181 and 182 and the inner surfaces of the through holes 191, an etching resist is formed, and then electrolytic copper plating is performed. Further, the etching resist is removed and soft etching is performed. Thereby, the conductor layer 42 is patterned on the resin insulating layer 33 and the resin insulating layer 34 (see FIG. 17). At the same time, the through-hole conductor 16 is formed in the through hole 191, and the via conductor 47 is formed in each via hole 181, 182.

  Thereafter, a hole filling process is performed. Specifically, the cavity of the through-hole conductor 16 is filled with an insulating resin material (epoxy resin) to form a closing body 17 (see FIG. 18).

  Next, a photosensitive epoxy resin is deposited on the resin insulating layers 33 and 34, and exposure and development are performed, whereby the resin insulating layers 35 and 184 having via holes 183 and 184 at positions where the via conductors 43 are to be formed. 36 is formed (see FIG. 18). Instead of depositing the photosensitive epoxy resin, an insulating resin or a liquid crystal polymer may be deposited. In this case, via holes 183 and 184 are formed at positions where the via conductors 43 are to be formed by a laser processing machine or the like. Next, electrolytic copper plating is performed according to a conventionally known method to form via conductors 43 in the via holes 183 and 184, and terminal pads 44 are formed on the resin insulating layer 35. A BGA pad 48 is formed.

  Next, solder resists 37 and 38 are formed by applying and curing a photosensitive epoxy resin on the resin insulating layers 35 and 36. Next, exposure and development are performed with a predetermined mask placed, and the openings 40 and 46 are patterned in the solder resists 37 and 38. Further, solder bumps 45 are formed on the terminal pads 44 and solder bumps 49 are formed on the BGA pads 48. It can be understood that the product in this state is a multi-cavity wiring board in which a plurality of product regions to be the wiring board 10 are arranged vertically and horizontally along the plane direction. Furthermore, when the multi-cavity wiring board is divided, a large number of wiring boards 10 which are individual products can be obtained simultaneously.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) According to the wiring board 10 of the present embodiment, the ceramic capacitor 101 is covered with the resin coating layer 151, so that a gap generated between the accommodation hole 90 and the ceramic capacitor 101 is reduced. Therefore, it is not necessary to fill a large amount of the resin insulating layer 33 (resin filling portion 33a) between the ceramic capacitor 101 and the ceramic capacitor 101. As a result, the gap can be sufficiently filled with a part of the resin insulation layer 33 (resin filling portion 33a) without increasing the thickness of the resin insulation layer 33 in contact with the core main surface 12. Can be prevented. Therefore, the wiring board 10 excellent in reliability can be obtained.

  Further, since it is not necessary to increase the thickness of the resin insulating layer 33 in contact with the core main surface 12, the laser output adjustment is performed when the via hole 181 is formed by performing laser drilling in the resin insulating layer 33 in the exposure process. Is not so difficult. Therefore, the main surface side power supply electrode 111 and the main surface side ground electrode 112 on the capacitor main surface 102 can be reliably exposed. As a result, since the ceramic capacitor 101 and the first buildup layer 31 can be reliably electrically connected, the reliability of the wiring board 10 is improved.

  (2) In the present embodiment, the resin filling portion that fills the gap between the inner wall surface 91 of the accommodation hole portion 90 and the surface of the resin coating layer 151 that covers the capacitor side surface 106 forms a part of the resin insulating layer 33. Since it is the portion 33a, it is not necessary to prepare a material different from the resin insulating layer 33 when forming the resin filling portion. Therefore, since the material necessary for manufacturing the wiring board 10 is reduced, the cost of the wiring board 10 can be reduced.

  (3) For example, when the capacitor back surface 103 is completely covered with the resin coating layer 151, the ceramic capacitor 101 may move unless the resin coating layer 151 is set in a cured state at the stage of the component preparation process.

  On the other hand, the resin coating layer 151 of the present embodiment does not completely cover the capacitor back surface 103, and the back surface side power supply electrode 121 and the back surface side ground electrode 122 are exposed. Therefore, the resin coating layer 151 does not need to be cured at the stage of the component preparation process, and the resin coating layer 151 is cured simultaneously with the resin insulating layer 33 (resin filling portion 33a) in the fixing process. Thereby, since the process at the time of manufacture of the wiring board 10 is simplified, while being able to manufacture the wiring board 10 easily, cost reduction can be achieved.

  (4) In this embodiment, since the ceramic capacitor 101 is disposed immediately below the IC chip 21 mounted in the IC chip mounting region 23, the wiring connecting the ceramic capacitor 101 and the IC chip 21 is shortened, and the wiring inductance is reduced. Increase in ingredients is prevented. Therefore, the switching noise of the IC chip 21 due to the ceramic capacitor 101 can be reliably reduced, and the power supply voltage can be reliably stabilized. In addition, since noise entering between the IC chip 21 and the ceramic capacitor 101 can be suppressed to a very low level, high reliability can be obtained without causing malfunction such as malfunction.

  (5) In this embodiment, since the IC chip mounting area 23 is located in the area immediately above the ceramic capacitor 101, the IC chip 21 mounted in the IC chip mounting area 23 has high rigidity and a thermal expansion coefficient. Supported by a small ceramic capacitor 101. Therefore, in the IC chip mounting area 23, the first buildup layer 31 is not easily deformed, so that the IC chip 21 mounted in the IC chip mounting area 23 can be supported more stably. Therefore, it is possible to prevent the IC chip 21 from cracking and poor connection due to large thermal stress. Therefore, the IC chip 21 is considered to be a large IC chip of 10 mm square or more, which has a large stress (strain) due to a difference in thermal expansion and is greatly affected by thermal stress, and has a large calorific value and severe thermal shock during use. A low-k (low dielectric constant) IC chip can be used.

  In addition, you may change embodiment of this invention as follows.

  In the ceramic capacitor 101 of the above embodiment, the entire capacitor main surface 102 and the entire capacitor side surface 106 are covered with the resin coating layer 151, while the capacitor back surface 103 is not completely covered with the resin coating layer 151. However, as shown in FIG. 19, in addition to the capacitor main surface 102 and the capacitor side surface 106, the capacitor back surface 103 may be a ceramic capacitor 195 completely covered with the resin coating layer 151. In this case, in order to prevent the ceramic capacitor 101 from moving, the resin coating layer 151 is set in a cured state.

  In the ceramic capacitor 101 of the above embodiment, the four capacitor side surfaces 106 are covered with the resin coating layer 151, but only one capacitor side surface 106 may be covered with the resin coating layer 151, or two or Three capacitor side surfaces 106 may be covered with the resin coating layer 151. Further, the resin coating layer 151 may completely cover the surfaces (capacitor main surface 102 and capacitor side surface 106) covered by the resin coating layer 151, or cover only a part of the surface covered by the resin coating layer 151. May be.

  The wiring substrate 10 of the above embodiment is configured by housing the ceramic capacitor 101 in the core substrate 11 and mounting the IC chip 21 on the IC chip mounting region 23. However, as shown in FIGS. 20 and 21, the IC chip 211 may be housed as a component in the core substrate 11, and the wiring substrate 213 may be mounted with the ceramic capacitor 212 on the IC chip mounting region 23. The IC chip 211 has one chip main surface 215 that is a component main surface, one chip back surface 216 that is a component back surface, and four chip side surfaces 217 that are component side surfaces. In the IC chip 211, the entire chip back surface 216 and the entire chip side surface 217 are covered with the resin coating layer 219, while the chip main surface 215 is not covered with the resin coating layer 219. In addition, surface connection terminals 218 protrude from a plurality of locations on the chip main surface 215. The IC chip 211 is accommodated with the core main surface 12 and the chip main surface 215 of the core substrate 11 facing the same side (see FIG. 21).

  20 has a signal wiring 214 for sending signals from the IC chip 211 to electronic components (not shown) mounted on the surface 39 of the first buildup layer 31. The wiring board 213 shown in FIG. You may do it. The signal wiring 214 is a wiring composed of the conductor layer 42, the via conductors 43 and 47, and the terminal pad 44.

  Next, the technical ideas grasped by the embodiment described above are listed below.

  (1) A core substrate having a core main surface and a core back surface and having an accommodation hole opening at least in the core main surface, a component main surface, a component back surface, and a component side surface, and covering at least the component side surface Housed in the housing hole with a resin coating layer, with the core main surface and the component main surface facing the same side, and with the inner wall surface of the housing hole facing the component side surface And a resin laminate that covers the inner wall surface of the housing hole and the side surface of the component, and a wiring laminated portion having a structure in which an interlayer insulating layer and a conductor layer are laminated on the core main surface and the component main surface. The part is fixed by filling a gap with the surface of the layer with a part of the interlayer insulating layer in contact with the core main surface, and the resin coating layer is a material having the same thermal expansion coefficient as the interlayer insulating layer Characterized by being formed by Wiring board with a built-in component that.

  (2) A core substrate having a core main surface and a core back surface and having an accommodation hole opening at least in the core main surface, a component main surface, a component back surface, and a component side surface, and at least covering the component side surface Housed in the housing hole with a resin coating layer, with the core main surface and the component main surface facing the same side, and with the inner wall surface of the housing hole facing the component side surface And a resin laminate that covers the inner wall surface of the housing hole and the side surface of the component, and a wiring laminated portion having a structure in which an interlayer insulating layer and a conductor layer are laminated on the core main surface and the component main surface. The part is fixed by filling a gap with the surface of the layer with a part of the interlayer insulating layer in contact with the core main surface, and the resin coating layer is formed of the same material as the interlayer insulating layer Wiring base with built-in components .

  (3) A core substrate having a core main surface and a core back surface and having an accommodation hole opening at least in the core main surface, a component main surface, a component back surface, and a component side surface, and covering at least the component side surface It has a resin coating layer, and is accommodated in the accommodation hole portion with the core main surface and the component main surface facing the same side, and with the inner wall surface of the accommodation hole portion and the component facing each other. And a resin laminate that covers the inner wall surface of the housing hole and the side surface of the component, and a wiring laminated portion having a structure in which an interlayer insulating layer and a conductor layer are laminated on the core main surface and the component main surface. The part is fixed by filling a gap with the surface of the layer with a part of the interlayer insulating layer in contact with the core main surface, and the thermal expansion coefficient of the interlayer insulating layer is equal to or higher than the thermal expansion coefficient of the resin coating layer And the resin coating layer Component built-in wiring board expansion coefficient, characterized in that it is larger than the thermal expansion coefficient of the component.

  (4) A substrate having a release surface, a capacitor main surface, a capacitor back surface, and a capacitor side surface, and having a structure in which a plurality of internal electrode layers are laminated via a dielectric layer, A plurality of capacitors that are spaced apart from each other along the release surface in a state of being disposed in parallel with the release surface, and an uncured resin coating layer that is filled between the capacitor side surfaces of adjacent capacitors. A capacitor assembly for wiring board built-in.

  (5) A substrate having a release surface, a capacitor main surface, a capacitor back surface, and a capacitor side surface, and a plurality of capacitors having a structure in which a plurality of internal electrode layers are stacked via a dielectric layer. A method of manufacturing a wiring board built-in capacitor assembly, comprising: a base material preparation step for preparing the base material; and the plurality of capacitors in the state in which the capacitor back surface is disposed in parallel with the mold release surface. Capacitor assembly with a built-in wiring board, comprising: a capacitor disposing step of disposing each other along a plane; and a resin filling step of filling an uncured resin coating layer between the capacitor side surfaces of adjacent capacitors Body manufacturing method.

  (6) A core substrate having a core main surface and a core back surface and having an accommodation hole opening at least in the core main surface; a component main surface, a component back surface, and a component side surface; and covering at least the component side surface A method of manufacturing a component built-in wiring board comprising: a component having a resin coating layer; and a wiring laminated portion having a structure in which an interlayer insulating layer and a conductor layer are laminated on the core main surface and the component main surface, A core substrate preparing step for preparing a core substrate, a component preparing step for preparing a component covered at least with a resin coating layer whose side faces are uncured, and after the core substrate preparing step and the component preparing step, Housing that accommodates the component in the housing hole of the core substrate with the core main surface and the component main surface facing the same side, and with the inner wall surface of the housing hole facing the component side surface Then, after the accommodating step, the interlayer insulating layer is laminated on the core main surface and the component main surface, and the core is disposed in a gap between the inner wall surface of the accommodating hole and the resin coating layer covering the component side surface. And a fixing step of fixing the component by curing the interlayer insulating layer in contact with the core main surface and the resin coating layer after filling a part of the interlayer insulating layer in contact with the main surface. A method for manufacturing a built-in wiring board.

  (7) A core substrate having a core main surface and a core back surface and having an accommodation hole opening at least in the core main surface; a capacitor main surface, a capacitor back surface, and a capacitor side surface; and via a dielectric layer It has a structure in which a plurality of internal electrode layers are arranged in a stack, and a plurality of via conductors in a capacitor connected to the plurality of internal electrode layers, at least at the end on the capacitor main surface side in the plurality of via conductors in the capacitor A plurality of connected surface layer electrodes, a capacitor having a resin coating layer covering at least the capacitor main surface and the capacitor side surface, and an interlayer insulating layer and a conductor layer were laminated on the core main surface and the capacitor main surface. A wiring board with a built-in capacitor having a wiring laminated portion having a structure, comprising: a core board preparing step for preparing the core board; At least a component preparation step of preparing a capacitor in which the capacitor main surface and the capacitor side surface are covered with a resin coating layer, and after the core substrate preparation step and the component preparation step, the core main surface and the capacitor main surface, Facing the same side, and with the inner wall surface of the housing hole and the capacitor side face facing each other, the housing step of housing the capacitor in the housing hole portion of the core substrate, and after the housing step, Laminating the interlayer insulating layer on the core main surface and the resin coating layer covering the capacitor main surface, and the core main surface in a gap between the inner wall surface of the housing hole and the resin coating layer covering the capacitor side surface A fixing step of fixing the capacitor by curing the interlayer insulating layer in contact with the core main surface after filling a part of the interlayer insulating layer in contact with the core, and after the fixing step, A capacitor built-in comprising: an exposure step of forming a via hole penetrating the edge layer and a resin coating portion covering the capacitor main surface to expose the plurality of surface layer electrodes on the capacitor main surface A method for manufacturing a wiring board.

  (8) A core substrate having a core main surface and a core back surface and having an accommodation hole opening at least in the core main surface; a capacitor main surface, a capacitor back surface, and a capacitor side surface; and via a dielectric layer A capacitor having a structure in which a plurality of internal electrode layers are laminated and having a resin coating layer covering at least the side surface of the capacitor, and an interlayer insulating layer and a conductor layer are laminated on the core main surface and the capacitor main surface. A method of manufacturing a capacitor-embedded wiring board comprising a wiring laminated portion having a structure, the core board preparing step for preparing the core substrate, the capacitor preparing step for preparing the capacitor, the core substrate preparing step, and the capacitor After the preparation step, the core main surface and the capacitor main surface are directed to the same side, and the inner wall surface of the housing hole and the capacitor side surface A housing step of housing the capacitor in the housing hole in a state of facing each other, and after the housing step, laminating the interlayer insulating layer on the core main surface and the capacitor main surface, and the housing hole portion After filling the gap between the inner wall surface of the capacitor and the resin coating layer covering the capacitor side surface with a part of the interlayer insulating layer in contact with the core main surface, the interlayer insulating layer in contact with the core main surface is cured to fix the capacitor In the capacitor preparing step, a plurality of base materials having a release surface and a plurality of capacitors spaced apart from each other along the release surface in a state where the capacitor back surface is arranged in parallel with the release surface. Wiring board built-in capacitor assembly comprising the capacitor and an uncured resin coating layer filled between the capacitor side surfaces of adjacent capacitors. Singulation is divided in the portion of the resin coating layer filled between the capacitor side of the capacitor, the capacitor built-in wiring board manufacturing method characterized by obtaining a plurality of capacitors.

1 is a schematic cross-sectional view showing a wiring board according to an embodiment of the present invention. The schematic sectional drawing which shows a ceramic capacitor. Schematic explanatory drawing for demonstrating the connection in the inner layer of a ceramic capacitor. Schematic explanatory drawing for demonstrating the connection in the inner layer of a ceramic capacitor. Explanatory drawing of the manufacturing method of a wiring board. Explanatory drawing of the manufacturing method of a wiring board. Explanatory drawing of the manufacturing method of a wiring board. Explanatory drawing of the manufacturing method of a wiring board. Explanatory drawing of the manufacturing method of a wiring board. Explanatory drawing of the manufacturing method of a wiring board. Explanatory drawing of the manufacturing method of a wiring board. Explanatory drawing of the manufacturing method of a wiring board. Explanatory drawing of the manufacturing method of a wiring board. Explanatory drawing of the manufacturing method of a wiring board. Explanatory drawing of the manufacturing method of a wiring board. Explanatory drawing of the manufacturing method of a wiring board. Explanatory drawing of the manufacturing method of a wiring board. Explanatory drawing of the manufacturing method of a wiring board. The schematic sectional drawing which shows the ceramic capacitor in other embodiment. The schematic sectional drawing which shows the wiring board in other embodiment. Similarly, explanatory drawing of the manufacturing method of a wiring board. Explanatory drawing of the manufacturing method of the wiring board in a prior art. Similarly, explanatory drawing of the manufacturing method of a wiring board. Similarly, explanatory drawing of the manufacturing method of a wiring board.

Explanation of symbols

10,213 ... Wiring board with built-in components (wiring board)
DESCRIPTION OF SYMBOLS 11 ... Core board | substrate 12 ... Core main surface 13 ... Core back surface 31 ... 1st buildup layers 33 and 35 as a wiring lamination | stacking part ... Resin insulating layer 33a as an interlayer insulation layer ... Resin filling part as a part of interlayer insulation layer 42 ... Conductive layer 90 ... Accommodating hole 91 ... Inner wall surface 101,195 of accommodating hole ... Ceramic capacitor 102 as capacitor for component and wiring board incorporation ... Condenser main surface 103 as component main surface ... Condenser back surface as component back surface DESCRIPTION OF SYMBOLS 105 ... Ceramic dielectric layer 106 as a dielectric layer ... Capacitor side surface 111 as a component side surface ... Main surface side power electrode 112 as a surface layer electrode ... Main surface side ground electrode 121 as a surface layer electrode ... Back surface as a surface layer electrode Side power electrode 122 ... Back side ground electrode 131 as a surface layer electrode ... Power source capacitor as a via conductor in the capacitor Via conductor 132... Ground capacitor via conductor 141 as a capacitor via conductor 141. Power supply internal electrode layer 142 as an internal electrode layer. Ground internal electrode layers 151 and 219 as internal electrode layers. Resin coating layer 211. IC chip 215 as a chip main surface 216 as a component main surface ... Chip back surface 217 as a component back surface ... Chip side surface as a component side surface

Claims (11)

A core substrate having a core main surface and a core back surface and having an accommodation hole opening at least in the core main surface;
It has a component main surface, a component back surface and a component side surface, and has a resin coating layer covering at least the component side surface, the core main surface and the component main surface are directed to the same side, and the inside of the accommodation hole portion With the wall and the component side facing each other, the component housed in the housing hole,
A wiring laminated portion having a structure in which an interlayer insulating layer and a conductor layer are laminated on the core main surface and the component main surface;
The component is fixed by filling a gap between the inner wall surface of the housing hole and the surface of the resin coating layer covering the component side surface with a part of an interlayer insulating layer in contact with the core main surface. Wiring board with built-in components.   The component built-in wiring board according to claim 1, wherein the interlayer insulating layer and the resin coating layer are thermosetting resins.   The component built-in wiring board according to claim 1, wherein the resin coating layer covers the component main surface and the component side surface, but does not cover the component back surface. The parts are
Having a structure in which a plurality of internal electrode layers are stacked via a dielectric layer;
A plurality of via conductors in the capacitor connected to the plurality of internal electrode layers;
A plurality of surface layer electrodes connected to at least an end portion on the component main surface side of the plurality of via conductors in the capacitor, and the plurality of via conductors in the capacitor are arranged in an array as a whole. The component built-in wiring board according to claim 1, wherein the wiring board has a built-in component.   The capacitor has a capacitor main surface, a capacitor back surface, and a capacitor side surface, and has a structure in which a plurality of internal electrode layers are laminated via a dielectric layer, and at least the capacitor side surface is covered with an uncured resin coating layer. A wiring board built-in capacitor.   6. The wiring board built-in capacitor according to claim 5, wherein the resin coating layer is a thermosetting resin.   7. The wiring board built-in capacitor according to claim 5, wherein the resin coating layer covers the capacitor main surface and the capacitor side surface, but does not cover the capacitor back surface. A plurality of via conductors in the capacitor connected to the plurality of internal electrode layers;
A plurality of surface layer electrodes connected to at least the capacitor main surface side end of the plurality of capacitor via conductors;
The wiring board built-in capacitor according to claim 5, wherein the plurality of via conductors in the capacitor are arranged in an array as a whole. It is a manufacturing method of the component built-in wiring board according to any one of claims 1 to 4,
A core substrate preparation step of preparing the core substrate;
A component preparation step of preparing a component in which at least the component side surface is covered with a resin coating layer;
After the core substrate preparation step and the component preparation step, a housing step for housing the component in the housing hole of the core substrate;
After the accommodating step, the interlayer insulating layer is laminated on the core main surface and the component main surface, and the core main surface is disposed in a gap between the inner wall surface of the accommodating hole and the resin coating layer covering the component side surface. And a fixing step of fixing the component by curing the interlayer insulating layer in contact with the core main surface after filling a part of the interlayer insulating layer in contact therewith.   The component prepared in the component preparation step is characterized in that the component main surface and the component side surface are covered with the resin coating layer, while the component back surface is not covered with the resin coating layer. A method for manufacturing a component-embedded wiring board as described in 1. The component prepared in the component preparation step, the component main surface, the component back surface and the component side surface is covered with the resin coating layer,
The method for manufacturing a component built-in wiring board according to claim 9, wherein the resin coating layer is in a cured state.

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