JP2002246755A - Manufacturing method of multilayer printed-wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To propose a method for manufacturing multilayer printed-wiring boards for incorporating semiconductor devices of high reliability. SOLUTION: An insulating resin board 30A for accommodating an IC chip 20 into a passage hole, and an insulating resin board 30B are laminated by interposing a prepreg 30C, and then are pressurized. An epoxy resin 30α seeps from the prepreg 30C for covering the upper surface of the IC chip 20, thus making the upper surface of the IC chip 20 and insulating resin board 30A completely flat, thus properly forming a via hole and wiring, when a build-up layer is formed, and hence enhancing reliability in the wiring of the multilayer printed-wiring board.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer printed wiring board incorporating a semiconductor element such as an IC chip.

[0002]

2. Description of the Related Art IC chips are manufactured by wire bonding,
The electrical connection with the printed wiring board has been established by a mounting method such as TAB or flip chip. Wire bonding is to bond the IC chip to the printed wiring board with an adhesive and connect the pad of the printed wiring board and the pad of the IC chip with a wire such as a gold wire, and then to protect the IC chip and the wire. To a sealing resin such as a thermosetting resin or a thermoplastic resin.

[0003] In TAB, bumps of an IC chip and pads of a printed wiring board are connected together by a wire called a lead by soldering or the like, and then sealed with a resin. The flip chip has been performed by connecting an IC chip and a pad portion of a printed wiring board via a bump, and filling a gap between the bump and the resin with a resin.

[0004] However, each mounting method is based on I
Electrical connection is made between the C chip and the printed wiring board via connection lead components (wires, leads, bumps). Each of these lead components is easily cut and corroded, which may cause the connection with the IC chip to be interrupted or a malfunction to occur. Also, in each mounting method, sealing is performed with a thermoplastic resin such as an epoxy resin to protect the IC chip, but if the resin is filled with air bubbles, the air bubbles become a starting point,
This leads to destruction of lead components, corrosion of IC pads, and a decrease in reliability. For sealing with thermoplastic resin, it is necessary to create a resin loading plunger and mold according to each part, and even for thermosetting resin, consider materials such as lead parts and solder resist Since it is necessary to select a suitable resin, the cost of each resin is also increased.

On the other hand, instead of mounting an IC chip on the outside of a printed wiring board (package substrate) as described above, a semiconductor element is embedded in a substrate and a build-up layer is formed thereon to provide electrical connection. Japanese Patent Laid-Open No. 9-321408 (USP5)
875100), JP-A-10-256429 and JP-A-11-126978.

Japanese Patent Application Laid-Open No. 9-321408 (USP 587)
No. 5100), a semiconductor element having a stud bump formed on a die pad is embedded in a printed wiring board, and a wiring is formed on the stud bump to make an electrical connection. However, since the stud bump has an onion shape and a large variation in height, when an interlayer insulating layer is formed, the smoothness is reduced, and even if a via hole is formed, the stud bump is easily disconnected. Further, the stud bumps are planted one by one by bonding, so that they cannot be arranged collectively, and there is a problem in terms of productivity.

Japanese Patent Laid-Open No. Hei 10-256429 discloses a structure in which a semiconductor element is housed in a ceramic substrate and is electrically connected in a flip-chip form. However, ceramic has poor external formability, and the semiconductor element is not easily accommodated. In addition, the bumps had large variations in height. Therefore, the smoothness of the interlayer insulating layer is impaired, and the connection is reduced.

Japanese Patent Application Laid-Open No. 11-126978 discloses a multilayer printed wiring board in which electronic components such as a semiconductor element are embedded in a space accommodating portion, connected to a conductor circuit, and stored through via holes. ing. However, since the accommodating portion is an air gap, it is easy to cause a positional shift and disconnection to a pad of the semiconductor element is apt to occur. Further, since the die pad and the conductor circuit are directly connected, there is a problem that an oxide film is easily formed on the die pad and the insulation resistance is increased.

[0009]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a method for manufacturing a multilayer printed wiring board incorporating a highly reliable semiconductor element. The purpose is to propose.

[0010]

Means for Solving the Problems As a result of intensive studies, the present inventor has created a method of forming a transition layer on a die pad of a semiconductor device. Even if the semiconductor element having the transition layer is housed in a printed wiring board,
Even if an interlayer insulating layer is formed thereon and a via hole is formed, a desired size and shape can be obtained.

The reason why the transition layer is provided on the die pad of the IC chip will be described. The pads of the IC chip are generally made of aluminum or the like. When via holes in the interlayer insulating layer were formed by photoetching with the die pad having no transition layer formed thereon, the resin was likely to remain on the surface of the pad after exposure and development if the die pad was still formed. In addition, the adhesion of the developing solution caused discoloration of the pad. On the other hand, even when a via hole was formed by a laser, if the process was performed under the condition that the die pad was not burnt, resin residue was left on the pad. Further, in a later step, when the substrate was immersed in an acid, an oxidizing agent, or an etching solution, or passed through various annealing steps, discoloration and dissolution of the IC chip pad occurred. Further, the pad of the IC chip is made with a diameter of about 40 μm, and the via hole is larger than that, so that disconnection is likely to occur at the time of displacement.

On the other hand, by providing a transition layer made of copper or the like on the die pad, it becomes possible to use a solvent and prevent resin residue on the pad. Also,
No discoloration or dissolution of the pad occurs even when the pad is immersed in an acid, an oxidizing agent, or an etching solution in a later step, or undergoes various annealing steps. This improves the connectivity and reliability between the pad and the via hole. Further, the via hole can be reliably connected by interposing a transition layer having a diameter larger than 40 μm on the pad of the IC chip. Desirably, the transition layer has a diameter equal to or greater than the diameter of the via hole.

Further, since the transition layer is formed, the operation and electrical inspection of the semiconductor element can be easily performed before or after the semiconductor element is housed in the printed wiring board. This is because a transition layer larger than the die pad is formed, so that the probe pins are easily brought into contact. As a result, the availability of the product can be determined in advance, and productivity and cost can be improved.

Therefore, by forming the transition layer, the semiconductor element can be suitably accommodated in the printed wiring. That is, it can be said that a semiconductor element having a transition layer is a semiconductor element to be embedded in a printed wiring board. The transition layer is formed by forming a thin film layer on a die pad and forming a thick layer thereon. It can be formed of at least two layers.

The transition layer defined in the present invention will be described. The transition layer means an intermediate mediation layer provided for directly connecting an IC chip as a semiconductor element and a printed wiring board without using a conventional IC chip mounting technique. It is characterized in that it is formed of two or more metal layers and is larger than a die pad of an IC chip as a semiconductor element. Thereby, electrical connection and alignment are improved, and via holes can be formed by laser or photoetching without damaging the die pad. Therefore, embedding, accommodation, accommodation, and connection of the IC chip in the printed wiring board can be ensured. In addition, it is possible to directly form a metal which is a conductor layer of a printed wiring board on the transition layer.
Examples of the conductor layer include via holes in an interlayer resin insulating layer and through holes on a substrate.

Although each of them functions only by a multilayer printed wiring board, in some cases, the connection to an external board such as a motherboard or a daughter board is required for the function as a package board as a semiconductor device.
GAs, solder bumps or PGAs (conductive connection pins) may be provided. In addition, with this configuration, the wiring length can be made shorter than in the case where the connection is made by the conventional mounting method, and the loop inductance can be reduced.

The resin substrate for incorporating electronic components such as an IC chip used in the present invention is a resin in which a reinforcing material such as a glass epoxy resin or a core material is impregnated with an epoxy resin, a BT resin, a phenol resin or the like, or an epoxy resin. A laminate of prepregs impregnated with is used, but those generally used for printed wiring boards can be used. In addition, a double-sided copper-clad laminate, a single-sided plate, a resin plate having no metal film, and a resin sheet can be used. However, if a temperature of 350 ° C. or more is applied, the resin will melt and carbonize.

A conductive metal film is formed on the entire surface of the IC chip by physical vapor deposition such as evaporation or sputtering. The metals include tin, chrome, titanium,
It is preferable to form one or more layers of a metal such as nickel, zinc, cobalt, gold, and copper. As the thickness, 0.001 to
It is preferable to form it between 2.0 μm. In particular, 0.01
It is desirable to form it between 0.1 μm and 0.1 μm. In particular, it is preferable to use nickel, chromium, or titanium. This is because there is no penetration of moisture from the interface and the metal adhesion is excellent.

A metal film may be further provided on the metal film by electroless plating or the like. The upper metal film is preferably formed by forming one or more layers of a metal such as nickel, copper, gold, and silver.

The metal film is thickened by electroless or electrolytic plating. Types of plating to be formed include nickel, copper, gold, silver, zinc, and iron. It is preferable to use copper because the electrical characteristics, economy, and the conductor layer, which is a build-up formed later, are mainly copper. The thickness is preferably in the range of 1 to 20 μm.
If the thickness is larger than that, an undercut occurs at the time of etching, and a gap may be generated at the interface between the formed transition layer and the via hole. afterwards,
An etching resist is formed, exposed and developed to expose portions of the metal other than the transition layer, and etching is performed to form a transition layer on the pads of the IC chip.

In addition to the above-described method for manufacturing a transition layer, a dry film resist is formed on a metal film formed on an IC chip and a core substrate, and a portion corresponding to the transition layer is removed. After thickening, the resist can be peeled off, and a transition layer can be similarly formed on the pad of the IC chip using an etching solution.

In the present invention, the insulating resin substrate accommodated in the through hole of the IC chip and the insulating resin substrate are laminated with a sheet impregnated with the resin interposed therebetween, and are pressed from above and below. The epoxy resin exudes from the sheet and covers the upper surface of the IC chip. Thereby, the upper surfaces of the IC chip and the insulating resin substrate become completely flat. For this reason, when forming the build-up layer, via holes and wiring can be appropriately formed, and the reliability of wiring of the multilayer printed wiring board can be improved.

It is preferable that the pressing of the core substrate and the resin plate is performed under reduced pressure. By reducing the pressure, no air bubbles remain between the core substrate and the resin plate and in the resin plate, and the reliability of the multilayer printed wiring board can be improved. Furthermore, by performing the curing of the resin plate under reduced pressure, no bubbles remain in the resin plate, and the reliability of the multilayer printed wiring board can be improved. It is also preferable to provide a taper in the through hole formed in the core substrate. This allows
No air bubbles remain between the core substrate and the resin plate,
The reliability of the multilayer printed wiring board can be improved.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. A. Semiconductor Device First, with respect to the configuration of the semiconductor device (IC chip) according to the first embodiment of the present invention, FIG.
This will be described with reference to FIG. 4A and FIG.

[First Embodiment] As shown in FIG. 3B, a die pad 22 and a wiring (not shown) are provided on the upper surface of the semiconductor element 20, and the die pad 22 and the wiring are provided on the die pad 22 and the wiring. , A passivation film 24 is covered, and an opening of the passivation film 24 is formed in the die pad 22. On the die pad 22, a transition layer 38 mainly made of copper is formed. The transition layer 38 includes a thin film layer 33 and an electrolytic plating film 37.

Next, a method of manufacturing the semiconductor device described above with reference to FIG. 3B will be described with reference to FIGS.

(1) First, a wiring 21 and a die pad 2 are formed on a silicon wafer 20A shown in FIG.
2 (see FIG. 1A and FIG. 4A which shows a plan view of FIG. 1B, and FIG. 1B shows a cross section taken along line BB of FIG. 4A). There). (2) Next, a passivation film 24 is formed on the die pad 22 and the wiring 21, and an opening 24a is provided on the die pad 22 (FIG. 1C).

(3) Physical vapor deposition such as vapor deposition and sputtering is performed on the silicon wafer 20A to form a conductive metal film (thin film layer) 33 on the entire surface (FIG. 2A).
The thickness is preferably in the range of 0.001 to 2.0 μm. If it is below the range, a thin film layer cannot be formed on the entire surface. If it is higher than this range, the thickness of the formed film will vary. The optimal range is from 0.01 to 1.0 μm. As a metal to be formed, a metal selected from tin, chromium, titanium, nickel, zinc, cobalt, gold, and copper is preferably used. These metals serve as a protective film for the die pad and do not degrade the electrical characteristics. In the first embodiment, the thin film layer 33 is formed of chromium.

(4) Thereafter, a resist layer of any of a liquid resist, a photosensitive resist, and a dry film is formed on the thin film layer 33. A mask (not shown) on which a portion for forming the transition layer 38 is drawn is placed on the resist layer, and through exposure and development, a non-formed portion 35a is formed in the resist 35. Electroplating is performed to provide a thick layer (electrolytic plating film) 37 on the non-formed portion 35a of the resist layer (FIG. 2B). Examples of the type of plating formed include copper, nickel, gold, silver, zinc, and iron. Electrical properties, economics, and because the conductor layer that is a build-up formed later is mainly copper, it is better to use copper,
In the first embodiment, copper is used. Its thickness is 1-20 μm
It is better to perform within the range.

(5) After the plating resist 35 is removed with an alkaline solution or the like, the metal film 33 under the plating resist 35 is coated with sulfuric acid-hydrogen peroxide, ferric chloride, cupric chloride, cupric complex-organic. By removing with an etching solution such as an acid salt, the transition layer 38 is formed on the pad 22 of the IC chip.
Is formed (FIG. 2C).

(6) Next, a roughened surface 38α is formed by spraying an etching solution onto the substrate by spraying and etching the surface of the transition layer 38 (FIG. 3A).
reference).

(7) Finally, the silicon wafer 20A on which the transition layer 38 is formed is divided into individual pieces by dicing or the like to form the semiconductor elements 20 (FIG. 3).
(B) and FIG. 4 (B) which is a plan view of FIG. 3 (B)). Then, if necessary, the divided semiconductor elements 2
An operation check of 0 or an electrical inspection may be performed. Since the semiconductor element 20 has the transition layer 38 larger than the die pad 22, the probe pins can be easily applied to the semiconductor element 20, and the inspection accuracy is high.

[Second Embodiment] A semiconductor device 20 according to a second embodiment will be described with reference to FIG. FIG.
In the semiconductor device according to the first embodiment described with reference to FIG. 3B, the transition layer 38 has a two-layer structure including the thin film layer 33 and the electrolytic plating film 37. On the contrary,
In the second embodiment, as shown in FIG. 7B, the transition layer 38 includes a thin film layer 33, an electroless plating film 36,
It has a three-layer structure composed of an electrolytic plating film 37.

Next, the method of manufacturing a semiconductor device according to the second embodiment described above with reference to FIG.
This will be described with reference to FIGS.

(1) First, the wiring 21 and the die pad 22 are formed on the silicon wafer 20A shown in FIG. 5A (FIG. 5B). (2) Next, a passivation film 24 is formed on the die pad 22 and the wiring (FIG. 5C).

(3) Physical vapor deposition such as vapor deposition and sputtering is performed on the silicon wafer 20A to form a conductive metal film (first thin film layer) 33 on the entire surface (FIG. 5).
(D)). The thickness is preferably formed in the range of 0.001 to 2 μm. If it is below the range, a thin film layer cannot be formed on the entire surface. If it is higher than this range, the thickness of the formed film will vary. The optimal range is from 0.01 to 1.0 μm. As a metal to be formed, a metal selected from tin, chromium, titanium, nickel, zinc, cobalt, gold, and copper is preferably used. These metals serve as a protective film for the die pad and do not degrade the electrical characteristics. In the second embodiment, the first thin film layer 33 is formed of chromium.

(4) Sputtering on the first thin film layer 33
An electroless plating layer (second thin film layer) 36 is laminated by vapor deposition and electroless plating (FIG. 6A). Its thickness is 0.
The thickness is preferably from 0.1 to 5 μm, particularly preferably from 0.1 to 3.0 μm. In this case, the metal that can be laminated is preferably selected from nickel, copper, gold, and silver. In particular, it is good to form with either copper or nickel. Copper is inexpensive and has good electrical conductivity. Nickel has good adhesion to a thin film and is unlikely to cause peeling or cracking. Second
In the embodiment, the second thin film layer 36 is formed by electroless copper plating. Note that a desirable combination of the first thin film layer and the second thin film layer is chromium-copper, chromium-nickel, titanium-
Copper and titanium-nickel. It is superior to other combinations in terms of bonding to metals and electrical conductivity.

(5) Then, a resist layer is formed on the second thin film layer 3
6 is formed. A mask (not shown) is placed on the resist layer, and a non-formed portion 35a is formed on the resist 35 through exposure and development. Electroplating is performed to provide a thick layer (electrolytic plating film) 37 in the non-formed portion 35a of the resist layer (FIG. 6B). Examples of the type of plating formed include copper, nickel, gold, silver, zinc, and iron. Electrical properties, economics, and because the conductor layer that is a build-up formed later is mainly copper, it is better to use copper,
In the second embodiment, copper is used. The thickness is preferably in the range of 1 to 20 μm.

(6) After the plating resist 35 is removed with an alkaline solution or the like, the electroless plating film 36 and the metal film 33 under the plating resist 35 are removed by using sulfuric acid-hydrogen peroxide solution, ferric chloride, cupric chloride, The transition layer 38 is formed on the pad 22 of the IC chip by removing the copper oxide complex with an etching solution such as an organic acid salt (FIG. 6C).

(7) Next, an etching solution is sprayed on the substrate by spraying, and the surface of the transition layer 38 is etched to form a roughened surface 38α (FIG. 7A).
reference).

(8) Finally, the silicon wafer 20A on which the transition layer 38 is formed is divided into individual pieces by dicing or the like to form the semiconductor elements 20 (FIG. 7).
(B)).

[Third Embodiment] A method of manufacturing a semiconductor device 20 according to a third embodiment will be described with reference to FIG. Third
The configuration of the semiconductor element of this embodiment is almost the same as that of the first embodiment described above with reference to FIG. However, in the first embodiment, the transition layer 38 was formed by forming the thickening layer 37 in the non-resist forming portion using a semi-additive process. On the other hand, in the third embodiment, a transition layer 38 is formed by forming a thick layer 37 uniformly using a full additive process, providing a resist, and removing the non-resist-formed portion by etching.

The manufacturing method of the third embodiment will be described with reference to FIG. (1) As described above with reference to FIG. 2B in the first embodiment, physical vapor deposition such as vapor deposition or sputtering is performed on the silicon wafer 20A to form a conductive metal film 33 on the entire surface ( FIG. 8 (A)). The thickness is 0.001
A range of 2.0 μm is preferable. If it is below that range,
A thin film layer cannot be formed on the entire surface. If it is higher than this range, the thickness of the formed film will vary. The optimum range is preferably formed in the range of 0.01 to 1.0 μm. Metals to be formed include tin, chromium,
From titanium, nickel, zinc, cobalt, gold and copper,
It is good to use what is chosen. These metals serve as a protective film for the die pad and do not degrade the electrical characteristics. In the third embodiment, the thin film layer 33 is formed of chromium.

(2) A thick layer (electrolytic plating film) 37 is uniformly provided on the thin film layer 33 by electrolytic plating (FIG. 8).
(B)). Examples of the type of plating formed include copper, nickel, gold, silver, zinc, and iron. Electrical properties, economics,
Further, since the conductor layer to be formed later is mainly made of copper, it is preferable to use copper. In the third embodiment, copper is used. The thickness is preferably in the range of 1 to 20 μm. If the thickness is larger than that, an undercut occurs during the etching described later, and a gap may be generated at the interface between the formed transition layer and the via hole.

(3) Thereafter, a resist layer 35 is formed on the thick layer 37 (FIG. 8C).

(4) The metal film 3 in the portion where the resist 35 is not formed
3 and the thickening layer 37 are removed with an etching solution such as sulfuric acid-hydrogen peroxide solution, ferric chloride, cupric chloride, cupric complex-organic acid salt, and the resist 35 is peeled off to remove the IC. A transition layer 38 on the chip pads 22
Is formed (FIG. 8D). Subsequent steps are the same as in the first embodiment, and a description thereof will not be repeated.

[Fourth Embodiment] A method of manufacturing a semiconductor device 20 according to a fourth embodiment will be described with reference to FIG. In the semiconductor device according to the third embodiment described above with reference to FIG. 8, the transition layer 38 has a two-layer structure including the thin film layer 33 and the electrolytic plating film 37. On the other hand, in the fourth embodiment, as shown in FIG. 9D, the transition layer 38 has a three-layer structure including the thin film layer 33, the electroless plating film 36, and the electrolytic plating film 37. Have been.

The manufacturing method of the fourth embodiment will be described with reference to FIG. (1) The second embodiment described above with reference to FIG.
Similarly to the embodiment, a second thin film layer 36 is laminated on the first thin film layer 33 by sputtering, vapor deposition, and electroless plating (FIG. 9A). The thickness is preferably 0.01 to 5 μm, and particularly preferably 0.1 to 3.0 μm. In this case, the metal that can be laminated is preferably selected from nickel, copper, gold, and silver. In particular, it is good to form with either copper or nickel. Copper is inexpensive and has good electrical conductivity. Nickel has good adhesion to a thin film and is unlikely to cause peeling or cracking. In the fourth embodiment, the second
The thin film layer 36 is formed by electroless copper plating. Desirable combinations of the first thin film layer and the second thin film layer are chromium-copper, chromium-nickel, titanium-copper, and titanium-nickel. It is superior to other combinations in terms of bonding to metals and electrical conductivity.

(2) The second thin film layer 36 is formed by electrolytic plating.
A thick layer (electrolytic plating film) 37 is uniformly provided on the substrate (FIG. 9B). The type of plating to be formed is copper,
Nickel, gold, silver, zinc, iron and the like. Its thickness is 1
It is preferable to carry out in the range of up to 20 μm.

(3) Thereafter, a resist layer 35 is formed on the thick layer 37 (FIG. 9C).

(4) The first thin film layer 33, the second thin film layer 36, and the thickening layer 37 where the resist 35 is not formed are formed by using sulfuric acid-hydrogen peroxide solution, ferric chloride, cupric chloride, and cupric copper. After removal with an etchant such as a complex-organic acid salt, the resist 3
By peeling 5, a transition layer 38 is formed on the pads 22 of the IC chip (FIG. 9D). Subsequent steps are the same as in the first embodiment, and a description thereof will not be repeated.

B. Multilayer Printed Wiring Board Incorporating Semiconductor Element Subsequently, the semiconductor element (I
The configuration of the multilayer printed wiring board in which the (C chip) 20 is housed in the through hole of the core substrate will be described. [First Embodiment] A multilayer printed wiring board 1 as shown in FIG.
0 denotes the IC of the first embodiment described above with reference to FIG.
It comprises a core substrate 30 for accommodating the chip 20, an interlayer resin insulation layer 50, and an interlayer resin insulation layer 150. Via holes 60 and conductive circuits 58 are formed in interlayer resin insulation layer 50, and via holes 16 and conductor circuits 58 are formed in interlayer resin insulation layer 150.
0 and a conductor circuit 158 are formed.

On the interlayer resin insulation layer 150, a solder resist layer 70 is provided. The conductor circuit 158 below the opening 71 of the solder resist layer 70 is provided with a solder bump 76 for connecting to an external board (not shown) such as a daughter board or a mother board.

In the multilayer printed wiring board 10 of this embodiment,
The IC chip 20 is built in the core substrate 30, and a transition layer 38 is provided on the pad 22 of the IC chip 20. Therefore, the electrical connection between the IC chip and the multilayer printed wiring board (package substrate) can be established without using a lead component or a sealing resin. Further, since the transition layer 38 is formed in the IC chip portion, the IC chip portion is flattened, so that the upper interlayer insulating layer 50 is also flattened and the film thickness becomes uniform. Further, the transition layer allows the upper via hole 6 to be formed.
Even when 0 is formed, the stability of the shape can be maintained.

Further, by providing the copper transition layer 38 on the die pad 22, resin residue on the pad 22 can be prevented. Also, in a later step, the resin can be immersed in an acid, an oxidizing agent, an etching solution, or the like. Discoloration and dissolution of the pad 22 do not occur even after various annealing processes. This improves the connectivity and reliability between the pads of the IC chip and the via holes. Further, by interposing the transition layer 38 having a diameter of 60 μm or more on the pad 22 having a diameter of 40 μm, a via hole having a diameter of 60 μm can be reliably connected.

Next, a method of manufacturing the multilayer printed wiring board described above with reference to FIG. 14 will be described with reference to FIGS.

(1) A 0.5 mm thick insulating resin substrate 30A obtained by laminating a prepreg impregnated with a resin such as BT (bismaleimide triazine) resin or epoxy on a core material such as glass cloth and curing the resin is used as a starting material. I do. First, a through hole 32 for accommodating an IC chip is formed in the insulating resin substrate 30A (see FIG. 10A). Here, the resin substrate 30A in which the core material is impregnated with the resin is used, but a resin substrate having no core material may be used. In addition, it is preferable to provide a taper 32 a at the lower end opening of the through hole 32. Due to the taper 32a, no bubbles remain between the IC chip 20, the insulating resin substrate 30A, the prepreg 30C, and the resin substrate 30B in a laminating step described later, and the reliability of the multilayer printed wiring board can be improved.

(2) Then, the first, second, third, or fourth embodiment described above with reference to FIG. 3B is inserted into the through hole 32 of the insulating resin substrate 30A. (See FIG. 10B).

(3) The insulating resin substrate 30A for accommodating the IC chip 20 and a prepreg impregnated with a core material such as glass cloth or a resin such as BT or epoxy are cured and cured to a thickness of 0%. .2 mm insulating resin substrate (core substrate) 30B and an uncured prepreg 30C in which a core material such as glass cloth is impregnated with a resin such as epoxy.
(Thickness: 0.1 mm)
(C)). Here, the resin substrate 30B in which the core material is impregnated with the resin is used, but a resin substrate having no core material may be used. Further, instead of the prepreg, various thermosetting resins or a sheet obtained by impregnating a core material with a thermosetting resin and a thermoplastic resin can be used.

(4) Stainless steel (SUS) press plate 10
At 0A and 100B, the above-described laminate is pressed from above and below. At this time, the epoxy resin 3 is removed from the prepreg 30C.
Oα exudes and fills the space between the through hole 32 and the IC chip 20 and covers the upper surface of the IC chip 20. Thereby, the upper surfaces of the IC chip 20 and the insulating resin substrate 30A become completely flat. (FIG. 10 (D)). For this reason, when forming the build-up layer in a step described later, the via hole and the wiring can be appropriately formed, and the reliability of the wiring of the multilayer printed wiring board can be improved.
The pressure and / or temporary curing is preferably performed under reduced pressure. By reducing the pressure, the IC chip 20, the insulating resin substrate 3
0A, between the prepreg 30C and the resin substrate 30B, and
No air bubbles remain in the prepreg 30C, and the reliability of the multilayer printed wiring board can be improved.

(5) Thereafter, the core substrate 30 accommodating the IC chip 20 is formed by heating and curing the uncured epoxy resin 30α (FIG. 10E). This main curing is preferably performed under reduced pressure. By reducing the pressure, no bubbles remain in the prepreg 30C,
The reliability of the multilayer printed wiring board can be improved.

(6) A substrate having a thickness of 50 μm
m of a thermosetting epoxy resin sheet at a temperature of 50-150.
Vacuum compression lamination at a pressure of 5 kg / cm ² while raising the temperature to 50 ° C.
(See FIG. 11A). The degree of vacuum during vacuum compression is 10 mmHg.

(7) Next, using a CO ₂ gas laser having a wavelength of 10.4 μm, a beam diameter of 5 mm, a top hat mode,
Under the conditions of a pulse width of 5.0 μsec, a mask hole diameter of 0.5 mm, and one shot, a via hole opening 48 having a diameter of 60 μm is provided in the interlayer resin insulating layer 50 (see FIG. 11B).
The resin residue in the opening 48 is removed using chromic acid or permanganic acid. By providing the copper transition layer 38 on the die pad 22, resin residue on the pad 22 can be prevented, thereby improving the connectivity and reliability between the pad 22 and via holes 60 described later. Furthermore,
By interposing the transition layer 38 having a diameter of 60 μm or more on the pad 22 having a diameter of 40 μm, the opening 48 for a via hole having a diameter of 60 μm can be reliably connected. Here, the resin residue is removed using chromic acid, but desmearing can be performed using oxygen plasma.

(8) Next, the surface of the interlayer resin insulating layer 50 is roughened with permanganic acid to form a roughened surface 50α (FIG. 1).
1 (C)).

(9) Next, an electroless plating film 52 is provided on the interlayer resin insulating layer 50 on which the roughened surface 50α is formed (see FIG. 12A). Copper and nickel can be used as the electroless plating. The thickness is 0.3μ
The range is preferably from m to 1.2 μm. If it is less than 0.3 μm, it may not be possible to form a metal film on the interlayer resin insulation layer. If the thickness exceeds 1.2 μm, the metal film remains due to the etching, and a short circuit between conductors is easily caused. A plating film was formed under the following plating solution and plating conditions. [Electroless plating aqueous solution] NiSO ₄ 0.003 mol / l tartaric acid 0.200 mol / l copper sulfate 0.030 mol / l HCHO 0.050 mol / l NaOH 0.100 mol / l α, α'-bipyryl 100 mg / l Polyethylene glycol (PEG) 0.10 g / l [Electroless Plating Condition] Dipped at a liquid temperature of 34 ° C. for 40 minutes.

Other than the above, using the same apparatus as in the above-described plasma processing, sputtering using a Ni—Cu alloy as a target was performed at a pressure of 0.6 Pa, a temperature of 80 ° C., and a power of 200
The process is performed under the condition of W for 5 minutes to form a Ni—Cu alloy 52 on the surface of the interlayer resin insulating layer 50. At this time, the thickness of the formed Ni—Cu alloy layer 52 is 0.2 μm.

(10) A commercially available photosensitive dry film is affixed to the substrate 30 that has been subjected to the above processing, a photomask film is placed thereon, and after exposure at 100 mJ / cm ² ,
Develop with 0.8% sodium carbonate to provide a plating resist 54 having a thickness of 18 μm. Next, electrolytic plating is performed under the following conditions to form an electrolytic plating film 56 having a thickness of 15 μm (see FIG. 12B). The additive in the electrolytic plating aqueous solution was Capparaside H manufactured by Atotech Japan.
L.

[Aqueous electrolytic plating solution] Sulfuric acid 2.24 mol / l Copper sulfate 0.26 mol / l Additive (manufactured by Atotech Japan, Capparaside HL) 19.5 ml / l [Electroplating conditions] Current density 1 A / dm ² Time 65 minutes Temperature 22 ± 2 ℃

(11) The plating resist 54 is made of 5% NaO
After removing with H, the plating film layer 52 under the plating resist is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide, and a thickness of 16 μm comprising the plating film layer 52 and the electrolytic plating film 56 is formed. Are formed, and roughened surfaces 58α and 60α are formed with an etchant containing a cupric complex and an organic acid (see FIG. 12C). In this embodiment, FIG.
As described above with reference to (E), since the upper surface of the core substrate 30 is formed completely smooth, the via hole 60
Accordingly, the connection to the transition layer 38 can be appropriately established. For this reason, it is possible to improve the reliability of the multilayer printed wiring board.

(12) Then, the above steps (6) to (11) are repeated to form an upper interlayer resin insulation layer 150 and a conductor circuit 158 (including via holes 160) (FIG. 13 ( A)).

(13) Next, a cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) so as to have a concentration of 60% by weight was used. Oligomer for imparting properties (molecular weight 4000) 46.67
15 parts by weight of a bisphenol A type epoxy resin (trade name: Epicoat 1001 manufactured by Yuka Shell Co., Ltd.) of 80% by weight dissolved in methyl ethyl ketone, imidazole hardener (trade name: 2E4MZ-CN)
1.6 parts by weight, 3 parts by weight of a polyfunctional acrylic monomer (manufactured by Kyoei Chemical Co., trade name: R604) as a photosensitive monomer,
Similarly, polyvalent acrylic monomer (manufactured by Kyoei Chemical Co., Ltd., trade name:
1.5 parts by weight of DPE6A) and 0.71 part by weight of a dispersant antifoaming agent (manufactured by San Nopco, trade name: S-65) are placed in a container, stirred and mixed to prepare a mixed composition. Of benzophenone (manufactured by Kanto Kagaku) and 0.2 parts by weight of Michler's ketone (manufactured by Kanto Kagaku) as a photosensitizer were added to give a viscosity of 25.
A solder resist composition (organic resin insulating material) adjusted to 2.0 Pa · s at ° C is obtained. The viscosity was measured using a B-type viscometer (DVL-B type, manufactured by Tokyo Keiki Co., Ltd.) at 60 rpm and rotor No. 4 at 6 rpm.
According to

(14) Next, the above-mentioned solder resist composition is applied to the substrate 30 at a thickness of 20 μm,
After performing a drying process at 70 ° C. for 30 minutes for 0 minute, a 5 mm-thick photomask on which a pattern of the opening of the solder resist resist is drawn is brought into close contact with the solder resist layer 70, and an ultraviolet ray of 1000 mJ / cm ² is applied. And developing with a DMTG solution to form an opening 71 having a diameter of 200 μm (see FIG. 13B).

(15) Next, the substrate on which the solder resist layer (organic resin insulating layer) 70 was formed was replaced with nickel chloride (2.3 × 10 ⁻¹ mol / l) and sodium hypophosphite (2.8 × 10 ^-1 mol / l) and an electroless nickel plating solution having a pH of 4.5 containing sodium citrate (1.6 × 10 ^-1 mol / l) for 20 minutes.
Then, a nickel plating layer 72 having a thickness of 5 μm is formed. Further, the substrate was subjected to potassium gold cyanide (7.6 × 10 ^−3).
mol / l), ammonium chloride (1.9 × 10 ^-1 mo)
1 / l), sodium citrate (1.2 × 10 ^-1 mol)
/ L), sodium hypophosphite (1.7 × 10 ^-1 mol)
/ L) is immersed for 7.5 minutes at 80 ° C. in an electroless plating solution containing
By forming the gold plating layer 74 of the length m, the conductor circuit 158 can be formed.
Then, a solder pad 75 is formed (see FIG. 13C).

(16) Thereafter, the solder resist layer 70
The solder paste is printed on the opening 71 of
To form the solder bumps 76. Thereby, the multilayer printed wiring board 10 having the IC chip 20 built-in and having the solder bumps 76 can be obtained (see FIG. 14).

In the above embodiment, the interlayer resin insulation layer 5
A thermosetting epoxy resin sheet was used for Nos. 0 and 150.
This epoxy resin contains a hardly soluble resin, soluble particles, a curing agent, and other components. Each is described below.

The epoxy resin used in the production method of the present invention comprises particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble particles”) in a resin which is hardly soluble in an acid or an oxidizing agent (hereinafter referred to as a “slightly soluble resin”). It is distributed in. The terms "sparingly soluble" and "soluble" used in the present invention are referred to as "soluble" for convenience when those immersed in a solution comprising the same acid or oxidizing agent for the same time have a relatively high dissolution rate. Those having a relatively low dissolution rate are referred to as "poorly soluble" for convenience.

Examples of the soluble particles include resin particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble resin particles”), inorganic particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble inorganic particles”), and an acid or an oxidizing agent. Soluble metal particles (hereinafter referred to as “soluble metal particles”) and the like. These soluble particles may be used alone or in combination of two or more.

The shape of the soluble particles is not particularly limited.
Spherical, crushed and the like. The shape of the soluble particles is desirably a uniform shape. This is because a roughened surface having unevenness with a uniform roughness can be formed.

The average particle size of the above-mentioned soluble particles is 0.1.
1 to 10 μm is desirable. Within this particle size range, 2
More than one kind of particles having different particle sizes may be contained. That is, it contains soluble particles having an average particle size of 0.1 to 0.5 μm and soluble particles having an average particle size of 1 to 3 μm.
Thereby, a more complicated roughened surface can be formed,
Excellent adhesion to conductor circuits. In the present invention, the particle size of the soluble particles is the length of the longest portion of the soluble particles.

Examples of the soluble resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like. When immersed in a solution containing an acid or an oxidizing agent, the soluble resin particles have a higher dissolution rate than the hardly soluble resin. If it is, there is no particular limitation. Specific examples of the soluble resin particles include, for example, those made of epoxy resin, phenol resin, polyimide resin, polyphenylene resin, polyolefin resin, fluororesin, and the like, and may be made of one of these resins. Alternatively, it may be composed of a mixture of two or more resins.

Further, as the soluble resin particles, resin particles made of rubber can be used. Examples of the rubber include polybutadiene rubber, various modified polybutadiene rubbers such as epoxy-modified, urethane-modified, (meth) acrylonitrile-modified, and (meth) acrylonitrile-butadiene rubber containing a carboxyl group. By using these rubbers, the soluble resin particles are easily dissolved in an acid or an oxidizing agent. In other words, when dissolving the soluble resin particles using an acid, an acid other than a strong acid can be dissolved, and when dissolving the soluble resin particles using an oxidizing agent, permanganese having a relatively weak oxidizing power is used. Acid salts can also be dissolved. Even when chromic acid is used, it can be dissolved at a low concentration. Therefore, the acid or the oxidizing agent does not remain on the resin surface, and as described later, when a catalyst such as palladium chloride is applied after forming the roughened surface, the catalyst is not applied or the catalyst is oxidized. Or not.

Examples of the soluble inorganic particles include particles made of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds and silicon compounds.

Examples of the aluminum compound include alumina and aluminum hydroxide. Examples of the calcium compound include calcium carbonate and
Examples of the potassium compound include potassium carbonate.Examples of the magnesium compound include magnesia, dolomite, and basic magnesium carbonate.Examples of the silicon compound include silica and zeolite. Is mentioned. These may be used alone or in combination of two or more.

The soluble metal particles include, for example,
Copper, nickel, iron, zinc, lead, gold, silver, aluminum,
Examples include particles made of at least one selected from the group consisting of magnesium, calcium, and silicon. These soluble metal particles may have a surface layer coated with a resin or the like in order to ensure insulation.

When two or more of the above-mentioned soluble particles are used in combination, the combination of the two types of soluble particles to be mixed is preferably a combination of resin particles and inorganic particles. Both have low conductivity, so that the insulation of the resin sheet can be ensured, and the thermal expansion can be easily adjusted with the poorly soluble resin, and no crack occurs in the interlayer resin insulation layer made of the resin sheet. This is because peeling does not occur between the interlayer resin insulating layer and the conductor circuit.

The hardly soluble resin is not particularly limited as long as it can maintain the shape of the roughened surface when the roughened surface is formed by using an acid or an oxidizing agent in the interlayer resin insulating layer. Examples thereof include thermosetting resins, thermoplastic resins, and composites thereof. Further, a photosensitive resin obtained by imparting photosensitivity to these resins may be used. By using a photosensitive resin, an opening for a via hole can be formed in an interlayer resin insulating layer by using exposure and development processes. Among these, those containing a thermosetting resin are desirable. Thereby, the shape of the roughened surface can be maintained even by the plating solution or various heat treatments.

Specific examples of the hardly soluble resin include, for example, epoxy resin, phenol resin, phenoxy resin,
Examples thereof include a polyimide resin, a polyphenylene resin, a polyolefin resin, and a fluorine resin. These resins may be used alone or in combination of two or more. Further, an epoxy resin having two or more epoxy groups in one molecule is more desirable. Not only can the above-described roughened surface be formed, but also excellent in heat resistance, etc., even under heat cycle conditions, stress concentration does not occur in the metal layer, and peeling of the metal layer does not easily occur. Because.

Examples of the epoxy resin include cresol novolak epoxy resin, bisphenol A epoxy resin, bisphenol F epoxy resin, phenol novolak epoxy resin, alkylphenol novolak epoxy resin, biphenol F epoxy resin, and naphthalene epoxy resin. Resin, dicyclopentadiene type epoxy resin, epoxidized product of condensate of phenols and aromatic aldehyde having phenolic hydroxyl group,
Triglycidyl isocyanurate, alicyclic epoxy resin and the like. These may be used alone or in combination of two or more. Thereby, it becomes excellent in heat resistance and the like.

In the resin sheet used in the present invention, it is preferable that the soluble particles are substantially uniformly dispersed in the hardly-soluble resin. It is possible to form a roughened surface with unevenness of uniform roughness, and even if via holes and through holes are formed in the resin sheet, it is possible to secure the adhesion of the metal layer of the conductor circuit formed thereon. Because you can.
Alternatively, a resin sheet containing soluble particles only in the surface layer forming the roughened surface may be used. Thereby, since the portions other than the surface layer of the resin sheet are not exposed to the acid or the oxidizing agent, the insulation between the conductor circuits via the interlayer resin insulating layer is reliably maintained.

In the resin sheet, the amount of the soluble particles dispersed in the poorly soluble resin is preferably 3 to 40% by weight based on the resin sheet. If the amount of the soluble particles is less than 3% by weight, a roughened surface having desired irregularities may not be formed.
When the soluble particles are dissolved using an acid or an oxidizing agent, they dissolve to the deep part of the resin sheet, failing to maintain the insulation between the conductor circuits via the interlayer resin insulation layer made of the resin sheet, and causing a short circuit. It may be.

The resin sheet desirably contains a curing agent, other components, and the like in addition to the soluble particles and the hardly-soluble resin. Examples of the curing agent include imidazole-based curing agents, amine-based curing agents, guanidine-based curing agents, epoxy adducts of these curing agents and those obtained by microencapsulating these curing agents, triphenylphosphine, and tetraphenylphosphonate. Organic phosphine-based compounds such as ammonium tetraphenylborate.

The content of the curing agent is desirably 0.05 to 10% by weight based on the resin sheet. 0.0
If the content is less than 5% by weight, the resin sheet is insufficiently cured, so that the degree of penetration of acid or oxidizing agent into the resin sheet becomes large, and the insulating property of the resin sheet may be impaired. On the other hand, when the content exceeds 10% by weight, an excessive curing agent component may modify the composition of the resin, which may cause a decrease in reliability.

Examples of the other components include fillers such as inorganic compounds or resins which do not affect the formation of the roughened surface. As the inorganic compound, for example,
Examples of the resin include silica, alumina, and dolomite. Examples of the resin include a polyimide resin, a polyacryl resin, a polyamideimide resin, a polyphenylene resin, a melanin resin, and an olefin resin. By incorporating these fillers, the performance of the multilayer printed wiring board can be improved by matching thermal expansion coefficients, improving heat resistance and chemical resistance, and the like.

Further, the resin sheet may contain a solvent. Examples of the solvent include ketones such as acetone, methyl ethyl ketone and cyclohexanone, ethyl acetate, butyl acetate, aromatic hydrocarbons such as cellosolve acetate, toluene and xylene. These may be used alone or in combination of two or more. However, these interlayer resin insulation layers are dissolved and carbonized when a temperature of 350 ° C. or more is applied.

[Second Embodiment] Next, a multilayer printed wiring board according to a second embodiment of the present invention will be described with reference to FIG. In the first embodiment described above, the case where the BGA is provided has been described. The second embodiment is almost the same as the first embodiment, but is configured as a PGA system in which connection is made via conductive connection pins 96 as shown in FIG. In the first embodiment described above, the via holes are formed by laser, but in the second embodiment, the via holes are formed by photoetching.

A method for manufacturing a multilayer printed wiring board according to the second embodiment will be described with reference to FIG. (4) As in the first embodiment, (1)-(3) a 50 μm thick thermosetting epoxy resin 5
0 (see FIG. 15A).

(5) Next, the photomask film 49 on which the black circle 49a corresponding to the via hole formation position is drawn is placed on the interlayer resin insulation layer 50 and exposed (FIG. 15).
(B)).

(6) Spray development with a DMTG solution and heat treatment are performed to obtain a via hole opening 4 having a diameter of 85 μm.
8 is provided (FIG. 15C).
reference).

(7) The surface of the interlayer resin insulating layer 50 is roughened with permanganic acid or chromic acid to form a roughened surface 50α (see FIG. 15D). Subsequent steps are the same as those in the above-described first embodiment, and a description thereof will not be repeated.

[0100]

According to the structure of the present invention, the connection between the IC chip and the printed wiring board can be established without the intervention of a lead component. Therefore, resin sealing is not required. Furthermore, since there is no problem caused by lead components or sealing resin,
Connectivity and reliability are improved. Also, since the pad of the IC chip and the conductive layer of the printed wiring board are directly connected,
Electrical characteristics can also be improved. Furthermore, conventional IC
Compared with the chip mounting method, the wiring length from the IC chip to the substrate to the external substrate can be shortened, and the loop inductance can be reduced. Further, in the present invention, the insulating resin substrate accommodating the IC chip in the through hole and the insulating resin substrate
The layers are laminated with a resin-impregnated sheet interposed therebetween and pressed from above and below. The epoxy resin exudes from the sheet and covers the upper surface of the IC chip. Thereby, the upper surfaces of the IC chip and the insulating resin substrate become completely flat. For this reason, when forming the build-up layer, via holes and wiring can be appropriately formed, and the reliability of wiring of the multilayer printed wiring board can be improved.

[Brief description of the drawings]

FIGS. 1A, 1B, and 1C are manufacturing process diagrams of a semiconductor device according to a first embodiment of the present invention.

FIGS. 2A, 2B, and 2C are manufacturing process diagrams of a semiconductor device according to a first embodiment of the present invention.

FIGS. 3A and 3B are manufacturing process diagrams of the semiconductor device according to the first embodiment of the present invention.

FIG. 4A is a plan view of a silicon wafer according to a first embodiment of the present invention, and FIG. 4B is a plan view of a singulated semiconductor element.

FIGS. 5A, 5B, 5C, and 5D are manufacturing process diagrams of a semiconductor device according to a second embodiment of the present invention.

FIGS. 6A, 6B, and 6C are manufacturing process diagrams of a semiconductor device according to a second embodiment of the present invention.

FIGS. 7A and 7B are manufacturing process diagrams of a semiconductor device according to a second embodiment of the present invention.

FIGS. 8A, 8B, 8C, and 8D are manufacturing process diagrams of a semiconductor device according to a third embodiment of the present invention.

FIGS. 9A, 9B, 9C, and 9D are manufacturing process diagrams of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 10 (A), (B), (C), (D), (E)
FIG. 3 is a manufacturing process diagram of the multilayer printed wiring board according to the first embodiment of the present invention.

FIGS. 11A, 11B, and 11C are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

FIGS. 12A, 12B, and 12C are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

FIGS. 13A, 13B, and 13C are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 14 is a sectional view of the multilayer printed wiring board according to the first embodiment of the present invention.

FIGS. 15A, 15B, 15C, and 15D are manufacturing process diagrams of the multilayer printed wiring board according to the second embodiment of the present invention.

FIG. 16 is a sectional view of a multilayer printed wiring board according to a second embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 20 IC chip (semiconductor element) 22 die pad 24 passivation film 30 core substrate 32 through hole 36 resin layer 38 transition layer 50 interlayer resin insulation layer 58 conductive circuit 60 via hole 70 solder resist layer 76 solder bump 90 daughter board 96 conductive connection pin 97 Conductive adhesive 120 IC chip 150 Interlayer resin insulation layer 158 Conductor circuit 160 Via hole

Continued from the front page F-term (reference)

Claims (8)

[Claims] 1. A method for manufacturing a multilayer printed wiring board comprising at least the following steps (a) to (d): (a) a step of housing a semiconductor element in a through hole formed in a core substrate; (B) laminating a core substrate accommodating the semiconductor element and a resin plate with a sheet impregnated with uncured resin in a core material interposed therebetween; (c) pressing the core substrate and the resin plate; (D) forming a build-up layer on the upper surface of the core substrate; 2. A method for manufacturing a multilayer printed wiring board, comprising at least the following steps (a) to (e): (a) forming a transition layer on a die pad of a semiconductor element; (b) A) a step of housing the semiconductor element in a through hole formed in the core substrate; and (c) laminating the core substrate housing the semiconductor element and a resin plate with a sheet impregnating a core material with an uncured resin interposed therebetween. (D) a step of pressing the core substrate and the resin plate; and (e) a step of forming a build-up layer on the upper surface of the core substrate. 3. The method for manufacturing a multilayer printed wiring board according to claim 2, wherein the transition layer is formed through at least the following steps: (1) a step of forming a thin film layer on the entire surface of a semiconductor element; A step of forming a resist layer on the thin film layer and forming a thick layer on a portion where the resist layer is not formed; (3) a step of removing the resist layer: (4) a step of removing the thin film layer by etching. 4. The method for manufacturing a multilayer printed wiring board according to claim 2, wherein the transition layer is formed through at least the following steps: (1) a step of forming a thin film layer on the entire surface of a semiconductor element; A step of forming a thick layer on the entire surface of the thin film layer and forming a resist on the thick layer; (3) a step of removing the thick layer and the thin film layer in a non-resist-formed portion by etching; 4) Step of stripping the resist layer. 5. The method for manufacturing a multilayer printed wiring board according to claim 1, wherein said sheet is a prepreg. 6. The method for manufacturing a multilayer printed wiring board according to claim 1, wherein the pressing of the core substrate and the resin plate is performed under reduced pressure. 7. The method according to claim 1, wherein the curing of the resin plate is performed under reduced pressure. 8. The method according to claim 1, wherein the through hole formed in the core substrate is provided with a taper.
Of manufacturing a multilayer printed wiring board.