JP2001339008A - Wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board in which its connection terminals and the terminals of its built-in capacitor are easily connected to the terminals of electronic parts, and connection wirings connected between the connection terminals and the built-in capacitor can be reduced in inductance. SOLUTION: A wiring board 100 is equipped with a first and second solid conductor layers 126 and 127 between a first and second connection terminals 134a and 134b and the first and second potential-side surface terminals 115a and 115b, and the solid conductor layers 126 and 127 are each connected with a first and second primary surface-side via conductors 132a and 132b and a first and second capacitor-side via conductors 130 and 131.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a wiring board having a built-in chip capacitor.

[0002]

2. Description of the Related Art Advances in integrated circuit technology are increasing ICs
Although the operation of the chip has been accelerated, noise may be superimposed on power supply wiring and the like, which may cause a malfunction. Therefore, in order to remove noise, for example, as shown in FIG. 14, the main surface 2A of the wiring board 2 on which the IC chip 1 is mounted.
Alternatively, a chip capacitor 3 is separately mounted on the back surface 2 </ b> B, and capacitor connection wirings 4 respectively connected to two electrodes of the capacitor 3 are provided inside the wiring board 2. Thus, the chip capacitor 3 is connected to the IC chip 1 via the capacitor connection wiring 4 and the flip chip pad 5.

On the other hand, as a chip capacitor of a multilayer ceramic type, as shown in a chip capacitor 6 shown in FIG.
It is known that side electrodes 8a and 8b formed on a and 7b take out internal electrodes 9a and 9b, respectively. Recently, the capacitor 1 shown in FIG.
0, four side surfaces 11a,
11b, 11c, and 11d have side terminals 12a to 1 respectively.
There has also been proposed one in which 2j is formed and connected to the internal electrodes 13a and 13b as shown in FIG.
In some cases, the side surface terminals are not formed on the side surfaces 11b and 11d.

[0004]

However, when the chip capacitor 3 is mounted on the wiring board 2 as described above, an area for mounting the chip capacitor 3 on the main surface 2A or the rear surface 2B of the wiring board 2 is secured in advance. Need to be
The degree of freedom of mounting a reinforcing member for mounting another electronic component or reinforcing a wiring board is reduced. Further, the length of the capacitor connection wiring 4 connecting the IC chip 1 and the chip capacitor 3 is increased by being limited to other wirings and the like, and the resistance and inductance of the capacitor connection wiring 4 itself are large because they are easily thinned. It is difficult to meet the demand for low resistance and low inductance.

Therefore, it is conceivable to incorporate a chip capacitor in the wiring board. At this time, the number and interval of the terminals of the capacitor (for example, the side terminals 8a, 8b, 11a to 11j), and the connection terminals (for example, the flip chip pads 5) formed on the main surface which are connected to each terminal of the capacitor (that is, the flip chip pads 5) Since the numbers and intervals of the power supply potential and the ground potential do not usually coincide with each other, the layout of the capacitor connection wiring for connecting them is likely to be complicated.

The present invention has been made in view of such a problem, and has facilitated connection between a connection terminal connected to a terminal of an electronic component such as an IC chip and each terminal of a built-in capacitor. An object is to provide a wiring board.
Still another object of the present invention is to provide a wiring board in which inductance generated in connection wiring between a connection terminal and a capacitor is reduced.

[0007]

A means for solving the problem is a wiring board having a main surface and a back surface, which is formed on the main surface side and has terminals for electronic components mounted on the main surface. A plurality of connection terminals connectable to the wiring board, the plurality of connection terminals including a plurality of first connection terminals having a common first potential, and a plurality of second connection terminals having a common second potential. One electrode is connected to a common first potential, the other electrode is connected to a common second potential, respectively, at least one first capacitor terminal connected to the one electrode, and at least one connected to the other electrode. At least one chip capacitor having one second capacitor terminal, a second conversion conductor layer interposed between the chip capacitor and the connection terminal, and extending in a plane direction, the second conversion conductor layer and the chip capacitor. A first conversion conductor layer interposed between the second conversion conductor layer and the first conversion terminal and extending from the first connection terminal toward the back side in the thickness direction of the wiring board; A first main surface side connection wiring electrically connected to the first conversion conductor layer, and a second conversion conductor extending from the second connection terminal toward a back surface in the thickness direction of the wiring board. A second main surface side connection wiring electrically connected to each of the layers,
A first capacitor-side connection wire extending from the capacitor terminal toward the main surface in the thickness direction of the wiring board and connected to the first conversion conductor layer; and a main surface in the thickness direction of the wiring substrate from the second capacitor terminal. And a second capacitor-side connection wiring connected to the second conversion conductor layer while being insulated from the first conversion conductor layer.

The wiring board of the present invention has first and second conversion conductor layers extending in a plane direction between the first and second connection terminals and the chip capacitor. The first and second connection terminals are connected by first and second main surface side connection wirings. Further, the first and second conversion conductor layers and the first and second capacitor terminals are connected by first and second capacitor-side connection wires. That is, the first and the first spreading in the plane direction
Due to the presence of the second conversion conductor layer, there is no restriction on the positional relationship between the first and second main surface side connection wirings and the first and second capacitor side connection wirings, and the mutual positions can be easily converted. For example, if the first main surface side connection wiring is connected to the common first conversion conductor layer, regardless of the position where the first capacitor side connection wiring is connected to the first conversion conductor layer, the first capacitor side connection wiring is connected. The connection can be made with the connection wiring, and as a result, the first connection terminal and the first capacitor terminal of the chip capacitor can be easily connected. The same applies to the second conversion conductor layer. Further, it is easy to select and route the formation positions of the first and second main surface side connection wirings and the first and second capacitor side connection wirings, and connect the first connection terminal and the first capacitor terminal with a shorter path. And the second connection terminal and the second
Capacitor terminals can be connected, and inductance generated in these paths can be suppressed. Furthermore, the presence of the first and second conversion conductor layers extending in the plane direction also makes it possible to reduce the resistance generated in the above-described path as compared with a case without these.

The first and second main surface side connection wirings and the
The second capacitor-side connection wiring is preferably in the form of a stacked via formed by coaxially stacking via conductors formed in each insulating layer or a buried via inserted through a plurality of insulating layers in order to shorten the path. Alternatively, a staggered via in which vias formed in the respective insulating layers are overlapped while being shifted from each other may be formed, or a wiring layer extending in the plane direction may be interposed in the middle. Further, the first and second capacitor terminals of the chip capacitor need only be connectable to the first and second capacitor side connection wiring, and for example, those formed on the main surface or side surface of the chip capacitor may be used. No.

The chip capacitor may be any one as long as it can be built in a wiring board, and examples thereof include a multilayer ceramic type, an electrolytic capacitor type, and a film capacitor type. In particular, multilayer ceramic type chip capacitors have good frequency characteristics, and their characteristics are relatively stable even if heat is applied during the manufacturing process of the wiring board after they are built in. This is preferable in that the yield is improved and the yield is improved.

Further, any wiring board can be used as long as it can incorporate a chip capacitor. Examples of the wiring board include resins such as epoxy resin, polyimide resin, BT resin and PPE resin, and these resins and glass fiber or polyester fiber. A composite material with fibers, a resin composite material obtained by impregnating a fluororesin with a three-dimensional network structure with an epoxy resin, etc., and a ceramic substrate such as alumina, mullite, aluminum nitride, glass ceramic, and these resins. A combination of a composite material and the like can be given. In addition, other types of chip-shaped electronic components can be built in a wiring board, which has a built-in chip capacitor. Such chip-shaped electronic components include chip-shaped passive components such as chip resistors, chip inductors, and chip filters, chip-shaped active devices such as transistors, low-noise amplifiers, active filters, IC chips, memory devices, and FETs, and SAW filters. , An LC filter, an antenna switch module, a coupler, a diplexer, and a combination thereof.

Further, the wiring board has a core main surface and a core back surface, includes a core substrate body including one or a plurality of core insulating layers, and includes a core substrate including the chip capacitor. It is good to

In the wiring board of the present invention, since the chip capacitor is built in the core board, the first and second conversion conductor layers, the first and second capacitor side connection wiring, and the first and second main surface side connection are provided. The wiring board can be easily and inexpensively formed from the wiring and the respective insulating layers by a method of manufacturing a build-up wiring board.

Still another solution is a wiring board having a main surface and a back surface, the plurality of connections being formed on the main surface side and being connectable to terminals of electronic components mounted on the main surface. A connection terminal including a plurality of first connection terminals having a common first potential and a plurality of second connection terminals having a common second potential, a core main surface and a core back surface, A core substrate body including one or a plurality of core insulating layers, and a built-in core substrate body, one electrode connected to a common first potential and the other electrode connected to a common second potential, and the one electrode A core substrate including a plurality of chip capacitors having a plurality of first capacitor terminals connected to the second electrode terminal and a plurality of second capacitor terminals connected to the other electrode; and between a core main surface of the core substrate and the connection terminals. Second intervening in the plane direction A conversion conductor layer, a first conversion conductor layer located between the second conversion conductor layer and the core main surface of the core substrate and extending in a plane direction, and a thickness direction of the wiring board from the first connection terminal. A first main surface side via conductor that extends toward the back surface and is electrically connected to the first conversion conductor layer while being insulated from the second conversion conductor layer; A second main surface side via conductor extending toward the rear surface side in the thickness direction of the wiring substrate and electrically connected to the second conversion conductor layer; and a thickness of the wiring substrate from a first capacitor terminal of the chip capacitor. A first capacitor-side via conductor extending toward the main surface in the thickness direction and connected to the first conversion conductor layer, and a second capacitor terminal of the chip capacitor toward the main surface in the thickness direction of the wiring board. Delay While insulating each from the first conversion conductor layer, a wiring substrate including a second capacitor side via conductor connected to the second conversion conductor layer.

A wiring board according to the present invention has first and second conversion conductor layers extending in a plane direction between first and second connection terminals and a core board containing a chip capacitor. The conversion conductor layer and the first and second connection terminals are connected by first and second main surface side via conductors. Further, the first and second conversion conductor layers and the first and second capacitor terminals are connected by first and second capacitor-side via conductors. In other words, the presence of the first and second conversion conductor layers extending in the plane direction eliminates the restriction on the positional relationship between the first and second main surface side via conductors and the first and second capacitor side via conductors, and the mutual positional relationship is eliminated. Can be easily converted. For example, if the first main surface side via conductor is connected to the common first conversion conductor layer, regardless of the position where the first capacitor side via conductor is connected to the first conversion conductor layer, the first capacitor side via conductor is connected to the first capacitor side via conductor. The connection can be made with the via conductor, and as a result, the first connection terminal and the first capacitor terminal of the chip capacitor can be easily connected. The same applies to the second conversion conductor layer. In addition, the first and second
It is easy to select and route the formation positions of the main surface side via conductor and the first and second capacitor side via conductors, connect the first connection terminal and the first capacitor terminal via a shorter path, and connect the second connection terminal to the first connection terminal. Can be connected to the second capacitor terminal,
Inductance and resistance generated in these paths can be suppressed. In addition, since the chip capacitor is built in the core substrate, the first and second conversion conductor layers and
A wiring substrate can be easily and inexpensively formed with the second capacitor side via conductor, the first and second main surface side via conductors, and the respective insulating layers by a method of manufacturing a build-up wiring substrate.

The first and second main surface side via conductors and the first and second main surface side via conductors
The second capacitor-side via conductor is preferably in the form of a stacked via or a through via in order to shorten the path, but may be in the form of a staggered via.

Still another solution is a wiring board having a main surface and a back surface, wherein a plurality of connection terminals are formed on the main surface side and connectable to terminals of electronic components mounted on the main surface. A connection terminal including a plurality of first connection terminals having a common first potential and a plurality of second connection terminals having a common second potential; a core main surface and a core back surface; Or, a core substrate main body composed of a plurality of core insulating layers, and one of the electrodes embedded in the core substrate main body and having a common first potential,
The other electrode is connected to the common second potential, and includes at least one chip capacitor having a plurality of first capacitor terminals connected to the one electrode and a plurality of second capacitor terminals connected to the other electrode. A core substrate, a first conversion conductor layer located on the core main surface, connected to the first capacitor terminal, and extending in the plane direction; interposed between the core main surface of the core substrate and the connection terminal in the plane direction; A second conversion conductor layer extending from the first connection terminal and extending from the first connection terminal toward a back surface in a thickness direction of the wiring board;
A first main surface side via conductor electrically insulated from the conversion conductor layer and electrically connected to the first conversion conductor layer, respectively;
A second main surface side via conductor extending from the second connection terminal toward the back surface side in the thickness direction of the wiring board and electrically connected to the second conversion conductor layer, respectively; and a second capacitor of the chip capacitor A second capacitor-side via conductor that extends from the terminal toward the main surface in the thickness direction of the wiring board and that is insulated from the first conversion conductor layer and connected to the second conversion conductor layer. It is a wiring board.

In the wiring board of the present invention, the first conversion conductor layer extending in the plane direction is located on the core main surface of the core substrate containing the chip capacitor, and the first conversion conductor layer extending in the plane direction between the connection terminal and the core main surface. It has two conversion conductor layers. In addition, the first and second
The conversion conductor layer and the first and second connection terminals are connected by first and second main surface side via conductors. Further, in addition to the connection between the first conversion conductor layer and the first capacitor terminal, the second conversion conductor layer and the second capacitor terminal are connected via a second capacitor-side via conductor. Therefore, the presence of the first and second conversion conductor layers extending in the plane direction eliminates the restriction on the positional relationship between the first and second main surface side via conductors, the first capacitor terminal, and the second capacitor side via conductor. Can be easily converted. For example, if the first main surface side via conductor is connected to the common first conversion conductor layer, it is connected to the first capacitor terminal regardless of the position where the first capacitor terminal is connected to the first conversion conductor layer. As a result, the first connection terminal and the first capacitor terminal of the chip capacitor can be easily connected. Further, if the second principal surface side via conductor is connected to the common second conversion conductor layer, the second capacitor side via conductor is connected to the second capacitor side regardless of the position where the second capacitor side via conductor is connected to the second conversion conductor layer. The connection can be made with the via conductor, and as a result, the second connection terminal and the second capacitor terminal can be easily connected.

Further, it is easy to select and route the formation positions of the first and second main surface side via conductors and the second capacitor side via conductor, and connect the first connection terminal and the first capacitor terminal with a shorter path. In addition, the second connection terminal and the second capacitor terminal can be connected, and the inductance and resistance generated in these paths can be suppressed. In addition, since the chip capacitor is built into the core substrate,
The second conversion conductor layer, the second capacitor-side via conductor, the first and second principal-surface side via conductors, and the respective insulating layers are easily and inexpensively formed by a method of manufacturing a build-up wiring board. be able to. Further, since the first conversion conductor layer is formed on the core main surface of the core substrate, the connection path between the first capacitor terminal of the chip capacitor and the first conversion conductor layer can be minimized. In particular, when the number of the first connection terminals is larger than the number of the first capacitor terminals of the chip capacitor, which is a general case, the inductance generated in the path can be particularly suppressed.

The first and second main surface side via conductors and the second capacitor side via conductor are preferably in the form of stacked vias or through vias in order to shorten the path, but may be in the form of staggered vias.

Further, in the above wiring board, further comprising at least one insulating layer between the connection terminal and the core main surface of the core substrate, wherein the second conversion conductor layer is provided on the core main surface. The wiring board may be formed on the side surface of the main surface of the insulating layer in contact with the wiring board.

In this wiring board, the first conversion conductor layer is provided on the core main surface, and the second conversion conductor layer is provided on the main surface side of the insulating layer in contact with the core main surface, that is, on the connection terminal side. Therefore, not only the first conversion conductor layer, but also the second conversion conductor layer is arranged at a position closest to the core substrate, and thus closest to the chip capacitor. Therefore, the connection path between the second capacitor terminal of the chip capacitor and the second conversion conductor layer can be minimized. In particular, when the number of the second connection terminals is larger than the number of the second capacitor terminals of the chip capacitor, which is a general case, it is possible to particularly suppress the inductance generated in the path between them.

[0023]

(Embodiment 1) A first embodiment of the present invention will be described with reference to FIGS. The wiring substrate 100 shown in FIG. 1 includes a core substrate 110 having a large number of chip capacitors 113 built therein, and resin insulating layers 121 to 125 and 141 to 145 made of epoxy resin laminated above the main surface 110A and below the rear surface 110B, respectively. Having. A large number of bumps (connection terminals) 134 are formed at the center of the main surface 100A of the wiring board 100, and I
Many terminals CHT formed on the lower surface CHA of the C chip CH
And each can be flip-chip connected. A large number of pads 154 are formed on substantially the entire back surface 100B in the drawing, and can be connected to a large number of connection terminals WBT formed on another wiring substrate WB such as a motherboard indicated by a broken line by solder balls (not shown). I have.

The core substrate 110 is, as shown in FIG.
Core substrate body 11 made of a glass-epoxy resin composite material having a rectangular plate shape of 31 mm × 31 mm and a thickness of 1.0 mm
One. Between the main surface 111A (110A) and the lower surface 111B (110B), a large (7.5 × 8.0 mm) substantially rectangular through hole 111CH for the capacitor penetrating the main surface 111A (110A) and the lower surface 111B (110B) are formed. A large number of through holes 111H are formed. As described above, the main body portion has a substantially rectangular parallelepiped shape (3.2 mm × 1.6 mm × 0.8 m) in the capacitor through-hole 111CH.
m) (in this embodiment, 8 = 4 × 2) chip capacitors 113 are built in, and the insulating resin bodies 116 made of epoxy resin are used to connect each other and the capacitor through-holes 111C.
H. For this reason, the individual chip capacitors 113 are connected to each other in the capacitor through-hole 111CH.
They are insulated from each other by the insulating resin body 116. On the other hand, a well-known through-hole conductor 112 is formed in the through-hole 111H.

Some of the bumps 134 are made of the resin insulating layer 1.
24 and 125 or the resin insulating layers 123 and 12
4 by the wiring layers 128 and 129 formed between them.
Each fan-out is on the peripheral side (in the right or left direction in FIG. 1), and is connected to the pad 154 formed on the back surface 100B through the via conductor 133, the through-hole conductor 112, and the via conductor 153. These are used, for example, as signal wiring.

The remaining of the bumps 134 is the resin insulating layer 1
Resin insulating layers 121 and 122 are formed by via conductors 132 passing through 25 to 122 or 125 to 123, respectively.
, Or between the resin insulating layers 122 and 123, a substantially flat solid conductor layer (conversion conductor layer) 126,
127. Specifically, the first bump (first connection terminal) 134a is a first main surface side via conductor (first main surface side connection wiring) penetrating through the resin insulating layers 125 to 122, respectively.
132a, the second solid conductor layer (second conversion conductor layer)
The first solid conductor layer (first conversion conductor layer) 1 formed between the resin insulating layers 121 and 122 while being insulated from the second solid conductor layer 127 through the inside of the through hole 127H formed in the second insulating layer 127.
26. Also, a second bump (second connection terminal) 1
34b is a second main surface side via conductor (second capacitor side connection wiring) 1 penetrating through the resin insulating layers 125 to 123, respectively.
32b connects to the second solid conductor layer 127 formed between the resin insulating layers 122 and 123. As described below, in the present embodiment, the first solid conductor layer 126 has +
To the power supply potential (common first potential) of the second solid conductor layer 127.
Are connected to the ground potential (common second potential). Further, the first solid conductor layer 126 is a first solid conductor layer 126 penetrating the resin insulation layer 121.
Capacitor-side via conductor (first capacitor-side connection wiring) 1
30 connects to one side terminal (first capacitor terminal) 115a of the chip capacitor 113. on the other hand,
The second solid conductor layer 127 is formed on the first solid conductor layer 12 by a second capacitor-side via conductor (second capacitor-side connection wiring) 131 penetrating through the resin insulating layers 121 and 122, respectively.
6 is connected to the other side surface terminal (second capacitor terminal) 115 b of the chip capacitor 113 while being insulated from the first solid conductor layer 126 through the inside of the through hole 126 </ b> H formed in 6.
Thus, when the IC chip CH is mounted, the capacitor 113 and the IC chip CH are connected at a very short distance, and the power supply potential and the ground potential are supplied.

Side terminal 115 of chip capacitor 113
Reference numerals a and 115b denote conversion wirings 146 and 146 formed between the resin insulating layers 141 and 142 or between the resin insulating layers 142 and 143 by via conductors 148 and 149, respectively.
147, the arrangement is adjusted, and the resin insulating layer 142 is adjusted.
Are connected to the respective pads 154 by via conductors 151 and 152 penetrating through. Through this pad 154, the one side terminal (first potential side terminal) 115a and the one electrode layer 114a have a positive power supply potential, and the other side terminal (second potential side terminal) 115b and the other electrode layer Power is supplied from the wiring board WB so that 114b becomes the ground potential. FIG. 1 shows the potential of the connection terminal WBT as the power supply potential (represented by the symbol “+”) and the ground potential (represented by the symbol “G”) in the wiring board WB. Therefore, if the wiring board 100 is used, the noise superimposed on the power supply wiring can be supplied to the IC chip CH by the very short via conductor 132 or the like while being absorbed by each chip capacitor 113.

The built-in chip capacitor 113 is a multilayer ceramic capacitor made of a BaTiO3-based high dielectric ceramic, as shown in the enlarged view at the bottom of FIG. The capacitor body 114 has a substantially rectangular shape (3.2 × 1.6 × 0.8 mm).
0, the upper surface 114u facing the lower surface 110B, the lower surface 114d facing the lower surface 110B, and the four side surfaces 114S.
(114S1, 114S2, 114S3, 114S4)
(See FIG. 2). Inside, one electrode layer 114a and the other electrode layer 114b are alternately arranged in parallel with the upper surface 114u (perpendicular to the side surface 114S) via the ceramic high dielectric layer 114c, and thus on the main surface 100A. Many are stacked in parallel. These electrode layers 114a,
114b is made of Ni. Each electrode layer 114a, 114b
Is partially similar to the capacitor shown in FIG.
The first side surface 114S1 and the third side surface 114S3 are respectively drawn out and connected to side terminals 115 made of Cu. Specifically, one electrode layer 114a is connected to one side terminal 115a, and the other electrode layer 114b is connected to the other side terminal 115b.

The side terminals 115a and 115b have upper surfaces 115au and 115bu on the upper surface 114u and lower surfaces 115ad and 115bd on the lower surface 114d, respectively. Therefore, the side surface terminals 115a and 115b extend from the upper surface portions 115au and 115bu beyond the periphery of the upper surface 114u to the side surface 114S from the upper surface 114u (that is, the main surface 100A side) to the lower surface 114d (that is, the back surface 100B).
Side), and is connected to the lower surface portions 115ad and 115bd beyond the periphery of the lower surface 114d. In this embodiment, the upper surface portions 115au, 115bu
Is the upper surface 111A of the core substrate main body (the main surface 11A of the core substrate).
0A). Also, the lower surface 115ad,
115bd is lower than the lower surface 111B of the core substrate main body, but the lower surface bump 117
a, 117b are the lower surface 111B (the lower surface 110 of the core substrate).
B).

In the chip capacitor 113 of this embodiment, the first side surface 114S1 and the third side surface 11
Four side terminals 115 are formed on 4S3, respectively, and no side terminals 115 are formed on the second side surface 114S2 and the fourth side surface 114S4. In addition, as shown in FIG.
Looking at the second side surface 114S2, the third side surface 114S3, and the fourth side surface 114S4 in this order from the side surface 114S1 clockwise,
The side terminals 115a and 115b are arranged alternately. That is, as described later, the electrode layers 114a, 11a
When any one of 4b is set to a + power supply potential (indicated by “+” in FIG. 2) and the other is set to a ground potential (indicated by “G” in FIG. 2), the power supply potential is connected to a power supply potential indicated by “+” Side terminal 115
a and a side terminal 115 connected to the ground potential indicated by “G”
b are alternately arranged.

Further, the chip capacitor 113 is provided as shown in FIG.
And, as shown in FIG.
3, the first side surface 114S1 and the third side surface 113S3 are arranged in a vertical and horizontal lattice shape when viewed from the main surface 100A such that the second side surface 114S2 and the fourth side surface 114S4 face each other. For this reason, by considering the connection of the power supply potential and the ground potential to each chip capacitor 113, as shown in FIG. 2, the side terminals 115 adjacent to each other are set to different potentials, Side terminal 115a
To the power supply potential and the other side terminal 115b to the ground potential.

By the way, when the chip capacitor 113 is charged and discharged, as described above,
5 flows (see FIGS. 1 and 3). Due to this current, self-inductance is generated in the side surface terminal 115 extending vertically on the side surface 114S1 and the like. The arrow in the figure indicates the direction of the current. Regarding one chip capacitor 113, the potentials to be connected are different in relation to the adjacent side terminal 115, so that the direction of the current flowing during charging and discharging is reversed. Therefore, the self-inductance can be reduced by the mutual inductance generated by the combination of the two.

In addition, the adjacent chip capacitors 11
As for the three side terminals 1, the side terminals 1 which are adjacent and face each other
Also in the relationship between the 15 components, the connected potentials are different, so that the directions of the currents flowing during charging and discharging are reversed. Therefore, the mutual inductance generated by the coupling between the two,
Self-inductance can be reduced. In the present embodiment, the chip capacitors 113 are arranged in a vertical and horizontal lattice. For this reason, it is possible to suppress the inductance as described above for the side terminals of the opposing first side surface 114S1 and the third side surface 114S3 of the adjacent capacitor, and also for any of the opposing and adjacent side terminals 115. Can reduce the inductance as a whole

In addition, in the present embodiment, as shown in FIG.
The interval (pitch) P2 between adjacent chip capacitors 113 and the adjacent opposing side terminals 115 is P2 = 0.4 mm, as compared with the interval (pitch) P1 between 0.85 and 0.8 mm.
Is smaller. Therefore, the coupling between the side terminals 115 that are adjacent to each other is increased, and the inductance can be further reduced. As described above, since the insulating resin body 116 is filled and interposed between the chip capacitors 113, the side terminals 115
The insulation between them is maintained.

Next, a method for manufacturing the wiring board 100 of the present embodiment will be described. First, a method for manufacturing the core substrate 110 will be described. First, as shown in FIG. 4A, a rectangular shape of 31 × 31 mm, made of a glass-epoxy resin composite material having a thickness of 1.0 mm, and 7.5 × penetrating between the main surface 111A and the lower surface 111B. A core substrate main body 111 having a large, approximately rectangular capacitor through hole 111CH of 8.0 mm and a large number of through hole through holes 111H formed therearound is prepared. These through holes 111CH and 111H are, for example, drills, routers,
Perforate by laser or the like.

Next, as shown in FIG. 4B, an adhesive tape TP is attached to the upper surface 111A of the core substrate main body 111, and is placed on the flat upper surface PLA of the flat table PL with the lower surface 111B facing upward. Place. Thereafter, the chip capacitors 113 are arranged at predetermined intervals in the capacitor through holes 111CH with the upper surface 113u (114u) facing downward by using a chip mounter (not shown). Since the chip capacitor 113 is adhered to the adhesive tape TP, the position of the chip capacitor 113 is prevented from shifting in the next step. Since the height of the chip capacitor 113 is lower than the thickness of the core substrate main body 111, the chip capacitor 113 is positioned lower than the back surface 111B.

Thereafter, a thermosetting epoxy resin having good fluidity is filled in the through hole 111CH for a capacitor, and is cured by heating (100 to 120 ° C., about 1 to 3 hours). The core substrate main body 111, the chip capacitors 113, and the chip capacitors 113 are fixed to each other via the insulating resin body 116. Thereafter, the adhesive tape TP is peeled off, and the back surface 111B side is polished with a belt sander to remove an extra insulating resin body 116. In order to surely expose the upper surface portions 115au and 115bu of the side terminals 115 of the chip capacitor 113, the upper surface 111A may be slightly polished as necessary.

Thereafter, as shown in FIG.
The lower surface portions 115ad, 115bd of the side terminals 115 from the side
A through hole 116H is formed in the upper insulating resin body 116 by, for example, laser processing. Thereafter, lower surface bumps 117a and 117b projecting from the lower surface 111B from the inside of the through hole 116H are formed by known electroless Cu plating, electrolytic Cu plating, and etching, and the upper surface portions 115au,
The thickness of 115 bu is increased to protrude from the upper surface 111A, the through-hole conductor 112 is formed in the through-hole 111H, and the necessary wiring layers are formed on the upper surface 111A (main surface 110A) and the lower surface 111B. Core substrate 11
0 is formed. As shown in the enlarged view b in the upper part of FIG. 5, as the through-hole conductor 112, an inner-peripheral through-hole conductor 112T is formed on the inner periphery of the through-hole 111H.
In addition to the formation of H, the center portion was filled with a filling resin 112R, and further a lid-like conductor layer 112C was formed.

Thereafter, each of the resin insulating layers 121 to 125, 141 is formed by a known build-up wiring board forming method.
To 145 are formed, and the first solid conductor layer 126, the second solid conductor layer 127, the wiring layers 128 and
9. Via conductors 130, 131, 132, 13 which form conversion wirings 146, 147 and penetrate each resin insulation layer
3, 151, 152, 153, and 154 are formed to complete the wiring board 100. Since the wiring board 100 has a large number of built-in chip capacitors 113 as described above,
Noise can be reliably removed, and since the plurality of chip capacitors 113 are connected in parallel, the inductance of the built-in capacitors as a whole can be reduced. In addition, when looking at each chip capacitor 113, the polarities of the adjacent side terminals 115 are different, and the direction of the flowing current is opposite. Therefore, the inductance can be further reduced, and the IC chip CH and the capacitor 1 can be further reduced in inductance.
13 can be connected.

Since the upper surface portions 115 au and 115 bu are formed on the side terminals 115 of the chip capacitor 113, the via conductors 130 and 131 formed on the resin insulating layer 121 laminated on the upper surface 110 A of the core substrate 110 have side surfaces. Connection with the terminal 115 (115a, 115b) is facilitated. On the other hand, the side surface terminal 115 has a lower surface portion 115ad,
115bd, and the lower surface bumps 117a,
7b, the lower surface 110 of the core substrate 110 is formed.
Via conductor 14 formed on resin insulating layer 121 laminated on B
8,149 and the side terminals 115 (115a, 115b) are also easily connected.

Further, in the first embodiment, the first solid conductor layer 126 and the second solid conductor layer 127 are interposed between the chip capacitor 113 and the main surface 100A or the bump 134, and the first main surface side via conductor 132a, the first solid conductor layer 126, and the first capacitor-side via conductor 130,
The first bump 134a and the first potential side terminal 115a of the chip capacitor 113 were connected. Further, the second bump 134b and the second potential side terminal 115b of the chip capacitor 113 were connected by the second main surface side via conductor 132b, the second solid conductor layer 127, and the second capacitor side via conductor 131. In this case, generally, the side terminals 1
The distance between the first and second potential side terminals 115 and the first and second potential side terminals 115 is larger than the number of the side terminals 115. There are advantages that can be easily achieved. Specifically, the first and second solid conductor layers 126 and 127 form the first and second main surface side via conductors 132a and 132b and the first and second main conductor vias 132a and 132b.
The number and position of the second capacitor-side via conductors 130 and 131 can be changed, and each can be connected to the first and second solid conductor layers 126 and 127 at an appropriate position. For this reason, it is necessary to connect the individual first bumps 134a to the first potential side terminals 115a of the chip capacitor 113 and connect the individual second bumps 134b and the second potential side terminals 115b with complicated connection wiring. No connection is possible.

Further, since the path between the first bump 134a and the first potential side terminal 115a of the chip capacitor 113 can be shortened, the inductance and resistance generated in the connection wiring between them can be suppressed. Second bump 1
The same applies to the inductance and the resistance generated in the path between the terminal 34b and the second potential side terminal 115b. Furthermore, since the inductance generated in the first and second solid conductor layers 126 and 127 can be suppressed lower than that generated in the normal wiring, the first bump 134a and the first potential side terminal 115a are also connected to this point. During this time, the inductance generated between the second bump 134b and the second potential side terminal 115b can be further suppressed.

Also, any first main surface side via conductor 132
a is once connected to the common first solid conductor layer 126, and similarly, the second main surface side via conductor 132 b is also connected to the common second solid conductor layer 1.
27 once. Therefore, for example, even if connection failure or disconnection occurs in any of the first and second capacitor-side via conductors 130 and 131, each of the first and second bumps 134a and 1
The power supply potential and the ground potential (common first and second
Potential) can be supplied, so that there is an advantage that the reliability of the wiring board 100 can be increased.

(Modification 1) In the first embodiment, the lower surface portions 115ad and 115bd of the chip capacitor 113 built in the core substrate main body 111 have the lower surface 111B.
And the upper part was covered with the insulating resin body 116 except for the bumps 117a and 117b. However, the upper surface of the side terminal may protrude from the upper surface of the core substrate main body, and the lower surface may also be formed to protrude from the lower surface of the core substrate main body.

The core substrate 210 according to the first modification is the same as that shown in FIG.
As shown in (a), the upper surface portions 215au and 215bu of the side terminals 215a and 215b of the chip capacitor 213 built in the capacitor through hole 211CH are thickened and protrude from the upper surface 211A of the core substrate main body 211. I have. Further, the lower surfaces 215ad and 215bd are also thickened, and protrude from the lower surface 211B of the core substrate main body 211. Therefore, as in the first embodiment, the bump 1
It is not necessary to form 17a and 117b. Even when such a core substrate 210 is used, the wiring substrate 200
(See FIG. 7). That is, this wiring board 200 uses a core substrate 210 in place of the core substrate 110 in the wiring board 100 of the first embodiment, and similarly to the first embodiment, the resin insulating layers 121 to 121 above the main surface 210A and below the rear surface 210B. 125, 141-145, first
This is a wiring board on which a solid conductor layer 126, a second solid conductor layer 127 and the like are formed. The chip capacitor 213 has the same structure as the chip capacitor 113 of the first embodiment, and similarly to the first embodiment, the through hole 211CH for the capacitor.
(See an enlarged view of FIG. 5, FIGS. 2 and 3).

Also in this wiring board 200, the adjacent side terminals 2 of the adjacent chip capacitors 213 are opposed to each other.
15 (215a, 215b) are opposite in direction to each other, so that the inductance generated in the side terminal 215 can be reduced.

As shown in FIG. 6B, a core substrate 210 used for the wiring substrate 200 is formed by using a core substrate main body 211 slightly thinner than the core substrate main body 111 of the first embodiment. A chip capacitor 213 is disposed in the capacitor through-hole 211CH, and an insulating resin body 216 is provided.
After filling and fixing, the upper and lower surfaces 211A and 211B are polished and the upper surface 215au,
215bu and the lower surfaces 215ad and 215bd are exposed. Thereafter, the through-hole conductor 212 is formed in the through-hole 211H for the through-hole by electroless Cu plating, electrolytic Cu plating and etching, and the upper surface portion 21 is formed.
5au, 215bu and lower surface portions 215ad, 215bd
By increasing the thickness of the main surface 210A shown in FIG.
And a core substrate 210 having a back surface 210B.

Thereafter, as in the first embodiment, the wiring board 200 may be formed according to a known build-up wiring board forming method. As in the first embodiment, since the upper surface portions 215au and 215bu are formed on the side surface terminal 215, the side surface terminal 215 (the capacitor 21) is provided on the main surface 200A side.
In order to draw out the potential of 3), connection is facilitated, which is convenient. Further, since the lower surfaces 215ad and 215bd are formed, it is convenient to draw out the potential of the side terminal 215 (capacitor 213) to the back surface 200B side.

Also in the first modification, similarly to the first embodiment, the first solid conductor layer 126 and the first solid conductor layer 126 are provided between the chip capacitor 213 and the main surface 200A or the bump 134.
The second solid conductor layer 127 is interposed. Therefore, the interval is generally narrower than the interval between the side terminals 215 and the like.
The advantage that connection between the second bumps 134a and 134b and the first and second potential side terminals 215a and 215b can be easily obtained can be similarly obtained. More specifically, the number and position of the first and second principal surface side via conductors 132a and 132b and the first and second capacitor side via conductors 130 and 131 are determined by the first and second solid conductor layers 126 and 127. Are respectively converted into the first and second solid conductor layers 126 and 12 at appropriate positions.
7 can be connected. Therefore, the individual first bumps 134a
And the first potential side terminal 115a of the chip capacitor 113
Also, it is not necessary to connect the individual second bumps 134b and the second potential side terminals 115b with complicated wiring arrangements, and the connection can be easily performed.

In addition, the first and second bumps 134a, 134
Since the path between the terminal 4b and the first and second potential side terminals 115a and 115b can be shortened, the inductance and resistance generated in the connection wiring between them can be suppressed. Also,
Since the inductance generated in the first and second solid conductor layers 126 and 127 can be suppressed lower than that generated in the normal wiring, the first and second bumps 13 are also considered from this point.
4a, 134b and first and second potential side terminals 115a, 1
15b can be further suppressed. Also, as in the first embodiment, even if a connection failure or disconnection occurs in the first and second capacitor-side via conductors 130 and 131, the first and second bumps 134a and 134b normally operate at the power supply potential or the ground potential ( Since the common first and second potentials can be supplied, there is an advantage that the reliability of the wiring board 100 can be increased.

(Modification 2) In Embodiment 1 and Modification 1, the core substrate main bodies 111 and 211 used for the core substrates 110 and 210 are each composed of a single core insulating layer made of a glass-epoxy resin composite material. Was used. However, the core substrate body may be a laminate of a plurality of core insulating layers. For example, in the wiring board 500 shown in FIG. 8, the core board 510 includes a core board main body 511 and a through-hole conductor 512 penetrating therethrough. In addition, the core substrate body 511 has a core insulating layer 513 made of a glass-epoxy resin composite material and a core insulating layer 514, 515 made of epoxy resin laminated on the main surface 500A side and the back surface 500B side. It includes three core insulating layers, and further includes core insulating layers 513 and 514.
Between the core insulating layers 513 and 515.
A conductor layer 517 is formed between the two. In the second modification, the conductor layers 516 and 517 are connected to the power supply potential or the ground potential via the through-hole conductor 512 as shown on the left side of the drawing.

As in the first embodiment and the first modification,
A large substantially rectangular capacitor through-hole 511CH penetrating the core substrate body 511 is formed in the core substrate main body 511, and the chip capacitor 1
13 is built in. The core substrate 510 and the wiring substrate 500 are formed by laminating the core insulating layers 514 and 515 on the core insulating layer 513 in which the conductor patterns corresponding to the conductor layers 516 and 517 are formed by a known build-up method. 511H and a capacitor through-hole 511CH are formed. Thereafter, an insulating layer or the like may be formed above the main surface 510A and below the back surface 510B of the core substrate 510 in the same manner as in the first embodiment. As described above, even when a core substrate body including a plurality of core insulating layers is used, a wiring substrate having a built-in chip capacitor can be similarly formed. The core substrate body including the plurality of core insulating layers may not include the conductor layers 516 and 517. Although the core insulating layer may be made of a different material like the core insulating layer 513 and the other core insulating layers 514 and 515, the core substrate body in which all of the plurality of core insulating layers are made of the same material Can also be used. Further, as shown in FIG. 8, the core insulating layer 513 is thicker than the other core insulating layers 514 and 515, but a core substrate body in which all of the plurality of core insulating layers have substantially the same thickness is used. Can also.

Also in the second modification, the chip capacitor 113 and the main surface 500 are similar to the first embodiment.
A or between the first solid conductor layer 12 and the bump 134.
6, the second solid conductor layer 127 is interposed. Therefore,
There are similar advantages such as easy connection between the first and second bumps 134a and 134b and the first and second potential side terminals 115a and 115b.

(Embodiment 2) In Embodiment 1 and Modifications 1 and 2, the main surfaces 100A, 200A, 500A of the wiring substrates 100, 200, 500 and the back surfaces 100B, 2B
The structure can be connected to the side terminals 115 and 215 of the chip capacitors 113 and 213 from both the 00B and 500B sides. However, the wiring board may be configured so as to be connected to the chip capacitor only on the main surface side.

That is, as shown in FIG. 9, the core board 310 used in the wiring board 300 of the present embodiment has a large number of chip capacitors 313 built in the capacitor through holes 311CH of the core board body 311. Terminal 315
(315a, 315b) are upper surface portions 315au, 3
15bu protrudes from the upper surface 311A of the core substrate main body 311 (the main surface 310A of the core substrate 310). But,
The lower surface 311B (rear surface 310B) side includes the lower surface 313d of the capacitor and the lower surfaces 315ad and 315ad of the side terminal 315.
15bd is covered with the insulating resin body 316, and the lower surface 31
The chip capacitor 313 from the 1B (rear surface 310B) side
(Side terminal 315).

Around the capacitor through-hole 311CH, a through-hole conductor 312 is provided similarly to the core substrate 110 of the first embodiment (see FIG. 5), and a power supply potential and a ground potential as described below. Through conductors 318 and 319 for passing through the upper and lower portions of the core substrate 310 are also formed. The chip capacitor 313 has the same structure as the chip capacitor 113 of the first embodiment, and is arranged in a vertical and horizontal lattice in the capacitor through-hole 311CH as in the first embodiment (enlarged view of FIG. 5, FIG. 2, see FIG. 3).

FIG. 10 is a sectional view of a wiring substrate 300 using such a core substrate 310. This wiring board 300
Has substantially the same structure as the wiring board 100 of the first embodiment. That is, a core substrate 310 having a large number of built-in chip capacitors 313, and upper and lower surfaces 3A and 3A of the main surface 310A.
10B, resin insulating layers 321 to 325, 3
41 to 345, respectively. A large number of bumps (connection terminals) 334 are formed at the center of the main surface 300A of the wiring board 300, and can be connected to the connection terminals CHT on the lower surface CHA of the IC chip CH indicated by broken lines. Also, back 3
A large number of pads 354 are formed on substantially the entire surface of 00B, and can be connected to connection terminals WBT formed on another wiring board WB indicated by broken lines.

Some of the bumps 334 are connected to the wiring layers 328 and 32.
9, fan-out to the peripheral side, via conductor 333, through-hole conductor 312, via conductor 353
Through the pad 354 formed on the back surface 300B. These are used, for example, as signal wiring.

The rest of the bumps 334 are connected to the via conductors 33.
2, the first solid conductor layer (first conversion conductor layer) 326 or the second solid conductor layer (second conversion conductor layer) having a substantially flat plate shape
327. Specifically, the first bump (first connection terminal) 334a is a first main surface side via conductor (first main surface side connection wiring) penetrating through the resin insulating layers 325 to 322, respectively.
The first solid conductor layer 326 formed between the resin insulating layers 321 and 322 while being insulated from the second solid conductor layer 327 by passing through the through hole 327H formed in the second solid conductor layer 327 by 332a. Connect to Further, the second bumps (second connection terminals) 334b are connected to the resin insulation layers 322 and 323 by the second main surface side via conductors (second main surface side connection wires) 332b penetrating the resin insulation layers 325 to 323, respectively. To the second solid conductor layer 327 formed between them. As described below, the first solid conductor layer 326 is connected to a positive power supply potential (common first potential), and the second solid conductor layer 327 is connected to ground potential (common second potential). Further, the first solid conductor layer 326 is connected to the chip capacitor 31 by the first capacitor side via conductor (first capacitor side connection wiring) 330.
3 is connected to one side terminal (first potential side terminal) 315a. On the other hand, the second solid conductor layer 327 passes through the through hole 326H formed in the first solid conductor layer 326 by the second capacitor-side via conductor (second capacitor-side connection wiring) 331, and is connected to the first solid conductor layer 326. The other side terminal (second potential side terminal) of the chip capacitor 313 while being insulated
315b. Thus, when the IC chip CH is mounted, the capacitor 313 and the IC chip CH are connected at a very short distance, and the power supply potential and the ground potential are supplied. Note that, as described above, unlike the wiring board 100 of the first embodiment, the side terminals 315 of the chip capacitor 313 are not directly drawn out to the back surface 300B side.

Therefore, a path is provided from the first solid conductor layer 326 to the conversion wiring 346 via the via conductor 335, the through-hole conductor 318 in the core substrate body 311 and the via conductor 348. . Similarly, a path from the second solid conductor layer 327 to the conversion wiring 347 is provided via the via conductor 336, the through-hole conductor 319 in the core substrate body 311, and the via conductor 349. After that, similarly to the wiring board 100 of the first embodiment, the arrangement is adjusted by the conversion wirings 346 and 347, and the connection is connected to each pad 354 by the via conductors 351 and 352 penetrating the resin insulating layers 342 to 345.

Through this pad 354, the first solid conductor layer 326 and one side terminal 315a (and one electrode layer connected to it) have a positive power supply potential, and the second solid conductor layer 327 and the other side terminal 315b ( And the other electrode layer connected thereto is supplied with power from the wiring board WB so as to be at the ground potential. Therefore, if this wiring board 300 is used, the noise superimposed on the power supply wiring can be supplied to the IC chip CH by the very short via conductor 332 or the like while being absorbed by each chip capacitor 313.

Moreover, in the wiring board 300,
For example, when the chip capacitor 313 is charged, a current flows in the side terminal 315 in the direction indicated by the arrow in FIG. It goes without saying that the opposite is true in the case of discharge. Therefore, the adjacent chip capacitors 313
Since the current flows in the opposite side terminals 315 in opposite directions, the inductance generated in the side terminals 315 can be further reduced. As in the first embodiment, the side surface terminal 315 has the upper surface portion 3
Since 15 au and 315 bu are formed, the first embodiment
Similarly to the above, connection is easy to draw out the potential of the side surface terminal 315 (capacitor 313) to the main surface 300A side, which is convenient.

The core board 310 used in the wiring board 300 of the present embodiment is formed in the same way as the manufacturing method of the core board 110 of the first embodiment.
A chip capacitor 313 is arranged in 1CH, filled with epoxy resin and cured to form an insulating resin body 316, and then the lower surface 311B is polished (see FIG. 4A). Then, unlike Embodiment 1, without piercing the through-hole 116H,
The upper surface portions 315au, 31 of the side terminals 315 by plating.
The thickness of 5 bu is increased, and the through-hole conductors 312, 318, 31 are formed in the through-holes 311 </ b> H.
9 may be formed to form the core substrate 310. Later,
The wiring board 3 is manufactured by a known build-up wiring board manufacturing method.
00 can be formed.

In the second embodiment, similarly to the first embodiment, the first solid conductor layer 326 and the second solid conductor layer 327 are interposed between the chip capacitor 313 and the main surface 300A or the bump 334. I have. Therefore, the first
There are similar advantages such as easy connection between the second bumps 334a and 334b and the first and second potential side terminals 315a and 315b.

(Embodiment 3) In Embodiments 1 and 2, etc., among the resin insulating layers 121 to 125, 321, to 325, the first solid conductor layers 126, 326 are replaced with the core substrates 110, 310, etc. Main surfaces 110A, 310A, 51
It was formed on the main surface side of the resin insulating layers 121 and 321 in contact with 0A. Further, the second solid conductor layers 127 and 327 are further formed on the main surface side of the resin insulating layers 122 and 132 on the main surface side. Thus, the first and second solid conductor layers 126, 12
7 is preferably located near the chip capacitors 113 and 313. As shown in FIGS. 1, 7, 8, and 10, generally, the first and second bumps 134a, 134b
Is larger than the number of the side terminals 115 and 315 of the chip capacitors 113 and 313. Therefore, the first and second
Bumps 134a, 134b, etc. and first and second solid conductor layers 1
26, 127, etc., the first and second main surface side via conductors 13
2a, 132b, 332a, and 332b correspond to the first and second capacitor-side via conductors 130 and 13 that connect the side terminals 115 and the first and second solid conductor layers 126 and 127, respectively.
1,330,331. Inductance and resistance generated in the connection wiring can be reduced as the number of paths provided in parallel and as the current flowing through each wiring is reduced, so that under such conditions, the first and second solid conductor layers 126, This is because it is preferable to provide 127 or the like near the chip capacitor 113 or the like.

Therefore, in the wiring board 600 of the third embodiment, as shown in FIG.
A first solid conductor layer (first conversion conductor layer) 626 is provided on A, and a second solid conductor layer (second conversion conductor layer) 627 is provided on the main surface side (upper side in the figure) of the resin insulating layer 122 in contact with the first solid conductor layer. Was. Specifically, the first bumps 134a are formed of the resin insulating layers 125-1 to 125-1.
The through holes 627 formed in the second solid conductor layer 627 by the first main surface side via conductors 132 a penetrating through
H, the first solid conductor layer 6 formed on the main surface 610 </ b> A of the core substrate 610, that is, between the core substrate 610 and the resin insulating layer 122 while being insulated from the second solid conductor layer 627.
26. The second bump 134b is connected to the second solid conductor layer 627 formed between the resin insulating layers 122 and 123 by the second main surface side via conductor 132b penetrating the resin insulating layers 125 to 123, respectively. . Further, the first solid conductor layer 626 is different from the first embodiment and the like.
Without the first capacitor-side via conductor 130 or the like,
The first potential side terminal of the direct chip capacitor 613 (the first potential side terminal)
Capacitor terminal) 615a. On the other hand, the second
The solid conductor layer 627 is a second conductor layer penetrating the resin insulating layer 122.
The capacitor-side via conductor 631 connects to the second potential side terminal (second capacitor terminal) 615b of the chip capacitor 613 formed in the through hole 626H formed in the first solid conductor layer 626.

Thus, the first solid conductor layer 626 is directly connected to the upper surface portion 615au of the first potential side terminal 615a of the chip capacitor 613, and the first and second solid conductor layers 626 and 627 are connected to the chip capacitor 613. Will be placed closest to the Therefore, the inductance and the resistance generated in the connection wiring between the chip capacitor 613 and the first and second bumps 134a and 134b can be further reduced. When the IC chip CH is mounted,
The capacitor 613 and the IC chip CH are connected at a very short distance, and a power supply potential and a ground potential are supplied.
Further, as can be easily understood from comparison with the wiring board 100 shown in FIG. 1, since the resin insulating layers 121 and 141 can be eliminated, a wiring board which is easy to manufacture and inexpensive can be obtained.

Next, a method of manufacturing the wiring board 600 will be described. First, a method for manufacturing the core substrate 610 (see FIG. 13) will be described. As in the first embodiment, the main surface 61
A core substrate main body 611 having a large and substantially rectangular capacitor through-hole 611CH penetrating between 1A and the lower surface 611B and a large number of through-hole through holes 611H formed therearound is prepared (FIG. 4 ( a)). After that, as in the first embodiment, the upper surface 6
Adhesive tape TP is stuck to 11A, and chip capacitors 613 are arranged at predetermined intervals in capacitor through holes 611CH with the upper surface 613u facing down (FIG. 4).
(B)). A thermosetting resin having good fluidity is filled in the through hole 611CH for the capacitor, and is cured by heating.
The core substrate main body 611, the chip capacitor 613, and the chip capacitors 613 are fixed to each other via the insulating resin body 616. The back surface 611B side is polished with a belt sander to remove excess insulating resin body 616.

Thereafter, the side surface terminals 61 are moved from the lower surface 611B side.
Insulating resin body 61 on lower surface portions 615ad and 615bd of 5
6, a through hole 616H is formed by, for example, laser processing. A package surface bump 617a is formed in the through-hole 616H by known electroless Cu plating, electrolytic Cu plating, and etching, and a conversion wiring directly connected to the bump 617a is formed on the back surface 610B. Also, the through hole 616H
Lower surface bump 617b projecting from inside from rear surface 610B
To form At the same time, the thickness of the upper surface portion 615bu is increased to protrude from the main surface 610A. Furthermore, the main surface 61
A first solid conductor layer 626 that is directly connected to the upper surface 615au is formed at 0A. In addition, through holes 611 for through holes
A through-hole conductor 612 is formed in H, and a core substrate 610 is formed.

Thereafter, each of the resin insulating layers 122 to 125 and 142 is formed by a known build-up wiring board forming method.
145, the second solid conductor layer 627, the wiring layers 128 and 129, and the conversion wiring 147 are formed between the respective layers, and the via conductors 630 and 6 penetrating through the respective resin insulating layers are formed.
31, 132, 133, 151, 152, and 153 are formed, and pads 154 are further formed to complete the wiring board 600. Since the wiring board 600 also includes a large number of chip capacitors 613 similarly to the wiring board 100 of the first embodiment, noise can be surely removed, and a plurality of chip capacitors 113 are connected in parallel. The inductance of the built-in capacitor as a whole can also be reduced. In addition, even when looking at each chip capacitor 613, the polarities of the side terminals 615 adjacent to each other are different, and the direction of the flowing current is opposite, so that the IC chip CH and the capacitor 113 are connected with even lower inductance. be able to.

In the above, the present invention has been described with reference to the respective embodiments and modifications. However, the present invention is not limited to the above embodiments and the like, and may be appropriately changed without departing from the gist of the present invention. It goes without saying that it can be applied. For example, in the first, second, and third embodiments and the first and second modifications, the first and third side surfaces of the chip capacitor have the same number (four in the embodiment), side terminals 115, and the like. Was used. However, for example, like the chip capacitor 413 shown in FIG. 11, not only the first side surface 413S1 and the third side surface 413S3, but also the side surface terminals 415 on the second side surface 413S2 and the fourth side surface 413S4.
(415a, 415b) having the same number (two in the figure) may be used. At this time, the adjacent side terminals 4
As shown in FIG. 11, the 15 potentials are arranged such that a common first potential (for example, a power supply potential indicated by “+”) and a common second potential (for example, a ground potential indicated by “G”) appear alternately. .
Even if such a chip capacitor 415 is used, the inductance is canceled by the side terminals 415 adjacent to each other facing each other, so that the chip capacitor can be connected to an IC chip or the like with lower inductance.

Further, the chip capacitors 413 are densely arranged, and the distance between the opposing side terminals 41 of the adjacent chip capacitors 413 is smaller than the distances P1 and P3 between the adjacent side terminals 415 in one chip capacitor.
If the distances P2 and P4 between the 5 are made smaller, the inductance can be further reduced. Further, in the above embodiments and the like, chip capacitors having the same shape were used, and these were arranged in a vertical and horizontal lattice. However, it is only necessary that the side terminals of the adjacent capacitors are adjacent to each other so as to face each other, and they are connected so that their polarities are different. This is because the inductance can be reduced at least between these side terminals.

In the above-described embodiments and the like, the chip capacitor 113 and the like are built in the core substrate main body 111.
The chip capacitor only needs to be built in the wiring board,
For example, it may be mounted on a core substrate or a resin insulating layer. Further, the present invention is not limited to the one using a core substrate body having a thickness such that the chip capacitor can be accommodated in the core substrate. Further, even when the chip capacitor is incorporated in the core substrate main body, a chip capacitor may be arranged and embedded in a concave portion formed in the core substrate main body in addition to the embodiment.

Further, in the above-described embodiments and the like, the first solid conductor layer 126, the second solid conductor layer 127, and the like are formed between the chip capacitor 113 and the like and the main surface 100A and the like. In this case, there is an advantage that the connection with the bump 134 having a narrower interval can be easily performed as compared with the interval between the side terminals 115 and the like. However, each bump 134
It is sufficient that the predetermined bumps can be appropriately connected to the side terminals 115a and 115b of the chip capacitor 113, and the via conductor penetrates the wiring layer formed between the resin insulating layers 121 to 125, the resin insulating layer 121, and the like. The terminal 115 and each bump 134 may be connected. Also, for example, a striped conductor layer is provided between the resin insulating layers 121 and 122, and the striped conductor layers are alternately shared by the first common layer.
Each of the striped conductor layers and the side terminals 115a and 115 are set to have a potential (power supply potential) and a common second potential (ground potential).
b is connected. Further, the striped conductor layer and each bump 134
May be connected.

Further, in the above embodiment and the like, the first and second
As the solid conductor layers 126, 127, etc., the through holes 126H, 1
Although the solid conductor layer has a height of 27H or the like, but has a solid shape extending in the plane direction, that is, a flat solid conductor layer is shown. However, it spreads in the plane direction, and the first and second main surface side via conductors 132a, 132a,
132b and the first and second capacitor-side via conductors 130, 1
If the connection to the first and second capacitor-side via conductors 132a, 132b and the like and the first and second capacitor-side via conductors 130, 131 and the like can be easily converted. The shape is not limited to a flat plate shape, and for example, a form such as a stripe shape or a mesh shape can be adopted. Further, the first and second main surface side via conductors 132a, 132b and the like are in the form of stacked vias or through vias penetrating the plurality of resin insulating layers 122 and the like, but a wiring layer extending in the plane direction of the wiring board is interposed on the way. It can also be done.

[Brief description of the drawings]

FIG. 1 is a sectional view of a wiring board according to a first embodiment.

FIG. 2 is an explanatory diagram showing potentials at respective side terminals of chip capacitors arranged in a vertical and horizontal lattice.

FIG. 3 is a perspective explanatory view showing states of chip capacitors arranged in a vertical and horizontal lattice and directions of current flowing through side terminals.

FIG. 4 is an explanatory diagram of a method of manufacturing a wiring board according to the first embodiment, where (a) shows a core substrate body to be used;
(B) shows how chip capacitors are arranged in the core substrate body.

FIG. 5 is an explanatory sectional view of the method for manufacturing the wiring board according to the first embodiment, showing a state where a core substrate is completed.
The upper circle is an enlarged explanatory diagram showing a through hole portion, and the lower circle is an enlarged explanatory diagram showing a chip capacitor portion.

FIGS. 6A and 6B are explanatory views showing a cross section of a core substrate used for a wiring substrate according to Modification 1, in which FIG. 6A is a state in which a core substrate is completed by plating, and FIG. Shows a state where the filling is polished.

FIG. 7 is a sectional view of a wiring board according to a first modification;

FIG. 8 is a sectional view of a wiring board according to a second embodiment.

FIG. 9 is a cross-sectional view of a core board used for the wiring board according to the second embodiment.

FIG. 10 is a sectional view of a wiring board according to a second embodiment.

FIG. 11 is an explanatory diagram showing another example of the arrangement of chip capacitors and the potential of each side terminal.

FIG. 12 is a sectional view of a wiring board according to a third embodiment;

FIG. 13 is a sectional view of a core substrate used for the wiring substrate according to the third embodiment;

FIG. 14 is an explanatory view showing a conventional wiring board having a chip capacitor mounted on a main surface or a back surface of the substrate.

15A and 15B are explanatory diagrams showing the shape and structure of a chip capacitor, wherein FIG. 15A shows a type in which each electrode is taken out from two opposing side surfaces, and FIG. 15B shows a case in which a large number of terminals are formed on the side surface to take out electrodes. (C) shows the structure of the chip capacitor shown in (b).

[Explanation of symbols]

100, 200, 300, 500, 600 Wiring board 100A, 200A, 300A, 500A, 600A
Main surface 100B, 200B, 300B, 500B, 600B
Back 110, 210, 310, 510, 610 Core substrate 110A, 210A, 310A, 510A, 610A
Main surface of core substrate (core main surface) 110B, 210B, 310B, 510B, 610B
Lower surface of core substrate (core back surface) 111, 211, 311, 511, 611 Core substrate body 111, 211, 311, 513, 514, 515, 6
11 Core insulating layer 112, 212, 312, 512, 612 Through-hole conductor 113, 213, 313, 613 Chip capacitor 113u Upper surface of chip capacitor 115a, 215a, 315a, 415a, 615a
One side terminal (first potential side terminal, first capacitor terminal) 115b, 215b, 315b, 415b, 615b
The other side terminal (second potential side terminal, 115au, 115bu, 215au, 215bu, 3
15au, 315bu, 615au, 615bu Upper surface portion 116, 216, 316, 616 Insulating resin body 126, 127, 326, 327, 626, 627 Solid conductor layer 126, 326, 626 First solid conductor layer (first conversion conductor layer) 127, 327, 627 Second solid conductor layer (second conversion conductor layer) 130, 330 First capacitor side via conductor (first capacitor side connection line) 131, 331 Second capacitor side via conductor (second capacitor side connection line) 132a, 332a First main surface side via conductor (first main surface side connection wiring) 132b, 332b Second main surface side via conductor (second main surface side connection wiring) 134, 334 Bump (connection terminal) 134a, 334a First bump (first connection terminal) 134b, 334b Second bump (second connection terminal)

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 23/12 E

Claims (5)

[Claims] 1. A wiring board having a main surface and a back surface, comprising: a plurality of connection terminals formed on the main surface side and connectable to terminals of electronic components mounted on the main surface; A connection terminal including a number of first connection terminals having a first potential and a number of second connection terminals having a common second potential, and one of the electrodes being built in the wiring board, and one of the electrodes having a common first potential; The other electrodes are each connected to a common second potential, at least one first capacitor terminal connected to the one electrode, and at least one first capacitor terminal connected to the other electrode.
At least one chip capacitor having two second capacitor terminals; a second conversion conductor layer interposed between the chip capacitor and the connection terminal and extending in a plane direction; the second conversion conductor layer and the chip capacitor; A first conversion conductor layer interposed between the first conversion terminal and the first conversion conductor layer, extending from the first connection terminal toward the back side in the thickness direction of the wiring board, and insulating the second conversion conductor layer from each other; A first main-surface-side connection wiring electrically connected to the first conversion conductor layer; and a second connection terminal extending from the second connection terminal toward a back surface in the thickness direction of the wiring board. A second main surface side connection wire electrically connected to the first capacitor terminal, a first capacitor extending from the first capacitor terminal toward the main surface in the thickness direction of the wiring board, and connected to the first conversion conductor layer; A second connection conductor extending from the second capacitor terminal toward the main surface in the thickness direction of the wiring board and insulated from the first conversion conductor layer and connected to the second conversion conductor layer. A wiring board comprising: a capacitor-side connection wiring; 2. The wiring board according to claim 1, wherein the core has a core main surface and a core back surface, includes a core substrate main body made of one or a plurality of core insulating layers, and includes the chip capacitor. A wiring board comprising a board. 3. A wiring board having a main surface and a back surface, comprising: a plurality of connection terminals formed on the main surface and connectable to terminals of electronic components mounted on the main surface; A connection terminal including a plurality of first connection terminals having a first potential and a plurality of second connection terminals having a common second potential, a core main surface and a core back surface, and one or a plurality of core insulation members; A core substrate body composed of layers, and embedded in the core substrate body, one electrode is connected to a common first potential, and the other electrode is connected to a common second potential,
A plurality of first capacitor terminals connected to the one electrode,
And a core substrate including a plurality of chip capacitors having a plurality of second capacitor terminals connected to the other electrode; and a second conversion interposed between the core main surface of the core substrate and the connection terminals and extending in a planar direction. A conductor layer, a first conversion conductor layer located between the second conversion conductor layer and the core main surface of the core substrate and extending in a plane direction, and a back surface in the thickness direction of the wiring substrate from the first connection terminal. A first main surface side via conductor extending toward the side and electrically connected to the first conversion conductor layer while being insulated from the second conversion conductor layer, respectively; and the wiring from the second connection terminal. A second main surface side via conductor extending toward the rear surface side in the thickness direction of the substrate and electrically connected to the second conversion conductor layer; and a thickness of the wiring substrate from a first capacitor terminal of the chip capacitor. A first capacitor-side via conductor connected to the first conversion conductor layer and extending from the second capacitor terminal of the chip capacitor toward the main surface in the thickness direction of the wiring board; A second capacitor-side via conductor connected to the second conversion conductor layer while being insulated from the first conversion conductor layer. 4. A wiring board having a main surface and a back surface, comprising: a plurality of connection terminals formed on the main surface side and connectable to terminals of electronic components mounted on the main surface; A connection terminal including a plurality of first connection terminals having a first potential and a plurality of second connection terminals having a common second potential, a core main surface and a core back surface, and one or a plurality of core insulation members; A core substrate body composed of layers, and embedded in the core substrate body, one electrode is connected to a common first potential, and the other electrode is connected to a common second potential,
A plurality of first capacitor terminals connected to the one electrode,
And a core substrate including at least one chip capacitor having a plurality of second capacitor terminals connected to the other electrode; and a first conversion conductor located on the core main surface and connected to the first capacitor terminal and extending in a plane direction. A second conversion conductor layer interposed between the core main surface of the core substrate and the connection terminal and extending in a plane direction; and from the first connection terminal toward the back side in the thickness direction of the wiring substrate. A first main surface side via conductor extending and electrically connected to the first conversion conductor layer while being insulated from the second conversion conductor layer; and a thickness of the wiring board from the second connection terminal. A second main surface via conductor extending toward the rear surface in the direction and electrically connected to the second conversion conductor layer, respectively; and a thickness of the wiring board from a second capacitor terminal of the chip capacitor. It extends toward the main surface side, while insulating each from the first conversion conductor layer, a wiring substrate comprising: a second capacitor side via conductor connected to the second conversion conductor layer. 5. The wiring board according to claim 4, wherein: between the connection terminal and the core main surface of the core board.
A wiring board comprising at least one insulating layer, wherein the second conversion conductor layer is formed on a side surface of the main surface of the insulating layer that is in contact with the main surface of the core.