JPH1140618A - Film carrier and laminate type mounting body using the film carrier - Google Patents

Film carrier and laminate type mounting body using the film carrier

Info

Publication number
JPH1140618A
JPH1140618A JP9297476A JP29747697A JPH1140618A JP H1140618 A JPH1140618 A JP H1140618A JP 9297476 A JP9297476 A JP 9297476A JP 29747697 A JP29747697 A JP 29747697A JP H1140618 A JPH1140618 A JP H1140618A
Authority
JP
Japan
Prior art keywords
film carrier
mounting
base element
conductive circuit
contact portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9297476A
Other languages
Japanese (ja)
Other versions
JP3490601B2 (en
Inventor
Yasuo Nakatsuka
康雄 中塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nitto Denko Corp
Original Assignee
Nitto Denko Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nitto Denko Corp filed Critical Nitto Denko Corp
Priority to JP29747697A priority Critical patent/JP3490601B2/en
Priority to US09/080,454 priority patent/US6208521B1/en
Publication of JPH1140618A publication Critical patent/JPH1140618A/en
Application granted granted Critical
Publication of JP3490601B2 publication Critical patent/JP3490601B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
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    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit

Abstract

PROBLEM TO BE SOLVED: To provide a film carrier for easily fabricating a laminate type mounting body and the laminate type mounting body using the carrier. SOLUTION: A film carrier has film carrier elements 1 (1a to 1c) which are junctioned via bending parts 3 in the direction of each surface being extended. Contacts 6 for mounting are provided on a mounting surface 2 and semiconductor chips 8 are mounted. One of the film carrier elements is a base element 1a, one surface of which is a mounting surface 2 and another surface of which is a junction surface. Contact parts for junction are provided on the junction surface. Each contact part for mounting is junctioned with the contact part for junction through inner conductive circuit. After element mounting each film carrier element is piled up on the base element by folding bending parts to be a laminating whole body and a laminate type mounting body of which interlayer junction is completed is obtained. Conditions of the contact parts for mounting and for junction and conditions of resin sealing can variously be selected.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体素子を実装
するためのフィルムキャリア、およびそれに半導体素子
を実装して組み立てた積層型の半導体装置に関する。[0001] 1. Field of the Invention [0002] The present invention relates to a film carrier for mounting a semiconductor element, and a stacked semiconductor device in which the semiconductor element is mounted and assembled.

【０００２】[0002]

【従来の技術】電子機器の高性能化、高機能化、小型化
に対応するため、半導体素子（特にウエハから個々に切
り出した裸状態のＩＣのチップ）をフィルムキャリアに
実装し、さらにそれらを基板上に積層し接続した積層型
実装体が提案されている（特開平２−２９００４８号公
報参照）。2. Description of the Related Art In order to cope with higher performance, higher function and smaller size of electronic equipment, semiconductor elements (especially, bare IC chips individually cut out from a wafer) are mounted on a film carrier, and furthermore, they are mounted on a film carrier. There has been proposed a stacked mounting body which is stacked and connected on a substrate (see Japanese Patent Application Laid-Open No. 2-290048).

【０００３】従来の積層型実装体は、図８に示すよう
に、ＴＡＢテープ１枚毎に個別に半導体素子６１が実装
された後、これらＴＡＢテープが複数用いられて外部回
路基板６３上に積層され、各層のＴＡＢテープに設けら
れたリード６２が、各々外部回路基板６３の電極６４に
接続されている。As shown in FIG. 8, in a conventional stacked mounting body, after a semiconductor element 61 is individually mounted for each TAB tape, a plurality of these TAB tapes are used and stacked on an external circuit board 63. The leads 62 provided on the TAB tape of each layer are connected to the electrodes 64 of the external circuit board 63, respectively.

【０００４】[0004]

【発明が解決しようとする課題】しかしながら、上記の
ような積層型実装体は、積層前の段階、即ち、チップが
ＴＡＢテープ一枚毎に実装された段階では、各々のチッ
プはＴＡＢテープと共に互いに別々であり、持ち運びや
保管等の点で不便である。However, at the stage before lamination, that is, at the stage where the chips are mounted one by one on the TAB tape, each of the chips is attached together with the TAB tape. It is separate and inconvenient in terms of carrying and storage.

【０００５】また、上記構造では積層の各階毎に、外部
回路基板６３までのリード６２の折り曲げ形状・寸法を
変える必要があり、リード曲げ加工には高度の技術が必
要になるという問題もある。また、積層に際しては、各
層の半導体素子６１のリード６２と外部回路基板の電極
６４との位置合わせが困難である。また、リード６２と
外部回路基板の電極６４との接続には特殊な接合ツール
（治具）を使用しなければならないという問題もある。
また、ＴＡＢ実装に必要なＴＡＢテープは高価なため、
上記構造のように半導体素子を個別にＴＡＢ実装する場
合ではコストが上昇する。Further, in the above structure, it is necessary to change the bent shape and dimensions of the leads 62 up to the external circuit board 63 for each floor of the stack, and there is also a problem that a high technology is required for lead bending. In addition, in stacking, it is difficult to align the leads 62 of the semiconductor element 61 of each layer with the electrodes 64 of the external circuit board. There is also a problem that a special joining tool (jig) must be used to connect the leads 62 and the electrodes 64 of the external circuit board.
Also, the TAB tape required for TAB mounting is expensive,
When the semiconductor elements are individually TAB-mounted as in the above structure, the cost increases.

【０００６】本発明の課題は、上記問題を解決し、積層
型実装体を容易に作製でき得るフィルムキャリアおよび
これを用いた積層型実装体を提供することにある。An object of the present invention is to solve the above-mentioned problems and to provide a film carrier capable of easily manufacturing a laminated mount and a laminated mount using the same.

【０００７】[0007]

【課題を解決するための手段】本発明のフィルムキャリ
アは、下記（Ａ）のフィルムキャリア要素が、各々の面
が拡張する方向に屈曲部を介して複数接続され、そのな
かの一つのフィルムキャリア要素をベース要素とし、ベ
ース要素は、絶縁性基板の一方の面が半導体素子を実装
するための実装面であり、他方の面は外部回路基板との
接続用面であり、該接続用面には外部回路基板との接続
用接点部が設けられ、該接点部は導電回路と導通してお
り、ベース要素以外のフィルムキャリア要素は、屈曲部
を折り曲げることによってベース要素の上に重なり合い
全体が１つの積層体となることができ、内部の導電回路
は屈曲部内部を通ってベース要素内部の導電回路に接続
されていることを特徴とするものである。（Ａ）絶縁性
基板の内部に導電回路が設けられてなり、絶縁性基板の
少なくとも一方の面は半導体素子を実装するための実装
面であり、実装面には実装用接点部が設けられ、実装用
接点部は前記導電回路と導通しているフィルムキャリア
要素。The film carrier of the present invention comprises a plurality of film carrier elements of the following (A) connected via a bent portion in a direction in which each surface expands. The element is a base element, and the base element has one surface of an insulating substrate as a mounting surface for mounting a semiconductor element, and the other surface as a surface for connection with an external circuit board. Is provided with a contact portion for connection to an external circuit board, the contact portion is in conduction with the conductive circuit, and the film carrier element other than the base element overlaps the base element by bending the bent portion so that the whole is 1 And wherein the conductive circuit inside is connected to the conductive circuit inside the base element through the inside of the bend. (A) a conductive circuit is provided inside an insulating substrate, at least one surface of the insulating substrate is a mounting surface for mounting a semiconductor element, and a mounting contact portion is provided on the mounting surface; The mounting contact portion is a film carrier element that is electrically connected to the conductive circuit.

【０００８】本発明のフィルムキャリアは、特に、上記
（Ａ）のフィルムキャリア要素が、各実装面が同じ側と
なるよう屈曲部を介して複数接続されたものであり、上
記（Ａ）のフィルムキャリア要素は、該絶縁性基板の一
方の面を実装面とするものである。[0008] The film carrier of the present invention is, in particular, one in which a plurality of the film carrier elements of the above (A) are connected via a bent portion so that each mounting surface is on the same side. The carrier element has one surface of the insulating substrate as a mounting surface.

【０００９】また、本発明の積層型実装体は、上記本発
明のフィルムキャリアが用いられ、各フィルムキャリア
要素の実装面には半導体素子が実装され、屈曲部が折り
曲げられて、ベース要素以外の各フィルムキャリア要素
が、半導体素子を実装された状態で、ベース要素の接続
用面が積層の最下面となるようにして、ベース要素上に
重なり合って１つの積層体となっているものである。Further, the laminated mounting body of the present invention uses the above-described film carrier of the present invention, a semiconductor element is mounted on the mounting surface of each film carrier element, and a bent portion is bent to form a part other than the base element. Each of the film carrier elements overlaps on the base element so that the connection surface of the base element is the lowermost surface of the stack in a state where the semiconductor element is mounted, thereby forming one laminate.

【００１０】[0010]

【作用】本発明のフィルムキャリアは、積層すべき数だ
けのフィルムキャリア要素が一枚のフィルムキャリアと
して展開的に面拡張方向に接続され、屈曲部を介して複
数接続されて構成されている。従って、半導体素子の実
装が、一枚のフィルムキャリアに対する実装で完了す
る。従って、従来のように半導体素子毎にフィルムキャ
リアを用意し、段取り換えをする必要がなく、実装され
た半導体素子がバラバラになることもない。更に、屈曲
部を折り曲げるだけで複数の半導体素子を一体的に積層
することができ、各半導体素子の位置合わせも容易に行
える。The film carrier according to the present invention is constructed by connecting a plurality of film carrier elements as many as the number of layers to be laminated as a single film carrier in a developing manner in a plane extending direction and a plurality of connecting members via a bent portion. Therefore, mounting of the semiconductor element is completed by mounting on one film carrier. Therefore, it is not necessary to prepare a film carrier for each semiconductor element and change the setup as in the related art, and the mounted semiconductor elements do not fall apart. Furthermore, a plurality of semiconductor elements can be integrally laminated only by bending the bent portion, and the positioning of each semiconductor element can be easily performed.

【００１１】また、本発明の積層型実装体では、実装さ
れた各半導体素子は、既に、絶縁性基板内部の導電回路
によって、ベース要素の実装用面に設けられた実装用接
点部に配線され、層間の接続は完了している。従来の積
層型実装体では、個々のフィルムキャリアを外部回路基
板上に積層し、各層と外部回路基板とをリードによって
接続して初めて積層型実装体が成立する。これに対し
て、本発明の積層型実装体では、フィルムキャリアを折
り重ねた時点で、外部回路基板との接続の前に、層間の
接続が完了しており、しかも、外部との接続用接点が１
つの面に集中しており、積層型実装体が成立しているの
である。これを従来のように外部回路基板上に実装する
ことによって、従来と互換性のある外部端子を有する積
層型実装体とすることができる。Further, in the stacked mounting body of the present invention, each mounted semiconductor element is already wired to the mounting contact portion provided on the mounting surface of the base element by the conductive circuit inside the insulating substrate. The connection between the layers has been completed. In a conventional multilayer mounting body, a multilayer mounting body is established only when individual film carriers are stacked on an external circuit board and each layer and the external circuit board are connected by leads. On the other hand, in the stacked mounting body of the present invention, when the film carrier is folded, the connection between the layers is completed before the connection with the external circuit board, and the contact for connection with the outside is provided. Is 1
It is concentrated on one side, and a stacked mounting body is established. By mounting this on an external circuit board as in the prior art, a laminated mounting body having external terminals compatible with the related art can be obtained.

【００１２】本発明の積層型実装体と外部回路基板との
接続は、ベース要素の接続用接点を利用するだけでよ
い。即ち、半導体素子毎にリードで外部回路基板に接続
する必要がないため、リード曲げ加工の高度な技術や手
間、リードと外部回路基板との位置合わせ、特殊ツール
の必要といった従来の問題点を全て解消することがで
き、外部回路基板との接続が容易に行える。The connection between the stacked mounting body of the present invention and the external circuit board can be made only by using the connection contacts of the base element. In other words, since there is no need to connect the external circuit board with leads for each semiconductor element, all the conventional problems such as advanced techniques and labor for lead bending, alignment between the leads and the external circuit board, and the need for special tools are all required. The connection with the external circuit board can be easily performed.

【００１３】[0013]

【発明の実施の形態】以下、本発明を、図を用いて詳細
に説明する。本発明のフィルムキャリアは、図１（ａ）
に例示するように、フィルムキャリア要素１（１ａ、１
ｂ、１ｃ）が、各々の面が拡張する方向に屈曲部３を介
して複数接続された構造を有するものである。図１の例
では、３つのフィルムキャリア要素が、一直線状に屈曲
部を介して接続されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 (a) shows a film carrier of the present invention.
As illustrated in FIG. 1, the film carrier element 1 (1a, 1a
b, 1c) have a structure in which a plurality of surfaces are connected via the bent portion 3 in a direction in which each surface expands. In the example of FIG. 1, three film carrier elements are connected in a straight line via a bent portion.

【００１４】フィルムキャリア要素は、例えば、図１
（ｂ）におけるフィルムキャリア要素１ｂのように、絶
縁性基板５の内部に導電回路４ｂが設けられた構造を有
し、絶縁性基板５の少なくとも一方の面（図１の例では
一方の面のみ）は、半導体素子を実装するための実装面
２となっている。実装面２には半導体素子を実装するた
めの実装用接点部６が設けられており、該実装用接点部
６は直下の導通路によって導電回路４ｂと導通してい
る。The film carrier element is, for example, shown in FIG.
As in the film carrier element 1b in (b), the conductive circuit 4b is provided inside the insulating substrate 5 and at least one surface of the insulating substrate 5 (only one surface in the example of FIG. 1). ) Is a mounting surface 2 for mounting a semiconductor element. A mounting contact portion 6 for mounting a semiconductor element is provided on the mounting surface 2, and the mounting contact portion 6 is electrically connected to the conductive circuit 4b by a conductive path immediately below.

【００１５】接続されたフィルムキャリア要素１ａ〜１
ｃのうち、一つのフィルムキャリア要素１ａをベース要
素１ａとする。ベース要素１ａは、絶縁性基板５の一方
の面が半導体素子を実装するための実装面２となってい
る点では他のフィルムキャリア要素と同様であるが、絶
縁性基板５の他方の面が外部回路基板との接続用面とな
っている点で他のフィルムキャリア要素と異なる。ベー
ス要素の接続用面には、外部回路基板への接続用接点部
７が設けられ、該接点部７は内部方向直下の導電回路４
ａと導通している。The connected film carrier elements 1a-1
Of c, one film carrier element 1a is the base element 1a. The base element 1a is similar to the other film carrier elements in that one surface of the insulating substrate 5 is a mounting surface 2 for mounting a semiconductor element, but the other surface of the insulating substrate 5 is It differs from other film carrier elements in that it is a surface for connection to an external circuit board. The connection surface of the base element is provided with a contact portion 7 for connection to an external circuit board, and the contact portion 7 is connected to the conductive circuit 4 just below the inside.
a.

【００１６】ベース要素１ａ以外のフィルムキャリア要
素１ｂ、１ｃは、屈曲部３を折り曲げることによって、
即ち、屈曲部に折り目がくるようにフィルムキャリア全
体を折り重ねることによって、ベース要素１ａの上に重
なり合い、全体が１つの積層体となることができるよう
になっている。これらのフィルムキャリア要素１ｂ、１
ｃの内部の導電回路４ｂ、４ｃは、各々、屈曲部３の内
部を通ってベース要素内部の導電回路４ａに接続されて
いる。The film carrier elements 1b and 1c other than the base element 1a are bent by bending the bent portion 3.
That is, by folding the entire film carrier so that the bent portion has a fold, the film carrier overlaps the base element 1a, and the entire film carrier can be formed into one laminate. These film carrier elements 1b, 1
The conductive circuits 4b and 4c inside c are connected to the conductive circuit 4a inside the base element through the inside of the bent portion 3, respectively.

【００１７】上記のような構成とすることによって、上
記作用の説明で述べたように、積層型実装体を容易に形
成し得るフィルムキャリアとなる。With the above-described configuration, as described in the above description of the operation, a film carrier that can easily form a stacked mounting body is obtained.

【００１８】フィルムキャリア要素の形状は、特に限定
されず、円形、方形やその他の多角形、異形等が挙げら
れる。但し、半導体素子の形状が方形であるため、実装
密度を高めるためには、フィルムキャリア要素の形状も
同様に図１（ａ）に示すように方形が好ましい。また、
フィルムキャリア要素の形状は、互いに異なる形状であ
ってもよいが、一つの積層体を形成する点から、全て合
同な形状とし、かつ、折り重ねたときに外形が一致する
ような向きで接続するのが好ましい。The shape of the film carrier element is not particularly limited, and examples thereof include a circle, a square, other polygons, and irregular shapes. However, since the shape of the semiconductor element is rectangular, the shape of the film carrier element is also preferably rectangular as shown in FIG. Also,
The shapes of the film carrier elements may be different from each other, but from the viewpoint of forming one laminated body, all are formed into a congruent shape, and are connected in a direction such that the outer shapes match when folded. Is preferred.

【００１９】接続すべきフィルムキャリア要素の数は、
目的の積層の数に応じて決定すればよく、特に限定され
るものではない。また、フィルムキャリア要素の互いの
配置のパターン（接続のパターン）は、ベース要素以外
のフィルムキャリア要素がベース要素上に重なり合い、
全体で一つの積層体となり得るパターンであればよく、
例えば、図１に示すような一直線状のパターンや、図２
に示すような十字状のパターンが挙げられる。The number of film carrier elements to be connected is
What is necessary is just to determine according to the number of target laminations, and it is not specifically limited. Further, the pattern of the arrangement of the film carrier elements (the pattern of connection) is such that the film carrier elements other than the base element overlap on the base element,
Any pattern that can be a single layered body as a whole,
For example, a linear pattern as shown in FIG.
And a cross-shaped pattern as shown in FIG.

【００２０】図１に示す例は、フィルムキャリア要素の
外形が全て合同な方形であって、３つのフィルムキャリ
ア要素が直列状に接続された例である。同図の例では、
中央のフィルムキャリア要素がベース要素である。The example shown in FIG. 1 is an example in which the outer shapes of the film carrier elements are all congruent squares, and three film carrier elements are connected in series. In the example of FIG.
The central film carrier element is the base element.

【００２１】また、図２に示す例は、５つのフィルムキ
ャリア要素が、面が拡張する方向に単純な十字状となる
よう接続されたパターンの例である。同図の例では、十
字状の中央のフィルムキャリア要素がベース要素であ
る。フィルムキャリア要素の外形は全て合同な方形とな
っており、外側の４つのフィルムキャリア要素は、中央
のベース要素上へ折り重ねたときに外形が互いに一致す
るように、ベース要素１ａの外周四辺に各１個ずつ屈曲
部３を介して接続され、ベース要素１ａを中心として十
字を描いている。The example shown in FIG. 2 is an example of a pattern in which five film carrier elements are connected so as to form a simple cross in the direction in which the plane expands. In the example shown in the figure, the cross-shaped central film carrier element is the base element. The outer shapes of the film carrier elements are all congruent squares, and the four outer film carrier elements are arranged on the four sides of the outer periphery of the base element 1a so that the outer shapes coincide when folded on the central base element. Each one is connected via the bent portion 3 and a cross is drawn around the base element 1a.

【００２２】図１、図２に示す例は、ベース要素を中心
とした直列状、十字状の一例であるが、ベース要素１ａ
の外周四辺には、フィルムキャリア要素１ｂをどのよう
に接続してもよく、接続されたフィルムキャリア要素１
ｂにさらに他のフィルムキャリア要素を接続し自在に延
長してもよい。また、ベース要素は、必ずしもフィルム
キャリア要素同士の配列の中心に位置する必要はなく、
端に位置していてもよい。The example shown in FIGS. 1 and 2 is an example of a series and a cross with the base element as the center.
The film carrier element 1b may be connected to the outer four sides of the film carrier element in any manner.
Another film carrier element may be connected to b to extend freely. Also, the base element need not necessarily be located at the center of the array of film carrier elements,
It may be located at the end.

【００２３】フィルムキャリア要素を形成する絶縁性基
板の材料は、特に限定されるものではなく、従来より一
般的なフィルムキャリアに使用されている樹脂材料を利
用することができる。図１、２の例に示したように、屈
曲部をフィルムキャリア要素と共通の絶縁性基板で形成
するのであるならば、折り曲げ性、機械的強度に優れて
いる等の点からポリイミド樹脂が好ましい。The material of the insulating substrate forming the film carrier element is not particularly limited, and a resin material conventionally used for a general film carrier can be used. As shown in the examples of FIGS. 1 and 2, if the bent portion is formed by an insulating substrate common to the film carrier element, a polyimide resin is preferable from the viewpoint of excellent bending property and mechanical strength. .

【００２４】フィルムキャリア要素に設けられる導電回
路は、絶縁性基板の内部でありかつ接点部と導通し得る
位置に設けられていればよい。導電回路の形成方法とし
ては公知の回路パターン形成方法が利用できる。導電回
路を絶縁性基板の内部に設ける方法としては、例えば、
初めに樹脂層の一方の面に金属層を設け、この金属層を
エッチングによって導電回路とし、その上に更に樹脂層
を形成して設ける方法が挙げられる。ベース要素以外の
フィルムキャリア要素の内部の導電回路は、屈曲部の内
部を通ってベース要素内部の導電回路に接続される。The conductive circuit provided in the film carrier element may be provided inside the insulating substrate and at a position where it can be electrically connected to the contact portion. As a method for forming the conductive circuit, a known circuit pattern forming method can be used. As a method of providing a conductive circuit inside an insulating substrate, for example,
First, there is a method in which a metal layer is provided on one surface of a resin layer, the metal layer is formed into a conductive circuit by etching, and a resin layer is further formed and provided thereon. The conductive circuit inside the film carrier element other than the base element is connected to the conductive circuit inside the base element through the inside of the bend.

【００２５】フィルムキャリア要素は、少なくとも一方
の面、即ち、その片面または両面を実装面とする。ただ
し、ベース要素だけは、一方の面だけが実装面であり、
他方の面は接続用面である。ベース要素以外のフィルム
キャリア要素が片面だけを実装面とする場合、その実装
面をベース要素の実装面に対して同じ側の面とするか裏
面側の面とするかは、フィルムキャリア要素毎に自由で
あり、当該フィルムキャリアの折り方や特別な用途に応
じて選択すればよい。通常は、図１、図２に示すよう
に、全ての実装面を同じ側の面に揃えた方が、半導体素
子を実装する上で好ましいものとなる。また、片面だけ
を実装面とするフィルムキャリア要素と、両面を実装面
とするフィルムキャリア要素とを併用してもよい。The film carrier element has at least one surface, that is, one or both surfaces, as a mounting surface. However, only one side of the base element is the mounting side,
The other surface is a connection surface. When only one side of the film carrier element other than the base element is used as the mounting surface, whether the mounting surface is the same side as the mounting surface of the base element or the back side is determined for each film carrier element. It is optional and may be selected according to the method of folding the film carrier or a special use. Normally, as shown in FIGS. 1 and 2, it is preferable to arrange all mounting surfaces on the same side surface in mounting a semiconductor element. Further, a film carrier element having only one mounting surface and a film carrier element having both mounting surfaces may be used in combination.

【００２６】フィルムキャリア要素の実装用接点部およ
びベース要素の接続用接点部は、接触対象となる半導体
素子、外部回路基板に対して電気的な接触を行い得るも
のであればよい。これら接点部の態様としては、絶縁性
基板の面から接点材料が半球状・ドーム状に突起した態
様（所謂、バンプ接点）が代表的であるが、必ずしも絶
縁性基板の面から突起する必要はなく、接続対象の形状
や接続の方法に応じて、絶縁性基板の面と同一面、凹面
を形成するものでもよい。さらには、絶縁性基板の面に
開口部を設け、その開口内部に導電回路の一部を露出さ
せ、露出した導電回路を接点として用いる態様であって
もよい。実装用接点部が、開口部の内部に露出した導電
回路の態様である場合、そのような態様の例として、図
３（ａ）、（ｂ）に示すものが挙げられる。The mounting contact of the film carrier element and the connecting contact of the base element may be any as long as they can make electrical contact with the semiconductor element and the external circuit board to be contacted. As a mode of these contact portions, a mode in which the contact material protrudes in a hemispherical / dome shape from the surface of the insulating substrate (a so-called bump contact) is typical, but it is not always necessary to protrude from the surface of the insulating substrate. Instead, the same surface as the surface of the insulating substrate or a concave surface may be formed according to the shape of the connection target and the connection method. Further, an opening may be provided on the surface of the insulating substrate, a part of the conductive circuit may be exposed inside the opening, and the exposed conductive circuit may be used as a contact. When the mounting contact portion is in the form of a conductive circuit exposed inside the opening, examples of such a form include those shown in FIGS. 3 (a) and 3 (b).

【００２７】図３（ａ）に示す例は、１つの半導体素子
に対して、その半導体素子の電極の数だけ開口部が設け
られた態様である。また、ベース要素の接続用接点部も
実装用接点部と同様の態様である。同図は、ベース要素
の部分だけを拡大して示している。実装面には、実装用
接点部が設けられるべき位置に対応して開口部６ａが個
々に設けられ、その内部底面には導電回路が露出してい
る。また、接続用面も同様に、接続用接点部が設けられ
るべき位置に対応して開口部７ａが個々に設けられ、そ
の内部底面には導電回路４ａが露出している。実装され
る半導体素子８は、接着剤層１３ａを介して実装面に装
着され、該素子の上面側に設けられた電極と、各実装用
接点部の開口内の導電回路とが、内部接続用のワイヤー
Ｗによって接続されている（ワイヤーボンディング）。In the example shown in FIG. 3A, one semiconductor element is provided with openings as many as the electrodes of the semiconductor element. Also, the connection contact portion of the base element is in the same mode as the mounting contact portion. The figure shows only the base element in an enlarged manner. Openings 6a are individually provided on the mounting surface corresponding to positions where the mounting contact portions are to be provided, and the conductive circuit is exposed on the inner bottom surface. Similarly, on the connection surface, openings 7a are individually provided corresponding to positions where connection contact portions are to be provided, and the conductive circuit 4a is exposed on the inner bottom surface thereof. The semiconductor element 8 to be mounted is mounted on a mounting surface via an adhesive layer 13a, and an electrode provided on the upper surface side of the element and a conductive circuit in an opening of each mounting contact portion are connected for internal connection. (Wire bonding).

【００２８】図３（ｂ）の例は、１つの半導体素子に対
して開口部が１つだけ対応して設けられる態様である。
開口部６ｂの開口形状は、実装すべき半導体素子８をは
め込むことが可能な形状であり、該開口部の内部に露出
した導電回路４ａは、はめ込まれる半導体素子の電極に
対して、直接的に接続が可能な位置に配置されている。
他方、はめ込まれる半導体素子の下面側には電極が設け
られており、各々の電極パッドと導電回路とは位置的に
対応しており、直接的に接触している。FIG. 3B shows an example in which only one opening is provided for one semiconductor element.
The opening 6b has such a shape that the semiconductor element 8 to be mounted can be fitted therein, and the conductive circuit 4a exposed inside the opening directly contacts the electrode of the semiconductor element to be fitted. It is located where it can be connected.
On the other hand, electrodes are provided on the lower surface side of the semiconductor element to be fitted, and each electrode pad and the conductive circuit correspond in position and are in direct contact with each other.

【００２９】接点部の形成方法は、公知の形成方法を利
用してよい。例えばバンプ接点であるならば、絶縁性基
板上における接点部を形成すべき位置に、導電回路が露
出するように孔を設け、導電回路を負極として電解めっ
きによって該孔内に良導体金属を析出させて充填し、更
に該金属を突起させて形成する方法が挙げられる。導電
回路は、接点部を形成すべき位置の内部方向直下または
接点部と導通が可能なように接点部の近傍を通過するよ
うに設計される。As a method for forming the contact portion, a known forming method may be used. For example, if it is a bump contact, a hole is provided at a position on the insulating substrate where the contact portion is to be formed so that the conductive circuit is exposed, and a good conductive metal is deposited in the hole by electrolytic plating using the conductive circuit as a negative electrode. And then forming the metal by protruding. The conductive circuit is designed to pass immediately below the position where the contact portion is to be formed or in the vicinity of the contact portion so as to be able to conduct with the contact portion.

【００３０】また、開口部の内部に導電回路を露出させ
る方法の一例を挙げると、既に銅箔と密着し被覆してい
る絶縁性基板に対しては、レーザー加工、フォトリソグ
ラフィー加工、化学エッチング加工等を用いる。一般的
には紫外域に発振波長を有する紫外レーザーを用いた開
口加工が好ましい。また、露出している銅箔面に対して
は、接着剤を用いて、既に穿孔加工の施されている絶縁
性フィルムを張り合わせることによって、開口内の底部
に導電回路が露出した構造とする方法が挙げられる。Further, as an example of a method of exposing a conductive circuit inside the opening, laser processing, photolithography processing, and chemical etching processing are performed on an insulating substrate which is already in close contact with and covered with a copper foil. And so on. Generally, aperture processing using an ultraviolet laser having an oscillation wavelength in the ultraviolet region is preferable. Also, the conductive circuit is exposed at the bottom in the opening by bonding an insulating film that has already been perforated to the exposed copper foil surface using an adhesive. Method.

【００３１】接点部は、図３（ａ）に示すような、開口
部の内部に導電回路が露出した態様をもとに、さらに該
開口部毎に半田ボールを形成した態様としてもよい。半
田ボールはバンプ接点の一種であるが、先に説明したバ
ンプ接点がめっきによる析出で成長し形成されるのに対
して、半田ボールは、各開口部毎に固形の半田の球状物
を配置しリフロー処理によって開口部内に充填しかつ接
続用面から略球状に突起させたものである。実装用接点
部・接続用接点部を半田ボールの態様とすることによっ
て、半導体素子の実装や外部回路基板との接続におい
て、従来の積層型実装体と同じ実装方法、例えば、リフ
ロー半田付け方法を容易に用いることができる。The contact portion may have a form in which the conductive circuit is exposed inside the opening as shown in FIG. 3A, and further a form in which a solder ball is formed for each opening. A solder ball is a type of bump contact, but the bump contact described above is grown and formed by deposition by plating, whereas a solder ball is a solid solder ball placed at each opening. The opening is filled in the opening by reflow treatment and is projected substantially spherically from the connection surface. By making the mounting contact portion and the connection contact portion in the form of solder balls, the same mounting method as that of a conventional multilayer mounting body, for example, a reflow soldering method can be used in mounting a semiconductor element or connecting to an external circuit board. Can be used easily.

【００３２】開口部の内部に露出した導電回路の表面に
は、半田ボールの形成に対して、また、ワイヤーボンデ
ィング法におけるワイヤーの接続に対して、接続の信頼
性を向上させることを目的として、金、銀、パラジウ
ム、または下層をニッケル表層を金とする積層構造な
ど、良導体であり金属接合の可能な金属による１層以上
の被覆層をさらに形成することが好ましい。On the surface of the conductive circuit exposed inside the opening, for the purpose of improving the reliability of connection with respect to the formation of solder balls and the connection of wires in the wire bonding method, It is preferable to further form one or more coating layers of a metal that is a good conductor and can be bonded to a metal, such as a laminated structure of gold, silver, palladium, or a lower layer having a nickel surface layer of gold.

【００３３】屈曲部は、ベース要素の内部の導電回路と
それ以外のフィルムキャリア要素の内部の導電回路とを
電気的に接続するための導電回路をその内部に有するも
のであり、折り曲げ可能に構成されたものであればよ
い。The bent portion has a conductive circuit for electrically connecting the conductive circuit inside the base element and the conductive circuit inside the other film carrier element, and is configured to be bendable. Whatever is done is good.

【００３４】屈曲部は、屈曲に好適な材料を用いて基板
を別途形成しフィルムキャリア要素に接続されるもので
あってよく、また、図１の例のように、フィルムキャリ
ア要素の絶縁性基板を延長し、連続した一枚の絶縁性基
板として一体的に形成されるものであってもよい。図１
のような態様は、取り扱いの点で好ましい。また、フィ
ルムキャリア要素となる領域と屈曲部となる領域とが一
体となった一枚の絶縁性基板に対して、導電回路を一括
して設け、フィルムキャリア要素となる領域に接点部を
設けるだけで本発明のフィルムキャリアを得ることがで
き、製造の容易性の点でも好ましい態様である。The bent portion may be formed separately from the substrate by using a material suitable for bending and connected to the film carrier element. Also, as shown in the example of FIG. May be extended to be integrally formed as one continuous insulating substrate. FIG.
Such an embodiment is preferable in terms of handling. Further, a conductive circuit is collectively provided on a single insulating substrate in which a region serving as a film carrier element and a region serving as a bent portion are integrated, and a contact portion is provided in a region serving as a film carrier element. Thus, the film carrier of the present invention can be obtained, which is a preferable embodiment also from the viewpoint of ease of production.

【００３５】屈曲部の内部の導電回路は、図１の例に示
すように、フィルムキャリア要素内部の導電回路がその
まま延長されたものとして形成されてもよい。As shown in the example of FIG. 1, the conductive circuit inside the bent portion may be formed by extending the conductive circuit inside the film carrier element as it is.

【００３６】屈曲部の位置は、前述したフィルムキャリ
ア要素の位置関係に合わせて決定すればよい。屈曲部の
長さ（フィルムキャリア要素間の距離）は、実装する半
導体素子の大きさや数、フィルムキャリア要素の厚み、
積層数に応じて決定すればよい。The position of the bent portion may be determined according to the above-described positional relationship of the film carrier elements. The length of the bent portion (the distance between the film carrier elements) depends on the size and number of the semiconductor elements to be mounted, the thickness of the film carrier element,
What is necessary is just to determine according to the number of laminations.

【００３７】次に、本発明のフィルムキャリアを用いた
積層型実装体を説明する。本発明では、本発明のフィル
ムキャリアを折り重ね、積層体とした状態のものを積層
型実装体と呼ぶ。半導体素子が実装されたものが単に積
層されただけでなく、外部接続用の接点部が積層の最外
面に確保され、それに対する各層の半導体素子の接続が
完了しているからである。図４はその一例を示す図であ
って、フィルムキャリアには、図１に示した態様のもの
を用いている。Next, a laminated package using the film carrier of the present invention will be described. In the present invention, a laminate in which the film carrier of the present invention is folded to form a laminate is referred to as a laminate mount. This is because not only the semiconductor elements mounted thereon are simply stacked, but also a contact portion for external connection is secured on the outermost surface of the stack, and the connection of the semiconductor element of each layer to the external connection is completed. FIG. 4 is a view showing one example, and the film carrier of the embodiment shown in FIG. 1 is used.

【００３８】図４（ａ）は、フィルムキャリアの屈曲部
３を折り曲げる前の状態を示している。各フィルムキャ
リア要素１（１ａ〜１ｃ）の実装面２には半導体素子８
が各々実装されている。半導体素子８は、実装用接点部
６（バンプ接点）を介して導電回路（４ａ〜４ｃ）と導
通・接続されている。半導体素子と実装面との間隙には
接着剤１３が充填され、これらを接着している。FIG. 4A shows a state before the bending portion 3 of the film carrier is bent. The semiconductor element 8 is mounted on the mounting surface 2 of each film carrier element 1 (1a to 1c).
Are implemented respectively. The semiconductor element 8 is conductively connected to the conductive circuits (4a to 4c) via the mounting contact 6 (bump contact). An adhesive 13 is filled in the gap between the semiconductor element and the mounting surface, and these are adhered.

【００３９】図４（ｂ）は、図４（ａ）に示したもの
が、屈曲部３で折り曲げられて、本発明の積層型実装体
となった状態を示している。図４（ａ）に示す半導体素
子を実装された状態から、ベース要素１ａの接続用面が
積層の最下面となるようにして、フィルムキャリア要素
１ｂ、１ｃをベース要素１ａ上に順次折り重ね、一つの
積層体を形成することで本発明の積層型実装体１０が形
成されている。図４（ｂ）の例では、ベース要素１ａ以
外のフィルムキャリア要素１ｂ、１ｃは、実装面２をベ
ース要素１ａ側に向けて重なりあっている。FIG. 4 (b) shows a state where the one shown in FIG. 4 (a) is bent at the bent portion 3 to form a stacked mounting body of the present invention. From the state in which the semiconductor element shown in FIG. 4A is mounted, the film carrier elements 1b and 1c are sequentially folded on the base element 1a such that the connection surface of the base element 1a is the lowermost surface of the stack. By forming one stacked body, the stacked mounting body 10 of the present invention is formed. In the example of FIG. 4B, the film carrier elements 1b and 1c other than the base element 1a overlap with the mounting surface 2 facing the base element 1a.

【００４０】半導体素子が実装された状態のフィルムキ
ャリアをどのように折り重ねるかは限定されない。例え
ば、フィルムキャリア要素が直列状に接続される場合で
説明するならば、実装面が全て同じ側の面にある場合に
は、「６」の字形のように渦巻きを基本とする折り重ね
方（図４（ｂ）の例）が挙げられる。また、実装面が互
いに異なる面にある場合には「Ｓ」の字形のようにジグ
ザグを基本とする折り重ね方も可能である。さらにこれ
らを複合した折り重ね方に加えて、フィルムキャリア要
素が十字状に接続される態様の折り重ね、十字状からさ
らに分岐して接続される態様の折り重ねを考慮すると、
折り重ね方のパターンは無限に存在するが、用途に応じ
て自由に選択してよい。How to fold the film carrier on which the semiconductor element is mounted is not limited. For example, in the case where the film carrier elements are connected in series, if all the mounting surfaces are on the same side, a folding method based on a spiral like a “6” ( FIG. 4B). Further, when the mounting surfaces are on different surfaces, a folding method based on zigzag like an “S” shape is also possible. Furthermore, in addition to the folding method in which these are combined, in consideration of the folding in which the film carrier elements are connected in a cross shape, and the folding in which the film carrier elements are further branched and connected from the cross shape,
There are endless patterns of folding, but they may be freely selected according to the application.

【００４１】図４に示すような積層型実装体を形成する
に際しては、折り重ねられた各層を隣合った層同士互い
に接着してもよい。図５の例では、図４に示す積層型実
装体１０において、ベース要素１ａに実装されている半
導体素子８ａと、ベース要素上に折り重ねられて次層と
なったフィルムキャリア要素１ｂに実装されている半導
体素子８ｂとが、接着剤層１４ａを介して互いに接着さ
れている。また、他のフィルムキャリア要素１ｃに実装
されている半導体素子８ｃは、下層側のフィルムキャリ
ア要素１ｂの絶縁性基板に接着剤層１４ｂを介して接着
されている。In forming a stacked package as shown in FIG. 4, adjacent layers may be bonded to each other. In the example of FIG. 5, in the stacked mounting body 10 shown in FIG. 4, the semiconductor element 8a mounted on the base element 1a and the film carrier element 1b folded on the base element and formed as the next layer are mounted. Semiconductor element 8b is bonded to each other via an adhesive layer 14a. The semiconductor element 8c mounted on the other film carrier element 1c is bonded to the insulating substrate of the lower film carrier element 1b via an adhesive layer 14b.

【００４２】上記各層間に用いる接着剤、ワイヤーボン
ディング時の素子装着用の接着剤、実装された半導体素
子とフィルムキャリア要素との間隙に充填する接着剤と
しては、一般的な半導体実装体に使用される公知の接着
剤を利用できる。The adhesive used between the above layers, the adhesive for mounting the element at the time of wire bonding, and the adhesive filling the gap between the mounted semiconductor element and the film carrier element may be used for general semiconductor mounted bodies. A known adhesive can be used.

【００４３】本発明の積層型実装体は、フィルムキャリ
アに半導体素子を実装し折り重ねたそのままの状態でも
よいが、樹脂を用いて種々の封止を施してもよい。図５
に示す例は、樹脂封止の一態様である。同図の例では、
本発明の積層型実装体１０全体が、ベース要素１ａの接
続用面だけを露出させ、それ以外の部分が樹脂９で封止
され、パッケージ化された装置となっている。The laminated mounting body of the present invention may be in a state in which a semiconductor element is mounted on a film carrier and folded, or may be variously sealed using a resin. FIG.
Is an embodiment of resin sealing. In the example of FIG.
The entire laminated mounting body 10 of the present invention exposes only the connection surface of the base element 1a, and the other parts are sealed with the resin 9 to form a packaged device.

【００４４】図６に示す例は、樹脂封止の他の態様であ
る。図６（ａ）は、フィルムキャリアの屈曲部３を折り
曲げる前の状態を示している。図６（ａ）の例では、半
導体素子８ａ、８ｂ、８ｃは、図３（ａ）に示すように
ワイヤーボンディング法によってフィルムキャリアに実
装され、その段階で樹脂９ａ、９ｂ、９ｃによって個々
に封止されている。図６（ｂ）は、図６（ａ）に示した
フィルムキャリアが折り重ねられ、本発明の積層型実装
体となった状態を示している。屈曲部を折り曲げ、互い
に重なり合ったフィルムキャリア要素は、接着剤層１４
ａ、１４ｂによって固定され、１つの積層体となってい
る。The example shown in FIG. 6 is another mode of resin sealing. FIG. 6A shows a state before bending the bent portion 3 of the film carrier. In the example of FIG. 6A, the semiconductor elements 8a, 8b and 8c are mounted on a film carrier by a wire bonding method as shown in FIG. 3A, and are individually sealed with resins 9a, 9b and 9c at that stage. Has been stopped. FIG. 6B shows a state in which the film carrier shown in FIG. 6A is folded to form a stacked mounting body of the present invention. The film carrier elements, which bend the bends and overlap one another, form an adhesive layer 14
a, 14b to form one laminated body.

【００４５】封止するための樹脂は、一般的な半導体素
子の封止に使用される公知の樹脂材料を利用できる。As a resin for sealing, a known resin material used for sealing a general semiconductor element can be used.

【００４６】本発明の積層型実装体は、それ自体単独で
半導体装置として機能するが、これをさらに外部回路基
板に接続することによって、外部接続用の端子配列など
の点で、図８に示すような従来の積層型実装体に対して
互換性のある積層型実装体となる。図７は、図５の積層
型実装体１０を外部回路基板１１に接続し、全体を従来
品と互換性のある積層型実装体とした例である。ベース
要素１ａの接続用接点部７が、外部回路基板１１のラン
ド部（導電性の接続対象部位）１２に接続されて導通し
ている。同図に示す例は、実装用接点部・接続用接点部
がバンプ接点であり、樹脂封止は積層体全体を一体的に
封止した態様であるが、これら接点、接続法、封止など
の態様を、上記説明の他の態様と各々入れ替え、任意に
組み合わせてよい。Although the stacked mounting body of the present invention functions as a semiconductor device by itself, it is further connected to an external circuit board to provide a terminal arrangement for external connection as shown in FIG. Such a multilayer mounting body is compatible with the conventional multilayer mounting body. FIG. 7 shows an example in which the multilayer mounting body 10 of FIG. 5 is connected to an external circuit board 11, and the whole is a multilayer mounting body compatible with a conventional product. The connection contact portion 7 of the base element 1a is connected to a land portion (conductive connection target portion) 12 of the external circuit board 11 and is in conduction. In the example shown in the figure, the mounting contact portion and the connection contact portion are bump contacts, and the resin sealing is a mode in which the entire laminate is integrally sealed. May be interchanged with the other embodiments described above, and may be arbitrarily combined.

【００４７】図７に示した態様のように外部回路基板に
接続し新たな積層型実装体とする場合、樹脂封止は、前
工程では行わず、外部回路基板に接続した後に外部回路
基板を含めた状態で行なう態様としてもよい。In the case of connecting to an external circuit board as in the embodiment shown in FIG. 7 to form a new multilayer mounting body, resin sealing is not performed in the previous process, and after connecting to the external circuit board, the external circuit board is connected. It is good also as a mode performed in the state where it included.

【００４８】[0048]

【実施例】以下、実施例を挙げて本発明を具体的に示
す。 実施例１ 本実施例では、図１に示すフィルムキャリアについて製
作を行い、次に、このフィルムキャリアを用いて図５に
示す積層型実装体を製作した。図１に示す態様は、フィ
ルムキャリア要素を直列状に接続した態様であり、フィ
ルム面の寸法を呼ぶに際しては、直列状に接続する方向
の寸法を「長さ」、これに垂直な方向の寸法を「幅」と
よぶ。EXAMPLES The present invention will be specifically described below with reference to examples. Example 1 In this example, the film carrier shown in FIG. 1 was manufactured, and then, the laminated package shown in FIG. 5 was manufactured using this film carrier. The embodiment shown in FIG. 1 is an embodiment in which the film carrier elements are connected in series. When referring to the dimensions of the film surface, the dimension in the direction in which the film carriers are connected in series is "length," and the dimension in the direction perpendicular to this. Is called "width".

【００４９】〔フィルムキャリアの作製〕フィルムキャ
リア要素の接続は、図１に示すように、３連直列状であ
り、中央のフィルムキャリア要素がベース要素である。
各フィルムキャリア要素の大きさを長さ１０ｍｍ×幅１
０ｍｍ、２つの屈曲部の大きさを各々長さ３ｍｍ×幅１
０ｍｍと長さ５ｍｍ×幅１０ｍｍとし、全体として、絶
縁性基板の大きさを、長さ３８ｍｍ×幅１０ｍｍとし
た。絶縁性基板は、ポリイミド樹脂からなり、厚みは
０．１ｍｍである。絶縁性基板上に銅からなる導電回路
を設けその上に絶縁性基板と同じ材料の被覆層を設け、
導電回路が絶縁性基板内に埋設された構造とした。次
に、この絶縁性基板の一方の面を実装面とし、絶縁性基
板上のフィルムキャリア要素となる領域に、実装用接点
部としてバンプ接点を設けた。更に、ベース要素の外部
回路基板との接続用面に接続用接点部としてバンプ接点
を設けて本発明のフィルムキャリアを得た。[Preparation of Film Carrier] As shown in FIG. 1, the connection of the film carrier elements is a three-series connection, and the central film carrier element is the base element.
The size of each film carrier element is 10 mm long x 1 width
0 mm, the size of each of the two bent portions is 3 mm in length x 1 in width
0 mm and a length of 5 mm × a width of 10 mm, and the size of the insulating substrate was 38 mm in length × 10 mm in width as a whole. The insulating substrate is made of a polyimide resin and has a thickness of 0.1 mm. A conductive circuit made of copper is provided on an insulating substrate, and a coating layer of the same material as the insulating substrate is provided thereon,
The structure was such that a conductive circuit was embedded in an insulating substrate. Next, one surface of the insulating substrate was used as a mounting surface, and a bump contact was provided as a mounting contact portion in a region to be a film carrier element on the insulating substrate. Further, a bump contact was provided as a connection contact portion on the surface of the base element for connection with the external circuit board to obtain a film carrier of the present invention.

【００５０】〔半導体素子の実装〕上記で作製したフィ
ルムキャリアにおける各フィルムキャリア要素の実装面
に、半導体素子として外形７ｍｍ×７ｍｍのＩＣベアチ
ップを実装した。実装面と半導体素子との接着には熱硬
化性接着剤を使用した。[Mounting of Semiconductor Element] An IC bare chip having an outer diameter of 7 mm × 7 mm was mounted as a semiconductor element on the mounting surface of each film carrier element in the film carrier prepared above. A thermosetting adhesive was used for bonding between the mounting surface and the semiconductor element.

【００５１】〔積層型実装体の作製〕半導体素子を実装
したフィルムキャリアの屈曲部を折り曲げ、層間（素子
と素子との間、素子と絶縁性基板との間）をエポキシ接
着剤で接着し、図４（ｂ）に示す積層型実装体を形成し
た。更にこの積層型実装体の全体を、ベース要素の接続
用面を除き樹脂で封止し、図５に示す態様とした。[Preparation of Stacked Mounted Body] The bent portion of the film carrier on which the semiconductor element is mounted is bent, and the layers (between the element and the element, between the element and the insulating substrate) are bonded with an epoxy adhesive. The stacked mounting body shown in FIG. 4B was formed. Further, the whole of the stacked mounting body was sealed with a resin except for the connection surface of the base element, to obtain an embodiment shown in FIG.

【００５２】〔外部回路基板との接続〕樹脂封止された
積層型実装体を、さらに図７に示すように、外部回路基
板１１に接続したところ、積層の各階の半導体素子ごと
に外部回路基板と接続する必要がないので容易に接続で
きた。また、半導体素子は予め一体的に積層されている
ため、取り扱いが簡単であった。[Connection with External Circuit Board] As shown in FIG. 7, the laminated type package body sealed with a resin was further connected to an external circuit board 11. There was no need to connect to the device, so it was easy to connect. In addition, since the semiconductor elements were previously integrally laminated, the handling was easy.

【００５３】実施例２ 本実施例では、図３（ａ）に示すように、半導体素子を
ワイヤーボンディング法にて各フィルムキャリア要素に
実装し、図６に示すように、半導体素子毎に個別に樹脂
封止を行なう態様のものを製作した。Embodiment 2 In this embodiment, as shown in FIG. 3A, a semiconductor element is mounted on each film carrier element by a wire bonding method, and as shown in FIG. An embodiment in which resin sealing was performed was manufactured.

【００５４】〔フィルムキャリアの作製〕フィルムキャ
リア要素の外形寸法、接続パターンなどは、実施例１と
同様である。実施例１と同様に、導電回路が絶縁性基板
内に埋設された回路基板を形成した後、紫外レーザーを
用いた開口加工によって実装用接点部・接続用接点部を
設けるべき位置に開口部を設け、内部に導電回路を露出
させた。開口内に露出した導電回路の表面に、めっきに
よって厚さ１μｍの金の被覆層を形成し、本発明のフィ
ルムキャリアを得た。[Preparation of Film Carrier] The external dimensions and connection patterns of the film carrier elements are the same as those in the first embodiment. After forming a circuit board in which a conductive circuit is embedded in an insulating substrate, an opening is formed at a position where a mounting contact portion and a connection contact portion are to be provided by an opening process using an ultraviolet laser in the same manner as in the first embodiment. The conductive circuit was exposed inside. A gold coating layer having a thickness of 1 μm was formed by plating on the surface of the conductive circuit exposed in the opening to obtain a film carrier of the present invention.

【００５５】〔半導体素子の実装〕上記で作製したフィ
ルムキャリアにおける各フィルムキャリア要素の実装面
に、半導体素子として外形７ｍｍ×７ｍｍのＩＣベアチ
ップを接着剤を用いて装着し、内部接続用のワイヤー
（金線）Ｗによってワイヤーボンディングを行い実装を
完了した。[Semiconductor Device Mounting] An IC bare chip having an outer diameter of 7 mm × 7 mm was mounted as a semiconductor device on the mounting surface of each film carrier element in the film carrier prepared above using an adhesive, and wires for internal connection ( (Gold wire) W was used for wire bonding to complete the mounting.

【００５６】〔樹脂封止〕図６に示すように、実装され
た半導体素子毎に、従来の封止方法によって個別に樹脂
封止を行った。[Resin Sealing] As shown in FIG. 6, each of the mounted semiconductor elements was individually resin-sealed by a conventional sealing method.

【００５７】〔積層型実装体の作製〕フィルムキャリア
の屈曲部を折り曲げ、層間（素子と素子との間、素子と
絶縁性基板との間）に両面接着テープを介在させ、図６
（ｂ）に示す積層型実装体を形成した。[Preparation of Laminated Mounted Body] The bent portion of the film carrier is bent, and a double-sided adhesive tape is interposed between the layers (between the elements, between the elements and the insulating substrate).
The stacked mounting body shown in FIG.

【００５８】〔外部回路基板との接続〕上記積層型実装
体の接続用面を上方に向け、接続用接点部として設けた
開口部に共晶組成の半田ボールを１個づつ配置し、リフ
ロー処理で半田ボールを溶融させ、開口部内に半田を充
填するとともに略球状の半田ボール接点（バンプ接点）
を形成した。得られた積層型実装体を外部回路基板の所
定の実装位置に装着し、リフロー処理によって容易に接
続できることを確認した。[Connection with External Circuit Board] The soldering balls of the eutectic composition are placed one by one in the openings provided as the connection contacts, with the connection surface of the multilayer mounting body facing upward, and the reflow treatment is performed. The solder ball is melted by filling the opening with the solder, and the contact point of the substantially spherical solder ball (bump contact)
Was formed. It was confirmed that the obtained multilayer mounting body was mounted on a predetermined mounting position of an external circuit board, and that the connection could be easily performed by a reflow process.

【００５９】[0059]

【発明の効果】本発明のフイルムキャリアを用いれば、
半導体素子の数だけフィルムキャリアを用意する必要が
なく、また実装後は半導体素子がバラバラにならず、持
ち運びや保管等が容易に行え、更に、積層型実装体の形
成が容易にでき、コストの低下を図ることができる。本
発明の積層型実装体は、外部回路基板に接続する前に、
すでに各層間の接続が内部で完了しており、かつ、全て
の素子の電極が外部接続用面に端子として集合してお
り、一個の独立した半導体装置として機能する。従っ
て、外部回路基板との接続に際しては、リードを設ける
必要がないため、リード加工の問題、リードと外部電極
との位置合わせや接合の問題を解消することができる。By using the film carrier of the present invention,
It is not necessary to prepare film carriers by the number of semiconductor elements, and the semiconductor elements do not fall apart after mounting, so that they can be easily carried and stored, and furthermore, the formation of a multilayer mounting body can be facilitated, and the cost can be reduced. It can be reduced. The stacked mounting body of the present invention, before connecting to an external circuit board,
The connection between the layers has already been completed internally, and the electrodes of all the elements are gathered as terminals on the external connection surface, and function as one independent semiconductor device. Therefore, when connecting to the external circuit board, there is no need to provide leads, so that the problems of lead processing and the problems of alignment and bonding between the leads and the external electrodes can be solved.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明のフィルムキャリアの一例を示す図であ
る。図１（ａ）は、ベース要素の実装面がある側の面を
見た図（上面図）であり、図１（ｂ）は、図１（ａ）の
フィルムキャリアを長手方向に切断した場合の断面図で
ある。図１（ａ）では屈曲部にのみハッチングを施して
おり、図１（ｂ）では導電回路にのみハッチングを施し
ている。FIG. 1 is a view showing one example of a film carrier of the present invention. FIG. 1A is a view (top view) of a surface on a side where a mounting surface of a base element is present, and FIG. 1B is a diagram when the film carrier of FIG. 1A is cut in a longitudinal direction. FIG. In FIG. 1A, only the bent portion is hatched, and in FIG. 1B, only the conductive circuit is hatched.

【図２】本発明のフィルムキャリアの他の例を示す図で
ある。本図は、図１（ａ）と同様、ベース要素の実装面
がある側の面を見た図（上面図）であって、屈曲部にの
みハッチングを施している。FIG. 2 is a view showing another example of the film carrier of the present invention. This figure is a view (top view) of the surface on the side where the mounting surface of the base element is present, as in FIG. 1A, and only the bent portions are hatched.

【図３】実装用接点部または接続用接点部の他の態様を
示す断面図である。FIG. 3 is a cross-sectional view showing another embodiment of a mounting contact portion or a connection contact portion.

【図４】本発明の積層型実装体の一例を示す断面図であ
る。導電回路にのみハッチングを施しており、半導体素
子については外形のみを示している（以下の図も、断面
図の場合は同様である）。FIG. 4 is a cross-sectional view showing one example of a stacked mounting body of the present invention. Only the conductive circuit is hatched, and only the outer shape of the semiconductor element is shown (the same applies to the following figures in the case of a cross-sectional view).

【図５】図４に示した積層型実装体の態様のバリエーシ
ョンを示す断面図である。また、同図では、樹脂モール
ドの一態様も示している。FIG. 5 is a cross-sectional view showing a variation of the embodiment of the stacked mounting body shown in FIG. FIG. 1 also shows one mode of the resin mold.

【図６】本発明の積層型実装体の他の例を示す断面図で
ある。同図では、樹脂モールドの他の態様も示してい
る。FIG. 6 is a cross-sectional view showing another example of the stacked mounting body of the present invention. FIG. 3 also shows another embodiment of the resin mold.

【図７】図５に示した積層型実装体が、さらに外部回路
基板に接続された態様を示す断面図である。FIG. 7 is a cross-sectional view showing a mode in which the stacked mounting body shown in FIG. 5 is further connected to an external circuit board.

【図８】従来の積層型実装体を示す斜視図である。FIG. 8 is a perspective view showing a conventional stacked mounting body.

【符号の説明】[Explanation of symbols]

１ フィルムキャリア要素 １ａ ベース要素 １ｂ、１ｃ ベース要素以外のフィルムキャリア要素 ２ 実装面 ３ 屈曲部 ４ａ〜４ｃ 導電回路 ５ 絶縁性基板 ６ 実装用接点部 ７ 接続用接点部 ８ 半導体素子 DESCRIPTION OF SYMBOLS 1 Film carrier element 1a Base element 1b, 1c Film carrier element other than base element 2 Mounting surface 3 Bending part 4a-4c Conductive circuit 5 Insulating substrate 6 Mounting contact part 7 Connection contact part 8 Semiconductor element

Claims (15)

【特許請求の範囲】[Claims] 【請求項１】 下記（Ａ）のフィルムキャリア要素が、
各実装面が同じ側となるよう屈曲部を介して複数接続さ
れ、そのなかの一つのフィルムキャリア要素をベース要
素とし、 ベース要素以外のフィルムキャリア要素は、屈曲部を折
り曲げることによってベース要素の上に重なり合い全体
が１つの積層体となることができ、内部の導電回路は屈
曲部内部を通ってベース要素内部の導電回路に接続さ
れ、 ベース要素の実装面の裏面である接続用面には外部基板
接続用の接点部が設けられており、該接点部は導電回路
と導通しているフィルムキャリア。（Ａ）絶縁性基板の
内部に導電回路を設けてなり、該絶縁性基板の一方の面
を実装面とし、該面には半導体素子を実装するための実
装用接点部が設けられており、該接点部は該導電回路と
導通しているフィルムキャリア要素。1. A film carrier element of the following (A):
A plurality of connecting parts are connected via a bent portion so that each mounting surface is on the same side, and one of the film carrier elements is used as a base element. The entire conductive circuit inside the base element is connected to the conductive circuit inside the base element through the inside of the bent portion, and the connection surface, which is the back surface of the mounting surface of the base element, is connected to the external surface. A film carrier provided with a contact portion for connecting a substrate, wherein the contact portion is electrically connected to a conductive circuit. (A) A conductive circuit is provided inside an insulating substrate, one surface of the insulating substrate is used as a mounting surface, and a mounting contact portion for mounting a semiconductor element is provided on the surface. The contact portion is a film carrier element that is in electrical communication with the conductive circuit. 【請求項２】 下記（Ａ）のフィルムキャリア要素が、
各々の面が拡張する方向に屈曲部を介して複数接続さ
れ、そのなかの一つのフィルムキャリア要素をベース要
素とし、 ベース要素以外のフィルムキャリア要素は、屈曲部を折
り曲げることによってベース要素の上に重なり合い全体
が１つの積層体となることができ、内部の導電回路は屈
曲部内部を通ってベース要素内部の導電回路に接続さ
れ、 ベース要素の実装面の裏面である接続用面には外部基板
接続用の接点部が設けられており、該接点部は導電回路
と導通しているフィルムキャリア。（Ａ）絶縁性基板の
内部に導電回路が設けられてなり、絶縁性基板の少なく
とも一方の面は半導体素子を実装するための実装面であ
り、実装面には実装用接点部が設けられ、実装用接点部
は前記導電回路と導通しているフィルムキャリア要素。2. The following (A) film carrier element:
A plurality of surfaces are connected via a bent portion in a direction in which each surface expands, and one of the film carrier elements is used as a base element, and the film carrier elements other than the base element are folded on the bent portion to be placed on the base element. The entire overlap can be a single laminate, and the conductive circuit inside is connected to the conductive circuit inside the base element through the inside of the bent portion, and the connection surface, which is the back surface of the mounting surface of the base element, is connected to an external substrate. A film carrier provided with a contact portion for connection, wherein the contact portion is electrically connected to a conductive circuit. (A) a conductive circuit is provided inside an insulating substrate, at least one surface of the insulating substrate is a mounting surface for mounting a semiconductor element, and a mounting contact portion is provided on the mounting surface; The mounting contact portion is a film carrier element that is electrically connected to the conductive circuit. 【請求項３】 屈曲部が絶縁性基板で形成されており、
屈曲部の絶縁性基板とフィルムキャリア要素の絶縁性基
板とが、連続した一枚の絶縁性基板である請求項１また
は２記載のフィルムキャリア。3. The bent portion is formed of an insulating substrate,
3. The film carrier according to claim 1, wherein the insulating substrate at the bent portion and the insulating substrate of the film carrier element are one continuous insulating substrate. 【請求項４】 上記フィルムキャリア要素の外形が全て
合同な方形であって、フィルムキャリア要素が直列状に
接続されたものである請求項１または２記載のフィルム
キャリア。4. The film carrier according to claim 1, wherein the outer shapes of the film carrier elements are all congruent squares, and the film carrier elements are connected in series. 【請求項５】 上記フィルムキャリア要素の外形が全て
合同な方形であって、ベース要素以外のフィルムキャリ
ア要素が、ベース要素の外周４辺に各１個ずつ接続され
たものである請求項１または２記載のフィルムキャリ
ア。5. The film carrier element according to claim 1, wherein the outer shapes of the film carrier elements are all congruent squares, and one film carrier element other than the base element is connected to each of four outer sides of the base element. 2. The film carrier according to 2. 【請求項６】 上記フィルムキャリア要素の実装用接点
部が、実装面から突起したバンプ接点である請求項１ま
たは２記載のフィルムキャリア。6. The film carrier according to claim 1, wherein the mounting contact portion of the film carrier element is a bump contact protruding from a mounting surface. 【請求項７】 上記フィルムキャリア要素の実装用接点
部が、実装面に設けられた開口部の内部に露出した導電
回路である請求項１または２記載のフィルムキャリア。7. The film carrier according to claim 1, wherein the mounting contact portion of the film carrier element is a conductive circuit exposed inside an opening provided on the mounting surface. 【請求項８】 上記フィルムキャリア要素の実装用接点
部が、実装面に設けられた開口部の内部に露出した導電
回路であって、該開口部の開口形状が、実装すべき半導
体素子をはめ込むことが可能な形状であり、該開口部の
内部に露出した導電回路は、半導体素子の電極との直接
的な接続が可能な位置に配置されている請求項１または
２記載のフィルムキャリア。8. The mounting circuit according to claim 1, wherein the mounting contact portion of the film carrier element is a conductive circuit exposed inside an opening provided on the mounting surface, and the opening shape of the opening is fitted with a semiconductor element to be mounted. 3. The film carrier according to claim 1, wherein the conductive circuit has a shape which allows the conductive circuit to be exposed to the inside of the opening, and is arranged at a position where the conductive circuit can be directly connected to an electrode of the semiconductor element. 【請求項９】 上記ベース要素に設けられる外部回路基
板との接続用接点部が、接続用面から突起するように設
けられたバンプ接点である請求項１または２記載のフィ
ルムキャリア。9. The film carrier according to claim 1, wherein the contact portion for connection with the external circuit board provided on the base element is a bump contact provided so as to project from the connection surface. 【請求項１０】 上記ベース要素に設けられる外部回路
基板との接続用接点部が、接続用面に設けられた開口部
の内部に露出した導電回路である請求項１または２記載
のフィルムキャリア。10. The film carrier according to claim 1, wherein the contact portion for connection with the external circuit board provided on the base element is a conductive circuit exposed inside an opening provided on the connection surface. 【請求項１１】 請求項１〜１０のいずれかに記載のフ
ィルムキャリアが用いられ、各フィルムキャリア要素の
実装面には半導体素子が実装され、屈曲部が折り曲げら
れて、ベース要素以外の各フィルムキャリア要素が、半
導体素子を実装された状態で、ベース要素の接続用面が
積層の最下面となるようにして、ベース要素上に重なり
合って１つの積層体となっている積層型実装体。11. The film carrier according to claim 1, wherein a semiconductor element is mounted on a mounting surface of each film carrier element, and a bent portion is bent to form a film other than the base element. A stacked mounting body in which a carrier element is mounted on a semiconductor element, and the connection surface of the base element is the lowermost surface of the stack, and is stacked on the base element to form a single stacked body. 【請求項１２】 フィルムキャリアが請求項１に記載の
フィルムキャリアであって、ベース要素以外の全てのフ
ィルムキャリア要素が、実装面をベース要素側に向けて
互いに重なり合っている請求項１１記載の積層型実装
体。12. The laminate according to claim 11, wherein the film carrier is the film carrier according to claim 1, wherein all the film carrier elements other than the base element overlap each other with the mounting surface facing the base element. Type implementation. 【請求項１３】 ベース要素に実装されている半導体素
子と、ベース要素の次層のフィルムキャリア要素に実装
されている半導体素子とが、互いに接着されており、他
のフィルムキャリア要素に実装されている半導体素子
は、その下層側のフィルムキャリア要素の絶縁性基板に
接着されている請求項１２記載の積層型実装体。13. A semiconductor element mounted on a base element and a semiconductor element mounted on a film carrier element in a layer next to the base element are adhered to each other and mounted on another film carrier element. 13. The stacked package according to claim 12, wherein the semiconductor element is bonded to the insulating substrate of the film carrier element on the lower layer side. 【請求項１４】 上記積層体の全体が、ベース要素の接
続用面を除いて、樹脂で一体的に封止されている請求項
１１〜１３のいずれかに記載の積層型実装体。14. The multilayer mounting body according to claim 11, wherein the whole of the multilayer body is integrally sealed with a resin except for a connecting surface of a base element. 【請求項１５】 実装された半導体素子が、フィルムキ
ャリア要素毎に個別に樹脂で封止されている請求項１１
〜１３のいずれかに記載の積層型実装体。15. The mounted semiconductor element is individually sealed with resin for each film carrier element.
14. The stacked package according to any one of items 13 to 13.
JP29747697A 1997-05-19 1997-10-29 Film carrier and laminated mounting body using the same Expired - Fee Related JP3490601B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP29747697A JP3490601B2 (en) 1997-05-19 1997-10-29 Film carrier and laminated mounting body using the same
US09/080,454 US6208521B1 (en) 1997-05-19 1998-05-19 Film carrier and laminate type mounting structure using same

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP12840697 1997-05-19
JP9-128406 1997-05-19
JP29747697A JP3490601B2 (en) 1997-05-19 1997-10-29 Film carrier and laminated mounting body using the same

Publications (2)

Publication Number Publication Date
JPH1140618A true JPH1140618A (en) 1999-02-12
JP3490601B2 JP3490601B2 (en) 2004-01-26

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ID=26464083

Family Applications (1)

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Country Link
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6486544B1 (en) 1998-09-09 2002-11-26 Seiko Epson Corporation Semiconductor device and method manufacturing the same, circuit board, and electronic instrument
US6756663B2 (en) 1997-09-16 2004-06-29 Matsushita Electric Industrial Co., Ltd. Semiconductor device including wiring board with three dimensional wiring pattern
US6867496B1 (en) 1999-10-01 2005-03-15 Seiko Epson Corporation Interconnect substrate, semiconductor device, methods of fabricating, inspecting, and mounting the semiconductor device, circuit board, and electronic instrument
US7122886B2 (en) 2003-11-11 2006-10-17 Sharp Kabushiki Kaisha Semiconductor module and method for mounting the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6756663B2 (en) 1997-09-16 2004-06-29 Matsushita Electric Industrial Co., Ltd. Semiconductor device including wiring board with three dimensional wiring pattern
US6486544B1 (en) 1998-09-09 2002-11-26 Seiko Epson Corporation Semiconductor device and method manufacturing the same, circuit board, and electronic instrument
US6867496B1 (en) 1999-10-01 2005-03-15 Seiko Epson Corporation Interconnect substrate, semiconductor device, methods of fabricating, inspecting, and mounting the semiconductor device, circuit board, and electronic instrument
US7009293B2 (en) 1999-10-01 2006-03-07 Seiko Epson Corporation Interconnect substrate, semiconductor device, methods of fabricating, inspecting, and mounting the semiconductor device, circuit board, and electronic instrument
US7122886B2 (en) 2003-11-11 2006-10-17 Sharp Kabushiki Kaisha Semiconductor module and method for mounting the same

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