TWI324385B - Multiple die integrated circuit package - Google Patents

Multiple die integrated circuit package Download PDF

Info

Publication number
TWI324385B
TWI324385B TW095140244A TW95140244A TWI324385B TW I324385 B TWI324385 B TW I324385B TW 095140244 A TW095140244 A TW 095140244A TW 95140244 A TW95140244 A TW 95140244A TW I324385 B TWI324385 B TW I324385B
Authority
TW
Taiwan
Prior art keywords
integrated circuit
lead
lead frame
leads
die
Prior art date
Application number
TW095140244A
Other languages
Chinese (zh)
Other versions
TW200746381A (en
Inventor
Robert Wallace
Original Assignee
Sandisk Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/264,556 external-priority patent/US7352058B2/en
Priority claimed from US11/264,112 external-priority patent/US7511371B2/en
Application filed by Sandisk Corp filed Critical Sandisk Corp
Publication of TW200746381A publication Critical patent/TW200746381A/en
Application granted granted Critical
Publication of TWI324385B publication Critical patent/TWI324385B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49537—Plurality of lead frames mounted in one device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Description

九、發明說明： 【發明所屬之技術領域】 本發明及所說明的各具體實施例一般係關於製造勺含夕 個積體電路裝置的封裝式半導體裝置，且更特定言 於製造具有多個積體裝置的封裝以形成一封裝式系統:、記 憶體或記憶體卡儲存裝置。 【先前技術】 在電子技術中，將半導體裝置提供在保護並提供與積體 電路的外部連接之封裝中。對裝置的整合及先進功能的需 求已產生單一封裝中提供的多個積體電路，其有時係稱為 晶片或晶粒。封裝可以採用各種方式及各種材料加以形 成，該等材料包含使用熱硬化或熱固化材料形成的模製封 裝（例如&quot;液態封膠&quot;或環氧封裝）、預形成的塑膠或陶瓷或者 金屬主體及類似物。所用的材料保護較小且易碎的半導體 積電路或&quot;晶粒&quot;免遭實體及某程度的濕氣損壞，並且保護 導電線或線路，其係用於將外部端子（通常為金屬或其他導 電接點）與積體電路上的導電焊墊（其為積體電路之外部電 性連接）耦合。 通常而言，將引線框架用於半導體封裝技術，以提供機 械支樓並在積體電路與封裝式裝置之外部電性接點或引線 之間進行電性連接。引線框架由導電材料（通常為銅或合 金，或諸如合金42之鐵鎳合金，其係通常塗布成增加與諸 如金、釕、把等材料的導電性及可焊性）組成，並且額外塗 層或錄、銅或其他材料之合金可用於改良連接之可焊性及 115880.doc 可製造性。導電材料上的塑膠塗層可用於形成引線框架。 引線可加以焊接或電鍍以在裝配前或裝配成品封裝之前或 之後進行焊接。引線框架係通常提供成整合帶形式，並可 進行蝕刻或衝壓成形，引線框架帶為以帶形式進行連接以 便於裝配及製造的若干引線框架，並接著在後來製造階段 中進行分離。 引線框架通常提供複數個引線（通常為手指形狀，雖然使 用其他形狀）’其從將為所需成品封裝之外部邊界的區域外 侧伸延至配置成接收積體電路的内部區域。在先前技術 中’應瞭解使用一配置，其中引線框架之一區域提供一中 G支撐’其係稱為用於接收矩形或正方形半導體晶粒的•，晶 粒塾，並且引線指狀物在晶粒塾之一或多個側上延伸至接 近於積體電路晶粒之外側邊緣的區域。將引線框架指狀物 固定成遠離晶粒並透過囊封式封裝之計劃外部邊界而延 伸。在先前技術之其他配置中，引線指狀物可在晶粒上（晶 片上引線或&quot;LOC&quot;型引線框架）或晶粒下（晶片下引線或 LUC&quot;型引線框架）延伸，同時引線提供機械支撐及電性路 徑。 以塗層或膠帶形式的絕緣體黏結劑可以用於將晶粒與引 線固定，或藉由將引線固定在一起並在裝配程序期間維持 其位置而使引線穩定。可使用晶粒附著黏結劑將晶粒黏結 於晶粒墊’該黏結劑可以為導電或絕緣材料並可以為樹脂 或熱硬化材料。 不管所用的引線框架之類型，必須提供耦合機制以將積 115880.doc =電路與引線框架電性叙合。通常使用焊絲。藉由絲焊程 將違等微型焊絲應用於半導體裝置；通常在透過毛細管 盆用焊絲時分配焊絲。絲焊程序使用熱及壓力且有時使用 執他能量（例如超聲波能量）以藉由將焊絲附於積體電路輝 而形成焊接，並接著使焊絲在積體電路上且遠離積體電 路而延伸至引線框架之引線指狀物之端部上的一區域，接 著毛細管再次使用熱及壓力以形成焊絲與引線框架的第二 連接。或者，焊絲可以在相反方向上形成，從而首先附於 引線框架指狀物並延伸至積體電路上而且附於焊墊。切割 的焊絲係通f加熱成於焊絲之端部上形成-球，其係接著 用於對積體電路晶粒的下—次焊接（,·球&quot;焊接），在不採用球 的It況下附於引線框架的焊絲之端部可稱為&quot;點焊&quot;。若需 要：則多個焊絲可以從積體電路之不同墊延伸至引線框架 之早-引線’例如可採用此方式對積體電路進行電源或接 地連接。焊絲可以為金或其他已知的導體材料，其具有足 夠的可鍛性及柔性以提供此類處理並可用於球焊及點焊步 驟而，不必要的中斷。絲焊程序可以高度自動化，並通常 在很高速率下加以執行。 /於裝配程序+，在將積體電路晶粒與引線框架絲焊之 ! ’可將引線框架及晶粒放置於模製裝備(例如傳送模製機 裔）中’其中分散液體或炫化模製化合物材料以將引線框架 與積體電路囊封在-起，以便提供機械保護及對晶粒之某 程度的濕氣抵抗力，如以上所說明。其他替代性方式包含 使用注射模製、環氧與樹脂（例如•，液態封膠材料並且可使 115880.doc 用其他已知用於積體電路密封的材料。代替模製的係可 改為將引線與晶粒裝配件安裝於陶瓷、金屬或塑膠主體 中’接著可使用蓋子或黏結劑或其他物品，藉由囊封劑而 ‘ 後來密封該主體。引線框架之引線的外端可自己形成封裝 ‘ 式裝置（例如DIP、四重平面包裝、SOP或其他引線式封裝） . 之外部接點，或者可使用額外連通技術，例如球格柵陣列 C'bga”）或接針格栅陣列（&quot;PGA&quot;)封裝等。引線框架可結合 ^ 其他互連插入物技術來使用，該等技術如印刷電路板、基 於以膜為基礎的材料之柔性電路、用於半導體製造的商用 膜（例如Kapton、upilex、Mylar等），或可使用陶瓷基板材 料。為可在先前技術中使用複雜的基板配置，通常將多層 插入物與所形成的金屬層一起使用，從而將外部連接器與 積體電路搞合。例如’底部表面上的一端子可透過基板或 插入物中的多層及通道與插入物之上表面上的引線框架或 絲焊平台端子耦合。該等插入物或基板通常為層壓結構， • 纟中絕緣體層係形成於各導電層上。-旦完成裝配，則可 對該等層壓物進行過模製以提供密封的封裝式裝置或可將 裝配件放置於所密封的一主體中。 隨耆不斷需要在封裝式裝置中增加整合，在該技術中還 應瞭解提供MCM或多晶片模組，其中在一封裝式裝置内提 供夕個積體電路晶粒。例如，可將一記憶體裝置应一控制 器封裝在-起以形成此模組…處理器與記憶體也可形成 模組該等裝置可另外為相同裝置以（例如）形成一較大記 憶體積體電路（例如商品DRAM或非揮發性記憶體裝置），可 115880.doc 將多個相同晶粒放置於一個封裝中，其中將此類裝置的共 同端子與封裝的外部接點並聯耦合在一起。 使用各種技術以便在系統組態中將多個積體電路耦合在 一起。形成柔性電路’其具有提供在柔性基板之一或兩侧 上的金屬化圖案，該等圖案因此作為用於將兩個積體電路 連接在一起的互連位準。層壓物（例如Fr_44bt樹脂卡）可 以裇用多個金屬層及層間通道技術加以形成，該等層壓插 入物再次作為用於將積體電路連接在一起的微型電路板並 提供用於外部連通的跡線（例如端子）。 當欲將相同裝置耦合在一起以增加整合（例如在〇尺八厘裝 置情況下）時，可使用晶粒堆疊。焊絲可從引線框架之引線 延伸至若干晶粒，例如DRAM封裝之位址引線可與堆疊的 若干dram積體電路連接。晶粒之堆疊可包含晶粒之間的 間隔物以使絲焊裝備能存取個別堆疊式整合晶粒之晶粒 墊。 當欲將相同裝置耦合在一起以增加整合（例如在0汉八河裝 置情況下）時，可使用晶粒堆疊。可以使用各種方法，例如 在朝上π配置中提供多個晶粒，並且可形成絲焊以使用焊 絲將每個晶粒與共同引線框架耦合從而將其並聯耦合。應 瞭解採用背對背關係將晶粒放置於引線框架上，然而，為 維持共同的烊墊覆蓋區域，在使用㈣背關係時，通常需 要&quot;鏡射晶粒”，以便將朝上的晶粒之—侧上的端子定位在 與朝下之對應晶粒上相同的位置及順序中。對”鏡射晶粒,， 的需求會在較大程度上増加製造的複雜性、發明控制阳與成 115880.doc 1324385 本，並需要每個封裳式裝置包含具有相同功能的兩個不同 晶粒。或者，可以使用一插入物或層壓電路以致動兩個相 同功能晶粒之背對昔闳$ 牙ί月固疋此層屋插入物也會對成品裝置 增加成本及複雜性β ‘ 近年來增加㈣重要性的特定封裝式裝置類型為可移除 .._錄儲存卡，其允許在各種電子裝置之間進行資料傳 送。此非揮發性記憶體或儲存卡可用於各種格式，包含 C，⑽FLASH、安全數位或SD、迷« USB驅動器、多媒體卡或MMC及其他格式。為提供強固可 靠且穩定的資料健存格式，在单一封裝式裝置中連同智慧 控制器一起提供非揮發性EEPR〇M或快閃記憶體裝置。智 慧控制器提供資料錯誤校正與偵測、測試、快取及冗餘^ 援功能，以便即使非揮發性記憶體裝置内的某些儲存位置 係預期會出現故障且在產品的使用壽命期間確實出現故 障’仍正確地儲存並擁取使用者資料並且使用者或系統不 • 去。曉未再使用記憶體陣列内的某些位置；智慧控制器採用 冗餘記憶體位置取代該等位置並維持可用位置之一映射， 其係用於維持資料之適當儲存及一致性。對於使用者系統 而言，裝置看似較大記憶體陣列，控制器與自動錯誤校正 特徵及冗餘支援為使用者提供透明自動記憶體控制操作， 其不會影響裝置的使用。該等可移除儲存卡已得到使用並 將繼續用於其中儲存資料的許多應用，尤其對於蜂巢式電 話、數位相機、數位媒體儲存（例如用於音樂播放機、視訊 播放機、電子遊戲、個人數位助理或pDA裝置的Μ”音樂 115880.doc •10- 1324385 及視訊）、病歷儲存、智能卡、信用卡等而言β 圖i描述一典型可移除儲存卡封裝之外部表面。此卡可以 為（例如）至該申請案之發明者Wallace的美國專利第號 6,410,355中所說明的類型，該申請案係以引用的方式併入 本文中。在圖la中，採用配置成接觸封裝1〇〇内的積體電路 之導電知子101來描述卡（例如安全數位或SD格式卡）之一 接觸側。圖1 b描述封裝1 〇〇之相對侧，其沒有電性接點，但 是通常承載具有用於使用者之視覺檢查及參考的資訊頻 帶名稱、媒體大小等之標識。端子之數目及所用的連接之 類型隨格式而發生變化，例如對於安全數位或3〇而言，圖 la所示的端子為典型端子，並且僅使用少數外部端子。對 於通常用於數位相機的小型快閃記憶體或&quot;CF&quot;卡而言，端 子之數目為較大，並且端子為定位在封裝之側面之一端上 的陰插頭。相機或卡讀取器具有一插座，其用於採用插座 内的陽端子或接針接收CF封裝之同一端’當將小型快閃記 憶體卡插入插座時，該等陽端子或接針進入對應的陰插 頭，從而完成連接。可使用其他連接，例如可將USB埠用 作連接。 用於可移除儲存卡裝置的先前技術封裝通常包含以多層 層壓印刷電路板或&quot;PC板&quot;之形式的複雜插入物或基板，其 為控制器積體電路與記憶體裝置或各裝置提供實體支撐及 裝置間的連通。可以為BT樹脂、FR4或玻璃纖維或類似物 的板通常為一層壓結構，其併入金屬層，該等金屬層得到 圖案化以形成導體跡線、耦合各層以進行電性連接的通 1158 肋.doc 1324385 第5，147,815號（其係以引用的方式併入本文中）描述兩個積 體電路晶粒及兩個引線框架，其係裝配並提供在單一模製 雙列直插塑膠或&quot;DIP&quot;封裒中》將積體電路晶粒及其個別引 • 隸架配置成背對背關係並且藉由使用焊絲而將每個晶粒 .· 肖個別引線框架耦合’或者，在-插入物之相對側上將積 • 冑電路配置成㈣面關係並且在覆晶配置巾將該等積體電 路與其個別引線框架麵合，將兩個積體電路與配2 = $裝置之相對側上的外部引線獨立地耦合而且該等積體電 路並非彼此進行電性通信。至Y〇shida等人的美國專利第 6,603’ i 97號（也係以引用的方式併入本文中）提供與至少兩 個不同積體電路裝置輕合的多個引線框架，將該等積體電 路裝置與引線框架之各引線搞合以形成一模組，其中在封 襄的外部（例如電源引線）將某些共同引線實體及電性耦合 在起，以便兩個積體電路裝置可接收信號。同樣，至park 等人的美國專利第6,316,825號（也係以引用的方式併入本 • 文中）提供一堆疊封裴以採用在封裝之外部得到實體耦合 的兩個引線框架在模製封裝中土 隹疊兩個相同積體電路裝置 (例，記憶體裝置），以便將與外部引線輕合的每個信號與以 並聯方式加以連接的兩個相同記憶獐裝置之每個實體及 性耦合。 。•該技術中已知的其他配置提供與多位準引線框架輕合的 早一積體電路，例如至McShane的美國專利第5 22〇，⑼號 (夕也係以弓1用的方式併入本文中）提供單一積體電路’其係與 多層引線框架絲焊並包含封裝内的多層引線框架之部分之 ^ 15880.doc 13- 間的實體連接，以及採用烊 ^ Μ ^ 5 S ，、形成的穿透孔通道，該等焊 絲延伸至通道t以與固定在積體 卜杳⑽Α 牡檟體電路下面的引線框架層進 订實體接觸，從而致動封襄式裝置㈣多電壓平面之形成。 在用於多個積體電路的先前技術封裝，但是不斷 认“ 〃在維持封裝之可靠性的同時提供減少 的生產成本》 此需要-改良式多積體電路封裝及用於封裝多個積體 電路^方法，其係簡單且可靠，允許各積體電路裝置之 間進订任意連接’ $需要昂貴的插入物、印刷電路板或基 板，並且製造成本係少於現有封裝及方法。 【發明内容】 本發明之各較佳具體實施例提供—種用於多半導體積體 電路或晶粒的封裝’其電性連接_或多個積體電路，提供 對該等積體電路的機械支撐，提供設施以在該等積體電路 之間進打任意連接，並且提供與封裝式裝置之外部連接的 電f連it本發明之封裝不需要先前技術中使用的類型之 插入物或基板，並且材料使用與半導體處理行業中已知的 現有裝備及自動化工廠機II相容之傳統絲焊及引線框架技 術，以便使用及實施本發明不需要重組或專用裝備。 在本發明之第-具體實施例中，提供第—引線框架並將 其固定成覆蓋-簡單的絕緣體層。該絕緣體層具有為形成 於某些位置中的開σ之通道以及覆蓋該等通道的引線框架 之某些引線。引線框架之其他引線可延伸至絕緣體之外部 邊界或絕緣體之邊緣以夕卜。引線框架之某些引線可以不延 115880.doc •14· 伸至外部連接器。提供第一積體電路晶粒並將其固定成接 近於引線框架之内部端，在某些具體實施例中，引線框架 可具有提供在内部的一開口並且可將晶粒放置在内部開口 中。在其他具體實施例中’晶粒可座落在引線框架之引線 上或在引線框架之引線下。在一較佳具體實施例中，將晶 粒與引線框架絲焊以將積體電路之該等引線之一或多個引 線與引線框架之引線電性連接。在其他較佳具體實施例 中，可使用覆晶技術將引線框架之引線與晶粒連接，此在 該技術中已為人所知。 接著將第二引線框架放置成t蓋絕緣體之第i且為相對 的表面上。至於第一引線框架之某些引線且與該等引線一 致的係’將第二引線框架之某些引線固定成覆蓋絕緣體之 穿透孔通if帛—引線框架之其他引線可延伸至絕緣體層 的外部以與成品裝置進行外部電性連接，並可延伸至絕緣 體之外部邊界以外。將第二積體電路晶粒放置成接近於第 一引線框架之内部引線。第二引線框架可具有鄰近於引線 框架之引線的内部端以接收晶粒的中心部分，或者可使用 曰曰片下的一引線或晶片引線框架配置上的引線。從第二積 體電路上的晶粒塾端子至第二引線框架之該等引線的至少 -個引線進仃電性連接，例如料連接或覆晶連接。在一 八里應用t，存在若干且有時存在許多焊絲，其從積體電 路延伸至引線框架。或者，可將第—及第二引線框架彼此 附著’然後將任—晶粒附於其對應引線框架。 有利的係’透過絕緣體中的通道來電性耦合第一及第二 115880.doc 1324385 引線框架之某些引線。本發明之此方面可以透過在兩個引 線框架之間透過絕緣體進行電性連接的設施於任意位置中 電性耦合第一及第二積體電路晶粒。在第一較佳具體實施 例中’藉由使第一及第二引線之引線框架引線在絕緣體中 的通道内之空間中實體變形，並接著在通道内的兩個引線 之間進行實體接觸，可進行連接。在一較佳具體實施例中， 因此在兩個引線框架之間進行導電焊接。可採用（例如）藉由 熱施加的能量、電能量、超聲波能量、雷射能量等進行焊 接。在其他較佳具體實施例中，可藉由提供固定於通道内 的導電材料（例如作為電性連接的導電膏並且可使用熱或 電能量來完成該連接）而在兩個引線框架之間進行電性連 接。 在其他較佳具體實施例中，絕緣體可由备向異性導電材 料形成’該材料最初在所有方向上作為絕緣體，但是當在 一區域中施加壓力或熱能量或兩者，同時使絕緣體保持在 平面方向上時，該材料在垂直方向上變為選擇性導電。一 般而言，一通道為一區域，其中在鄰近於絕緣體之頂部表 面的一導體與鄰近於絕緣體之底部表面的一導體之間達到 電性連通。 可將積體電路晶粒固定成覆蓋絕緣體之相對表面，以便 積體電路晶粒可以為背對背關係。不像先前技術之背對背 配置一樣，當使用本發明時不需要鏡射晶粒，因為透過藉 由本發明提供的絕緣體形成電性連接的方法允許任意連接 兩個裝置的端子。至於先前技術封裝之某些，不需要對準 115880.doc •16· 或反射兩個積體電路晶粒的端子。 此外’在某些具體實施例中，對於dram、eepr〇 閃或其他動態或非揮發性記憶體裝置而言、 可以係相同的，在料裝置中， ”晶粒 路曰粉鯉人y &amp; 由將夕個相同積體電 路日曰粒Μ。在-起而建立—較大封裝式裝置。在其他較佳 :體實施例中’晶粒可具有不同功能，例如記憶體控制器 1己憶體裝置、類比電路與數位裝置、感測器與控制器裝IX. INSTRUCTIONS OF THE INVENTION: TECHNICAL FIELD The present invention and the specific embodiments described above generally relate to a packaged semiconductor device for manufacturing a spoon-shaped integrated circuit device, and more specifically for manufacturing a plurality of products. The package of the body device forms a packaged system: memory or memory card storage device. [Prior Art] In electronic technology, a semiconductor device is provided in a package that protects and provides an external connection to an integrated circuit. The need for device integration and advanced functionality has resulted in multiple integrated circuits provided in a single package, sometimes referred to as wafers or dies. The package can be formed in a variety of ways and in a variety of materials, including molded packages formed using thermally cured or thermally cured materials (eg, &quot;liquid sealant&quot; or epoxy package), preformed plastic or ceramic or metal. Main body and the like. The materials used protect the small and fragile semiconductor circuit or &quot;die&quot; from physical and some degree of moisture damage and protect the wires or wires used to connect external terminals (usually metal or Other conductive contacts are coupled to conductive pads on the integrated circuit that are electrically connected externally to the integrated circuit. In general, lead frames are used in semiconductor packaging techniques to provide mechanical wraps and to electrically connect the integrated circuits to external electrical contacts or leads of the packaged device. The leadframe consists of a conductive material (usually copper or an alloy, or an iron-nickel alloy such as Alloy 42, which is typically coated to increase electrical conductivity and weldability with materials such as gold, tantalum, etc.) and additional coatings. Or alloys of copper, copper or other materials can be used to improve the solderability of the joint and 115880.doc manufacturability. A plastic coating on the conductive material can be used to form the lead frame. The leads can be soldered or plated for soldering prior to or after assembly or after assembly of the finished package. The lead frame system is usually provided in the form of an integrated tape which can be etched or stamped, and the lead frame tape is a plurality of lead frames which are connected in a tape form for assembly and manufacture, and then separated in a later manufacturing stage. The lead frame typically provides a plurality of leads (typically in the shape of a finger, although other shapes are used) that extend from the outside of the area that will be the outer boundary of the desired finished package to an interior area that is configured to receive the integrated circuit. In the prior art 'should be understood to use a configuration in which one region of the lead frame provides a medium G support' which is referred to as a chip for receiving rectangular or square semiconductor grains, a germanium die, and a lead finger in the crystal One or more sides of the crucible extend to a region close to the outer side edge of the integrated circuit die. The leadframe fingers are secured away from the die and extend through the planned outer boundary of the encapsulated package. In other configurations of the prior art, the lead fingers can be extended on the die (on-wafer leads or &quot;LOC&quot; type leadframe) or under the die (wafer down leads or LUC&quot; type leadframe) while the leads are provided Mechanical support and electrical path. An insulator bond in the form of a coating or tape can be used to secure the die to the leads or to stabilize the leads by securing the leads together and maintaining their position during the assembly process. The die attach adhesive can be used to bond the die to the die pad. The bond can be a conductive or insulating material and can be a resin or a thermosetting material. Regardless of the type of leadframe used, a coupling mechanism must be provided to electrically combine the product with the lead frame. A wire is usually used. The micro-wire is applied to the semiconductor device by a wire bonding process; the wire is usually dispensed when the wire is passed through the capillary tube. The wire bonding process uses heat and pressure and sometimes uses other energy (such as ultrasonic energy) to form a weld by attaching the wire to the integrated circuit, and then extending the wire on the integrated circuit and away from the integrated circuit. To a region on the end of the lead fingers of the lead frame, the capillary then uses heat and pressure again to form a second connection of the wire to the lead frame. Alternatively, the wire may be formed in the opposite direction to first attach to the lead frame fingers and extend to the integrated circuit and to the pads. The cut wire is heated to form a ball on the end of the wire, which is then used for the next-order welding of the integrated circuit die (, ball &quot;welding), without the use of the ball. The end of the wire attached to the lead frame may be referred to as &quot;spot weld&quot;. If desired: a plurality of wires can be extended from different pads of the integrated circuit to the early leads of the lead frame. For example, the integrated circuit can be powered or grounded in this manner. The wire may be gold or other known conductor material that is sufficiently malleable and flexible to provide such treatment and can be used for ball and spot welding steps without unnecessary interruption. Wire soldering procedures can be highly automated and are typically performed at very high speeds. /In the assembly process +, the integrated circuit die and the lead frame are soldered! 'The lead frame and the die can be placed in the molding equipment (for example, transfer molding machine)' in which the liquid or the stencil is dispersed. The compound material is formed to encapsulate the leadframe and the integrated circuit to provide mechanical protection and some degree of moisture resistance to the die, as explained above. Other alternatives include the use of injection molding, epoxy and resin (eg, liquid encapsulants and the ability to use 115880.doc for other materials known to be used in integrated circuit seals. The lead and die assembly is mounted in a ceramic, metal or plastic body. 'The lid or adhesive or other item can then be used to seal the body later by the encapsulant. The outer end of the lead of the lead frame can be packaged by itself. '-type devices (such as DIP, quad flat package, SOP or other leaded package). External contacts, or you can use additional connectivity technologies such as ball grid array C'bga" or pin grid array (&quot PGA&quot;) packages, etc. Lead frames can be used in conjunction with other interconnect interposer technologies such as printed circuit boards, flexible circuits based on film-based materials, and commercial films for semiconductor fabrication (eg Kapton) , upilex, Mylar, etc., or ceramic substrate materials can be used. In order to use complex substrate configurations in the prior art, multilayer inserts and formed metals are typically used. Used together to integrate the external connector with the integrated circuit. For example, a terminal on the bottom surface can be coupled to the lead frame or wire bonding platform terminal on the substrate or the upper surface of the insert through the substrate or multiple layers and channels in the insert. The inserts or substrates are typically laminated structures, and the interlayer of the insulator is formed on each of the conductive layers. Once the assembly is completed, the laminates can be overmolded to provide a sealed packaged device. Alternatively, the assembly can be placed in a sealed body. There is a continuing need to add integration to packaged devices, and it is also known in the art to provide MCM or multi-chip modules in which a packaged device is provided. An integrated circuit die. For example, a memory device can be packaged in a controller to form the module... The processor and the memory can also form a module. The devices can be additionally the same device (for example) Forming a larger memory volume circuit (such as a commercial DRAM or non-volatile memory device), which can place multiple identical dies in a package, where such devices are The common terminal is coupled in parallel with the external contacts of the package. Various techniques are used to couple multiple integrated circuits together in a system configuration. Forming a flexible circuit that has metal provided on one or both sides of the flexible substrate Patterns, which thus serve as interconnect levels for joining two integrated circuits together. Laminates (eg, Fr_44bt resin cards) can be formed using multiple metal layers and interlayer via techniques, such The laminate insert again acts as a microcircuit board for connecting the integrated circuits together and provides traces (eg, terminals) for external communication. When the same devices are to be coupled together to increase integration (eg, at 8 feet) In the case of a device, a die stack can be used. The wire can extend from the leads of the leadframe to a number of dies, for example, the address leads of the DRAM package can be connected to a plurality of stacked damb integrated circuits. The stack of dies may include spacers between the dies to enable the wire bonding apparatus to access the die pads of the individual stacked integrated dies. A die stack can be used when the same devices are to be coupled together to increase integration (e.g., in the case of a Hanbahe device). Various methods can be used, such as providing a plurality of dies in an upward π configuration, and wire bonding can be formed to couple each die to a common lead frame using a wire to couple them in parallel. It should be understood that the die is placed on the lead frame in a back-to-back relationship. However, in order to maintain a common pad coverage area, when using the (iv) back relationship, it is often necessary to "mirror the grain" so that the upwardly facing grains are The terminals on the side are positioned in the same position and sequence as the corresponding crystals facing downwards. The need for "mirror-grained grains", to a large extent, adds to the complexity of manufacturing, the invention controls the yang and becomes 115880 .doc 1324385, and requires each of the seal-type devices to contain two different dies with the same function. Alternatively, an insert or lamination circuit can be used to actuate the two opposing functional dies to the back of the 闳 闳 ί 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 层 层 层 层 层 层 层 层 层 层 疋 疋 疋 层 层 疋 疋 疋 疋(d) The importance of the specific packaged device type is removable.. _ record memory card, which allows data transfer between various electronic devices. This non-volatile memory or memory card can be used in a variety of formats, including C, (10) FLASH, Secure Digital or SD, USB Drive, Multimedia Card or MMC and other formats. To provide a robust and stable data-storage format, a non-volatile EEPR〇M or flash memory device is provided in conjunction with a smart controller in a single packaged device. The Smart Controller provides data error correction and detection, test, cache and redundancy functions so that even some storage locations in non-volatile memory devices are expected to fail and do occur during the life of the product. The fault 'still stores and retrieves user data correctly and the user or system does not go. Some locations within the memory array are no longer used; the smart controller replaces these locations with redundant memory locations and maintains a map of available locations, which is used to maintain proper storage and consistency of the data. For the user system, the device appears to be a larger memory array, and the controller and automatic error correction features and redundancy support provide the user with transparent automatic memory control operations that do not affect device usage. These removable memory cards have been used and will continue to be used in many applications where data is stored, especially for cellular phones, digital cameras, digital media storage (eg for music players, video players, video games, individuals). Digital assistant or pDA device Μ "music 115880.doc • 10-1324385 and video), medical record storage, smart card, credit card, etc. β Figure i depicts the external surface of a typical removable memory card package. This card can be ( For example, the type described in U.S. Patent No. 6,410,355, the entire disclosure of which is incorporated herein by reference. The conductive transistor 101 of the integrated circuit describes one of the contact sides of the card (such as a secure digital or SD format card). Figure 1 b depicts the opposite side of the package 1 , which has no electrical contacts, but typically has a bearer for use The visual inspection of the person and the identification of the information band name, media size, etc. The number of terminals and the type of connection used vary with the format, for example For safety digits or 3 turns, the terminals shown in Figure la are typical terminals and only a few external terminals are used. For small flash memory or &quot;CF&quot; cards commonly used in digital cameras, the number of terminals To be larger, and the terminal is a female plug positioned on one side of the side of the package. The camera or card reader has a socket for receiving the same end of the CF package using a male terminal or a pin within the socket 'When small When the flash memory card is inserted into the socket, the male terminals or the pins enter the corresponding female plugs to complete the connection. Other connections can be used, for example, the USB port can be used as a connection. For the previous use of the removable memory card device Technology packages typically include complex inserts or substrates in the form of multilayer laminated printed circuit boards or &quot;PC boards&quot; that provide physical support and inter-device communication between the controller integrated circuit and the memory device or devices. The sheet, which may be BT resin, FR4 or fiberglass or the like, is typically a laminate structure that incorporates a metal layer that is patterned to form conductor traces, coupling </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; In a single-molded dual-in-line plastic or &quot;DIP&quot; package, the integrated circuit die and its individual leads are configured in a back-to-back relationship and each die is made by using a wire. Lead frame coupling 'or, on the opposite side of the - insert, the product is configured in a (four) plane relationship and the integrated circuit is surfaced with its individual lead frames in a flip chip, and the two integrated circuits are The external leads on opposite sides of the device 2 = $ are independently coupled and the integrated circuits are not in electrical communication with each other. U.S. Patent No. 6,603 'i 97 to the name of U.S. Pat. The circuit device and the leads of the lead frame are combined to form a module, wherein some common leads are physically and electrically coupled outside the package (eg, power leads) so that the two integrated circuit devices can receive signals . Also, U.S. Patent No. 6,316,825, the disclosure of which is incorporated herein by reference in its entirety, in its entirety, in the entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire portion Two identical integrated circuit devices (eg, memory devices) are stacked to couple each of the signals that are lightly coupled to the outer leads to each of the two identical memory devices connected in parallel. . • Other configurations known in the art provide an early integrated circuit that is lightly coupled to a multi-position lead frame, such as U.S. Patent No. 5,22, (9) to McShane (which is also incorporated by way of bow 1) Provided herein is a single integrated circuit that is wire bonded to a multilayer leadframe and includes a physical connection between portions of the multilayer leadframe within the package, and is formed using 烊^ Μ ^ 5 S Through-hole passages, the wires extend to the passage t to contact the lead frame layer of the lead frame layer fixed under the integrated body (10) oyster body circuit, thereby actuating the formation of the multi-voltage plane of the sealed device (4). Prior art packages for multiple integrated circuits, but continue to recognize "providing reduced manufacturing costs while maintaining package reliability." This need-improved multi-integrated circuit package and for packaging multiple integrated packages The circuit method is simple and reliable, allowing for any connection between the integrated circuit devices, requiring expensive inserts, printed circuit boards or substrates, and manufacturing costs are less than existing packages and methods. DETAILED DESCRIPTION OF THE INVENTION Various preferred embodiments of the present invention provide a package for a multi-semiconductor integrated circuit or die that is electrically connected or integrated to provide mechanical support for the integrated circuit. The facility is arbitrarily connected between the integrated circuits and provides an electrical connection to the external connection of the packaged device. The package of the present invention does not require an insert or substrate of the type used in the prior art, and the material is used. Conventional wire bonding and lead frame technology compatible with existing equipment and automated factory machines II known in the semiconductor processing industry for use and implementation of the present invention Group or special equipment. In a first embodiment of the invention, a first lead frame is provided and secured to a cover-simple insulator layer. The insulator layer has a channel for opening σ formed in certain locations and Covering certain leads of the lead frame of the channels. Other leads of the lead frame may extend to the outer boundary of the insulator or the edge of the insulator. Some leads of the lead frame may not extend 115880.doc •14· extend to the outside a connector. The first integrated circuit die is provided and secured adjacent to an inner end of the lead frame. In some embodiments, the lead frame can have an opening provided therein and the die can be placed inside In other embodiments, the 'die can be seated on the lead of the lead frame or under the lead of the lead frame. In a preferred embodiment, the die is wire bonded to the lead frame to integrate the die. One or more of the leads of the circuit are electrically connected to the leads of the lead frame. In other preferred embodiments, flip chip bonding can be used to laminate the leads of the lead frame with Die bonding, which is known in the art. The second leadframe is then placed on the i-th and opposite surfaces of the t-cap insulator. As for the leads of the first leadframe and with the leads A consistent system 'fixes certain leads of the second lead frame to cover the through holes of the insulator. Other leads of the lead frame may extend to the outside of the insulator layer for external electrical connection with the finished device and may be extended Out of the outer boundary of the insulator, the second integrated circuit die is placed close to the inner lead of the first lead frame. The second lead frame may have an inner end adjacent to the lead of the lead frame to receive the central portion of the die, Alternatively, the leads on the lead or the wafer lead frame under the cymbal may be used. From the die 塾 terminal on the second integrated circuit to the at least one lead of the leads of the second lead frame For example, a material connection or a flip chip connection. Applying t in eighteen, there are several and sometimes many wires that extend from the integrated circuit to the lead frame. Alternatively, the first and second lead frames may be attached to each other' and then any of the die is attached to its corresponding lead frame. Advantageously, some of the leads of the first and second 115880.doc 1324385 lead frames are electrically coupled through the channels in the insulator. In this aspect of the invention, the first and second integrated circuit dies can be electrically coupled in any position through a device that is electrically connected through the insulator between the two lead frames. In a first preferred embodiment, 'by physically deforming the leadframe leads of the first and second leads in a space within the channel in the insulator, and then physically contacting the two leads within the channel, Can be connected. In a preferred embodiment, conductive bonding is therefore performed between the two lead frames. Welding can be performed, for example, by heat applied energy, electric energy, ultrasonic energy, laser energy, or the like. In other preferred embodiments, between the two lead frames can be performed by providing a conductive material that is fixed within the channel (eg, as an electrically conductive conductive paste and that can be accomplished using thermal or electrical energy) Electrical connection. In other preferred embodiments, the insulator may be formed of an anisotropic conductive material 'the material initially acts as an insulator in all directions, but when pressure or thermal energy or both are applied in a region while maintaining the insulator in a planar orientation On top, the material becomes selectively conductive in the vertical direction. In general, a channel is an area in which a conductor adjacent to the top surface of the insulator is in electrical communication with a conductor adjacent the bottom surface of the insulator. The integrated circuit dies can be fixed to cover the opposite surfaces of the insulator so that the integrated circuit dies can be in a back-to-back relationship. Unlike the back-to-back configuration of the prior art, mirrored dies are not required when using the present invention because the method of forming an electrical connection through the insulator provided by the present invention allows for the arbitrarily connecting the terminals of both devices. As for some of the prior art packages, it is not necessary to align the terminals of the two integrated circuit dies. In addition, in some embodiments, for dram, eepr flash or other dynamic or non-volatile memory devices, the same can be used in the device, "grain roller powder y &amp; By the same integrated circuit, it is established as a larger package device. In other preferred embodiments, the die can have different functions, such as the memory controller 1 Body device, analog circuit and digital device, sensor and controller

置等，以在成品封裝式裝置中提供整合功能。Set to provide integration capabilities in a finished packaged device.

在替代性較佳具體實施例中，本發明可提供具有形成於 選擇位置中的通道之-絕緣體、覆蓋絕緣體層之—表面的 第-引線框架、覆蓋相對絕緣體層的第二引線框架、使用 已知的覆晶技術與第一引線框架耦合的第一積體電路，其 中將積體電路焊墊固^成實體上接近於所需引線並且形成 4料之球或塾，接著使用能量來回流該等球或塾以在晶粒 墊與引線的内部之間形成機械及電性連接，如以前成品裝 置具有透過絕緣體中的通道在第一積體電路與第二積體電 路之間進行的電性連接一樣，可使用覆晶技術同樣地將第 二積體電路與第二引線框架耦合。因為使用覆晶技術將此 較佳具體實施例中的第一及第二晶粒皆與引線框架耦合， 所以可將積體電路裝置配置成面對面關係。 在本發明及所附申請專利範圍内預期的替代性具體實施 例’包含組合覆晶連接與絲焊連接以便可使用覆晶技術將 一個晶粒與第一引線框架耦合，並且可使用（例如）絲焊將第 二晶粒與第二引線框架耦合。 115880.doc -17· 1324385In an alternative preferred embodiment, the present invention can provide an insulator having a channel formed in a selected location, a first lead frame covering the surface of the insulator layer, a second lead frame covering the opposite insulator layer, and a use A first integrated circuit in which a flip chip technique is coupled to a first leadframe, wherein the integrated circuit pads are solidly close to the desired leads and form a ball or crucible of 4 materials, followed by energy to reflow the The ball or the crucible is formed to form a mechanical and electrical connection between the die pad and the inside of the lead, as in the prior art device having electrical properties between the first integrated circuit and the second integrated circuit through the passage in the insulator. Similarly, the second integrated circuit can be coupled to the second lead frame using flip chip technology. Since the first and second dies in the preferred embodiment are coupled to the lead frame using flip chip technology, the integrated circuit device can be configured in a face to face relationship. Alternative embodiments that are contemplated within the scope of the present invention and the appended claims include a combined flip chip bond and a wire bond connection such that a die can be coupled to the first lead frame using flip chip technology and can be used, for example, Wire bonding couples the second die to the second lead frame. 115880.doc -17· 1324385

在另-較佳具體實施例中，使用本發明之封裝設備及方 法形成可移除儲存卡；—絕緣體層具有形成於選擇位置中 :通道，第-引線框架係固定成覆蓋絕緣體並具有覆蓋絕 、·體中的通道之某些引線’將為非揮發性記憶體裝 -積體電路固定成接近於第一引線框架並且 體電路與引線框架之間進行至少—個電性連接，將第二積 :電路提供成接近於第二引線框架’其係固定成覆蓋絕緣 體之相對表面並具有某些引線，該等引線覆蓋絕緣體中的 通道’第二積體電路為用於操作非揮發性記憶體I置的控 制器電路，將第二積體電路與第二㈣框架電性連接。 藉由使用本發明之方法，透過絕緣體中的通道在第一引 線框架與第二引線框架之間形成電性連接，在記憶體控制 器與非揮發性記憶體之間進行電性連接。可藉由下列方式 完成儲存）：過才莫製或密封絕緣冑、第—及第二積體電路 與第-及第二引線框架之部分，將該等引線框架之其餘外 部部分用於形成成品儲存卡之外部連接。 有利的係，用於本發明之較佳具體實施例的絕緣體可包 括各種已知材料。因為在絕緣體内或上不需要電性連接、 複雜的多層選路或金屬化圖案，所以絕緣體可採用將第— 及第二引線框架彼此電性絕緣的任何材料形成並且還可具 有形成於其内的穿透孔通道。可使用塑膠、玻璃、陶瓷、 玻璃纖維、樹脂、PC板、膠帶、膜、紙及其他絕緣體。化 學蝕刻光微影、雷射鑽孔或機械鑽孔程序可形成通道。可 將塑膠或樹脂模製用於形成其中形成通道的絕緣體。絕緣 115880.doc -18·In another preferred embodiment, the removable memory card is formed using the packaging apparatus and method of the present invention; the insulator layer is formed in a selected location: the channel, the first lead frame is fixed to cover the insulator and has a cover Some of the leads of the channel in the body will be fixed for the non-volatile memory-integrated circuit to be close to the first lead frame and at least one electrical connection between the body circuit and the lead frame, and the second Product: the circuit is provided close to the second lead frame 'which is fixed to cover the opposite surface of the insulator and has certain leads that cover the channel in the insulator'. The second integrated circuit is used to operate the non-volatile memory. The controller circuit disposed in the first step electrically connects the second integrated circuit to the second (four) frame. By using the method of the present invention, an electrical connection is made between the first lead frame and the second lead frame through a channel in the insulator, and an electrical connection is made between the memory controller and the non-volatile memory. The storage can be completed by: replacing or insulating the insulating germanium, the first and second integrated circuits, and the portions of the first and second lead frames, and using the remaining outer portions of the lead frames to form the finished product External connection to the memory card. Advantageously, the insulator used in the preferred embodiment of the invention may comprise a variety of known materials. Since no electrical connection, complicated multilayer routing or metallization pattern is required in or on the insulator, the insulator may be formed of any material that electrically insulates the first and second lead frames from each other and may also have a formation therein Through the hole channel. Plastic, glass, ceramic, fiberglass, resin, PC board, tape, film, paper and other insulators can be used. Chemical etching lithography, laser drilling or mechanical drilling procedures can form channels. Plastic or resin molding can be used to form an insulator in which the channels are formed. Insulation 115880.doc -18·

OJ 可以形成為具有較大範圍的厚度並可按需要而為剛性或 柔性材料。可對絕緣體進行過模製以完成封裝式裝置 者可將絕緣體、積體電路及引線框架裝配件㈣在外殼之 空腔中或預形成的主體結構内，該結構係後來使用蓋子或 層以黏結劑或密封劑進行密封。 在另-較佳具體實施例中，可藉由併人絕緣體之任—侧 上的多個積體電路晶粒而在單一封裝中提供整合系統，將 多個晶粒與透過絕緣體中的通道所輕合的引線框架絲焊以 在積體電路之間進行任意連接，#中用於系統的封裝式裝 配件包含被動元件，例如電阻器、電容器或感應器。接著 可以將整個裝配件過模製成使用本發明之方法加以提供的 成品封裝式系統。 本發明之具體實施例的優點包含使用與現有工具相容的 傳統絲焊或覆晶技術與封裝模製方法，並使用與現有自動 化半導體封裝基礎構造相容的材料，提供形成包含得到彼 此電性麵合的多積體電路裝置之多積體電路模組而無需先 前技術之複雜插入物、柔性電路、層壓基板或圖案化印刷 電路板的設備與方法。 以上說明已更廣泛地概述本發明之具體實施例的特徵與 技術優點以便可較佳地瞭解以下本發明之詳細說明。熟習 技術人士應瞭解可將揭示的概念及特定具體實施例輕易地 用作修改或設計其他結構或程序以實行本發明之相同目的 之依據。熟習技術人士應瞭解此類等效構造並不脫離如所 附申請專利範圍提出的本發明之精神與範疇。 115880.doc •19- 【實施方式】 、乂下說明目則較佳具體實施例的操作與製造。然而，所 說月的具體實&amp;例及範例並非本發明所預期的僅有應用或 ^用。所說明的特定具體實施例僅說明用於實施及使用本 &amp;月的特定方式’而不限制本發明之範_。該等圖係用於 說明之目的而非按比例繪製。 圖3拖述用於本發明之一較佳具體實施例的一絕緣體層 3〇〇之俯視圖。絕緣體層3〇〇可包括與半導體處理步驟相容 的許多絕緣材料之任何絕緣材料，例如μ，γ、卿以、 Kapton及其他膜、絕緣紙 '樹脂、聚醯亞胺、玻璃、玻璃 纖維4其在s亥技術中已為人所知。層300具電性絕緣性且 較佳具有與某些熱程序（例如傳送模製）相容的實體特徵。絕 緣層中的穿透孔通道3〇丨係形成於預定位置處，如以下詳細 說明，並提供形成於絕緣層300中的穿透孔。穿透孔通道可 以具有任何大小但在一較佳具體實施例中為約3至1〇 mil的 直仫且較佳為約5 mii的直徑。在欲加以說明的第一較佳具 體實施例通道為開放式穿透孔；在以下說明的其他具 體實施例中，通道可採用導電膏或黏結劑加以填充。 圖4以斷面圖描述圖3之絕緣層。在圖4中，穿透孔通道丄 係顯示為延伸穿過絕緣層3〇〇β可採用（例如）雷射鑽孔、機 械鑽孔、蝕刻、衝孔或使用其他措施來形成穿透孔通道3〇1 以在材料（例如模製）中形成孔。可將光微影用於採用定界孔 之位置及尺寸所使用的陽或陰光阻來圖案化表面上的蝕刻 阻抗層，可應用選擇性蝕刻來移除材料，並接著可剝離圖 115880.doc •20- 1324385 案層’此在該技術中已為人所知。 圖5描述在已完成若干裝配步驟之後，本發明之一較佳具 體實施例的俯視圖。在圖5中，絕緣體層300已具有形成於 選擇位置中的穿透孔通道301。一引線框架具有引線5〇2並 包含覆蓋穿透孔通道位置301的某些引線。將積體電路晶粒 303固定成接近於引線5〇2之内部端。焊絲5〇5得以形成並將 知墊507與引、線502電性輕合。雖然在圖5中所描述的視圖中 不可見，.但是執行對稱操作以定位絕緣體層3〇〇之相對表面 上的第二引線框架及第二積體電路晶粒，其中將第二引線 框架之某些引線定位在穿透孔通道3〇丨下面。 圖6描述本發明之一較佳具體實施例在裝配之中間階段 的斷面圖。在圖6中’積體電路晶粒303係顯示成固定在絕 緣體層300之第一表面上。引線框架5〇2係以斷面圖顯示， 並且焊絲505係顯示成將積體電路晶粒之焊墊與引線框架 引線502連接。穿透孔通道3〇1係顯示為形成於絕緣層3〇〇 中的選擇位置處。 引線框架601係顯示成固定在絕緣體層3〇〇下面並在穿透 孔通道301下面延伸。使用焊絲605將積體電路晶粒604從焊 墊603耦合至引線框架601引線。 如圖6所說明，可將引線框架引線耦合在一起以透過穿透 孔通道位置301内的絕緣體形成實體及電性連接。在圖6 中將焊接工具607用於在穿透孔通道301中將引線5〇2及 602掛壓在-起並使其變形，而且將施加能量以使兩個引線 變為焊接在可將超聲波、電性及/或熱能量用於形成 115880.doc •21 · 1324385 焊接，所預期的方法包含使用電阻焊接、電容放電或雷射 悍接。在某些具體實施例中，可在裝配前使用材料藉由點 電鍍或其他方法而塗布引線框架引線以協助形成焊接。在 每個穿透孔通道位置3〇lt執行此輕合操作。藉由適當地設 計引線框架及絕緣體層遍，可以在兩個積體電路之間的任 何所需位置處進行電性連接，如圖5及6所示。 在一較佳方法中，將一工具（例如圖6中的工具⑼乃用於 在上與下引線框架引線之間形成焊接並同時在絕緣體層 3〇〇中形成穿透孔通道3〇1，即絕緣體最初並沒有形成於其 中的孔，在任一側上將引線框架固定成彼此相對，而且在 所需位置處將自上與下引線框架的引線耦合在一起。在此 較佳方法中，焊接工具6〇7係用於將能量（例如熱）施加於在 需要連接之位置處的引線，絕緣體材料會熔化或蒸發以回 應能量，並且在移除絕緣體材料時形成穿透孔通道3〇1，使 引線在穿透孔通道3〇1中實體變形並接著在單一連續操作 中將該等引線焊接在一起。以此方法，因為絕緣體不需要 圖案化或設計，所以可在較大程度上減少絕緣體層的成本。 圖7a與7b描述用於在絕緣體層3〇〇中的穿透孔通道位置 301處連接上與下引線框架引線的替代性方法。在圖7a中， 以採用導電材料705加以填充的穿透孔通道301來描述用於 本發明之封裝的絕緣體層300之一部分。將導電材料（例如 引線膏）沉積在穿透孔通道3〇1中並後來隨裝配程序的繼續 而將該材料固定在引線框架引線之間。導電材料完成如圖6 所7F的兩個積體電路裝置之間的電性連接。導電材料可以 115880.doc -22· 體電路曰曰粒並且執行絲焊或覆晶處理以在採用或不採用黏 、’。劑或膠帶的情況下將積體電路與引線框㈣合；接著將 引=框架裝配件固定在絕緣體層3⑽之個別相對表面上，藉 由提則圖案化絕緣體層3〇〇而已經提供穿透孔通道％ 1，並 接著藉由焊接，使用如以上說明的導電膏或焊料或各向性 導體連接而將引線框架_合在—起。最後，可賴品裝配 件進行過模製或液態封膠囊封，從而完成封裝。可採用另 替代f生方法提供如以上說明的絕緣體層3〇〇而無形成於 其内的穿透孔通道3〇卜並可將工具用於焊接且同時形成絕 緣體層300中的穿透孔通道3〇ι。 雖然在本文中詳細說明本發明之較佳具體實施例及其優 點，但疋應瞭解可對所說明的具體實施例進行各種改動、 替換及變更而不脫離如所附申請專利範圍定義的本發明之 精神與範疇。此外，本發明之範疇並非意欲限於該說明書 中說明的電路、結構 '方法及步驟之特定具體實施例。因 此，所附申請專利範圍係欲意在其範疇内包含利用本發明 的該等程序、機器、製造、事件的組成、構件、方法或步 驟以及利用本發明的該等變動與解決方&amp;，其為熟習技術 人士所明白。 【圖式簡單說明】 為更完全地瞭解本發明及其優點，現在參考以上結合附 圖所作的說明，該等附圖為代表性說明’其係提供以便於 瞭解而非按比例繪製，在該等附圖中： 圖1以圖la之俯視圖及圖ib之仰視圖描述一先前技術可 115880.doc -26 - 移除儲存卡封製； 圖2描述包含一記憶體裝置及一控制器裝置的一先前技 術可移除儲存卡（例如圖1所說明）之斷面圖； 圖3描述具有可併入本發明之一較佳具體實施例中的穿 透孔通道之一絕緣體層的俯視圖； 圖4描述圖3之該絕緣體層之斷面圖； 圖5描述一絕緣體層（例如圖3、4所說明且具有固定在該 絕緣體層上的一引線框架及一積體電路）之俯視圖； 圖6以斷面圖描述圖5之裝置，後隨額外的處理步驟； 圖7a、7b以斷面圖描述本發明之該絕緣體層之額外較佳 具體實施例； 圖8描述為本發明之一較佳具體實施例的一成品封裝式 裝置之斷面圖； 圖9描述為本發明之另一較佳具體實施例的另一成品封 裝式裝置之斷面圖； 圖10描述圖9之裝置的俯視圖，以及 圖11描述為本發明之另一較佳具體實施例的另一成品封 裝式裝置之斷面圖。 不同圖中的對應數字及符號一般指對應的部件，除非另 有指示。該等圖係繪製成清楚地說明較佳具體實施例之相 關方面而不必按比例繪製。 【主要元件符號說明】 100 封裝 101 端子 115880.doc -27- 1324385 200 儲存卡 201 外殼 203 焊絲 204 積體電路晶粒 205 積體電路晶粒 206 平台 208 層壓基板 209 晶粒附者材料 211 囊封劑 300 絕緣體層 301 穿透孔通道 303 積體電路晶粒 502 引線 505 焊絲 507 焊墊 601 引線框架 602 引線 603 焊墊 604 積體電路晶粒 605 焊絲 607 焊接工具 609 附著物 705 導電材料 801 封裝 115880.doc 28 1324385 803 微囊 807 焊接 809 積體電路 901 封裝 902 囊封區域 903 囊封劑The OJ can be formed to have a wide range of thicknesses and can be a rigid or flexible material as desired. The insulator can be overmolded to complete the packaged device. The insulator, integrated circuit, and lead frame assembly (4) can be placed in the cavity of the housing or in the preformed body structure, which is later bonded using a cover or layer. The agent or sealant is sealed. In another preferred embodiment, an integrated system can be provided in a single package by a plurality of integrated circuit dies on either side of the insulator, the plurality of dies and the channels in the permeable insulator Light-bonded lead frame wire bonds for arbitrary connection between integrated circuits, and packaged assemblies for systems in # contain passive components such as resistors, capacitors or inductors. The entire assembly can then be overmolded into a finished packaged system that is provided using the method of the present invention. Advantages of particular embodiments of the present invention include the use of conventional wire bonding or flip chip techniques and package molding methods compatible with existing tools, and the use of materials that are compatible with existing automated semiconductor package infrastructures, providing formation including electrical properties A multi-integrated circuit module of a multi-integrated circuit device that does not require prior art complex inserts, flexible circuits, laminated substrates, or devices and methods for patterning printed circuit boards. The features and technical advantages of the specific embodiments of the present invention are set forth in the <RTIgt; Those skilled in the art will recognize that the concept and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures or procedures to practice the same. Those skilled in the art will appreciate that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. 115880.doc • 19- [Embodiment] The following is a description of the operation and manufacture of a preferred embodiment. However, the specific examples and examples of the month are not the only applications or uses contemplated by the present invention. The specific embodiments described are merely illustrative of specific ways to implement and use the present invention and do not limit the scope of the invention. The figures are for illustrative purposes and are not drawn to scale. Figure 3 is a top plan view of an insulator layer 3 for use in a preferred embodiment of the present invention. The insulator layer 3 can comprise any insulating material of a plurality of insulating materials compatible with the semiconductor processing steps, such as μ, γ, 卿, Kapton and other films, insulating paper 'resin, polyimine, glass, fiberglass 4 It is already known in the shai technology. Layer 300 is electrically insulative and preferably has physical features that are compatible with certain thermal procedures, such as transfer molding. The through hole passage 3 in the insulating layer is formed at a predetermined position as will be described in detail below, and a penetration hole formed in the insulating layer 300 is provided. The through-hole passageway can have any diameter, but in a preferred embodiment, a diameter of about 3 to 1 mil mil and preferably about 5 mii. The first preferred embodiment channel to be described is an open through hole; in other specific embodiments described below, the channel may be filled with a conductive paste or a binder. Figure 4 depicts the insulating layer of Figure 3 in a cross-sectional view. In FIG. 4, the through-hole channel lanthanide is shown extending through the insulating layer 3〇〇β, for example, by laser drilling, mechanical drilling, etching, punching, or using other measures to form a through-hole channel. 3〇1 to form a hole in a material such as molding. Photolithography can be used to pattern the etched resistive layer on the surface using the positive or negative photoresist used to position and size the hole. Selective etching can be used to remove the material, and then the strippable pattern 115880. Doc •20-1324385 Case 'This is already known in the technology. Figure 5 depicts a top plan view of a preferred embodiment of the present invention after several assembly steps have been completed. In Fig. 5, the insulator layer 300 already has a through hole passage 301 formed in a selected position. A lead frame has leads 5〇2 and includes certain leads that cover the through-hole channel locations 301. The integrated circuit die 303 is fixed close to the inner end of the lead 5〇2. The wire 5〇5 is formed and the pad 507 is electrically coupled to the lead wire 502. Although not visible in the view depicted in FIG. 5, a symmetrical operation is performed to position the second lead frame and the second integrated circuit die on the opposite surfaces of the insulator layer 3, wherein the second lead frame is Some leads are positioned below the through hole channel 3〇丨. Figure 6 depicts a cross-sectional view of a preferred embodiment of the present invention at an intermediate stage of assembly. In Fig. 6, the integrated circuit die 303 is shown to be fixed to the first surface of the insulator layer 300. The lead frame 5〇2 is shown in a cross-sectional view, and the wire 505 is shown as connecting the pads of the integrated circuit die to the lead frame leads 502. The through hole passage 3〇1 is shown to be formed at a selected position in the insulating layer 3〇〇. The lead frame 601 is shown to be fixed under the insulator layer 3 and extends below the through hole passage 301. Integrated circuit die 604 is coupled from bond pad 603 to leadframe 601 leads using wire 605. As illustrated in Figure 6, the leadframe leads can be coupled together to form a physical and electrical connection through the insulator within the through-hole channel location 301. The soldering tool 607 is used in Fig. 6 to hang the leads 5〇2 and 602 in the through-hole passage 301 and deform them, and energy will be applied to make the two leads become soldered to the ultrasonic wave. , electrical and / or thermal energy is used to form 115880.doc • 21 · 1324385 welding, the expected method includes the use of resistance welding, capacitor discharge or laser splicing. In some embodiments, the leadframe leads can be coated with materials prior to assembly by spot plating or other methods to aid in the formation of the weld. This light fitting operation is performed at each penetration hole passage position 3 〇 lt. By appropriately designing the lead frame and the insulator layer, electrical connections can be made at any desired location between the two integrated circuits, as shown in Figures 5 and 6. In a preferred method, a tool (e.g., tool (9) in Fig. 6 is used to form a weld between the upper and lower lead frame leads while simultaneously forming a through hole channel 3?1 in the insulator layer 3? That is, the insulator does not initially have holes formed therein, the lead frames are fixed to each other on either side, and the leads from the upper and lower lead frames are coupled together at a desired position. In the preferred method, soldering The tool 6〇7 is used to apply energy (for example, heat) to the lead at a position where connection is required, the insulator material melts or evaporates in response to energy, and forms a through-hole passage 3〇1 when the insulator material is removed, The leads are physically deformed in the through-hole channels 3〇1 and then soldered together in a single continuous operation. In this way, the insulator can be reduced to a large extent because the insulator does not require patterning or design. The cost of the layers. Figures 7a and 7b depict an alternative method for joining the upper and lower lead frame leads at the through hole channel locations 301 in the insulator layer 3A. In Figure 7a, A portion of the insulator layer 300 used in the package of the present invention is described by a conductive material 705 filled through hole channel 301. A conductive material (e.g., a lead paste) is deposited in the through hole channel 3〇1 and later with the assembly process. Continuing to fix the material between the lead frame leads. The conductive material completes the electrical connection between the two integrated circuit devices of Figure 7F. The conductive material can be granulated and Perform wire bonding or flip chip processing to bond the integrated circuit to the lead frame (4) with or without adhesive, tape or tape; then attach the frame = frame assembly to the individual opposing surfaces of the insulator layer 3 (10) Providing the through hole channel % 1 by drawing the patterned insulator layer 3 并 and then bonding the lead frame by soldering using a conductive paste or solder or an isotropic conductor connection as explained above Finally, the package can be molded or sealed in a liquid state to complete the package. The insulator layer 3 as described above can be provided instead of being formed in the package. The through hole channel 3 can be used for soldering and simultaneously forming the through hole channel 3〇 in the insulator layer 300. Although a preferred embodiment of the present invention and its advantages are described in detail herein, It is to be understood that various modifications, alternatives and changes may be made to the specific embodiments described without departing from the spirit and scope of the invention as defined in the appended claims. Specific embodiments of the circuits, structures, methods, and steps. Accordingly, the scope of the appended claims is intended to include within their scope the compositions, components, methods, or These variations and solutions of the present invention will be apparent to those skilled in the art. BRIEF DESCRIPTION OF THE DRAWINGS For a fuller understanding of the present invention and its advantages, reference now to the The drawings are provided for the purpose of illustration and description, The bottom view depicts a prior art 115880.doc -26 - removing the memory card seal; Figure 2 depicts a prior art removable memory card (such as illustrated in Figure 1) including a memory device and a controller device 3 is a plan view of an insulator layer having a through-hole passage that can be incorporated into a preferred embodiment of the present invention; FIG. 4 depicts a cross-sectional view of the insulator layer of FIG. 3; A top view of an insulator layer (such as illustrated in Figures 3 and 4 and having a lead frame and an integrated circuit mounted on the insulator layer); Figure 6 depicts the device of Figure 5 in a cross-sectional view, followed by additional processing steps 7a, 7b are cross-sectional views showing additional preferred embodiments of the insulator layer of the present invention; FIG. 8 is a cross-sectional view of a finished package device in accordance with a preferred embodiment of the present invention; A cross-sectional view of another finished packaged device is described as another preferred embodiment of the present invention; FIG. 10 depicts a top view of the device of FIG. 9, and FIG. 11 depicts another preferred embodiment of the present invention. Another finished packaged device Sectional view. Corresponding numerals and symbols in the different figures generally refer to the corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily to scale. [Main component symbol description] 100 package 101 terminal 115880.doc -27- 1324385 200 memory card 201 housing 203 wire 204 integrated circuit die 205 integrated circuit die 206 platform 208 laminated substrate 209 die attach material 211 capsule Sealant 300 Insulator layer 301 Through-hole channel 303 Integrated circuit die 502 Lead 505 Wire 507 Pad 601 Lead frame 602 Lead 603 Pad 604 Integrated circuit die 605 Wire 607 Soldering tool 609 Attachment 705 Conductive material 801 Package 115880.doc 28 1324385 803 Microcapsules 807 Soldering 809 Integral Circuit 901 Package 902 Encapsulated Area 903 Encapsulant

115880.doc -29115880.doc -29

Claims (1)

第095140244號專利申請案 中文申請專利範圍替換本(9'8年9月） 十、申請專利範圍： L 一種多晶粒半導體封裝，其包括： ?絕緣體，其具有一第一表面、與該第一表面相對的 一第二表面、以及在預定位置處的一或多個穿透孔通道； 第一引線框架，其至少部分地覆蓋該第一表面並具 有複數個引線，覆蓋一或多個穿透孔通道之該等引線的 部分偏轉入該或該等穿透孔通道； 一第一積體電路晶粒，其係鄰近於該第一引線框架之 該複數個引線之至少一個引線且與該至少一個引線電性 耦合； 一第二引線框架’其至少部分地覆蓋該第二表面並具 有複數個引線；以及 一第二積體電路晶粒’其係鄰近於該第二引線框架之 4複數個引線之至少一個引線且與該至少一個引線電性 耦合； 其中透過該絕緣體中的該等穿透孔通道之一將該第一 引線框架之該複數個引線之至少一個引線與該第二引線 框杀之s亥複數個引線之一對應引線電性叙合。 2·如請求項丨之封裝，其中該封裝進一步包括一囊封劑，其 至少部分地密封該絕緣體層、該等第一及第二積體電路 晶粒、以及該等第一及第二引線框架。 如π求項1之封裝，其中該等第一及第二積體電路晶粒係 相同的。 如叫求項1之封裝’其中該等第一及第二積體電路晶粒分 115880-980911.doc 制时積體电路及一記憶體陣列積體I 5.如請求項4之封 】檟體電路。 裝其中S玄記憶體陣列積體電路包括__非 揮發性記憶體裝置。 岭包括非 6 ·如凊求項1之封_，装由1丄 ΐ裝其中藉由焊絲將該等第— -路晶粒分別與該等第-貝- 7·如請求们之封梦H 線框表電性輕合。 、八中藉由覆晶連接將該等第—及第一 合。曰叔刀別與該等第-及第二引線框架電性耦 8. 如請求項6之封裝 背對背關係。 9. 如請求項7之封裝 面對面關係。 其中該等第一及第二積體電路晶粒係 其中該等第一及第二積體電路晶粒係 月求項1之封裝，其中該等穿透孔通道係採用導電材料 充°亥材料實體接觸該第一引線框架之該至少一個引 線0 士吻求項1之封裝’其中該等第一及第二引線框架之每個 的至少—彳 ''個引線在該絕緣體層中的該等穿透孔通道之至 少一個通道内係彼此實體焊接。 12.如請求項1 巧1之封裝，其中覆蓋寶透孔通道之一或多個該第 '、泉樞木的S玄專引線的部分偏轉入該或該等穿透孔通 道。 種氣造—多晶粒積體電路封裝的方法，其包含步驟： 提供一絕緣層’其具有一第一表面及一第二相對表面； §Λ、、邑緣層中的所需位置處形成一或多個穿透孔通 115880-9S09H.doc 提供一第一引線框架，其具有複數個引線至少部分地 覆蓋該第一表面； 提供一第二引線框架，其具有複數個引線至少部分地 覆蓋該第二表面； 將一第一積體電路晶粒耦合至該第一引線框架的至少 一引線； 將一第二積體電路晶粒耦合至該第二引線框架的至少 一引線； 在覆蓋一穿透孔通道的一位置，將該第一引線框架的 一引線變形進入該穿透孔通道； 使變形進入該通道的該引線，在該絕緣層中經過該穿 透孔通道，電性連結至該第二引線框架的一對應引線； 藉此該等第一及第二積體電路晶粒彼此電性耦合。 14. 如請求項13的方法，其進一步包含步驟： 至少部分地囊封該絕緣層、該等第一及第二積體電路 晶粒及該等第一及第二引線框架。 15. 如請求項13的方法，其進—步包含形成該第二引線框架 的該對應引線的一部份進入該穿透孔通道之步驟。 16. 如清求項15的方法，其中電性連結之步驟包含在該穿透 孔通道内泫等第—及第二引線框架間形成一實體焊接。 17. 如明求項15的方法，其中電性連結之步驟包含在該穿透 孔通道内§玄等第一及第二弓丨線框架間的第一及第二部分 之間提供一導電黏結劑。 115880-980911 .doc 1324385 方法，其中將第—及第 及第二引線框架的步驟 18.如請求項13的 合至該等第一 電路晶粒。 二積體電路晶粒耦 包含耦合相同積體 19.如知求項13的方法，其 ^ 合至該等第一月笛__ 及第二積體電路晶粒耦 二=電路晶粒輕合至該第—引 積體電路晶粒輕合至該第二引線框架。#控心 20.如請求項19的方法，盆 耦人5 # # 、 . 6己I體陣列積體電路晶粒 ^第一引線框架之步驟包含 體陣列積體電路晶粒。 匕3輕。非揮發性記憶 21. 步包含在非揮發性記憶體陣列 的非揮發性記憶體積體電路晶 如請求項1 3的方法，進— 積體電路晶粒上堆疊額外 粒之步驟。 22.如請求項13的方法，其中 甲將°&quot;第—及第二積體電路晶 拉輕口至該等第-及第二引線框架之步驟包含在該等第 -及弟二積體電路晶粒與該等第—及第二引線框架間形 成絲焊。 23. 如請求項15的方法，其中輕合該等第—及第二積體電路 晶粒之步驟進一步包含將該等積體電路晶粒放置成背對 背關係之步驟。 24. 如請求項13的方法，其中將該等第—及第二積體電路晶 粒麵合至料第一及第二引線框架之步驟包含在該等第 一及第二積體電路晶粒與該等第—及第二引線框架之間 形成覆晶連接。 25. 如請求項24的方法，其中將該等第—及第二積體電路晶 115880-980911.doc 1324385 粒耦合至該等第一及第二引線框架之步驟進一步包含將 該等第一及第二積體電路晶粒放置成面對面關係。Patent Application No. 095140244 (Replacement of Chinese Patent Application Scope (September 9'8) X. Patent Application Range: L A multi-die semiconductor package comprising: an insulator having a first surface and the same a second surface opposite the surface, and one or more through hole channels at the predetermined position; the first lead frame at least partially covering the first surface and having a plurality of leads covering one or more of the through holes Portions of the leads of the through-hole channel are deflected into the or-through vias; a first integrated circuit die adjacent to at least one of the plurality of leads of the first lead frame and The at least one lead is electrically coupled; a second lead frame 'which at least partially covers the second surface and has a plurality of leads; and a second integrated circuit die 'which is adjacent to the second lead frame 4 At least one lead of the plurality of leads is electrically coupled to the at least one lead; wherein the plurality of leads of the first lead frame are passed through one of the through hole channels in the insulator At least one lead and the second lead frame s Hai kill one of a plurality of leads corresponding to the leads are electrically bonded Syria. 2. The package of claim 1, wherein the package further comprises an encapsulant at least partially sealing the insulator layer, the first and second integrated circuit dies, and the first and second leads frame. The package of claim 1, wherein the first and second integrated circuit chips are identical. For example, the package of claim 1 wherein the first and second integrated circuit dies are 115880-980911.doc integrated circuit and a memory array integrated body I 5. As claimed in claim 4 槚Body circuit. The S-shaped memory array integrated circuit includes a __ non-volatile memory device. The ridge includes a non-6 · 凊 项 1 1 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The wire frame is electrically light. The eighth is connected to the first and the first by flip chip connection. The 曰 knife is electrically coupled to the first and second lead frames. 8. The package of claim 6 is back-to-back. 9. The encapsulation of claim 7 is a face-to-face relationship. The first and second integrated circuit dies are the packages of the first and second integrated circuit dies, wherein the through-hole channels are made of a conductive material. a package in which the at least one lead of the first lead frame contacts the first lead frame, wherein the at least one of each of the first and second lead frames is in the insulator layer At least one of the channels of the through-hole passage is physically welded to each other. 12. The package of claim 1, wherein a portion of one or more of the S-channels of the first and second pivots is deflected into the or through-hole channels. A method for encapsulating a multi-die integrated circuit package, comprising the steps of: providing an insulating layer having a first surface and a second opposing surface; forming a desired location in the germanium and germanium edge layers One or more through-holes 115880-9S09H.doc provide a first lead frame having a plurality of leads at least partially covering the first surface; providing a second lead frame having a plurality of leads at least partially covered The second surface; a first integrated circuit die is coupled to the at least one lead of the first lead frame; a second integrated circuit die is coupled to the at least one lead of the second lead frame; a position of the through hole channel, the lead of the first lead frame is deformed into the through hole channel; the lead that is deformed into the channel passes through the through hole channel in the insulating layer, and is electrically connected to a corresponding lead of the second lead frame; whereby the first and second integrated circuit dies are electrically coupled to each other. 14. The method of claim 13, further comprising the step of: at least partially encapsulating the insulating layer, the first and second integrated circuit dies, and the first and second lead frames. 15. The method of claim 13, further comprising the step of forming a portion of the corresponding lead of the second leadframe into the through-hole passage. 16. The method of claim 15, wherein the step of electrically connecting comprises forming a solid weld between the first and second lead frames in the through-hole passage. 17. The method of claim 15, wherein the step of electrically connecting comprises providing a conductive bond between the first and second portions of the first and second archwire frames in the through-hole channel Agent. 115880-980911 .doc 1324385, wherein the steps of the first and second and second lead frames are as disclosed in claim 13 to the first circuit dies. The second integrated circuit die coupling includes a method of coupling the same integrated body 19. According to the method of claim 13, the method is coupled to the first moon flute __ and the second integrated circuit die coupling 2 = circuit die bonding The die of the first-integrator circuit is lightly coupled to the second lead frame. #控心 20. The method of claim 19, the basin coupling person 5 # #, . 6 hex I body array integrated circuit die ^ the first lead frame step comprises a body array integrated circuit die.匕 3 light. Non-Volatile Memory 21. Steps include a non-volatile memory bulk circuit circuit in a non-volatile memory array, as in the method of claim 13, and the step of stacking additional particles on the integrated circuit die. 22. The method of claim 13, wherein the step of gently pulling the first and second lead circuits to the first and second lead frames is included in the first and second integrated bodies A wire bond is formed between the circuit die and the first and second lead frames. 23. The method of claim 15, wherein the step of aligning the first and second integrated circuit dies further comprises the step of placing the integrated circuit dies in a back-to-back relationship. 24. The method of claim 13, wherein the step of planarizing the first and second integrated circuit dies to the first and second lead frames is included in the first and second integrated circuit dies A flip chip connection is formed between the first and second lead frames. 25. The method of claim 24, wherein the step of coupling the first and second integrated circuit crystals 115880-980911.doc 1324385 to the first and second lead frames further comprises: The second integrated circuit dies are placed in a face to face relationship. 115880-980911.doc 1324385 第095140244號專利申請案 中文圖式替換頁(98年9月）115880-980911.doc 1324385 Patent Application No. 095140244 Chinese Graphic Replacement Page (September 98) unocoUnoco CSIS 80CVJ 60CSI U&lt;N 115880-fig-980911.doc 1324385 第095140244號專利申請案 中文圖式替換頁(98年9月）CSIS 80CVJ 60CSI U&lt;N 115880-fig-980911.doc 1324385 Patent Application No. 095140244 Chinese Graphic Replacement Page (September 98) 115880-fig-980911.doc 1324385 第095140244號專利申請案-中文圖式替換頁(98年9月）-115880-fig-980911.doc 1324385 Patent Application No. 095140244 - Chinese Graphic Replacement Page (September 98) - 115880-fig-980911.doc 1324385 第095140244號專利申請案 中文圖式替換頁(98年9月） «115880-fig-980911.doc 1324385 Patent Application No. 095140244 Chinese Graphic Replacement Page (September 98) « 115880-fig-980911.doc -9- 1324385 第095140244號專利申請案 中文圖式替換頁(98年9月）115880-fig-980911.doc -9- 1324385 Patent Application No. 095140244 Chinese Graphic Replacement Page (September 98) 115880-fig-980911.doc115880-fig-980911.doc
TW095140244A 2005-11-01 2006-10-31 Multiple die integrated circuit package TWI324385B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/264,556 US7352058B2 (en) 2005-11-01 2005-11-01 Methods for a multiple die integrated circuit package
US11/264,112 US7511371B2 (en) 2005-11-01 2005-11-01 Multiple die integrated circuit package

Publications (2)

Publication Number Publication Date
TW200746381A TW200746381A (en) 2007-12-16
TWI324385B true TWI324385B (en) 2010-05-01

Family

ID=37680599

Family Applications (2)

Application Number Title Priority Date Filing Date
TW098135181A TWI475662B (en) 2005-11-01 2006-10-31 Multiple die integrated circuit package
TW095140244A TWI324385B (en) 2005-11-01 2006-10-31 Multiple die integrated circuit package

Family Applications Before (1)

Application Number Title Priority Date Filing Date
TW098135181A TWI475662B (en) 2005-11-01 2006-10-31 Multiple die integrated circuit package

Country Status (4)

Country Link
EP (1) EP1949440A2 (en)
KR (1) KR100996982B1 (en)
TW (2) TWI475662B (en)
WO (1) WO2007053606A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI405279B (en) * 2010-07-23 2013-08-11 Global Unichip Corp Packaging of semiconductor components

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4288841A (en) 1979-09-20 1981-09-08 Bell Telephone Laboratories, Incorporated Double cavity semiconductor chip carrier
US4423468A (en) * 1980-10-01 1983-12-27 Motorola, Inc. Dual electronic component assembly
JPS5763850A (en) * 1980-10-06 1982-04-17 Nec Corp Semiconductor device
US5138438A (en) 1987-06-24 1992-08-11 Akita Electronics Co. Ltd. Lead connections means for stacked tab packaged IC chips
JPH0330494A (en) * 1989-06-28 1991-02-08 Sharp Corp Through-hole forming method for flexible circuit board
AU4058693A (en) * 1992-06-15 1994-01-04 Dyconex Patente Ag Process for producing subsequently conditionable contact points on circuit substrates and circuit substrates with such contact points
DE19522338B4 (en) * 1995-06-20 2006-12-07 Pac Tech-Packaging Technologies Gmbh Chip carrier assembly with a via
FR2746678B1 (en) * 1996-03-26 1998-07-03 Commissariat Energie Atomique METHOD FOR MAKING A DEPOSIT ON A REMOVABLE MEDIUM, AND DEPOSIT CARRIED OUT ON A MEDIUM
KR0179921B1 (en) * 1996-05-17 1999-03-20 문정환 Stacked semiconductor package
US5715193A (en) * 1996-05-23 1998-02-03 Micron Quantum Devices, Inc. Flash memory system and method for monitoring the disturb effect on memory cell blocks due to high voltage conditions of other memory cell blocks
DE19648492A1 (en) * 1996-11-22 1997-11-13 Siemens Ag Three=dimensional multi-chip module, e.g. memory module
JP3296306B2 (en) * 1997-10-28 2002-06-24 ソニーケミカル株式会社 Anisotropic conductive adhesive and adhesive film
KR100285664B1 (en) 1998-05-15 2001-06-01 박종섭 Stack package and method for fabricating the same
JP3674333B2 (en) * 1998-09-11 2005-07-20 株式会社日立製作所 Power semiconductor module and electric motor drive system using the same
JP2000332055A (en) * 1999-05-17 2000-11-30 Sony Corp Flip-chip mounting structure and mounting method
US6720644B2 (en) * 2000-10-10 2004-04-13 Sony Corporation Semiconductor device using interposer substrate and manufacturing method therefor
JP2004199887A (en) * 2002-12-16 2004-07-15 Agilent Technol Inc Electrical contact switching device using conductive fluid and its manufacturing method

Also Published As

Publication number Publication date
WO2007053606A3 (en) 2007-09-07
TW200746381A (en) 2007-12-16
TWI475662B (en) 2015-03-01
KR20080087790A (en) 2008-10-01
TW201003888A (en) 2010-01-16
EP1949440A2 (en) 2008-07-30
WO2007053606A2 (en) 2007-05-10
KR100996982B1 (en) 2010-11-26

Similar Documents

Publication Publication Date Title
US7511371B2 (en) Multiple die integrated circuit package
US7514297B2 (en) Methods for a multiple die integrated circuit package
KR100459971B1 (en) Semiconductor device, method and device for producing the same, circuit board, and electronic equipment
US7772686B2 (en) Memory card fabricated using SiP/SMT hybrid technology
JP3960479B1 (en) Manufacturing method of semiconductor device having double-sided electrode structure
JP2936320B2 (en) Semiconductor package
KR101015266B1 (en) High density three dimensional semiconductor die package
US8728864B2 (en) Method of fabricating a memory card using SIP/SMT hybrid technology
TW200901435A (en) Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing apparatus for packaging semiconductor devices, and methods of manufacturing semiconductor components
US20040135243A1 (en) Semiconductor device, its manufacturing method and electronic device
JP2009105334A (en) Semiconductor device and manufacturing method therefor
JP2002009236A (en) Multiple layer semiconductor device and its manufacturing method
KR101106234B1 (en) Methods of forming a single layer substrate for high capacity memory cards
US6380624B1 (en) Stacked integrated circuit structure
JPH07106509A (en) Multilayer structure semiconductor device
TWI324385B (en) Multiple die integrated circuit package
JP2003133516A (en) Laminated semiconductor device
TW201007909A (en) Ball grid array package without solder balls
JP2001060656A (en) Semiconductor device, manufacture thereof, circuit board and manufacture thereof

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees