TW201007909A - Ball grid array package without solder balls - Google Patents

Ball grid array package without solder balls Download PDF

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Publication number
TW201007909A
TW201007909A TW97130894A TW97130894A TW201007909A TW 201007909 A TW201007909 A TW 201007909A TW 97130894 A TW97130894 A TW 97130894A TW 97130894 A TW97130894 A TW 97130894A TW 201007909 A TW201007909 A TW 201007909A
Authority
TW
Taiwan
Prior art keywords
ball
substrate
grid array
array package
ball grid
Prior art date
Application number
TW97130894A
Other languages
Chinese (zh)
Inventor
Ming-Yao Chen
Original Assignee
Powertech Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Powertech Technology Inc filed Critical Powertech Technology Inc
Priority to TW97130894A priority Critical patent/TW201007909A/en
Publication of TW201007909A publication Critical patent/TW201007909A/en

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92142Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92147Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

Disclosed is a ball grid array (BGA) package, primarily comprising a substrate, at least a chip on the substrate, and a molding compound. The substrate has a plurality of socket holes, a plurality of traces and a plurality of shell electrodes where the shell electrodes are aligned with and connected to the socket holes, further protruded from a bottom surface of the substrate. The chip is electrically connected to the traces. The molding compound is formed on the substrate and fills in the internal spaces of the shell electrodes through the socket holes to form a plurality of insulating bumps connected as a whole. Accordingly, the shell electrodes filled with the molding compound inside are configured as integrally ball terminals of the package to replace solder balls to eliminate the conventional problems of ball crack or ball dropping. And also, it can save the step of disposing solder balls in conventional BGA packaging processes.

Description

% %201007909 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor semiconductor device, and in particular to a solder ball ball grid array package structure. [Prior Art] Ball grid array (Ball Grid Array) is packaged into a semi-conductive semiconductor package technology. The substrate is used to set the wafer and after the wafer is encapsulated, a plurality of substrates are implanted on the lower surface of the substrate. Matrix-arranged solder balls, such as tin-lead solder balls, are soldered to the ballast of the substrate, and then bonded to the surface to form a ball grid array package:: Electrically connected to the external printed circuit Board or other electronic products. As shown in Fig. 1, a conventional ball grid array package structure (8) is a window type ball grid array package type, and a substrate 10 having an internal electrical connection channel 117 is used as a wafer carrier and an internal electrical transfer medium. The internal electrical connection channel 117 is a long slot and communicates with the upper surface 11U and the lower surface 112 of the substrate 110. An active surface 121 of a wafer 120 is attached to the upper surface 1U of the substrate 110 by adhesion of a bonding layer 14A. One of the back faces 122 of the wafer 120 is relatively far from the substrate 110. The wafer 120 has a plurality of pads 123 on the active surface, the alignment of which is exposed to the internal electrical connection channel 117_. And the plurality of bonding wires 16 〇 pass through the internal electrical connection channel to electrically connect the pads 123 of the wafer 12 to the substrate 11 〇. A colloid 130 is formed on the upper surface of the substrate 110 and the internal electrical connection channel 117 to seal the wafer 120 and the solder lines 201007909, and a plurality of solder balls 170 are disposed on the substrate. The ball pad of the lower surface 112 is used as the outer soldering end point. The following manufacturing process shows that the solder balls 170 are disposed after the encapsulant i 3 is formed, and the ball pads of the substrate 110 are easily contaminated by the gel of the encapsulant 13 , so that the solder balls 170 cannot be soldered. The substrate 11 is bent to form a false soldering phenomenon, which is problematic in that the solder ball is broken or dropped. The manufacturing process of the conventional window type ball grid array package structure is as shown in Figs. 2A to 2D. First, as shown in Fig. 2A, the substrate 110' is provided to have a wiring structure (not shown). The internal electrical connection channel 117 extends through the substrate no and is located approximately at a central location of the substrate 11'. A tape or a layer of adhesive-coated adhesive layer 140 is preliminarily formed on the upper surface m of the substrate 11 for subsequent adhesion. As shown in FIG. 2B, in the bonding step, the active surface 12 of the wafer 120 is adhered to the upper surface 111' of the substrate 11 by the bonding layer 140, as shown in FIG. 2C. The line 160 is formed to be Φ. In the wire bonding step, the pads 123 of the wafer 120 are electrically connected to the substrate 11 through the internal electrical connection channel 117. As shown in FIG. 2D, the encapsulant 130 is formed in a molding step to seal the wafer 120 and the bonding wires 16 , and no solder balls are disposed in the molding step to make the substrate 110 Surface 112 can be tiled to the next template. Finally, as shown in Fig. 1, the solder balls 17 are placed on the lower surface 112 of the substrate 110 to form a ball grid array package structure (BGA package). The solder ball 170 is subjected to a high temperature reflow step to re-melt the solder ball 170 into a spherical shape and soldered to the ball pad of the substrate 201007909 110. Once the sealant * ^ t, 130 is at the bottom of the substrate 1 10 . Easily produced two spills of glue may contaminate the ball, making the solder balls = split or fall off, affecting the reliability of the package. [Summary of the Invention] In this case, the main purpose of the present invention is to provide a ball grid array package structure that is free of solder balls, and that is not required to be separately set after the sealing of the glue Φ LING "An electrical connection with the external device, and can solve the problem of the solder ball breaking or falling in the conventional ball grid array package structure. The object of the present invention and the solution to the problem are the following technical solutions. According to the present invention, a solder ball ball grid array package structure is disclosed, which mainly comprises a substrate, at least one wafer, and a gel. The substrate has a top surface, a lower surface, a plurality of end vias, a plurality of traces, and a plurality of shell electrodes connecting the traces, wherein the shell electrodes are aligned and connected To the end vias, the dog is disposed on the lower surface of the substrate. The active surface of the wafer has a plurality of pads, and the pads are electrically connected. To these traces. The encapsulation system is formed on the upper surface of the substrate and filled into the inner spaces of the shell-type electrodes through the end vias. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the ball grid array package configuration described above, the shell electrodes and the traces are integrally connected to a wiring layer. In the ball grid array package structure described above, the wiring layer can be formed on the wiring layer to form the shell-type electrode system. The encapsulant is on the lower surface of the substrate of the 201007909. This upper surface of the substrate is described in the structure of the ball 拇 1 1 卞 骏 。. In the ball grid array package configuration described above, one of the end vias is planarly covered. In the foregoing ball grid array package structure + - the internal space of the electrode is formed as a plurality of integral interconnections. In the ball grid array sealing structure, the image may additionally include a picture of a sticky crystal > The patterned and die-bonded layer of the wafer and the substrate are sealed to form the vias to interconnect the insulating bumps. In the spherical thumb array package structure, the shell-shaped electrodes have a circular arc-shaped cross section. In the ball grid array package construction described above, the shell electrodes have a square strip cross section. In the ball grid array package construction described above, a metal layer may be further included to cover the exposed surfaces of the shell electrodes. In the ball grid array package construction described above, the encapsulation system can seal the wafer. In the foregoing ball grid array package structure, the substrate may have a partial electrical connection channel extending through the upper surface to the lower surface, and the active surface of the wafer is attached to the upper surface of the substrate to enable the Cover the pads. In the ball grid array package structure described above, the traces can be extended to a non-shell type edge-forming system, and the substrate can be extended to 201007909. In the package structure, the plurality of bonding wires may be further connected to the soldering pads, and the plurality of bonding wires may be further connected through the internal lightning circuit 14 connecting channels to electrically connect the wires. Solder pads and the traces. In the above-mentioned ball-and-buckle array, the encapsulation system can be further filled with the internal electrical connection channel. In the ball grid array package construction described above, the internal electrical connection channel can be a central elongated slot. In the ball grid array package structure, the wafer system may have a back surface opposite to the active surface, and the back surface is attached to the upper surface of the substrate. The long gate array sealing structure further includes a plurality of bonding wires. The pads and the traces are electrically connected. In the case of the J-spring array package structure, the shell-type electrode systems may be metal pads and deformed by a lead bQnd method. It can be seen from the above technical solution that the ball-free package structure of the solder ball of the present invention has the following advantages and effects: J is filled with the sealing body into the inner space of the shell electrode, and can be used as an integrated external ball end. In place of the solder ball as the input/output terminal for external bonding, there is no need to increase the force of the packaging step and no additional ball is required. In the system: the solder ball setting step after the conventional sealing can be omitted, and the structure can be eliminated. The problem of the solder ball breaking or falling. An insulating bump is formed by filling the inner space of the shell electrode by the sealant to prevent deformation or displacement of the shell electrode. Using a low-cost substrate with a single-sided wiring layer while providing a shell-type power can omit the package components and the process, and omitting the conventional solder ball 201007909. The pole and the trace are on the same circuit layer, and the cost of the signal is increased. 4. The exposed surface of the shell-shaped electrode coated with metal # can be used as a strong electrode to increase the structural strength of the shell electrode. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The following is a simplified illustration of the embodiments of the present invention, which are merely illustrative of the basic architecture or implementation of the present invention. Therefore, only the relevant parts of the case are displayed, and the components displayed are not drawn in the actual implementation shape and size ratio. Some size ratios and other ratios have been modified or simplified to provide a clearer description of the actual implementation. The number, shape and size ratios are an alternative design' and the detailed component layout may be more complicated. According to a first embodiment of the present invention, a spare solder ball | ❹ grid array package structure is illustrated in a cross-sectional view of FIG. The gate array package structure 200 mainly includes a substrate 21 〇, at least one 220, and a colloid 23 〇. The substrate 210 is a wafer carrier that can be used to carry and electrically connect the wafer 220. The substrate 210 has an upper surface 211 and a surface 212' which serves as a wafer mounting surface, and the lower portion 212 is an external surface. The substrate 21 further includes a plurality of end holes 213, a plurality of traces 214, and a plurality of shell electrodes 215 connected to the traces, wherein the shell electrodes 215 are aligned and stepped to complement each other. The ball of the characterization of the ball is turned to the surface point 214 to connect 10 201007909 to the end holes 213, more prominently on the lower surface 212, the traces 214 are the substrate One of the 21 〇 internal circuit layers, rather than the additional components, is usually a copper line. In the fabrication of the substrate, the traces 214 are patterned by a copper foil by exposing, develping, etching, or the like. Preferably, the shell electrodes 215 and the traces 214 are integrally connected to a circuit layer 216, so that the two layers are in the same layer structure to simplify the number of layers, thereby reducing substrate cost and free soldering. The effect of the ball. In this embodiment, the circuit layer 2 16 may be formed on the lower surface 212 of the substrate 21 . The substrate 210 may be a circuit substrate having a single-sided circuit layer, such as a printed circuit board, a ceramic circuit board, or a circuit. The thin film, the substrate 210 can form the shell electrodes 215 by using the circuit layer 216, and the traces 214 can eliminate the complexity of the two-sided circuit layout and the plated through holes and the process troubles, and can improve the speed of the signal. The shell electrode 2 15 can replace the conventional solder ball as an input/output (inPut/outPut, 1/〇) end electrically connected to the external device, and is not integrated with the sealant 230. Shedding (detailed later). In addition, the substrate 210 can have an internal electrical connection channel 217' extending through the upper surface 21 of the substrate 210. The main lower surface of the substrate 210 is attached to the substrate. The upper surface 2U' of the upper surface 2U' is aligned with the internal electrical connection channel 217 so that the substrate 210 does not cover the fresh slabs 223. The traces 2 1 4 can extend into the internal electrical extension, s a money channel 217 and are directly bonded to the pads 223. The sealant 23 can be filled into the 11 201007909 internal electrical connection channel 217. Preferably, as shown in FIG. 3, the substrate 210 may further include a solder resist layer 218 covering the circuit layer 216 but exposing the shell electrodes 215 to provide surface insulation protection to avoid external moisture or Dust pollution. The solder resist layer 2 18 is a low-cost insulating ink that can be adjusted in thickness to control the thickness of the substrate. Since the substrate 210 can have only a single-sided wiring layer 216, the substrate cost can be reduced and the fresh balls can be saved. As shown in FIG. 3, the wafer 220 is disposed on the upper surface 211 of the substrate 210. The wafer 220 includes an active surface 221 and a corresponding back surface 222. The active surface 221 has a plurality of pads 223, such as pads 223 electrically connected to the traces 214. The electrical connection method may be a lead bond or a wire bond. The encapsulant 230 is formed on the upper surface 211 of the substrate 21 and is filled into the shell electrodes 215 through the end vias 213.

The pole 215 2 00 may further comprise a patterned doped germanium which reinforces deformation or displacement of the shell electrode 21 215. The ball grid array package structure 2〇 12 201007909

The layer 240 is adhered to the crystal H piece 220 and the substrate 210. The patterned doped layer 240 is not sealed but the end hole 213 (as shown in FIG. 5) is used to mask the insulation. . The ghost 231 is physically interconnected with the sealant 230. Preferably, the ball grid array package structure 2 further includes a metal smear layer 250 covering the exposed surfaces of the shell electrodes. Preferably, the thickness of the metal bonding layer 25 可 is greater than The thickness of the shell electrode 2 serves as a reinforcing electrode to increase the structural strength of the shell electrode 215.制造 In accordance with a first embodiment of the present invention, the method of fabricating the ball grid array package structure 200 illustrates a cross-sectional view of the components in the process of FIGS. 4A through 4D and a top view of the upper surface of the substrate of FIG. 5. As shown in FIG. 4A, a substrate 21 is first provided, and the substrate 21 is used as a wafer carrier of the ball grid array package structure, and can be pre-cut to a desired size or a plurality of matrix arrays. The tantalum is formed on a stack of substrate strips which are then diced into individual semiconductor package structures after packaging. The lower surface 212 of the substrate 210 is provided with the circuit layer 216, and the circuit layer 216 is covered by the solder resist layer 218, but does not cover the relative positions of the end vias 2 1 3 for subsequent These locations form the shell electrodes 215. In particular, the end vias 213 can be formed by laser, mechanical drilling or reactive ion etching, and the circuit layer 216 is not interrupted. The end vias 213 correspond to the pins of the ball grid array package structure 200. Next, as shown in FIG. 4B, the punching holes 213 are aligned with the end points 13 201007909 by a punching tool 1 ,, and the line calling layer 216 is punched down to form a plurality of shells protruding from the lower surface 212. Type electric earth electrode 215. Specifically, the shell-shaped electrodes 215 are non-planar thin-packed #, and TJ covers the ends of the end-holes 213 to avoid the 封-A of the sealant 230. In the present embodiment, the 型-type electrodes 2丨5 may have a square strip section to provide a flat surface. However, the cross-section of the shell-shaped electrodes 215 may be various shapes of 4V-shaped strips or other strips. The formation of the shell electrodes 215 can be formed without complicated steps and additional additional components, and can be used as an integrated external ball end to replace the solder balls. Further, as shown in FIG. 4B, the upper surface 2102 of the substrate 21 can be preliminarily provided with the patterned doped layer 240 for subsequent adhesion to the wafer. The patterned doped layer 240 can be formed on the upper surface 211 of the substrate 210 by screen printing or syringe dispensing or attachment. The patterned doped layer 240 can be selected from one of a B-stage colloid, a liquid glue, or a poly-nalylene (ρι) tape. As shown in FIG. 5, preferably, the patterned doped layer Φ 240 does not cover the end vias 213 and forms a mold via hole in the wafer cover region for subsequent filling of the encapsulant 230. In. Thereafter, as shown in Fig. 4C, the wafer 22 is placed on the substrate 21A. The wafer 220 is adhered to the upper surface 211 of the substrate 210 by the patterned doped layer 240. In this embodiment, the active surface 221 of the wafer 220 is directed downward, and the pads 223 are located in a central region of the wafer 220. The internal electrical connection channel 217 is also formed in a central region of the substrate 210. The pads 223 are aligned to be exposed within the internal electrical connection channel 217. Specifically, as shown in Figures 3 and 5, the internal electrical connection 14 201007909 217 can be a central elongated slot. The traces 2i4 can extend into the internal electrical connection channel 217 and can be directly bonded to the pads 223. Therefore, one of the traces 214 can be extended and suspended in the position of the internal electrical connection channel 217 corresponding to the pads 223, and a stamping tool will be placed in the internal electrical connection by using the pin-connected σ technique. The floating traces 214 in the channel 217 are thermocompression bonded to the pads 223 to electrically connect the wafer 220 to the substrate 210. φ The end vias 213 are substantially circular holes, the positions of which correspond to the feet t of the ball grid array package structure, but the end vias 2 1 3 may also be rectangular holes or other shapes. In this embodiment, the shell-shaped electrodes .215 can be metal tantalum and deformed by pin bonding (ieaij b〇n(j) method. The metal pads are covered by the plane before being punched. Corresponding ports of the end through holes 2 1 3. Finally, as shown in FIG. 3, the encapsulant 230 is formed on the upper surface 211 of the substrate 210 by a molding (or transfer forming) method, and the # is filled in The internal electrical connection channel 217 and the end vias 213 can completely seal the wafer 220' to hermetically isolate the internal components from the outside from external impact or contamination. Therefore, the shell electrodes 215 The input/output (1/0) input/output end is electrically connected to the external device, and the insulating body 230 is filled into the inner space of the shell-shaped electrode 215 to form the insulation of the integral interconnection. The bumps 231 ′ can prevent the shell-shaped electrodes 215 from being deformed or displaced. In addition, the exposed surfaces of the shell-shaped electrodes 215 can be used as reinforcing electrodes by the metal bonding layer 250 to increase the shell-shaped electrodes 15 201007909 Structural strength of 215. According to the second aspect of the present invention DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT, FIG. 6 is a cross-sectional view of another solder ball. The ball grid-substrate 210 and at least one wafer 220 ball grid array package structure are mainly included in the first array package structure 300 and include a package (four) 230. The first embodiment of the present invention is the same as the first embodiment and is represented by the same reference numerals, so that it can be understood that the above-mentioned functions are not described. e In this embodiment, the ball grid array package structure 3 can additionally include a plurality of The bonding wires 360 are electrically connected to the soldering pads 223 and the traces 214 through the internal electrical connection channels 217. The bonding wires 360 may be made of gold wires, inscribed wires or copper. a wire in which a gold wire is more commonly used. In this embodiment, a wire bonding electrical connection is used instead of a wire 2 i 4 stamping to directly bond to the pads 223 ^but without limitation, the wafer 22 can be removed. In addition to the wire-bonding, the electrical interconnection between the wafers 220 and the substrate 210 can also be accomplished by flip-chip bonding (fHp chip) or other known electrical connections. Specific embodiment, another exemption The spherical ball grid array package structure is illustrated in a cross-sectional view of Fig. 7. The ball grid array package structure 400 mainly includes a substrate 21, at least one wafer 220, and a colloid 230. The main components are the same as the first embodiment. Preferably, the circuit layer 216 is formed on the upper surface 211 of the substrate 210 to prevent the shell electrodes 215 from being generated by the substrate 21 2010 16 201007909 stripping In the present embodiment, the back surface 222 of the wafer 220 can be attached to the upper surface 211 of the substrate 210, and the solder pads 22 3 and the traces 214 are electrically connected by a plurality of bonding wires 460. . The ball grid array package structure 400 can be applied to a package of a multi-wafer stack, that is, a plurality of wafers 22 are stacked on the upper surface 211 of the substrate 21, and then electrically connected to the substrate 210. Further, in this embodiment. The shell-shaped electrodes 215 have a circular arc-shaped cross section and the internal space is filled by the encapsulant 230 to form an insulating bump 23 1 'to extend the variation of the existing packaging material so as to omit the conventional solder ball setting. It can be used as an integrated external ball end, without adding packaging steps or adding additional solder balls. In the process, the solder ball setting step after the conventional sealing can be omitted, and the conventional solder ball can be broken or dropped in the structure. question. The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention in any way. The technical scope of the present invention is subject to the scope of the appended patent application. Any person skilled in the art can make any equivalent changes or modifications to the equivalent embodiments by using the technical content of the above-mentioned disclosure, but the above embodiments are implemented according to the technical essence of the present invention without departing from the technical solution of the present invention. Any simple modifications, equivalent changes and modifications made by the examples are still within the scope of the technical solution of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a conventional ball grid array package structure. 2A-2D: A schematic cross-sectional view of a conventional ball grid array package constructed in process 17 201007909. Fig. 3 is a cross-sectional view showing a ball grid array sealing structure of a solderless ball in accordance with a first embodiment of the present invention. 4A and 4D are cross-sectional views showing the components of the ball-to-rug array package constructed in the process according to the first embodiment of the present invention. The fifth embodiment is a schematic view of the upper surface of the substrate of the ball grid array package structure according to the present invention. φ 帛6图' is a schematic cross-sectional view of a ball-to-pole array package structure of a Xue-free ball in accordance with a second embodiment of the present invention. Figure 7 is a cross-sectional view showing a ball-like array package structure of a solderless ball according to a third embodiment of the present invention. [Major component symbol description] 10 stamping tool 100 ball grid array package structure 110 substrate 111 upper surface 117 internal electrical connection channel 120 wafer 121 active 123 pad 130 encapsulant 14 〇 晶 170 170 solder ball 200 ball grid array package structure 210 Substrate 211 on the table 213 end point through hole 2 14 trace 216 line layer 112 lower surface 122 back side 160 wire surface 212 lower surface 215 shell electrode 217 internal electrical connection channel 201007909 218 solder mask 222 back 220 wafer 221 active Surface 223 solder pad 230 encapsulant 231 insulating bump 240 patterned adhesive layer 250 metal bonding layer 300 ball grid array package structure 3 60 0 wire 400 ball grid array package structure 460 460 wire 19

Claims (1)

  1. 201007909 X. Patent application scope: 1. A ball grid array package structure for eliminating solder balls, comprising: a substrate having an upper surface, a lower surface, a plurality of end point through holes, a plurality of traces, and a plurality of connections a shell-shaped electrode of the traces, wherein the shell-type electrodes are aligned and communicated to the end-point vias to protrude further from the lower surface; at least one wafer is disposed on the upper surface of the substrate, the wafer The active surface has a plurality of pads electrically connected to the traces; and a gel is formed on the upper surface of the substrate and filled through the end vias To the internal space of the shell-shaped electrodes. 2. The ball grid array package structure of the spare solder ball of the invention of claim </ RTI> wherein the shell electrodes are integrally connected to the trace layers. 3. The ball grid array package of the solder ball of the exemption solder ball described in claim 2, wherein the circuit layer is formed on the lower surface of the substrate. 4. The ball grid array package structure of the free solder ball according to claim 2, wherein the circuit layer is formed on the upper surface of the substrate. 5. The ball grid array sealing structure of the free solder ball according to claim 1, wherein the shell electrodes are non-planarly covering the end vias - end 0.6, as in the patent application scope The ball grid array package structure of the solder ball of the above-mentioned item 1 wherein the sealant is formed in the inner space of the shell electrodes as a plurality of integrally interconnected insulating bumps. 20 201007909 7. As claimed in the patent application, the structure ′ further includes a plate, and the patterned viscous bumps are integrated with a patterned viscous layer as described in item 6, and the layer does not seal the connections. The ball grid array package of the solder ball adheres the wafer and the base end via hole to make the spherical ball drop-down structure of the solder ball as described in claim 8, wherein the shell The type electrode system has a circular arc cross section.
    9. The ball grid array package structure of the material-free ball of claim i, wherein the shell-type electrodes have a square strip section. 1 . The ball-free ball grid array package structure of the free-bead ball according to the above-mentioned patent scope is further included as a metal bonding layer covering the exposed surfaces of the shell-shaped electrodes. U, such as the scope of patent application! The ball grid array package construction of the spare solder ball described in the item wherein the encapsulation system completely seals the wafer. 12. The ball grid array package structure of the free solder ball according to claim i, wherein the substrate has an internal electrical connection channel extending through the upper surface to the lower surface when the wafer is The active surface is attached to the upper surface of the substrate such that the substrate does not cover the pads. 13. The ball grid array package construction of the free solder ball of claim 12, wherein the traces extend into the internal electrical connection channel and are directly bonded to the solder pads. 14. The ball grid array package structure of the spare solder ball according to claim 12, further comprising a plurality of bonding wires, wherein the pads are electrically connected to the traces through the internal electrical connection channels line. 15. The ball grid array seal of the spare solder ball according to claim 12 of the patent application scope of claim 12, wherein the seal is further filled with the internal electrical connection passage. 16. The ball grid array package structure of the free-recording ball described in claim 12, wherein the internal electrical connection channel is a central elongated slot. 17. The ball-and-eye array package structure of the exempted glow ball of claim i, wherein the wafer has a back surface of the active surface attached to the substrate The surface of the ball grid array package structure further includes a plurality of bonding wires electrically connected to the fresh pads and the traces. 18. The ball grid array package structure of the free solder ball according to claim 1, wherein the shell electrodes are metal crucibles and are deformed by a lead bond. twenty two
TW97130894A 2008-08-13 2008-08-13 Ball grid array package without solder balls TW201007909A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW97130894A TW201007909A (en) 2008-08-13 2008-08-13 Ball grid array package without solder balls

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW97130894A TW201007909A (en) 2008-08-13 2008-08-13 Ball grid array package without solder balls

Publications (1)

Publication Number Publication Date
TW201007909A true TW201007909A (en) 2010-02-16

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI549248B (en) * 2011-11-01 2016-09-11 住友電木股份有限公司 Method of manufacturing semiconductor package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI549248B (en) * 2011-11-01 2016-09-11 住友電木股份有限公司 Method of manufacturing semiconductor package

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