KR100996982B1 - Multiple die integrated circuit package - Google Patents

Abstract

A multi die package for an integrated circuit is disclosed. An insulator is provided, and one or more vias are formed in the insulator. After the insulator is prepared without the vias, the vias can be formed later. At least one integrated circuit is provided and electrically connected to at least one lead of the first leadframe covering one surface of the insulator. The electrical connection between the two lead frames and the first integrated circuit and the second integrated circuit is formed through an insulator at a position selected by connecting at least one lead of the first lead frame and the second lead frame to each other. . Leads of the first leadframe and the second leadframe may be physically connected by welding in the via in the insulator. Removable storage card packages are also disclosed.

Multi-die packages, insulators, vias and leadframes for integrated circuits

Description

MULTIPLE DIE INTEGRATED CIRCUIT PACKAGE

This application is related to a US patent application entitled "Multi-die Integrated Circuit Package Manufacturing Method" (management number SDK-0594.001) filed on the same day as this application.

The present invention and many embodiments disclosed herein relate generally to the manufacture of a packaged semiconductor device comprising one or more integrated circuit devices, in particular having multiple integrated devices to provide a package system, memory or memory card storage device. It is related with manufacture of the package to comprise.

In the electronics industry, semiconductor devices are provided in packages that protect the integrated circuit and provide external contacts to the integrated circuit. In response to the need to integrate devices and improve functionality, multiple integrated circuits, sometimes referred to as chips or dies, are being provided in a single package. Such packages may be modified in various ways and molded packages made of preformed plastic or ceramic or metallic bodies, other similar materials and heat-curable resins or thermosetting resins, eg, "glop top" or epoxy packages. It can be made of a variety of materials, including. The materials prevent small and rigid semiconductor integrated circuits or “dies” from physical damage and some humidity damage, and are external terminals that are external electrical contacts of an integrated circuit, generally metallic or other conductive contacts. Is used to protect the conductive leads used to connect the conductive bond pads on the integrated circuit.

In the semiconductor packaging industry, leadframes are often used to provide mechanical support and to provide an electrical connection between the integrated circuit and the leads or external electrical contacts of the package element. The leadframe is sometimes made of a conductive material that is an iron-nickel alloy such as copper, grit alloy, or Alloy 42 coated with gold, ruthenium, palladium and similar materials to improve conductivity and solderbility, and the soldering of the contacts Additional plating layers or nickel alloys, copper alloys or other materials may be used to improve performance and manufacturability. A plastic plating layer may be used on the conductive material to form the leadframe. The leads can be soldered or plated prior to assembly or after assembling the finished package. The leadframe is generally provided in the form of an integrated strip, can be etched or stamped out, and the leadframe strips are subsequent manufacturing steps as a plurality of leadframes connected in strip form to facilitate assembly and fabrication. Are separated into a plurality.

Generally, leadframes provide a number of leads that extend from the outside of the area that is the outer boundary of the desired finished package to an interior area disposed to receive the integrated circuit. In this case, the lead is generally a finger shape, but a different shape may be used. In the prior art, one area of the leadframe provides a central support, also referred to as a "die pad," which houses a rectangular or square semiconductor die, and a lead finger is integrated on one or more sides of the die pad. It is known to use a configuration that extends to an area near the outer edge of the circuit die. The leadframe fingers extend beyond the outer boundary of the encapsulated package out of the die. In another configuration of the prior art, the lead fingers extend over the die (lead on chip or "LOC" type leadframe) or extend below the die (lead under chip or "LUC") so that the leads provide mechanical support as well as an electrical passage. Type leadframe).

Insulator adhesive in the form of a plated layer or tape may be used to secure the leads to each other and to maintain their position during the assembly process, or to stabilize the leads by securing the die to the leads. The dies may be adhered to the die pad using a die attach adhesive, which may be a conductive or insulating material, and may also be a resin or a thermoset material.

Regardless of the type of leadframe used, there is a need to provide a connection mechanism for electrically connecting the integrated circuit to the leadframe. Generally, bond wires are used. These fine wires are attached to the semiconductor element by a wire bonding process; The wire is generally distributed and attached through a capillary. The wire bonding process uses heat and pressure, and sometimes other energy, such as ultrasonic energy, to form the bond by attaching the wire to the integrated circuit bond pads, which then come out of the integrated circuit and form the lead finger of the lead frame in the leadframe. Extending to the area above the end, the capillary again uses heat and pressure to form a second contact to the leadframe of the bond wire. Alternatively, the bond wire may be formed so as to be attached to the bond pad above the integrated circuit, extending in the opposite direction, ie first attached to the leadframe finger and then upward. The cut wire is heated to form a ball over the end of the bond wire, which is then used for subsequent bonding to the integrated circuit die (" ball " bonding) and attached to the leadframe where the ball is not formed. The ends of the bonded bond wires are called "stitch". If desired, if necessary, multiple bond wires may extend from different pads of the integrated circuit to one single lead of the leadframe, for example in this way the power or ground for the integrated circuit. Contacts may be formed. The bond wires may be gold or other known conductive materials that are soft and flexible enough for use in ball and stitch bonding steps without easy breakage and unwanted breakage. The wire bonding process can be highly automated and is generally performed at very high speeds.

In the assembly process, after the integrated circuit die is attached to the leadframe, the leadframe and the die are placed in a molding equipment, for example a transfer molding device, and integrated with the leadframe using liquid or melt molding compound material in the molding equipment. Encapsulating the circuits together mechanically protects the die and imparts some moisture resistance as described above. Other alternative implementations, including injection molding, include resins such as epoxy and "glob top" materials and other known materials as integrated circuit encapsulants. Instead of molding, the leadframe and die assembly may be placed in a ceramic, metal or plastic body, and then encapsulated and sealed using lids and adhesives or other materials. The outer end of the lead of the leadframe itself forms the external contact of a packaged device such as a DIP, quad flat pack (SFP), SOP, or other leaded package, or a ball grid array ("BGA") or pin grid Additional connection techniques may be used in array ("PGA") packages and similar packages. Leadframes are interconnect interposers, such as film-based flexible circuits based on film materials available from printed circuit boards, Kapton, Upilex, Mylar and other semiconductor manufacturers. ) Or a ceramic substrate may be used. In the prior art, multilayer interposers with metal layers connecting external connectors to integrated circuits have been used to fabricate possible complex substrate configurations. For example, the bottom terminal may be connected to a wire bonding land terminal or leadframe on the top surface of the interposer through the multilayer and via hole in the substrate or interposer. The interposers or substrates generally have a laminate structure in which an insulator is formed on various conductive layers. Once assembly is complete, these linings may be overmolded to provide a sealed packaged element, or the assembly may be placed in a sealed body.

As the demand for higher integration for packaged devices increases, it is already known in the art to provide MCMs or multi-chip modules in which one or more integrated circuit dies are provided within packaged devices. For example, the memory element and the controller may be packaged together to form such a module. The processor and the memory may also form one module. These devices may optionally be the same device that forms a large memory integrated circuit, such as, for example, a commodity DRAM or a nonvolatile memory device, and many of the same may be shared, with the shared terminals of those devices connected in parallel with the external contacts of the package. The dies may be located in one package.

Various techniques are used to combine multiple integrated circuits together in one system configuration. Flexible circuits are formed having metallization patterns formed on one or both sides of the flexible substrate, which then function as interconnect levels connecting the two integrated circuits to each other. Laminates, such as FR-4 or BT resin cards, can be fabricated with multiple metal layers and cross-level via technology, and these laminate interposers act as small circuit boards that connect the integrated circuits together, providing traces for external connections such as terminals. trace).

To increase the degree of integration, die stacking may be used when the same devices are connected to each other, as in the case of DRAM devices, for example. The bond wire may extend from the lead of the leadframe to a plurality of dies, for example, to be wired to a plurality of DRAM integrated circuits in which address leads of the DRAM package are stacked. Including a spacer between the stacked dies allows access to the die pads of the individual integrated dies in which the wire bonding equipment is stacked.

To increase the degree of integration, die stacking may be employed when the same devices are connected, such as in the case of DRAM devices, for example. Various methods may be used to provide multiple dies in a “face up” configuration, and wire bonding may connect each die to a shared leadframe using bond wires that connect the dies in parallel. However, it is known to install the die in a back-to-back manner over the leadframe to maintain a shared bond pad footprint, but the die is installed in a back-to-back manner. Sometimes a "mirror die" is needed so that the terminals on one side of the top facing die must be located in the same position and in the same order on the bottom facing die corresponding to the top facing die. The need for a "mirror die" increases manufacturing complexity, inventory control, and cost, and each packaged device must include two different dies with the same functionality. Alternatively, an interposer or laminate circuit can be used to position two identically functional dies in series, but the laminate interposer also increases the cost and complexity of the final device.

Recently, packaged devices of increasing commercial importance are removable non-volatile storage cards that can transport data between many electronic devices. Such nonvolatile memory or storage cards are available in a variety of formats including Compact FLASH, Secure Digital or SD, Mini-SD, Memory Stick, USB Drive, Multimedia Card or MMC, and other formats. To provide a powerful, reliable and stable data storage format, nonvolatile EEPROM or FLASH memory devices are provided with an intelligent controller in a single packaged device. Intelligent controllers provide data error correction and detection, testing, caching, and redundancy support functions to ensure that user data is stored, even if some storage locations in a nonvolatile memory device are predicted to fail or are likely to fail during product use. Saved, modified and recovered, the user or system does not know where it is unavailable in the memory array, and the intelligent controllers replace these faulty locations with redundant memory locations to maintain consistency and proper storage of data. Maintain a map of available locations. In a user system, the device is similar to a large memory array, controller, and automatic error corrector, and redundant support allows for user transparent automatic memory control operations without affecting the use of the device. These portable storage cards are used and include digital media storage devices such as mobile phones, digital cameras, MP3 music and video for music players, video players, electronic game consoles, personal digital assistants or PDA devices, medical record storage devices, smart cards, It will continue to be used in many areas where data is stored, such as credit cards and the like.

1 shows the appearance of a typical removable storage card package. The card may be, for example, in the form disclosed in US Pat. No. 6,410,355 by Wallace, the inventor of the present invention, which is incorporated herein by reference. In FIG. 1A, the contact portion of the card, for example a secure digital or SD type card, is shown as a conductive terminal 101 disposed in contact with the integrated circuit in the package 100. FIG. 1B shows the opposite side of the package 100, which has no electrical contacts and is generally labeled with the user's visual censorship and reference information, brand name, media size and other similar information. It is. The number of terminals and the type of connection used vary, for example, with forms such as Secure Digital or SD, and the terminal shown in FIG. 1A is typical and only a small amount of external terminals are used. Compact flash or "CF" cards with a large number of terminals are often used in digital cameras, which are female receptacles located at one end of one side of the package. The camera or card reader has a socket for receiving the same end of a CF package with a male terminal or pin so that when the compact flash card is inserted into the socket the female receptacle corresponds to the male terminal. Enter to complete the connection. Other connection methods may be used, for example a USB port may be used as the connection.

Conventional packages for removable storage card devices typically include controller integrated circuits and memory elements or substrates in the form of multilayer laminate printed circuit boards or " PC boards " or complex interposers that provide device-to-device connectivity and physical support of the devices. It includes. Boards, which may be BT resin, FR4, or fiberglass or the like, generally include conductor traces, via holes connecting each layer to form electrical connections, and traces on the board surface to integrated circuit dies or other components. It is a laminate structure containing a metal layer patterned to form the land for wire bonding to connect. Multiple memory elements may be provided side by side or stack, for example, or only one single memory element may be used, although in the prior art packaged storage cards are at least two elements. Are complex packaged devices that are packaged and connected together. 2 shows a cross section of a typical configuration. 2 illustrates a prior art storage card 200 having an integrated circuit die 204 and an integrated circuit die 205 mounted on the same surface of a laminate substrate 208. Bond wires 203 connect bond pads 204 on the active surface or face of the integrated circuit die to lands 206 or conductive regions on the top surface of the substrate. Two such bond wires are shown connected to lands 206 to electrically connect the two die pads of the integrated circuit, whereby the integrated circuits are electrically connected, the integrated circuit being for example memory and controller integrated. May be a circuit. Die attach material 209 is used to attach the dies 204, 205 to the substrate 208. After forming the bond wire 203 and attaching the bond wire to the land 206 on the substrate and the integrated circuit dies 204 and 205, the bond wire and the integrated circuit dies are encapsulant. Encapsulated in 211. In this case, the encapsulant may be a thermosetting or room temperature molding compound or other encapsulation material. The package is completed with a shell 201. The cell may be a plastic covering the substrate and the molding material. Another approach, US Pat. No. 6,639,309 by Wallace, inventor of the present invention, which is incorporated herein by reference, discloses that a memory device and a control device are integrated on both surfaces of a multilayer PC board material, and wire bonded connections. And a removable storage card that is overmolded.

Another approach to packaged semiconductor integrated circuits is to integrate multiple level leadframes or multiple leadframes that are interconnected. For example, US Pat. No. 5,147,815 to Casto, which is incorporated herein by reference, discloses two integrated circuit dies and two leadframes assembled into a single molded dual inline plastic or It is shown what is provided in the "DIP" package. The integrated circuit dies and their respective leadframes are arranged in a back-to-back manner and each die is connected to each leadframe by a bond wire, or optionally integrated circuit dies are interposer Arranged face-to-face on both sides of the circuit board, connected to each leadframe in a flip-chip arrangement, and two integrated circuits separately arranged on both sides of the packaged device. It is connected to an external lead and is not in electrical communication with each other. US Pat. No. 6,603,197 to Yoshida et al., Incorporated herein by reference, provides a multiple leadframe connected to at least two separate integrated circuit elements that are connected to many leads of the leadframe to form a module. Some shared leads are physically and electrically connected outside the package, for example power leads, so that both integrated circuit devices accept signals. Similarly, US Pat. No. 6,316,825 to Park et al., Which is incorporated herein by reference, discloses stacking two integrated circuit devices, such as memory devices, in a single molded package having two leadframes. In a stacked package, leadframes are physically connected external to the package such that each signal connected to an external lead is physically and electrically coupled in parallel to each of the two identical memory elements.

Another configuration known in the art for providing a single integrated circuit connected to a multilevel leadframe, such as US Pat. No. 5,220,195 to McShane, which is incorporated herein by reference, is incorporated herein by reference. Leadframes that provide a single integrated circuit that is bonded, physical contacts are formed between parts of the multilayer leadframe in the package, and through-hole vias formed with bond wires extending into the vias are located underneath the integrated circuit. Physical contact of the layers allows multiple voltage planes to be formed in the packaged device.

Although there are prior packages for multiple integrated circuits, there is a continuing need for multiple die packages that can reduce manufacturing costs while maintaining package reliability.

This allows for simple, reliable, arbitrary connection between multiple integrated circuit devices, eliminates the use of expensive interposers, printed circuit boards or boards, and reduces manufacturing costs compared to conventional packages and methods. There is a need for integrated circuit packages and multiple integrated circuit packaging methods.

Various preferred embodiments of the present invention provide for electrically connecting two or more integrated circuits, mechanically supporting the integrated circuits, allowing arbitrary connections between integrated circuits, and packaged devices to electrically connect external contacts. A package for multiple semiconductor integrated circuits or dies is provided. The package of the present invention does not require a substrate or interposer of the type used in the prior art, and the materials are known in the semiconductor processing industry so that no retooling or special equipment is required to use and practice the present invention. Use conventional wire bonding and leadframe technology that is compatible with automated production equipment and devices.

In a first embodiment of the invention, a first leadframe is provided and positioned to cover a simple insulator. The insulator has vias formed in a specific position, and some leads of the leadframe rest on the vias. The remaining leads of the leadframe may extend beyond the edge of the insulator or to the outer boundary of the insulator. Some leads of the leadframe may not extend to the external connector. A first integrated circuit die may be provided and positioned near the inner end of the leadframe, and in some embodiments, an opening may be formed in the interior of the leadframe, and the die may be placed in the inner through hole. In other embodiments, the die may be placed over the leads of the leadframe or under the leads of the leadframe. In a preferred embodiment, the die is wire bonded to the leadframe to electrically connect one or more leads of the integrated circuit to the leads of the leadframe. In another preferred embodiment, the leads of the leadframe may be connected to the die using flip chip technology as is known in the art.

The second leadframe is then placed on the second and opposite surfaces of the insulator. Some leads of the second leadframe are positioned to cover the through-hole vias of the insulator so as to correspond to some leads of the first leadframe. The remaining leads of the second leadframe may extend outside of the insulator such that external electrical contacts are connected to the finished device and may extend beyond the insulator outer boundary. The second integrated circuit die may be located near an internal lead of the second leadframe. The central portion near the inner end of the lead of the second leadframe may be formed with a space for accommodating the die, or a lead below the chip or a lead above the chip leadframe apparatus may be used. Electrical connections, such as bond wire connections or flip chip connections, are formed between the die pad terminals on the second integrated circuit and at least one lead of the second leadframe. In typical applications, many bond wires extend from the integrated circuit to the leadframe. Alternatively, the first leadframe and the second leadframe may be attached to each other before the die corresponding to each leadframe is attached.

Particular leads of the first leadframe and the second leadframe are preferably electrically connected via vias in the insulator. This teaching of the present invention allows the electrical connection of the first integrated circuit die and the second integrated circuit die at any location using equipment that electrically connects the two leadframes through the insulator. In a first preferred embodiment, a connection is formed by physically deforming the leadframe leads of the first and second leads into spaces in the vias in the insulator, and then physically connecting between the two leads in the vias. Can be. Next, in a preferred embodiment, conductive welding is carried out between the two lead frames. Such welding can be performed, for example, by adding heat, electrical energy, ultrasonic energy, laser energy and the like. In another preferred embodiment, an electrical connection can be made between the two leadframes by providing a conductive material, such as a conductive paste, that serves as an electrical contact, in the via and completing the connection using thermal or electrical energy.

In another preferred embodiment, the insulator initially functions as an insulator in all directions, but is selectively conductive in the vertical direction while maintaining the insulator in the planar direction when both pressure or heat energy or pressure and heat energy is applied to the insulator. Can be made of an anisotropic conductive material. In general, a via is an area in which electrical conduction occurs between a conductor adjacent the top surface of the insulator and a conductor adjacent the bottom surface of the insulator.

Integrated circuit dies may be positioned to cover both surfaces of the insulator such that the integrated circuit dies are in a back-to-back manner. Unlike the conventional back-to-back arrangement, the method of forming an electrical connection through the insulator by the present invention allows the terminals of the two elements to be arbitrarily connected, thus implementing a mirror symmetric die in the practice of the present invention. Is not necessary. As in some prior art packages, the terminals of the two integrated circuit dies do not require alignment or mirror symmetry.

In addition, the integrated circuit die in some embodiments may be the same integrated for DRAM, EEPROM, FLASH or other dynamic memory devices or non-volatile memory devices that can connect multiple identical integrated circuit dies together to form a large packaged device. It may be a circuit die. In other preferred embodiments, the dies may have different functions, such as memory controllers, memory devices, analog circuits and digital devices, sensors and controllers, and the like, to provide integrated functionality within the final packaged device. .

In an alternative preferred embodiment, the invention provides an insulator with vias formed in selected positions, a first leadframe covering one surface of the insulator, a second leadframe covering another surface of the insulator, a known flip chip. Technology to provide a first integrated circuit connected to a first leadframe, the circuit being located physically close to a pad or ball of solder and desired leads, in which an integrated circuit bond pad has already been formed, and then energy Reflow to form a mechanical and electrical connection between the die pad and the interior of the lid; The second integrated circuit is similarly connected to the second leadframe using flip chip technology, and electrical connections are made between the first integrated circuit and the second integrated circuit through vias in the insulator before the device is completed. In the preferred embodiment, since both the first die and the second die are connected to the leadframe using flip chip technology, the integrated circuit elements can be arranged in a face-to-face manner.

An alternative embodiment, which is included within the scope of the present invention and contained in the appended claims, combines a flip chip connection and a wire bonding connection, such that one die is connected to the first leadframe using, for example, flip chip technology. The second die may be connected to the second leadframe by wire bonding.

In another preferred embodiment, a removable storage card manufactured using the method and packaging apparatus of the present invention; An insulator having vias formed in a selected position, a first leadframe positioned to cover the insulator, wherein some leads are covering the vias in the insulator, and located near the first leadframe and between the nonvolatile integrated circuit and the leadframe A first integrated circuit in which at least one electrical contact is formed, a second integrated circuit is provided in proximity to a second leadframe having some leads covering the vias of the insulator and positioned to cover the opposite surface of the insulator. The second integrated circuit is a controller circuit for operating a nonvolatile memory device, and the second integrated circuit is electrically connected to the second leadframe.

Using the method of the present invention, an electrical connection is made between the first leadframe and the second leadframe through the vias in the insulator, thereby forming an electrical connection between the memory controller circuit and the nonvolatile memory. The storage card is completed by sealing or overmolding the insulator, the first integrated circuit and the second integrated circuit, and the first leadframe portion and the second leadframe portion, and the remaining outer portions of the first and second leadframes are completed storage cards. Is used to connect to the outside.

More advantageously, the insulator used in the preferred embodiment of the present invention may use a variety of known materials. The insulator has through-hole vias formed in the insulator and does not require electrical connections, complex multilayer routing or metallization patterns in or on the insulator and electrically connects the first lead frame and the second lead frame. Any material that insulates may be used. Plastics, glass, ceramics, fiberglass, resins, PC boards, tapes, films, paper and other insulators can be used. The vias may be formed by chemical etching, photolithography, laser drilling or mechanical drilling processes. Plastic or resin molding may be used to form the insulators in which the vias are formed. The insulator can be made of a rigid material or a flexible material as desired and of various thicknesses. Insulators may be overmolded to complete a packaged device, optionally with an insulator, integrated circuit, and leadframe assembly placed in a cavity of the shell or in a preformed body structure, followed by adhesive or sealing with a cover or layer It can seal zero.

In another preferred embodiment, the integrated system may be provided in a single package incorporating multiple integrated circuit dies on both sides of the insulator. The multiple die is wire bonded to a leadframe that is connected to form any connection between integrated circuits through vias in the insulator. The packaged assembly for the system includes passive elements such as resistors, capacitors or inductors. The entire assembly is overmolded using the method of the present invention to complete the packaged system.

An advantage of embodiments of the present invention is the use of materials compatible with existing automated semiconductor packaging infrastructure, using conventional wire bonding or flip chip techniques, and package molding methods that are compatible with existing tooling. To provide a method and apparatus for forming a multiple integrated circuit module comprising multiple integrated circuit elements that can be electrically connected to one another without the need for complex interposers, flexible circuits, laminates or patterned printed circuit boards. Include.

The foregoing descriptions outline the features and technical advantages of embodiments of the present invention in order that the detailed description of the invention that follows may be better understood. Those skilled in the art will recognize that the specific embodiments and concepts disclosed can be readily used as a basis for the design or modulation of processes or other structures to achieve the same purposes as the present invention. Those skilled in the art should recognize that such equivalents do not depart from the scope and spirit of the invention as set forth in the appended claims.

In order to more fully understand the present invention and its advantages, the present invention will be described in detail with reference to the accompanying drawings. However, the accompanying drawings are for ease of understanding and are not drawn to scale.

1 shows a detachable storage card package according to the prior art, in which FIG. 1A is a plan view thereof and FIG. 1B is a bottom view.

FIG. 2 is a cross-sectional view of a removable storage card according to the prior art as shown in FIG. 1, including a memory element and a control element.

3 is a plan view of an insulator having through-hole vias, which may be incorporated into a preferred embodiment of the present invention.

4 is a cross-sectional view of the insulator of FIG. 3.

FIG. 5 is a plan view of the insulator shown in FIGS. 3 and 4 having a lead frame and an integrated circuit positioned over the insulator.

FIG. 6 is a cross-sectional view of the device of FIG. 5 undergoing further processing steps.

7A and 7B are cross-sectional views of a further preferred embodiment of the insulator of the present invention.

8 is a cross-sectional view of a completed packaged device as a preferred embodiment of the present invention.

9 is a cross-sectional view of a completed packaged device as another preferred embodiment of the device of FIG. 8 of the present invention.

10 is a plan view of the device of FIG.

11 is a cross-sectional view of another completed packaged device as another embodiment of the present invention.

Reference numerals and symbols corresponding to each other in different drawings refer to corresponding parts unless otherwise indicated. The drawings are intended to clearly illustrate related aspects of the preferred embodiments and are not drawn to scale.

Hereinafter, the process and manufacture of the preferred embodiments will be described in detail. However, the disclosed embodiments and examples are not only applicable to the practice of the present invention. The specific embodiments mentioned are merely illustrative of specific ways of carrying out the invention and do not limit the scope of the invention. The drawings are not to scale, for illustrative purposes.

3 is a plan view of an insulator 300 used in the preferred embodiment of the present invention. The insulator 300 is a semiconductor such as Mylar, Upilex, Kapton, other films, insulating papers, resins, polyimides, glass, glass fibers and other materials known in the art. It can include any of a number of insulating materials that are compatible in the process step. Insulator 300 preferably has physical properties that are electrically insulated and that can be used interchangeably in certain thermal processes, such as transfer molding. The insulator is formed with a through hole via 301 at a predetermined position, as described in detail below, to provide a through-hole in the insulator 300. The through-hole vias can be any size, but in a preferred embodiment the diameter is about 3-10 mils, preferably about 5 mils. In a first preferred embodiment disclosed below, the vias are open through holes, and in other preferred embodiments the vias may be filled with a conductive paste or adhesive.

4 is a cross-sectional view of the insulator of FIG. 3. In FIG. 4, it can be seen that the through hole vias 301 extend through the insulator 300. The through hole vias 301 may be formed by other means for forming holes in the material, such as, for example, laser drilling, mechanical drilling, etching, punching or molding. As is known in the art, photolithography can be used by patterning an etch resist layer across the surface with a positive or negative resist to define the location and dimension of the hole, and selective etching is utilized to remove the material. And then strip away the pattern layer.

5 is a plan view of a preferred embodiment of the present invention, in which several assembly steps have been completed. In FIG. 5, the insulator 300 has a through hole via 301 formed at a selected position. A lead 502 is formed in the lead frame, and some leads are placed on the through hole vias 301. An integrated circuit die 303 is located near the interior of the lid 502. Bond wires 505 are formed to electrically connect the bond pads 507 to the leads 502. Although not shown in FIG. 5, the same process was performed to position the second leadframe and the second integrated circuit on the opposite surface of the insulator 300. Some leads of the second leadframe are positioned under the through hole vias 301.

6 is a cross-sectional view of a preferred embodiment of the present invention in an intermediate assembly step. In FIG. 6, it can be seen that the integrated circuit die 303 is located above the first surface of the insulator 300. A cross sectional view of a leadframe lead 502 is shown and a bond wire 505 connecting the bond pad of the integrated circuit die to the leadframe lead 502. It can be seen that the through hole via 301 is formed at a selected position in the insulator 300.

The lead frame 601 is positioned below the insulator 300 and extends below the through hole via 301. Integrated circuit die 604 is connected via bond wire 605 from bond pad 603 to leadframe 601.

As shown in FIG. 6, the leadframe leads are physically and electrically coupled to each other through the insulator in the through hole via 301. In FIG. 6, the lead 502 and the lead 602 are pressed and deformed in the through hole via 301 using the welding tool 607, and the two leads are welded to each other by applying energy. Ultrasonic, electrical and / or thermal energy may be used to form the welds, and methods including electrical resistance welding, capacitive discharge, or laser welding may also be considered. In some embodiments, leadframe leads may be coated with a material by spot plating or other methods prior to assembly to aid in weld formation. This coupling process is performed in each through hole via 301. By properly designing the leadframe and insulator 300, electrical contacts can be formed at any desired point between the two integrated circuits, as shown in FIGS.

In a preferred embodiment, initially no holes are formed in the insulator and the leadframes are located on both sides opposite to each other and are shown at 607 in FIG. 6 in a position where the leads from the upper and lower leadframes are to be joined. A tool such as one is used to form a weld between the upper and lower leadframe leads and to form a through hole via 301 in the insulator 300. In this preferred embodiment, the welding tool 607 is used in one continuous process to apply energy, such as heat, to the lead at the point to be connected to melt or evaporate the insulating material by the energy, thereby providing an insulating material. The through hole via 301 is formed while being removed, and the leads are physically deformed and welded into the through hole via 301. The method does not require design or patterning for the insulator, so the cost of the insulator is greatly reduced.

7A and 7B illustrate alternative methods of connecting the upper and lower leadframe leads in the through hole vias 301 in the insulator 300. FIG. 7A shows a portion of the insulator 300 used in the package of the present invention having a through hole via 301 filled with a conductive material 705. A conductive material such as a conductive paste is stacked in the through hole via 301, and as the assembly process proceeds, the conductive material is positioned between the leadframe leads. The conductive material completes the electrical connection between the two integrated circuit elements shown in FIG. The conductive material may be a conductive paste that is screened in the via hole in a manner well known in the art, or may be, for example, a conductive ink sold under the trade name Parmod VLT from Parlek, Rocky Hill, NJ. The material may be a conductive ink, and these materials may be attached by screen printing, laser mill and filling or ink printing process. Heat or other energy may be applied to complete the conductive path and physically bond the conductive material to the leads.

7B illustrates the use of an anisotropic conductive material as the insulator 300. The material is initially insulated in the horizontal and vertical directions. Under pressure and / or heat or other energy, the material containing the conductive filaments becomes conductive in the vertical direction in the selected area. Accordingly, in FIG. 7B, a conductive path is formed at a point lying between two lead frame leads, one upper lead frame and a lower lead frame, and the conductive path is used to connect the lead frame leads at a randomly selected point. It is used in place of the through hole vias 301 of FIGS. 5 and 6. St. Paul, Minnesota, Inc. provides a pressure sensitive adhesive transfer tape that is anisotropic conductors. An example of a product that can be used is 3M Tape 9703. Anisotropic films and conductive pastes used in the examples, such as FIG. 7B (film) or FIG. 7A (paste), can also be purchased from common vendors, such as Henkel Technologies, Dusseldorf, Germany. These materials may be used in conjunction with other films, or used alone to form the insulator 300.

8 illustrates an alternative preferred embodiment using flip chip technology to couple an integrated circuit die to a leadframe. In FIG. 8, a package 801 is formed of an encapsulant 803 that protects devices and leadframes and covers both sides of the insulator 300. The through hole via 301 is formed in the insulator 300 and is connected to the lead 502 from the upper and lower lead frames as described above. An integrated circuit die 303, which may be a memory control element, is flip-chip bonded to an upper leadframe using a known bump or wafer bumping process to form solder bumps, balls, or columns on die pads of an integrated circuit, and Afterwards, the solder bumped die is aligned to the inner ends of the leadframe leads, positioned “face down” so that the die pads engage with the leadframe leads and reflow the solder using thermal energy to leadframe The connection to is completed. Similarly, the integrated circuit 809, which may be a nonvolatile memory such as, for example, a flash memory element, is also flip-chip mounted to the lower leadframe, and a weld is formed as shown at 807 in the through-hole via 301. The upper and lower leadframes are coupled to each other. 8 also shows that the dies may form contacts at any point between two or more integrated circuits in a package, even if the dies are not the same size or very similar size to each other.

FIG. 9 shows a completed package 901 using an alternative preferred embodiment of wire bonding connections using a lead under chip or " LUC " leadframes for upper and lower leadframes. In FIG. 9, the leads extend through the encapsulant boundary to provide external contacts for the package. As described above, a package 901 having encapsulant 903 on both sides of the insulator 300 is shown in cross section, which again prevents the integrated circuit die, leadframe and bond wires from being damaged. It also protects from moisture. The integrated circuit die 303 is provided to cover the lid 502 of the upper leadframe and is preferably mounted to the leadframe using a tape or epoxy die attach 609. The bond pads 605 of the upper and lower integrated circuits are wire-bonded to the leadframe leads 502 using wire bonding as described above, and the bond wires 505 extend to the leadframe leads. A weld 807 that joins the upper and lower leadframe leads is shown in the through hole via 301. The lead 502 extends through the encapsulant boundary to form an external terminal such that the package 901 is externally connected using, for example, a socket element. In this embodiment, the leads coming out of the upper leadframe are exited to either side of the package and the leads coming out of the lower leadframe are exiting to the other side of the package.

FIG. 10 is a plan view of the package 901 of FIG. 9. It can be seen that the encapsulant 903 is formed on the insulator 300. It can be seen that the lead 502 covers the insulator 300 and extends through the boundary of the encapsulant region 902. It can be seen that the weld 807 lies in the via hole formed below the specific lead 502. An integrated circuit die 303 is located over the leads 502 so that the leadframe is a lead under an LUC or chip arrangement, which can be supported by tape or epoxy. The bond pads on the integrated circuit are coupled to the leadframe leads 520 by bond wires 505. Although not shown in the figure, there is a leadframe assembly placed under the second integrated circuit and insulator 300 and connected to the upper leadframe by a weld 807.

11 shows a lower surface 101 of a lid 502 selected to be electrically connected to the outside although a portion of the lid 502 is formed downwardly from one side of the package and the encapsulant 903 surrounds the entire assembly. Another preferred embodiment is shown in which the area is exposed to the outside. The external connection area may be located as shown in FIG. 1 or may be of a similar pattern as is well known in the art.

The method of practicing the present invention may be changed, and such modified embodiments should be regarded as falling within the scope and claims of the present invention. For example, the leadframe and insulator 300 may be assembled together in a pre-molded assembly and may be integrated into the die using integrated circuit dies located near corresponding leadframes, wire bonding or flip-chip couplings. After completion of the overmolding or glop top encapsulation may be performed. Optionally, the leadframe may be provided in the form of a strip, in which the integrated circuit dies are located, performing a wire bonding or flip-chip process to connect the integrated circuit to the leadframe with or without adhesive or tape. Can; A leadframe assembly is positioned on each of the opposing surfaces of the insulator 300 and previously patterned the insulator 300 to form the through hole vias 301 and then welded, conductive paste or solder, or the anisotropic conductive described above. Join the leadframes by using a connection. Finally, the finished assembly is overmolded or glove-top sealed to complete the package. As described above, the insulator 300 may be provided in another manner without the through hole vias 301 in the insulator, and the tooling is used to simultaneously form the through hole vias 301 in the insulator 300. You may.

While certain preferred embodiments of the present invention and the advantages thereof are described in detail in the specification, many modifications, substitutions, and exchanges can be made without departing from the spirit and scope of the invention as set forth in the appended claims. Keep in mind that you can. In addition, the scope of the present application is not limited to the circuits, structures, methods, and steps of specific embodiments disclosed herein. Accordingly, the appended claims are intended to cover the scope of processes, equipment, manufacture, material compositions, means, methods, or steps used in the present invention, and modifications that utilize the present invention will be apparent to those skilled in the art.

Claims (27)

An insulator having a first surface, a second surface opposite the first surface, and one or more through hole vias formed in a predetermined position; A first leadframe having a plurality of leads and at least partially covering the first surface; A first integrated circuit die positioned near and electrically connected to at least one of the plurality of leads of the first leadframe; A second leadframe having a plurality of leads and at least partially covering the second surface; A multi-die semiconductor package comprising a second integrated circuit die positioned near and electrically connected to at least one of the plurality of leads of the second lead frame. At least one lead of the plurality of leads of the first leadframe is the corresponding one of the plurality of leads of the second leadframe through the through hole via of any one of the through hole vias in the insulator. And a multi-die semiconductor package electrically connected thereto. The semiconductor device of claim 1, further comprising an encapsulant that encapsulates the insulator, the first integrated circuit die, the second integrated circuit die, the first leadframe, and the second leadframe at least partially. Multi-die semiconductor package, characterized in that. The multi-die semiconductor package of claim 1, wherein the first integrated circuit die and the second integrated circuit die are the same integrated circuit die. 2. The multi-die semiconductor package of claim 1, wherein the first integrated circuit die and the second integrated circuit die each comprise a controller integrated circuit and a memory array integrated circuit. 5. The multiple die semiconductor package of claim 4, wherein the memory array integrated circuit comprises a nonvolatile memory device. The multi-die semiconductor package of claim 1, wherein the first integrated circuit die and the second integrated circuit die are electrically connected to the first lead frame and the second lead frame by bond wires, respectively. The multi-die semiconductor package of claim 1, wherein the first integrated circuit die and the second integrated circuit die are electrically connected to the first lead frame and the second lead frame by flip chip connections, respectively. The multi-die semiconductor package of claim 6, wherein the first integrated circuit die and the second integrated circuit die are arranged in a back-to-back manner. 8. The multi-die semiconductor package of claim 7, wherein the first integrated circuit die and the second integrated circuit die are arranged in a face-to-face manner. The multi-die semiconductor package of claim 1, wherein the through-hole via is filled with a conductive material and is in physical contact with at least one lead of the first leadframe. The insulator of claim 1, wherein the insulator comprises an anisotropic conductive material at the one or more through-hole via locations, and wherein the anisotropic conductive material is conductive at a predetermined one or more predetermined positions to form an electrical connection. Multi die semiconductor package. The multi-die semiconductor package of claim 1, wherein at least one lead of each of the first lead frame and the second lead frame is physically welded to each other in the at least one through hole via in the insulator. The multi-die semiconductor package of claim 12, wherein at least one lead of each of the first lead frame and the second lead frame is deformed into a through hole through which the leads are welded to each other. A method of manufacturing a multi die integrated circuit package, Preparing an insulator having a first surface and a second surface opposite the first surface; Forming one or more through hole vias in a desired position in the insulator; Preparing a first leadframe having a plurality of leads at least partially covering the first surface; Preparing a second leadframe having a plurality of leads at least partially covering the second surface; Coupling a first integrated circuit die to at least one lead of the first leadframe; Coupling a second integrated circuit die to at least one lead of the second leadframe; Electrically connecting at least one lead of the first leadframe to a corresponding lead of the second leadframe through one or more vias in the insulator; And wherein the first integrated circuit die and the second integrated circuit die are electrically connected to each other. 15. The multiple die of claim 14 further comprising at least partially encapsulating the insulator, the first integrated circuit die, the second integrated circuit die, the first leadframe, and the second leadframe. Integrated circuit package manufacturing method. The method of claim 14, wherein the electrically connecting step, Forming a portion of one lead of the first leadframe in at least one through hole via in the insulator; Forming a corresponding portion of one lead of said second leadframe in said through hole via in said insulator; And And physically connecting the first lead frame and the second lead frame to form an electrical connection in the through hole via. 17. The multi-die integrated circuit package of claim 16, wherein physically connecting comprises forming a physical weld between the first leadframe and a portion of the second leadframe in the through hole via. Manufacturing method. 18. The multi-die integrated circuit package of claim 17, wherein forming one or more through hole vias in the insulator is performed in connection with physically connecting the first lead frame and the second lead frame. Manufacturing method. 17. The method of claim 16, wherein physically connecting comprises providing a conductive adhesive between the first and second portions of the first leadframe and the second leadframe in the through hole via. A multi-die integrated circuit package manufacturing method. 15. The multiple die integrated circuit of claim 14, wherein coupling the first integrated circuit die and the second integrated circuit die to the first leadframe and the second leadframe comprises connecting the same integrated circuit dies. Package manufacturing method. 15. The method of claim 14, wherein connecting the first integrated circuit die and the second integrated circuit die to the first leadframe and the second leadframe comprises connecting the memory array integrated circuit die to the first leadframe and connecting the controller integrated circuit die. And connecting to a second leadframe. 22. The method of claim 21, wherein coupling the memory array integrated circuit die to the first leadframe comprises connecting a nonvolatile memory array integrated circuit die. 23. The method of claim 22, further comprising stacking additional nonvolatile memory array integrated circuit dies on the nonvolatile memory array integrated circuit dies. 15. The method of claim 14, wherein connecting the first integrated circuit die and the second integrated circuit die to the first leadframe and the second leadframe comprises: a first integrated circuit die and a second integrated circuit die and a first leadframe and a second lead. Forming a wire bond between the frames. 25. The multi-die integrated circuit package of claim 24, wherein connecting the first integrated circuit die and the second integrated circuit die further comprises arranging the integrated circuit dies back-to-back. Manufacturing method. 15. The method of claim 14, wherein connecting the first integrated circuit die and the second integrated circuit die to the first leadframe and the second leadframe comprises: a first integrated circuit die and a second integrated circuit die and a first leadframe and a second lead. Forming a flip chip connection between the frames. 27. The method of claim 26, wherein connecting the first integrated circuit die and the second integrated circuit die to the first leadframe and the second leadframe comprises arranging the first integrated circuit die and the second integrated circuit die in a face-to-face manner. And further comprising the step of: a multi-die integrated circuit package manufacturing method.

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