TWI495082B - Multi-layer semiconductor package - Google Patents

Multi-layer semiconductor package Download PDF

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Publication number
TWI495082B
TWI495082B TW100105024A TW100105024A TWI495082B TW I495082 B TWI495082 B TW I495082B TW 100105024 A TW100105024 A TW 100105024A TW 100105024 A TW100105024 A TW 100105024A TW I495082 B TWI495082 B TW I495082B
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TW
Taiwan
Prior art keywords
substrate
die
major planar
encapsulating resin
package
Prior art date
Application number
TW100105024A
Other languages
Chinese (zh)
Other versions
TW201130110A (en
Inventor
Rajendra D Pendse
Original Assignee
Stats Chippac Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Priority to US11/608,164 priority Critical patent/US7608921B2/en
Application filed by Stats Chippac Inc filed Critical Stats Chippac Inc
Publication of TW201130110A publication Critical patent/TW201130110A/en
Application granted granted Critical
Publication of TWI495082B publication Critical patent/TWI495082B/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
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    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2924/181Encapsulation

Description

Multilayer semiconductor package

This invention relates to semiconductor packages.

Electronic devices typically utilize multiple semiconductor components, such as several microchips. Some devices may be designed as "multi-chip modules", which typically include a printed circuit board (PCB) substrate onto which a separate set of microchips is attached directly. These multi-chip modules can increase circuit density and miniaturization results, but their size can be very large.

One of the methods used to reduce the size of multi-wafer modules and thereby increase their effective density is to stack the dies or wafers in a vertical manner. Conventional embodiments of this approach have a package-on package (PoP) configuration and a package-in package (PiP) configuration that can save space on the PCB. These packages may be, for example, of a size rating of about 15 mm square and have a height of about 2 mm.

Some package designs place an interposer on the die. For example, a method for fabricating a stacked semiconductor package includes providing a substrate and placing a first semiconductor device on the substrate, as disclosed in U.S. Patent No. 6,861,288, issued toS. The interposer may be supported over the first semiconductor device opposite the substrate. The interposer may be electrically connected to the substrate. Next, the second semiconductor device is disposed on the interposer." See the abstract. However, the package area caused by this design may be much larger than the area of the packaged die.

In view of the above, there is a need for improved semiconductor packaging and packaging methods.

A semiconductor package may include a base substrate on which a semiconductor die is placed on top of the base substrate, and an interposer substrate is disposed on top of the die. The underside of the interposer substrate may be electrically coupled to the top side of the base substrate via a vertical connector. The top side of the interposer substrate is substantially exposed to accommodate additional electronic components. The base substrate and the interposer substrate may be configured with input/output (I/O) terminals such that components disposed on the substrates are electrically coupled to each other via a vertical connector. The base substrate may also be electrically coupled to another electronic component, such as a PCB.

In one embodiment, a semiconductor package includes: a first substrate having a first major planar surface and a second major planar surface defined by the first perimeter; a first semiconductor die electrically coupled to the a second major planar surface of the first substrate; a second substrate having a first major planar surface and a second major planar surface defined by the second perimeter; a first plurality of vertical connectors configured to Electrically coupling a first major planar surface of the second substrate to a second major planar surface of the first substrate; and a first encapsulating resin anchored to the second surface of the semiconductor die and the first substrate The encapsulating resin also covers at least a portion of at least some of the vertical connectors, wherein the vertical connectors are positioned substantially within the first perimeter and the second perimeter, and wherein The second major planar surface of the second substrate is substantially operative to house one or more electronic components. The first semiconductor die may be electrically coupled to the second major planar surface of the first substrate in a flip chip configuration. In other embodiments, the first semiconductor die is electrically coupled to the second major planar surface of the first substrate using at least one bond wire.

The package is more likely to include a second encapsulating resin between the second surface of the first substrate and the first surface of the second substrate. In some embodiments, the first encapsulating resin and the second encapsulating resin comprise a continuous encapsulating resin. In still other embodiments, at least one of the first plurality of vertical connectors comprises a bond-on-lead (BOL) connection. In still other embodiments, at least one of the first plurality of vertical connectors comprises a stud bump. In some embodiments, the first encapsulating resin comprises at least one of the following: an epoxy material, a thermoset material, and a thermoplastic material.

In some embodiments, the second major planar surface of the second substrate is configured to receive an electronic component. The second major planar surface of the second substrate may be further configured to receive a ball grid array having a ball pitch of at least a portion of the ball grid array between about 0.25 mm and about 1.0 mm. In other embodiments, the second major planar surface of the second substrate may be further configured to accommodate at least one of: a flip chip assembly, a quad flat package, a wireless flat package, a molded package, Or passive components. In other embodiments of the semiconductor package, the first perimeter includes a plurality of peripheral sides, and wherein at least some of the first plurality of vertical connectors are located on two sides, three sides, and four sides of the surrounding sides Or more on the side. In some embodiments, at least some of the first plurality of vertical connectors are generally opposite each other along at least one of the first perimeter and the second perimeter.

In another embodiment, the first substrate has a first substrate edge and the first semiconductor die has a first die edge, and a horizontal distance between the first die edge and the first substrate edge The system is between about 0.25 mm and about 1.5 mm. In a further embodiment, the distance is between about 0.25 mm and about 1.0 mm. In other embodiments, the horizontal distance is approximately equal to the width of a vertical connector. In a further embodiment, the vertical distance between the surface of the first semiconductor die facing the first substrate and the first major planar surface of the second substrate is less than about 0.2 mm.

In other embodiments, the semiconductor package further includes: a third substrate having a first major planar surface and a second major planar surface defined by the third perimeter; a second semiconductor die electrically coupled to a second major planar surface of the third substrate; and a second plurality of vertical connectors, the connectors being configured to electrically couple the first major planar surface of the first substrate to the third substrate Two main plane surfaces.

In another embodiment, a method of fabricating a semiconductor package includes: providing a first substrate, a semiconductor die, a second substrate, and one or more vertical connectors, the first substrate and the second substrate Each having a first major planar surface and a second major planar surface; a second major planar surface via the first substrate, a first major planar surface of the second substrate, and at least one of the one or more vertical connections Electrically coupling the die to a second major planar surface of the second substrate, wherein electrically coupling the die comprises coupling at least one or more vertical connectors to a second major planar surface of the first substrate; Providing an encapsulating resin between the die and the first substrate, wherein the encapsulation is provided after coupling at least one or more of the vertical connectors to a second major planar surface of the first substrate a resin, and wherein the second major planar surface of the second substrate is substantially operative to receive one or more electronic components. The method is more likely to include providing an encapsulating resin between the first substrate and the second substrate. A portion of the encapsulating resin may be located between the die and the first substrate, and a portion may be located between the first substrate and the second substrate, the portions being substantially simultaneously provided . In some embodiments, the encapsulating resin is provided by the following processes: a printing encapsulation process; a transfer molding process; a no-flow bottom encapsulation filling process; or other molding process, a bottom encapsulation process, or a pouch Sealing process.

In some embodiments of the method, electrically coupling the die to the second major planar surface of the second substrate may include: electrically coupling the die to a second major planar surface of the first substrate; and via the One or more vertical connectors electrically couple the second surface of the first substrate to the first surface of the second substrate. Electrically coupling the die to the second major planar surface of the second substrate via the second major planar surface of the first substrate may include attaching the die to the second of the first substrate using a plurality of solder balls The main planar surface, and the one or more vertical connectors and the solder balls are backfilled in an approximately simultaneous manner.

In a further embodiment of the method, the first substrate has a first edge and the die has a first edge, and wherein the first edge of the first die and the first edge of the first substrate The horizontal distance between the lines is between about 0.25 mm and about 1.5 mm. In other embodiments, the horizontal distance is between about 0.25 mm and about 1.0 mm.

In some embodiments of the method, the steps of attaching the semiconductor die and providing the second substrate are performed in a substantially simultaneous manner. In other embodiments, the method further includes electrically coupling an additional semiconductor device to a second major planar surface of the second substrate.

Other embodiments of the techniques disclosed herein include semiconductor packages made in accordance with one or more embodiments of the methods disclosed herein.

In some further embodiments, a semiconductor package includes: a first substrate having a first major planar surface and a second major planar surface defined by the first perimeter, the second major planar surface having a second primary planar surface coupled to the second a semiconductor die on a surface of the main plane; and a second substrate composed of a first major planar surface defined by the second perimeter and a second major planar surface, the first major planar surface of the second substrate being One or more vertical connectors are operatively coupled to the second major planar surface of the first substrate, wherein the vertical connectors are positioned substantially within the first perimeter and the second perimeter, wherein the first a substrate has a first substrate edge and the die has a first die edge, and wherein a horizontal distance between the first die edge and the first substrate edge is between about 0.25 mm and about 1.5 mm between.

The foregoing and other objects, features and advantages of the techniques disclosed herein will become apparent from the Detailed Description.

Unless the context clearly dictates otherwise, the singular forms "a" and "the" are used in the application and the scope of the application. Apart from this, the word "include" also means "including". Furthermore, the term "coupled" as used herein is electrically or electromagnetically or mechanically coupled or linked and does not exclude the presence of intermediate elements between the coupled items.

Although the operation of the exemplary embodiments of the methods disclosed herein is illustrated in a particular, sequential order for the convenience of the description, it should be understood that the embodiments disclosed herein may still encompass the particulars disclosed herein. The order of operations other than the sequential order. For example, in some cases, it may be possible to rearrange or simultaneously perform the operations described herein. In addition, for the sake of brevity, the drawings may not show various ways in which the systems, methods and devices disclosed herein can be used in conjunction with other systems, methods and devices (because those skilled in the art can Easy to know). In addition, this description sometimes uses terms such as "produce" and "provide" to describe the method disclosed herein. These words are the upper abstract concepts that can be implemented in practice. For example, "providing" a component may refer to a component that can be used or configured with another component. The actual operation corresponding to the words may vary depending on the particular mode of implementation, and those skilled in the art will readily appreciate this disclosure.

Regardless of the orientation of the components, the term "horizontal" as used herein is defined as being in the plane of the predominantly planar opposing surface of the appropriate component. The term "vertical" refers to a direction that is generally perpendicular to the horizontal direction defined herein. Words such as "above", "above", "below", "bottom", "top", "side", "above", "below", and "below" are in accordance with the horizontal plane. To define.

(Exemplary embodiment of semiconductor package)

1 is a plan view of an embodiment of a semiconductor package 100. The package 100 may include an interposer substrate 110 that is effectively positioned relative to a semiconductor die 120, such as being positioned on top of the die 120 (shown in phantom in the figure); and a substrate Substrate 130. In some embodiments, the substrates 110 and 130 have approximately the same horizontal area. In other embodiments, they may have substantially different horizontal areas. The embodiment of FIG. 1 shows that substrate 110 is slightly smaller than substrate 130. The interposer substrate 110 may include one or more I/O terminals 140 that may be arranged to be electrically coupled to the die 120 or the base substrate 130 as desired.

2 is a side cross-sectional view of the package 100 taken along line 2-2 of FIG. As shown in FIG. 2, the interposer substrate 110 includes two major planar inversion surfaces defined by the perimeter formed by the edges of the substrate 110, that is, a top surface 112 and a bottom surface 114. The base substrate 130 also includes two major planar opposing surfaces defined by the perimeter formed by the edges of the substrate 130, namely, a top surface 132 and a bottom surface 134. The base substrate 130 may include one or more I/O terminals 142, which may be identical to the I/O terminals 140 of the interposer substrate 110 (some features in the figure, for example, terminals 140, 142, It is drawn in a simplified manner to more clearly illustrate other features of the embodiments. The terminals 140, 142 may be configured to carry an electrical signal between a point on a surface of the substrate and another point on the surface, or to carry an electrical signal between two different substrate surfaces .

In the embodiment of FIG. 2, the die 120 is disposed in a flip chip configuration having a plurality of solder balls 122 or similar electrical connections to electrically couple the die 120 to one of the base substrate terminals 142. Or multiple. The base substrate 130 may be electrically coupled to the interposer substrate 110 via one or more vertical connectors, such as representative vertical connectors 150, 154. In this manner, the electrical connection lines from the base substrate 130 can "wrap" the die 120 around the interposer substrate 110. In some embodiments, the vertical connector 150 does not extend horizontally beyond the edges of the substrates 110, 130, allowing for a tight package.

As shown in FIG. 1, package 100 can be constructed such that a vertical connector can be positioned proximate to one, two, three, four, or more edges of package 100, such as vertical connectors 150, 152. 154, 156 model interpreters. 10 is a plan view showing an exemplary embodiment of a package 1000 being constructed such that the vertical connector system is positioned proximate to the five edges of the package 1000 (see, for example, vertical connectors 1010, 1020, 1030, 1040, 1050). Exemplary embodiments of such connectors are described below. As shown in FIG. 2, the package 100 is more likely to include a material 160 interposed between the substrates 110, 130 and between the die 120 and one or both of the substrates 110, 130. In some embodiments, material 160 includes an encapsulating resin and is applied via a bottom encapsulation process (eg, a needle dispensing process, a no-flow underfill process). The term "encapsulating resin" as used in this specification and the scope of the claims refers to a material in a package that defines a space between two or more components; at least a portion Filling a gap between two or more components; and/or being seated around one or more of the substrates to at least partially define a shape of the package and/or seal an area of the package. The encapsulating resin may provide, for example, a predetermined thermal conductivity; a predetermined electrical conductivity; and a barrier to block environmental contaminants. For example, some of the following suitable materials can be used as the encapsulating resin: epoxy resin materials, thermosetting materials, and thermoplastic materials. In some embodiments, these materials can be used with filler particles; in other embodiments, they do not need to be used with filler particles. In other embodiments, the material 160 is applied by a overmolding process (for more clarity of the base substrate 130, material 160 is not shown in FIG. 1). Solder balls 170 or other electrical connections may be provided to electrically couple the base substrate 130 to other circuit elements or components, such as a printed circuit board.

The package 100 can be constructed such that the area occupied by the package 100 on a seating surface (eg, a printed circuit board) is only slightly larger than the horizontal area of the die 120. In some embodiments, the distance d2 between the edge 124 of the die 120 and the edge 136 of the base substrate 130 (or the edge of the interposer substrate 110) is between about 0.25 mm and about 1 mm. Similar distances in some wafer level package (CSP) designs may be between about 2 mm and about 3 mm. However, package 100 can also be designed to have an area that is much larger than the area of die 120. In a further embodiment, package 100 may include a plurality of semiconductor packages (not shown) that are positioned over and electrically coupled to substrate substrate 130.

In other embodiments, the top surface 112 of the substrate 110 is at least partially occupied by an additional semiconductor die (or other electronic component) that is coupled to the terminals 140, 142. 11 is a side cross-sectional view showing an exemplary embodiment of a package 1100 that includes a portion 1110 and is similar to package 100. The package 1100 further includes an additional substrate 1120 (possibly similar to the substrates 110, 130) positioned on top of the additional die 1130, while the vertical connectors 1140, 1142 (which may be similar to the vertical connectors 150, 152, 154, 156) The additional substrate 1120 is electrically coupled to the terminals 140, 142. Thus, the package 1100 may include a plurality of dies sandwiched between the multilayer substrates.

One advantage of some configured packages 100 is that the I/O terminals can be configured to be exposed on both the top and bottom surfaces of the package. In addition, a majority or all of the top surface 112 of the interposer substrate 110 can be used by the terminal 140. The top surface 112 may present a flat or approximately flat seating surface, while other packages may sometimes have raised features, such as a die casting cover that interrupts the seating surface. These features of the package 100 may facilitate three-dimensional integration of multiple semiconductor components.

In other embodiments, FIG. 3 illustrates a side cross-sectional view of package 100 with an electronic component 180 disposed on top of package 100. Electronic component 180 may be electrically coupled to package 100 via one or more terminals 140 at top surface 112 of interposer substrate 110. In one embodiment, the terminals 140, 142 and the vertical connectors 150, 152, 154, 156 can be configured to electrically couple the electronic component 180 with the die 120. In another embodiment, the terminals 140, 142 and the vertical connector 150 can be configured to provide one or more electrical connections between the electronic component 180 and the plurality of solder balls 170. In other embodiments, the terminals 140, 142 and the vertical connector 150 can be configured to create an electrical connection between the electronic component 180, the die 120, and the solder balls 170.

In some embodiments, the die 120 of the package 100 is a microprocessor or other microchip; and the electronic component 180 is a package containing a memory component capable of operating in conjunction with the die 120. In other embodiments, electronic component 180 includes, for example, one or more additional processors, one or more discrete components (eg, passive or active), a flip chip assembly, a quad flat package (QFP), a Wireless Square Flat Package (QFN), a molded package, or a combination thereof.

The electronic component 180 shown in FIG. 3 includes a ball grid array (BGA) 182 for connection to the interposer substrate 110. Some semiconductor packages provide a seating surface along the surrounding area of the package for receiving the BGA, with a raised feature in the center or near the seating surface (eg, a mold sleeve for the die in the package). When an additional device using the BGA is placed on the package, the ball spacing of the BGA is often selected so as to be large enough to lift the additional device above the raised feature. For example, in such devices, the ball pitch may be approximately 0.65 mm. In some embodiments of the package 100 of FIG. 3, the substantially horizontal top surface 112 of the interposer substrate 110 does not require the BGA 182 of the electronic component 180 to lift the electronic component 180 above a raised region. Accordingly, the spacing of the BGA 182 may be less than at least some prior art designs. This smaller BGA pitch may result in a smaller overall package height (e.g., in some embodiments, from the bottom surface 134 of the substrate 130 to the top surface 112 of the substrate 110 of about 0.28 mm) and a higher density BGA. 182. For example, in some embodiments, the ball pitch may be between about 0.25 mm and about 0.3 mm; however, in other embodiments, the ball pitch may be smaller or larger. In some further embodiments, the electronic component 180 may be coupled to the substrate 110 using wire bonding techniques or other techniques known in the art. In an alternate embodiment of the package 100, the top surface 112 of the interposer substrate 110 may include one or more raised features.

4 is a side cross-sectional view of the semiconductor package 400. In this embodiment, package 400 is similar to package 100. However, for the embodiment of FIG. 4, the die 420 is not configured as a flip chip, but will be configured as a bond wire bonded die, wherein the bond wires 444, 446 will electrically couple the die 420. To the base substrate 430. A semiconductor package 480 (or other electronic component) can be placed on top of the package 400. 12 is a side cross-sectional view of a further exemplary embodiment of a semiconductor package 1200. This embodiment is similar to package 400 because the semiconductor package 1200 includes die 1210 that is coupled to surface 1220 of substrate 1230 in a wire bond configuration. In this package 1200, the die 1210 is at least partially separated from the substrate surface 1220 by encapsulating the resin 1240 layer.

There are several embodiments of the vertical connector 150 that can be used in the packages 100, 400. 5 is an enlarged view of a region 190 of FIG. 2 showing an embodiment of a vertical connector 550 for electrically coupling an interposer substrate 510 to a base substrate 530. Also shown in this enlarged view is an encapsulating resin (e.g., epoxy material, thermoset, or thermoplastic) 560 and a die 520 that is formed by one or more solder balls 522 or the like. The connector is electrically coupled to the base substrate 530. For example, an attachment layer 524 that includes an adhesive may provide a physical connection between the substrate 510 and the die 520. In some embodiments of the package shown in FIG. 5 (and in some embodiments of the package shown in FIGS. 6 and 7 below), the system is replaced by a space occupied by, for example, a layer of the attachment layer 524. It may be filled with a molding compound. However, in order for the molding compound to penetrate this region, sufficient clearance should be provided for the molding operation between the top of the die 520 and the bottom of the interposer substrate 510. The necessary "forming clearance" is usually at least about 0.2 mm. Thus, in some embodiments, the package height can be reduced because the molding compound is not placed between the top of the die 520 and the bottom of the interposer substrate 510. The embodiment shown in the figures further shows that the vertical connector 550 includes a conductor bead 552 that is electrically coupled to a conductor trace 556 on the interposer substrate 510. Bead 552 is also electrically coupled to a conductive substrate, such as wire 554, to form a wire-on-wire (BOL) connection. Wire 554 may be further electrically coupled to conductor trace 558 on base substrate 530. Bead 552 may include one or more conductor materials, such as gold or solder, and may be applied to traces 556 using on-contact soldering (SOP) techniques, or may also be coupled to traces 556.

6 is an enlarged view of a region 190 of FIG. 2 showing a further embodiment of a vertical connector 650 for electrically coupling an interposer substrate 610 to a base substrate 630. Also shown in this enlarged view is an encapsulating resin (eg, epoxy material, thermoset, or thermoplastic) 660 and a die 620 that is formed by one or more solder balls 622 or A similar connector is electrically coupled to the base substrate 630. For example, an attachment layer 624 that includes an adhesive may provide a physical connection between the substrate 610 and the die 620. In this embodiment, the vertical connector 650 includes a conductor bead 652 that is electrically coupled to a conductor trace 656 over the interposer substrate 610. Bead 652 may include one or more conductor materials, such as gold or solder, and may be applied to traces 656 using solder-on-pad (SOP) techniques well known in the art. Beads 652 can also be electrically coupled to a conductive substrate, such as stud bumps 654, which may include those known in the art. Several different stud bump materials. In some embodiments, the stud bumps 654 are constructed of gold. The stud bumps 654 may be further electrically coupled to a conductor trace 658 over the base substrate 630.

Figure 7 is an additional embodiment of region 190 of Figure 2. This embodiment shows a solder ball 750 as a vertical connector between a base substrate 730 and an interposer substrate 710. The solder ball 750 is electrically coupled to a conductor trace 756 on the interposer substrate 710 and is electrically coupled to a conductor trace 758 on the base substrate 730. Also shown in this enlarged view is a die 720 that is electrically coupled to the base substrate 730 using one or more solder balls 722 and similar connectors; also shown in this enlarged view as an encapsulating resin (eg, , epoxy resin material, thermosetting material, or thermoplastic material) 760. For example, an attachment layer 724 that includes an adhesive may provide a physical connection between the substrate 710 and the die 720.

A given package configuration can be constructed to use one or more of the vertical connector embodiments described above, as well as other types of vertical connectors.

The package using the vertical connectors shown in Figures 5 and 6 can be constructed to be more compact than the package using the vertical connector shown in Figure 7. The vertical connector embodiments of Figures 5 and 6 can be constructed to use smaller traces (e.g., traces of Figure 5) compared to the corresponding traces used by the vertical connectors of Figure 7 (e.g., traces 756, 758). 556, 558 and traces 656, 658 of Figure 6. Accordingly, the vertical connectors of Figures 5 and 6 are capable of achieving improved path selection efficiency in a given substrate space and allow for edge and maximum substrate at the die (in the embodiment of Figures 5-7) The largest substrate has a short distance d between the edges of the base substrates 530, 630, 730, respectively. The distances d shown in Fig. 5, Fig. 6, and Fig. 7 are d 5 , d 6 , and d 7 , respectively . In the embodiment shown, d 7 >d 5 and d 7 >d 6 . The distance d may be about the same as the width of a vertical connector. Therefore, this enables the horizontal size of a package to be close to the horizontal size of the packaged die.

(Exemplary embodiment of the method disclosed herein)

A flow diagram of an exemplary embodiment of a method 800 of fabricating a semiconductor package is shown in FIG. A package component is provided in step 810. These components may include a base substrate, an interposer substrate, a semiconductor die, and one or more vertical connectors. Both the base substrate and the interposer substrate have a top surface and a bottom surface. In some embodiments, one or more components may be provided simultaneously or approximately simultaneously. For example, vertical connectors and interposer substrates may be provided at the same time. In step 820, the die is electrically coupled to the top surface of the interposer substrate.

9 is a flow diagram of an embodiment of a method for implementing step 820 of FIG. The method includes electrically coupling the die to a top surface of the base substrate (step 910). As noted above, the die and base substrate may be electrically coupled using several configurations known in the art, such as wire bond configuration or flip chip configuration. One or more vertical connectors may be formed (eg, on the top surface of the base substrate, on the bottom surface of the interposer substrate, or both) (step 920). Both the base substrate and the interposer substrate may be electrically coupled via a vertical connector (step 930). In a further embodiment, the interposer substrate may be provided by a pick-and-place process simultaneously or approximately simultaneously with the die coupled to the base substrate.

Referring back to FIG. 8, in a further embodiment, method 800 may further include one or more backfilling steps 830 as necessary. A refill step may be used for packages with dies with flip chip configurations and for packages with vertical connector configurations as described in Figures 5-7. In some embodiments, the first backfilling step may be performed after the die is placed, and a second backfilling step may be performed after the interposer substrate is placed. In other embodiments, a single backfilling step may be used for both the die and the vertical connector between the base substrate and the interposer substrate.

In other embodiments, method 800 may further include one or more bottom sealant fill steps 840 as necessary. In some embodiments, if the die is electrically coupled to the base substrate in a flip chip configuration, then the encapsulating resin (eg, epoxy material, thermoset) can be used as is well known in the art. Material or thermoplastic material) to fill the die with a bottom seal. It is also possible to perform a bottom encapsulation filling of the space between the interposer substrate and the base substrate in a later step. When the flip chip is subjected to a bottom seal filling, the encapsulating resin may create a fillet near the edge of the wafer that extends along the top surface of the base substrate. If the vertical connectors are added after the fillet is formed, the vertical connectors can be placed outside the fillet. However, this increases the amount of space used on the top surface of the base substrate and does not allow the surface below the fillet (sometimes referred to as the "keep-out region"). This configuration may require a larger substrate and thus increase the size of the package. The multi-pass bottom seal fill step may result in one or more interfaces between the materials of the different bottom seal fill steps. In some embodiments, the flip chip and the interposer substrate may be after the vertical connector is in place (in some embodiments, the encapsulating resin may surround at least a portion of some of the vertical connectors) At the same time, the bottom sealant is filled. This can reduce the number of underfill steps 840 and can place the vertical connector closer to the die (possibly achieving a smaller package size).

For embodiments in which the die is coupled to the base substrate in a wire bond configuration, the bottom seal fill step 840 may include a space between the die face and the base substrate and between the interposer substrate and the base substrate. The space between the bottoms is filled with a sealant. In other embodiments, the bottom seal fill step 840 may include (with prior to placing the interposer substrate) encapsulating the die with a encapsulating resin via a print encapsulation process (eg, by printing a layer of material on top of the die). In such embodiments, at least a portion of the vertical connectors may be formed on the interposer substrate, and the interposer substrate may be placed (step 830) such that the vertical connectors are pushed past the printed encapsulating resin. Thereby, the interposer substrate becomes electrically coupled to the base substrate. A backfilling step 830 can then be provided.

In a further embodiment, an additional semiconductor component can be electrically coupled to the top surface of the interposer substrate (step 850). This step can be done independently of any bottom seal fill or backfill steps.

The materials and structures disclosed herein, as well as the examples of methods for making and using such materials and structures, are not to be considered in any limiting sense. Instead, the present disclosure is intended to cover all of the novel and non-obvious features, aspects, and equivalents of the various embodiments disclosed herein. The technology disclosed herein is not limited to any particulars, features, or combinations thereof, and the disclosed materials, structures, and methods are not required to have any particular advantages or advantages. The present invention claims the full scope of the following claims.

100, 400, 480. . . Semiconductor package

110, 510, 610, 710. . . Interposer substrate

112. . . Interposer substrate top surface

114. . . Interposer substrate bottom surface

120. . . Semiconductor grain

122, 170, 622, 722, 750. . . Solder ball

124. . . Grain edge

130, 430, 530, 630, 730. . . Base substrate

132. . . Base substrate top surface

134. . . Base substrate bottom surface

136. . . Base substrate edge

140, 142. . . Input/output terminal

150, 152, 154, 156, 550, 650, 1010, 1020, 1030, 1040, 1050, 1140, 1142. . . Vertical connector

160. . . material

180. . . Electronic component

182. . . Ball grid array

190. . . Some areas in the semiconductor package

420, 520, 620, 720, 1130. . . Grain

444, 446, 522. . . Welding wire

524, 624, 724. . . Attachment layer

552, 652. . . Conductor bead

554. . . wire

556, 558, 656, 658, 756, 758. . . Trace of conductor

560, 660, 760, 1240. . . Encapsulating resin

654. . . Column bump

1000, 1100. . . Package

1110. . . section

1120, 1230. . . Substrate

1200. . . Semiconductor package

1210. . . Grain

1220. . . surface

1 is a plan view of an embodiment of a semiconductor package;

Figure 2 is a side cross-sectional view showing the package of Figure 1;

Figure 3 is a side cross-sectional view showing the package of Figure 1 with an additional semiconductor package;

4 is a side cross-sectional view showing an alternative embodiment of the semiconductor package disclosed by the present invention;

Figure 5 is an enlarged cross-sectional view showing an embodiment of a vertical connector;

Figure 6 is an enlarged cross-sectional view showing an embodiment of a vertical connector;

Figure 7 is an enlarged cross-sectional view showing an embodiment of a vertical connector;

8 is a flow chart of one embodiment of a method of fabricating a semiconductor package;

9 is a flow diagram of one embodiment of a method of electrically coupling a die to a top surface of an interposer substrate;

Figure 10 is a plan view of an embodiment of a semiconductor package;

Figure 11 is a side cross-sectional view showing an embodiment of a semiconductor package;

Figure 12 is a side cross-sectional view of an embodiment of a semiconductor package.

100. . . Semiconductor package

110. . . Interposer substrate

120. . . Semiconductor grain

130. . . Base substrate

140. . . Input/output terminal

150. . . Vertical connector

152. . . Vertical connector

154. . . Vertical connector

156. . . Vertical connector

Claims (15)

  1. A method of fabricating a semiconductor package, the method comprising: providing a first substrate, a semiconductor die, a second substrate, and one or more vertical connectors, both of the first substrate and the second substrate having a first a major planar surface and a second major planar surface; the second principal planar surface of the first substrate, the first major planar surface of the second substrate, and at least one of the one or more vertical connectors The particles are electrically coupled to the second major planar surface of the second substrate, wherein electrically coupling the die comprises coupling at least one or more vertical connectors to a second major planar surface of the first substrate; and Providing an encapsulating resin between the first substrate and the first substrate, wherein the encapsulating resin is provided after coupling the at least one or more of the vertical connectors to the second major planar surface of the first substrate, wherein The vertical connector includes a conductor bead electrically coupled to the electrically conductive substrate, and wherein the second major planar surface of the second substrate is substantially operable to receive one or more electronic components.
  2. The method of claim 1, wherein the method further comprises providing an encapsulating resin between the first substrate and the second substrate.
  3. The method of claim 2, wherein at least some of the encapsulating resin is provided by a printing envelope sealing process.
  4. The method of claim 2, wherein at least some of the encapsulating resin is provided by a transfer molding process.
  5. The method of claim 2, wherein at least some of the encapsulating resin is filled with a non-flowing bottom sealant. Come on.
  6. The method of claim 2, wherein at least some of the encapsulating resin is provided by a bottom seal filling process.
  7. The method of claim 2, wherein a portion of the encapsulating resin between the die and the first substrate is provided, and the encapsulating resin is located on the first substrate and the A portion between the second substrates.
  8. The method of claim 2, wherein a portion of the encapsulating resin between the die and the first substrate is provided in a step and the encapsulating resin is located at the first a portion between the substrate and the second substrate.
  9. The method of claim 1, wherein electrically coupling the die to the second major planar surface of the second substrate comprises electrically coupling the die to a second major planar surface of the first substrate And electrically coupling the second surface of the first substrate and the first surface of the second substrate via the one or more vertical connectors.
  10. The method of claim 1, wherein electrically coupling the die to the second major planar surface of the second substrate via the second major planar surface of the first substrate comprises: utilizing a plurality of solder balls Attaching the die to a second major planar surface of the first substrate; and backfilling the one or more vertical connectors and the solder balls in an approximately simultaneous manner.
  11. The method of claim 1, wherein the first substrate has a first edge and the die has a first edge, and wherein the first edge of the die and the first substrate The horizontal distance between the first edges is between about 0.25 mm and about 1.5 mm.
  12. The method of claim 11, wherein a horizontal distance between the first edge of the die and the first edge of the first substrate is between about 0.25 mm and about 1.0 mm.
  13. The method of claim 1, wherein the step of attaching the semiconductor die and providing the second substrate is performed in a substantially simultaneous manner.
  14. The method of claim 1, further comprising electrically coupling an additional semiconductor device to a second major planar surface of the second substrate.
  15. The method of claim 1, wherein the conductive substrate comprises a wire or a stud bump.
TW100105024A 2006-12-07 2007-10-11 Multi-layer semiconductor package TWI495082B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/608,164 US7608921B2 (en) 2006-12-07 2006-12-07 Multi-layer semiconductor package

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