JPH11260999A - Laminated semiconductor device module with reduced noise - Google Patents
Laminated semiconductor device module with reduced noiseInfo
- Publication number
- JPH11260999A JPH11260999A JP10063111A JP6311198A JPH11260999A JP H11260999 A JPH11260999 A JP H11260999A JP 10063111 A JP10063111 A JP 10063111A JP 6311198 A JP6311198 A JP 6311198A JP H11260999 A JPH11260999 A JP H11260999A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- passive components
- semiconductor device
- device module
- laminated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/107—Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/144—Stacked arrangements of planar printed circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、積層可能なＢＧＡ
(Ball Grid Array) タイプの半導体装置モジュールに関
し、より詳しくは、複数の受動部品をコンパクトに搭載
できる積層構造を有するＢＧＡタイプの積層半導体装置
モジュールに関する。TECHNICAL FIELD The present invention relates to a stackable BGA.
The present invention relates to a (Ball Grid Array) type semiconductor device module, and more particularly, to a BGA type stacked semiconductor device module having a stacked structure capable of compactly mounting a plurality of passive components.
【０００２】[0002]
【従来の技術】回路基板に半導体素子を搭載した半導体
装置 (以下、半導体パッケージともいう) は、例えばＣ
ＰＵモジュール等に使用する場合、多数個の半導体素子
を搭載するのが一般的である。その場合、多数個の半導
体素子を１つの回路基板に搭載するのではなく、複数の
回路基板に分けて搭載し、基板間の導通を保持しながら
基板を上下に積層すれば、マザー基板（実装基板）上で
の半導体装置の占有面積が大きく減少し、マザー基板の
小型化と高密度化が実現できる。2. Description of the Related Art A semiconductor device having a semiconductor element mounted on a circuit board (hereinafter, also referred to as a semiconductor package) is, for example, a C-type semiconductor device.
When used for a PU module or the like, it is common to mount a large number of semiconductor elements. In such a case, instead of mounting a large number of semiconductor elements on one circuit board, the semiconductor elements are mounted separately on a plurality of circuit boards, and the boards are stacked vertically while maintaining conduction between the boards. The occupied area of the semiconductor device on the substrate) is greatly reduced, and the size and density of the mother substrate can be reduced.
【０００３】一方、近年の半導体装置の多端子化要求と
小型化要求により、実装基板との接続を球状金属からな
る接続部材により行うＢＧＡタイプの半導体装置 (ＢＧ
Ａパッケージ) が、回路基板上に外部端子を格子 (アレ
イ）状に配置でき、しかも同じく格子状配置が可能なピ
ン端子を用いたＰＧＡ(Pin Grid Array)パッケージより
端子間隔を狭くすることができるため、盛用されるよう
になってきた。一般に、回路基板の外部端子となるこの
球状金属にはハンダボール (高温ハンダあるいは共晶ハ
ンダ) が使用され、この球状金属の外部端子と実装基板
との接続には共晶ハンダが使用される。On the other hand, in response to recent demands for increasing the number of terminals and miniaturization of a semiconductor device, a BGA type semiconductor device (BG) in which connection to a mounting substrate is made by a connection member made of a spherical metal.
A package) allows external terminals to be arranged in a grid (array) on a circuit board, and the terminal spacing can be made narrower than in a PGA (Pin Grid Array) package using pin terminals that can also be arranged in a grid. Therefore, it has come to be used frequently. Generally, a solder ball (high-temperature solder or eutectic solder) is used for the spherical metal which is an external terminal of the circuit board, and eutectic solder is used for connecting the external terminal of the spherical metal to the mounting board.
【０００４】両者の利点を活かした、積層ＢＧＡパッケ
ージモジュール (複数のＢＧＡパッケージを積層したモ
ジュール) のアイデアも従来からあった。例えば、特開
平４−280695号公報および特開平６−13541 号公報に開
示されている。積層ＢＧＡパッケージモジュールでは、
上にくる回路基板の下面に設けられた球状金属からなる
外部端子を用いて、隣接する回路基板間の電気的接続を
とると同時に、これらの基板を物理的にも連結する。[0004] There has been an idea of a stacked BGA package module (a module in which a plurality of BGA packages are stacked) utilizing the advantages of both. For example, it is disclosed in JP-A-4-280695 and JP-A-6-13541. In the stacked BGA package module,
Using external terminals made of spherical metal provided on the lower surface of the upper circuit board, electrical connection between adjacent circuit boards is established, and these boards are also physically connected.
【０００５】ところで、近年、コンピュータの性能を向
上させるため、マザー基板の動作スピードが向上してい
る。動作スピードの向上は、一方で回路のノイズを増大
させるという問題を招く。ノイズは回路を誤動作させる
危険性があり、その低減は重要な問題である。[0005] In recent years, in order to improve the performance of a computer, the operation speed of a mother board has been improved. On the other hand, the improvement of the operation speed causes a problem of increasing the noise of the circuit. Noise can cause the circuit to malfunction, and its reduction is an important issue.
【０００６】そこで、マザー基板にはノイズを低減させ
る様々な工夫がなされている。例えば、トランジスタの
ON-OFFが切り替わる時に生じるスイッチングノイズの低
減には、バイパスコンデンサを半導体装置の近傍に、ま
たは半導体装置そのものに搭載することがよく知られて
いる。また、信号の反射を抑制するためには、信号ライ
ンの終端に終端抵抗を挿入する方法が有名である。その
ため、マザー基板に搭載される、コンデンサ、抵抗等の
ノイズ低減に使用される受動部品の数は増える傾向にあ
る。Therefore, various measures have been taken to reduce noise on the motherboard. For example, for transistors
It is well known that a bypass capacitor is mounted near a semiconductor device or mounted on a semiconductor device itself in order to reduce switching noise generated when ON-OFF is switched. In order to suppress signal reflection, a method of inserting a terminating resistor at the end of a signal line is well known. Therefore, the number of passive components mounted on the mother board and used for noise reduction such as capacitors and resistors tends to increase.
【０００７】これら個々の受動部品のほとんどは、表面
実装できるようにチップ部品化されており、通常は、図
１の平面図に示すように、マザー基板上の半導体装置
（パッケージ）の近傍に配置される。チップ部品化され
ているため、それによるマザー基板上のスペースの占有
は従来は許容されてきた。しかし、チップ部品の数が増
えると、チップ部品が占めるスペースが無視できなくな
る。即ち、従来の積層半導体装置モジュールでは、実装
密度が増大するのは、半導体装置の部分だけであり、数
多くの受動部品は、チップ部品化してもマザー基板に平
面的に搭載しなければならず、受動部品については実装
密度が向上しない。Most of these individual passive components are formed into chip components so that they can be mounted on a surface. Usually, as shown in a plan view of FIG. 1, they are arranged near a semiconductor device (package) on a mother substrate. Is done. Occupation of the space on the motherboard due to chip components has heretofore been permitted. However, as the number of chip components increases, the space occupied by the chip components cannot be ignored. That is, in the conventional laminated semiconductor device module, the mounting density is increased only in the semiconductor device portion, and a large number of passive components must be mounted on the motherboard even if they are formed into chip components. The mounting density of passive components does not improve.
【０００８】また、上記のノイズ低減用の受動部品は、
半導体装置の近くに配置しなければ期待した効果を発揮
しない。バイパスコンデンサ等をマザー基板ではなく、
半導体装置に搭載するのは、このためである。[0008] The passive components for noise reduction described above include:
Unless it is arranged near the semiconductor device, the expected effect is not exhibited. Bypass capacitors etc. are not on the motherboard,
This is why the semiconductor device is mounted on the semiconductor device.
【０００９】上述の積層半導体装置モジュールは、半導
体装置については実装密度の向上に有効である。しか
し、このように三次元的な実装を行うと、それぞれ半導
体素子を搭載した個々の回路基板には、受動部品を搭載
するスペースがない。従って、必要な受動部品はマザー
基板に搭載しなければならなかった。受動部品のノイズ
低減効果は半導体素子に近い方が良くなる。このため、
従来の積層半導体装置モジュールは、ノイズを十分に低
減することができにくかった。The above-described laminated semiconductor device module is effective for improving the packaging density of a semiconductor device. However, when three-dimensional mounting is performed in this way, there is no space for mounting passive components on each circuit board on which a semiconductor element is mounted. Therefore, the necessary passive components had to be mounted on the motherboard. The noise reduction effect of the passive component is better when it is closer to the semiconductor element. For this reason,
The conventional laminated semiconductor device module has difficulty in sufficiently reducing noise.
【００１０】[0010]
【発明が解決しようとする課題】このように、従来のＢ
ＧＡタイプの積層半導体装置モジュールでは、モジュー
ル内部 (半導体素子のごく近傍) にノイズ低減用受動部
品を搭載することができず、半導体素子から遠いマザー
基板に搭載するため、ノイズ低減効果が十分でないとい
う問題と、数多くの受動部品をマザー基板に搭載するた
め、受動部品によりマザー基板のスペースが占有され、
それほど実装密度が向上しないという問題があった。As described above, the conventional B
In the case of a GA type stacked semiconductor device module, it is not possible to mount passive components for noise reduction inside the module (in the immediate vicinity of the semiconductor element), and since it is mounted on a mother board far from the semiconductor element, the noise reduction effect is not sufficient. The problem and mounting a large number of passive components on the motherboard, the passive components occupy space on the motherboard,
There is a problem that the mounting density is not so improved.
【００１１】本発明の目的は、ノイズ低減効果を十分に
発揮させることができ、かつさらに実装密度の向上が可
能な積層半導体装置モジュールを提供することである。An object of the present invention is to provide a laminated semiconductor device module that can sufficiently exhibit a noise reduction effect and can further improve the mounting density.
【００１２】[0012]
【課題を解決するための手段】上記課題を解決するに
は、マザー基板のスペースを占有してしまう受動部品群
を積層半導体装置モジュールの内部に搭載することが有
効である。しかし、上述したように、積層された各回路
基板間には、上下の回路基板同士を接続する数多くの球
状金属接続部材が配置されており、受動部品を搭載でき
るスペースはごくわずかしかなく、多くの受動部品を搭
載できない。In order to solve the above-mentioned problems, it is effective to mount a group of passive components which occupy the space of the motherboard inside the laminated semiconductor device module. However, as described above, between the stacked circuit boards, a number of spherical metal connecting members for connecting the upper and lower circuit boards are arranged, and there is very little space for mounting passive components, and many Cannot mount passive components.
【００１３】そのため、本発明によれば、受動部品用の
専用の回路基板を別に用意し、この基板に受動部品を一
緒に搭載し、半導体素子を搭載した他の回路基板と積層
して積層半導体装置モジュールとすることにより、上記
課題を解決する。この受動部品用の回路基板には半導体
素子を搭載しないため、その回路基板面を受動部品搭載
スペースに当てることができ、多数の受動部品の搭載が
可能となる。Therefore, according to the present invention, a dedicated circuit board for passive components is separately prepared, the passive components are mounted together on this board, and the circuit board is stacked on another circuit board on which the semiconductor element is mounted. The above problem is solved by using a device module. Since no semiconductor element is mounted on the circuit board for passive components, the surface of the circuit board can be applied to a space for mounting passive components, and mounting of a large number of passive components becomes possible.
【００１４】ここに、本発明は、(a) 上面または内部に
半導体素子を搭載し、下面に球状金属接続部材を備えた
１または２以上の回路基板と、(b) 上面に複数の受動部
品を搭載し、下面に球状金属接続部材を備えた少なくと
も１つの回路基板とを、該球状金属接続部材で基板間を
接続して積層してなる積層半導体装置モジュールであ
る。Here, the present invention provides (a) one or two or more circuit boards each having a semiconductor element mounted on the upper surface or inside and a spherical metal connecting member on the lower surface, and (b) a plurality of passive components on the upper surface. And a circuit board having at least one circuit board provided with a spherical metal connecting member on a lower surface thereof, and connecting the substrates with the spherical metal connecting member to form a laminated semiconductor device module.
【００１５】この場合、ノイズを除去したい半導体素子
と積層する層が異なっており、半導体素子から遠いと思
われがちであるが、実際には回路基板の厚みを介して受
動部品と半導体素子は接続されており、マザー基板に受
動部品を搭載した場合に比べて距離は非常に近くなる。
これは三次元的に実装するためである。従って、ノイズ
低減効果も高くなる。In this case, the semiconductor element from which noise is to be removed and the layer to be laminated are different and tend to be considered far from the semiconductor element. However, in practice, the passive component and the semiconductor element are connected through the thickness of the circuit board. Therefore, the distance is much shorter than when passive components are mounted on the motherboard.
This is for three-dimensional implementation. Therefore, the noise reduction effect also increases.
【００１６】また、マザー基板に受動部品を搭載した場
合には、半導体素子間に受動部品が搭載されるため、半
導体装置同士を接続する信号ラインが長くなり、ノイズ
が大きくなりやすい。従って、本発明のような構成を有
するモジュールでは、半導体装置同士の信号ラインが短
くなるという点からも、ノイズ低減効果が効果的に発揮
されるといえる。When passive components are mounted on the mother board, the passive components are mounted between the semiconductor elements, so that a signal line connecting the semiconductor devices becomes longer, and noise tends to increase. Therefore, in the module having the configuration as in the present invention, it can be said that the noise reduction effect is effectively exhibited also from the viewpoint that the signal line between the semiconductor devices is shortened.
【００１７】さらに、半導体素子を搭載しない回路基板
を余分に積層するため、コストが上昇するように思える
が、その分だけマザー基板を小型化することができ、ト
ータルコストで考えればむしろ安価なぐらいである。[0017] Further, since it seems that the cost is increased due to the extra lamination of the circuit board on which the semiconductor element is not mounted, the mother board can be made smaller by that much, and it is rather inexpensive considering the total cost. It is.
【００１８】[0018]
【発明の実施の形態】本発明は、一般に、ＢＧＡタイプ
の積層半導体装置モジュール、即ち、それぞれ上面（ま
たは内部）に半導体素子を搭載し、下面に球状金属接続
部材を備えたＢＧＡタイプの複数の半導体装置（ＢＧＡ
パッケージ）を上下に積層したモジュールの改良に関す
る。各ＢＧＡパッケージの構造は、従来と同様でよく、
特に制限されるものではない。なお、半導体素子を搭載
した回路基板は必ずしも複数である必要ななく、１層だ
けであってもよい。その場合には、本発明に従って、受
動部品を搭載した回路基板を積層することにより、積層
半導体装置モジュールとなる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention generally relates to a stacked semiconductor device module of the BGA type, that is, a plurality of BGA type stacked semiconductor devices each having a semiconductor element mounted on the upper surface (or inside) and a spherical metal connecting member on the lower surface. Semiconductor device (BGA
Package) is improved. The structure of each BGA package may be the same as before,
There is no particular limitation. Note that the number of circuit boards on which the semiconductor elements are mounted does not necessarily need to be plural, and may be only one layer. In this case, a laminated semiconductor device module is obtained by laminating circuit boards on which passive components are mounted according to the present invention.
【００１９】一般に、ＢＧＡパッケージは、半導体素子
を搭載した回路基板の下面に球状金属 (金属ボール) か
らなる外部端子を備えた構造を持つ。球状金属は、銅等
のハンダ以外の金属もしくは合金、またはハンダ合金か
ら形成することができる。ハンダ合金の場合には、共晶
ハンダと高温ハンダのいずれも可能であるが、球状の形
状を保持したい場合には高温ハンダとすることが好まし
い。Generally, a BGA package has a structure in which external terminals made of a spherical metal (metal ball) are provided on the lower surface of a circuit board on which a semiconductor element is mounted. The spherical metal can be formed from a metal or alloy other than solder, such as copper, or a solder alloy. In the case of a solder alloy, either a eutectic solder or a high-temperature solder is possible, but if it is desired to maintain a spherical shape, it is preferable to use a high-temperature solder.
【００２０】回路基板は、その表面に電極と金属配線が
形成されている。多層基板では基板内部にも金属配線が
形成される。半導体素子は、その表面に設けられた電極
から、回路基板の上面の電極とその金属配線を経て、回
路基板の下面の外部端子へと電気的に接続される。な
お、各回路基板には、基板の表裏の導通のためにスルー
ホールが一般に設けられる。The circuit board has electrodes and metal wirings formed on its surface. In a multilayer substrate, metal wiring is also formed inside the substrate. The semiconductor element is electrically connected from an electrode provided on the surface thereof to an external terminal on a lower surface of the circuit board through an electrode on an upper surface of the circuit board and a metal wiring thereof. Note that each circuit board is generally provided with a through hole for conduction between the front and back of the board.
【００２１】ＢＧＡパッケージは、球状金属からなる外
部端子を格子状に配置することができ、多端子化に対応
可能である。さらに、ピン状の外部端子を格子状に配置
したＰＧＡパッケージに比べて、端子間隔を狭くできる
ので、単位面積当たりの端子数をさらに増加させること
ができる。In the BGA package, external terminals made of a spherical metal can be arranged in a lattice, and can be adapted to multi-terminals. Further, the terminal interval can be narrowed as compared with a PGA package in which pin-shaped external terminals are arranged in a lattice, so that the number of terminals per unit area can be further increased.
【００２２】ＢＧＡパッケージは、回路基板の絶縁性材
料が樹脂質の材料であるＰＢＧＡパッケージと、セラミ
ックス材料であるＣＢＧＡパッケージに大別されるが、
本発明の回路基板は、そのどちらでもよく、また両者を
組合わせて積層することもできる。The BGA package is roughly classified into a PBGA package in which the insulating material of the circuit board is a resinous material and a CBGA package in which the insulating material of the circuit board is a ceramic material.
The circuit board of the present invention may be either one of them, or may be laminated by combining both.
【００２３】ＢＧＡパッケージの積層モジュール化は、
その下面に位置する外部端子の球状金属を接続部材とし
て行われる。即ち、上になるＢＧＡパッケージの回路基
板の下面にある球状金属を、下になるＢＧＡパッケージ
の回路基板の上面にある電極と接続させて、電気的接続
と機械的な連結を行う。この接続は、球状金属がハンダ
から作製された場合には、その部分的な溶融により達成
してもよいが、外部端子の球形という形状を維持するた
め、共晶ハンダなどの低融点ハンダを利用して行う方が
好ましい。The BGA package is made into a laminated module
The spherical metal of the external terminal located on the lower surface is used as a connection member. That is, the spherical metal on the lower surface of the circuit board of the BGA package on the upper side is connected to the electrode on the upper surface of the circuit board of the BGA package on the lower side, and electrical connection and mechanical connection are performed. This connection may be achieved by partial melting when the spherical metal is made of solder, but using a low melting point solder such as eutectic solder to maintain the spherical shape of the external terminals. It is more preferable to do this.
【００２４】本発明によれば、抵抗、コンデンサといっ
た受動部品を搭載するための回路基板を別に用意する。
この受動部品搭載用の回路基板は、半導体素子を搭載し
た回路基板と同種の材料（即ち、セラミックまたはプラ
スチック材料）から形成することが好ましい。According to the present invention, a circuit board for mounting passive components such as a resistor and a capacitor is separately prepared.
The circuit board for mounting the passive components is preferably formed of the same material as the circuit board on which the semiconductor element is mounted (that is, ceramic or plastic material).
【００２５】受動部品を搭載した回路基板は、積層半導
体装置モジュールのどの位置に配置することもできる
が、受動部品の搭載数が多い場合には、最上段に配置す
ることが有利である。２段目以下では、回路基板の周辺
部は上下の基板の接続用に利用され、搭載用のスペース
は中央部に限られるが、最上段であると受動部品の搭載
用スペースをより広く確保できるため、２段目以下の場
合よりも多数の受動部品を搭載できる。なお、２段目以
下に配置する場合などで、１層だけでは受動部品の搭載
スペースが確保できない時には、受動部品搭載用の回路
基板を２段以上に増やしてもよい。その場合、２段以上
の受動部品搭載用の回路基板は隣接させる必要はなく、
任意の段に配置することができる。The circuit board on which the passive components are mounted can be arranged at any position of the laminated semiconductor device module. However, if the number of passive components mounted is large, it is advantageous to arrange the circuit board at the top. In the second and lower stages, the peripheral portion of the circuit board is used for connecting the upper and lower substrates, and the mounting space is limited to the central portion, but the uppermost stage can secure a wider space for mounting the passive components. Therefore, more passive components can be mounted than in the second and lower stages. When the mounting space for the passive components cannot be ensured by only one layer, for example, when the passive components are mounted in the second or lower stage, the number of circuit boards for mounting the passive components may be increased to two or more. In that case, the circuit board for mounting two or more passive components does not need to be adjacent,
They can be arranged at any stage.
【００２６】回路基板に搭載する受動部品は、チップ部
品、即ち、リード線やピンを持たず、球状金属または金
属バンプもしくはパッド等により接続されるチップ化さ
れた部品とすることが好ましい。チップ部品は、一般に
小型であり、かつ表面実装により簡便に実装できるから
である。特に、２段目以下に配置される回路基板に受動
部品を搭載する場合には、部品高さに制約があるので、
チップ部品とする必要がある。The passive component mounted on the circuit board is preferably a chip component, that is, a chip component having no lead wires or pins and connected by a spherical metal or metal bump or pad. This is because chip components are generally small and can be easily mounted by surface mounting. In particular, when passive components are mounted on the circuit board arranged in the second stage or lower, the height of the components is limited,
It must be a chip component.
【００２７】一般にマザー基板に多数搭載される受動部
品は、バイパスコンデンサや信号波形矯正用の終端抵抗
等が多い。これらは、半導体素子近傍に配置すること
で、ノイズ低減という所期の効果が向上することが知ら
れている。従って、本発明に従ってモジュール内部の回
路基板に搭載する受動部品としては、バイパスコンデン
サおよび／または終端抵抗を含むことが好ましい。ただ
し、搭載する受動部品には特に制限はないので、これら
以外の機能を果たす、ノイズフィルタ、インダクア等の
受動部品をそれらだけで、或いは上記のバイパスコンデ
ンサや終端抵抗と一緒に搭載してもよい。モジュールの
内部に受動部品を搭載することで、半導体素子との距離
が短くなり、バイパスコンデンサや終端抵抗によるノイ
ズ除去効果も大きくなる。In general, a large number of passive components mounted on a motherboard often include a bypass capacitor and a terminating resistor for correcting a signal waveform. It is known that by arranging them near the semiconductor element, the expected effect of noise reduction is improved. Therefore, the passive components mounted on the circuit board inside the module according to the present invention preferably include a bypass capacitor and / or a terminating resistor. However, the passive components to be mounted are not particularly limited, and passive components such as a noise filter and an inductor that perform other functions may be mounted by themselves or together with the bypass capacitor and the terminating resistor. . By mounting passive components inside the module, the distance from the semiconductor element is shortened, and the noise removal effect by the bypass capacitor and the terminating resistor is increased.
【００２８】さらに、モジュール内部の専用の回路基板
にこれら受動部品を搭載することにより、マザー基板に
おける受動部品用のスペースが不要になるので、マザー
基板を小型化することが可能になり、低コスト化に寄与
するとともに、実装密度をさらに向上させることができ
る。Further, by mounting these passive components on a dedicated circuit board inside the module, the space for the passive components on the mother substrate is not required, so that the mother substrate can be reduced in size and the cost can be reduced. And the mounting density can be further improved.
【００２９】[0029]
【実施例】以下、図面を参照して本発明を説明する。図
２(a) 〜(d) は、本発明の積層半導体装置モジュールの
各種の態様の断面を示す説明図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIGS. 2A to 2D are explanatory views showing cross sections of various embodiments of the laminated semiconductor device module of the present invention.
【００３０】図中、１は半導体素子Ａを搭載した回路基
板、２はバイパスコンデンサや終端抵抗といった複数の
チップ部品（受動部品）Ｂを搭載した回路基板、３はマ
ザー基板である。各回路基板は下面に球状金属からなる
接続部材４を備え、この接続部材によりその下の回路基
板またはマザー基板と接続されている。In the figure, 1 is a circuit board on which a semiconductor element A is mounted, 2 is a circuit board on which a plurality of chip components (passive components) B such as bypass capacitors and terminating resistors are mounted, and 3 is a mother board. Each circuit board has a connection member 4 made of spherical metal on the lower surface, and is connected to a circuit board or a mother board thereunder by this connection member.
【００３１】図示例では、簡略化のために、半導体素子
を搭載した回路基板１は１または２段しか示していない
が、その段数は特に制限されず、例えば、４段またはそ
れ以上であってもよい。また、半導体素子は各回路基板
に１つずつしか搭載されていないが、場合によっては２
以上の半導体素子を回路基板に搭載することも可能であ
る。さらに、図示例では、半導体素子を搭載した回路基
板１にはチップ部品を搭載していないが、搭載するスペ
ースがあれば、チップ部品用の回路基板２に搭載しきれ
ないチップ部品を、半導体素子用の回路基板１に搭載す
ることも、もちろん可能である。In the illustrated example, for simplicity, only one or two stages of the circuit board 1 on which the semiconductor elements are mounted are shown, but the number of stages is not particularly limited. For example, four or more stages are provided. Is also good. Although only one semiconductor element is mounted on each circuit board, in some cases, two
The above semiconductor elements can be mounted on a circuit board. Further, in the illustrated example, the chip component is not mounted on the circuit board 1 on which the semiconductor element is mounted. However, if there is a space for mounting the chip component, the chip component that cannot be mounted on the circuit board 2 for the chip component is replaced with the semiconductor element. Of course, it is also possible to mount it on the circuit board 1 for use.
【００３２】図２(a) 〜(c) は、半導体素子を搭載した
回路基板（即ち、半導体装置）１を２段積層したモジュ
ールを示し、チップ部品を搭載した回路基板２は、図２
(a)では最上段に、図２(b) では中段に、図２(c) では
最下段にそれぞれ配置されている。このように、チップ
部品を搭載した回路基板２はどの段に配置することもで
きるが、図２(a) に示すように最上段に配置することが
好ましい。この場合であると、チップ部品に接続させる
ための電極をなるべく最上段回路基板の外周部から確保
することによってチップ部品を搭載する面積を広く確保
でき、チップ部品の搭載数を増大させることができるか
らである。FIGS. 2A to 2C show a module in which a circuit board (ie, a semiconductor device) 1 on which semiconductor elements are mounted is stacked in two stages, and a circuit board 2 on which chip components are mounted is shown in FIG.
In FIG. 2A, it is arranged at the top, in FIG. 2B, at the middle, and in FIG. 2C, at the bottom. As described above, the circuit board 2 on which the chip components are mounted can be arranged at any stage, but is preferably arranged at the uppermost stage as shown in FIG. In this case, it is possible to secure a large area for mounting the chip component by securing an electrode to be connected to the chip component as much as possible from the outer peripheral portion of the uppermost circuit board, thereby increasing the number of mounted chip components. Because.
【００３３】図２(d) は、半導体素子を搭載した回路基
板１が１段だけで、その上にチップ部品を搭載した回路
基板２を積層したモジュールを示す。この場合も、回路
基板１と２の積層順序を逆にしてもよい。例えば、回路
基板１が２以上の半導体素子を搭載したマルチチップタ
イプのものである場合には、この回路基板を上段にし、
下段にチップ部品を搭載した回路基板を配置する方がよ
い場合もある。FIG. 2D shows a module in which a circuit board 1 on which a semiconductor element is mounted is only one stage, and a circuit board 2 on which chip components are mounted is stacked thereon. Also in this case, the stacking order of the circuit boards 1 and 2 may be reversed. For example, when the circuit board 1 is of a multi-chip type having two or more semiconductor elements mounted thereon,
In some cases, it is better to arrange a circuit board on which chip components are mounted in the lower stage.
【００３４】各回路基板１、２の材料は選ばないが、マ
ザー基板３と同種の絶縁材料であることが、信頼性の観
点からは望ましい。マザー基板３は通常は樹脂質のプリ
ント基板であるので、回路基板１、２の材料も同様に樹
脂系のものが好ましいことになる。或いは、半導体素子
を搭載した回路基板１がセラミック基板である場合に
は、それに合わせてチップ部品を搭載する回路基板２も
セラミック基板とすることもできる。その場合には、最
下段の回路基板とマザー基板との間に、接続を強化する
手段（例えば、両基板間に樹脂を充填）を付加すること
が好ましい。Although the material of each of the circuit boards 1 and 2 is not limited, it is desirable from the viewpoint of reliability that the same insulating material as that of the mother board 3 is used. Since the mother board 3 is usually a printed board made of resin, the material of the circuit boards 1 and 2 is preferably made of resin. Alternatively, when the circuit board 1 on which the semiconductor elements are mounted is a ceramic substrate, the circuit board 2 on which the chip components are mounted can also be a ceramic substrate. In that case, it is preferable to add a means for strengthening the connection (for example, filling a resin between the two substrates) between the lowermost circuit substrate and the mother substrate.
【００３５】回路基板１において、半導体素子の搭載方
法は特に制限されない。例えば、フリップチップといっ
た表面実装型の方法と、リードフレーム等のワイヤボン
ディングが必要な方法のいずれでもよい。また、半導体
素子は、基板の上面と内部のいずれに搭載することもで
きる。The method for mounting the semiconductor elements on the circuit board 1 is not particularly limited. For example, either a surface mounting type method such as a flip chip or a method requiring wire bonding such as a lead frame may be used. Further, the semiconductor element can be mounted on either the upper surface or the inside of the substrate.
【００３６】[0036]
【発明の効果】従来例の積層半導体装置モジュールは、
半導体素子を搭載した回路基板１だけを積層するため、
回路基板にスペースの余裕があれば、一部の受動部品は
積層半導体装置モジュール内に配置することができるも
のの、特に受動部品の数が多い場合には、その全部をモ
ジュール内に配置することはできなかった。即ち、半導
体素子は積層できるものの、受動部品の多くは積層でき
ないため、マザー基板には受動部品を搭載するためのス
ペースが必要であり、それほど実装密度が向上しない。
また、マザー基板に搭載された受動部品と半導体素子の
距離が遠くなるため、ノイズ低減効果も十分ではなく、
近年の高速動作に対応できない。The laminated semiconductor device module of the prior art is
Since only the circuit board 1 on which the semiconductor element is mounted is laminated,
If there is enough space on the circuit board, some passive components can be placed in the stacked semiconductor device module.However, especially when the number of passive components is large, it is not possible to place all of them in the module. could not. That is, although semiconductor elements can be stacked, most of the passive components cannot be stacked. Therefore, a space for mounting the passive components is required on the mother substrate, and the mounting density is not so improved.
In addition, since the distance between the passive component mounted on the motherboard and the semiconductor element is long, the noise reduction effect is not sufficient,
It cannot respond to recent high-speed operations.
【００３７】これに対し、本発明によれば、従来はマザ
ー基板上に配置されていた受動部品の少なくとも一部、
場合によっては全部を、積層半導体装置モジュール内に
配置することができる。そのため、マザー基板に必要な
受動部品搭載用のスペースが大幅に減り、マザー基板を
小型化することができるので、半導体素子の実装密度が
著しく向上する。On the other hand, according to the present invention, at least a part of the passive components conventionally arranged on the motherboard,
In some cases, all of them can be arranged in the stacked semiconductor device module. Therefore, the space required for mounting passive components on the motherboard is greatly reduced, and the size of the motherboard can be reduced, so that the mounting density of the semiconductor elements can be significantly improved.
【００３８】本発明では、受動部品の搭載用に回路基板
が余分に必要になるが、通常のマザー基板が４〜６層の
多層基板であることから、同程度の多層基板にしても高
コストとはならない。むしろ、マザー基板が著しく小型
化できるので、トータルコストはかえって低減できる。According to the present invention, an extra circuit board is required for mounting passive components. However, since a normal mother board is a multilayer board having four to six layers, even a multilayer board of the same degree is expensive. Does not. Rather, the total cost can be reduced since the mother substrate can be significantly reduced in size.
【００３９】さらに、ノイズ低減用の受動部品を、従来
のマザー基板に搭載する場合より半導体素子の近くに配
置することができ、半導体素子間の信号ラインが長くな
らないため、ノイズ低減効果が高い。そのため、近年の
高速動作要求にも十分応えることができる、ノイズの少
ない、高性能で信頼性の高い積層半導体装置モジュール
にすることができる。Further, the passive components for noise reduction can be arranged closer to the semiconductor elements than when mounted on a conventional mother board, and the signal line between the semiconductor elements does not become long, so that the noise reduction effect is high. Therefore, a high-performance and highly reliable laminated semiconductor device module with little noise that can sufficiently meet the recent demand for high-speed operation can be obtained.
【図１】マザー基板上での従来の受動部品の配置を平面
図で示す説明図である。FIG. 1 is an explanatory view showing an arrangement of conventional passive components on a mother board in a plan view.
【図２】本発明に係る積層半導体装置モジュールの各種
態様を断面図で示す説明図である。FIG. 2 is an explanatory view showing, in cross-sectional views, various aspects of the laminated semiconductor device module according to the present invention.
１、２：回路基板 ３：マザー基板 Ａ：半導体素子 Ｂ：受動部品（チップ部品） 1, 2: circuit board 3: mother board A: semiconductor element B: passive component (chip component)
Claims (1)
し、下面に球状金属接続部材を備えた１または２以上の
回路基板と、(b) 上面に複数の受動部品を搭載し、下面
に球状金属接続部材を備えた少なくとも１つの回路基板
とを、該球状金属接続部材で基板間を接続して積層して
なる積層半導体装置モジュール。(A) one or two or more circuit boards each having a semiconductor element mounted on the upper surface or inside thereof and a spherical metal connecting member on the lower surface; and (b) mounting a plurality of passive components on the upper surface, and And a circuit board provided with a spherical metal connecting member, and connecting the substrates by the spherical metal connecting member to form a laminated semiconductor device module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10063111A JPH11260999A (en) | 1998-03-13 | 1998-03-13 | Laminated semiconductor device module with reduced noise |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10063111A JPH11260999A (en) | 1998-03-13 | 1998-03-13 | Laminated semiconductor device module with reduced noise |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11260999A true JPH11260999A (en) | 1999-09-24 |
Family
ID=13219865
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10063111A Pending JPH11260999A (en) | 1998-03-13 | 1998-03-13 | Laminated semiconductor device module with reduced noise |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11260999A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020073648A (en) * | 2001-03-15 | 2002-09-28 | 주식회사 글로텍 | Package having passive element |
| JP2003526221A (en) * | 2000-03-03 | 2003-09-02 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Printed circuit board assembly with improved bypass decoupling for BGA packages |
| US6943430B2 (en) | 2002-07-19 | 2005-09-13 | Samsung Electronics Co., Ltd | Semiconductor wafer having electrically connected passive device chips, passive devices and semiconductor package using the same |
| KR100712549B1 (en) | 2006-01-31 | 2007-05-02 | 삼성전자주식회사 | Multi stack package with package lid |
| US7282791B2 (en) | 2004-07-09 | 2007-10-16 | Elpida Memory, Inc. | Stacked semiconductor device and semiconductor memory module |
| US7371607B2 (en) | 2003-05-02 | 2008-05-13 | Seiko Epson Corporation | Method of manufacturing semiconductor device and method of manufacturing electronic device |
| JP2008147628A (en) * | 2006-12-07 | 2008-06-26 | Stats Chippac Inc | Multilayer semiconductor package |
| JP2009252893A (en) * | 2008-04-03 | 2009-10-29 | Elpida Memory Inc | Semiconductor device |
| US8017448B2 (en) | 2008-04-18 | 2011-09-13 | Oki Semiconductor Co., Ltd. | Method for manufacturing semiconductor device |
| US8659151B2 (en) | 2007-06-22 | 2014-02-25 | Lapis Semiconductor Co., Ltd. | Semiconductor device and manufacturing method thereof |
| EP3255669A1 (en) * | 2016-06-08 | 2017-12-13 | Samsung Electronics Co., Ltd | Semiconductor assembly with package on package structure and electronic device including the same |
-
1998
- 1998-03-13 JP JP10063111A patent/JPH11260999A/en active Pending
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003526221A (en) * | 2000-03-03 | 2003-09-02 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Printed circuit board assembly with improved bypass decoupling for BGA packages |
| KR20020073648A (en) * | 2001-03-15 | 2002-09-28 | 주식회사 글로텍 | Package having passive element |
| US6943430B2 (en) | 2002-07-19 | 2005-09-13 | Samsung Electronics Co., Ltd | Semiconductor wafer having electrically connected passive device chips, passive devices and semiconductor package using the same |
| US7211469B2 (en) | 2002-07-19 | 2007-05-01 | Samsung Electronics Co., Ltd. | Semiconductor wafer having electrically connected passive device chips, passive devices and semiconductor package using the same |
| US7371607B2 (en) | 2003-05-02 | 2008-05-13 | Seiko Epson Corporation | Method of manufacturing semiconductor device and method of manufacturing electronic device |
| US7282791B2 (en) | 2004-07-09 | 2007-10-16 | Elpida Memory, Inc. | Stacked semiconductor device and semiconductor memory module |
| KR100712549B1 (en) | 2006-01-31 | 2007-05-02 | 삼성전자주식회사 | Multi stack package with package lid |
| JP2008147628A (en) * | 2006-12-07 | 2008-06-26 | Stats Chippac Inc | Multilayer semiconductor package |
| US8659151B2 (en) | 2007-06-22 | 2014-02-25 | Lapis Semiconductor Co., Ltd. | Semiconductor device and manufacturing method thereof |
| JP2009252893A (en) * | 2008-04-03 | 2009-10-29 | Elpida Memory Inc | Semiconductor device |
| US8017448B2 (en) | 2008-04-18 | 2011-09-13 | Oki Semiconductor Co., Ltd. | Method for manufacturing semiconductor device |
| EP3255669A1 (en) * | 2016-06-08 | 2017-12-13 | Samsung Electronics Co., Ltd | Semiconductor assembly with package on package structure and electronic device including the same |
| CN107482002A (en) * | 2016-06-08 | 2017-12-15 | 三星电子株式会社 | Semiconductor subassembly with package-on-package structure and the electronic equipment including the component |
| US10529676B2 (en) | 2016-06-08 | 2020-01-07 | Samsung Electronics Co., Ltd. | Semiconductor assembly with package on package structure and electronic device including the same |
| US11037890B2 (en) | 2016-06-08 | 2021-06-15 | Samsung Electronics Co., Ltd. | Semiconductor assembly with package on package structure and electronic device including the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7968991B2 (en) | Stacked package module and board having exposed ends | |
| JP3916854B2 (en) | Wiring board, semiconductor device, and package stack semiconductor device | |
| US6888240B2 (en) | High performance, low cost microelectronic circuit package with interposer | |
| US6621156B2 (en) | Semiconductor device having stacked multi chip module structure | |
| JP5222509B2 (en) | Semiconductor device | |
| JP2894071B2 (en) | Semiconductor device | |
| US5834832A (en) | Packing structure of semiconductor packages | |
| US6628527B2 (en) | Mounting structure for electronic parts and manufacturing method thereof | |
| US6313998B1 (en) | Circuit board assembly having a three dimensional array of integrated circuit packages | |
| JPH0234184B2 (en) | ||
| JPH07263625A (en) | Perpendicular integrated circuit chip laminated body with discrete chip carrier formed of dielectric tape | |
| JP2001035960A (en) | Semiconductor device and manufacture thereof | |
| JP2004228323A (en) | Semiconductor apparatus | |
| JPH11260999A (en) | Laminated semiconductor device module with reduced noise | |
| US20080230886A1 (en) | Stacked package module | |
| JP3413147B2 (en) | Multi-line grid array package | |
| JP3450477B2 (en) | Semiconductor device and manufacturing method thereof | |
| KR100546359B1 (en) | Semiconductor chip package and stacked module thereof having functional part and packaging part arranged sideways on one plane | |
| KR100713898B1 (en) | Stack package | |
| JP4083376B2 (en) | Semiconductor module | |
| KR20010073345A (en) | Stack package | |
| JP2005150771A (en) | Wiring board, semiconductor device, and package stacks semiconductor device | |
| US20090039493A1 (en) | Packaging substrate and application thereof | |
| KR100650049B1 (en) | Assembly-stacked package using multichip module | |
| JP2002270723A (en) | Semiconductor device, semiconductor chip, and mounting board |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20010710 |