JP2003347722A - Multilayer electronic parts mounting substrate and its fabricating method - Google Patents

Multilayer electronic parts mounting substrate and its fabricating method

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Publication number
JP2003347722A
JP2003347722A JP2002149660A JP2002149660A JP2003347722A JP 2003347722 A JP2003347722 A JP 2003347722A JP 2002149660 A JP2002149660 A JP 2002149660A JP 2002149660 A JP2002149660 A JP 2002149660A JP 2003347722 A JP2003347722 A JP 2003347722A
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Japan
Prior art keywords
substrate
substrates
resin
electronic component
method
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
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JP2002149660A
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Japanese (ja)
Inventor
Terumasa Ninomaru
輝正 二の丸
Original Assignee
Ibiden Co Ltd
イビデン株式会社
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Application filed by Ibiden Co Ltd, イビデン株式会社 filed Critical Ibiden Co Ltd
Priority to JP2002149660A priority Critical patent/JP2003347722A/en
Publication of JP2003347722A publication Critical patent/JP2003347722A/en
Application status is Pending legal-status Critical

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15192Resurf arrangement of the internal vias
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer electronic parts mounting substrate with high reliability in electrical connection between the substrates. <P>SOLUTION: A fabricating method of a multilayer electronic parts mounting substrate having at least two substrates 11 to 15 and arranged with the electronic parts 3 between both of the substrates, comprises a process where a plurality of the substrates 11 to 15 are prepared in which conductor circuits 4 are provided on insulation substrates 5, and a process where substrates 12 to 15 are mounted with the electronic parts 3 to be arranged between the substrates 12 to 15 when laminating the substrates. A plurality of the substrates 11 to 15 are laminated and then the electronic parts are arranged between the substrates 11 to 15 and each of conductor circuits 4 provided on the substrates 11 to 15 that are adjacent to one another are mutually connected electrically by solder balls 2 serving as connecting terminals and thereafter the gaps between the substrates are sealed with resin 6. <P>COPYRIGHT: (C)2004,JPO

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【技術分野】本発明は,基板間に電子部品を収容した多層電子部品搭載用基板及びその製造方法に関する。 TECHNICAL FIELD The present invention relates to a multilayer electronic component carrier and a manufacturing method thereof accommodating the electronic component between the substrates.

【0002】 [0002]

【従来技術】従来,多層電子部品搭載用基板としては, Description of the Prior Art Conventionally, as a multi-layer electronic component mounting board,
図10に示すごとく,上基板91と下基板92との間に電子部品93を搭載し樹脂94により封止したものがある。 As shown in FIG. 10, there is sealed by mounting a resin 94 an electronic component 93 between the upper substrate 91 and lower substrate 92. 上基板91と下基板92との間は半田ボール95により電気的に接続されている。 Between the upper substrate 91 and lower substrate 92 are electrically connected by solder balls 95. 電子部品93はフリップチップ型であり,下基板92の上に搭載されている。 Electronic components 93 are flip-chip type is mounted on the lower substrate 92.

【0003】上記多層電子部品搭載用基板を製造するに当っては,図11に示すごとく,絶縁基板905に導体回路900を形成し,これを上基板91とする。 [0003] hitting the manufacturing the multilayer electronic component carrier is, as shown in FIG. 11, to form a conductor circuit 900 on the insulating substrate 905, which is the upper substrate 91.

【0004】また,他の絶縁基板906に導体回路90 [0004] The conductor circuits 90 on the other insulating substrate 906
2を形成し,これを下基板92とする。 2 was formed, which is the lower substrate 92. 上面の導体回路902には,電子部品93を半田904にて接合する。 The conductive circuit 902 of the upper surface, bonding the electronic component 93 by soldering 904.
また,基板周縁部の導体回路902には,半田ボール9 Moreover, the conductor circuit 902 on the peripheral edge of the substrate, the solder balls 9
5を接合する。 5 joining. 次いで,電子部品93及び上面の導体回路902を樹脂94により封止する。 Then, the electronic component 93 and the upper surface of the conductor circuit 902 is sealed with a resin 94.

【0005】その後,下基板92の上に上基板91を積層し,加熱圧着する。 [0005] Then, the upper substrate 91 laminated on the lower substrate 92, thermocompression bonding. このとき,下基板92に接合した半田ボール95を,上基板91の導体回路900に接合する。 At this time, the solder balls 95 joined to the lower substrate 92 is bonded to the conductor circuit 900 of the upper substrate 91. 以上により,図10に示す多層電子部品搭載用基板96を得る。 Thus, to obtain a multi-layer electronic component carrier 96 shown in FIG. 10.

【0006】 [0006]

【解決しようとする課題】しかしながら,上記従来の多層電子部品搭載用基板の製造方法においては,上基板9 [SUMMARY] However, in the method of manufacturing the conventional multilayer electronic component carrier, the upper substrate 9
1と下基板92とを積層する前に,電子部品93を樹脂94により封止している。 Before laminating the 1 and the lower substrate 92, and the electronic component 93 is sealed with a resin 94. このため,下基板92の半田ボール95が,樹脂94により被覆されてしまい,上基板91の導体回路900と接合しない場合があり,上基板91と下基板92との間に電気接続不良が発生する場合がある。 Therefore, the solder balls 95 of the lower substrate 92, will be coated with a resin 94, may not bonded to the conductor circuit 900 of the upper substrate 91, the electrical connection failure is caused between the upper substrate 91 and lower substrate 92 there is a case to be.

【0007】本発明はかかる従来の問題点に鑑み,基板間の電気的接続信頼性が高い多層電子部品搭載用基板及びその製造方法を提供しようとするものである。 [0007] The present invention has been made in view such conventional problems, it is intended to provide an electrical connection reliable multilayer electronic component carrier and a manufacturing method thereof between substrates.

【0008】 [0008]

【課題の解決手段】第一発明は,少なくとも2つの基板からなり,両基板間に電子部品を配置している多層電子部品搭載用基板の製造方法において,絶縁基板に導体回路を設けてなる基板を複数準備する工程と,上記基板に,積層時に基板間に配置されるべき電子部品を搭載する工程とを行い,次いで,上記複数の基板を積層して, [Challenge A first invention consists of at least two substrates, the method for manufacturing a multilayer electronic component carrier are arranged electronic components between the two substrates, the substrate comprising a conductor circuit provided on an insulating substrate a step of multiple preparations, the above substrate, subjected to a step of mounting the electronic components to be placed between the substrates during lamination, then stacking the plurality of substrates,
上記電子部品を上記基板間に配置するとともに,隣合う上記基板に設けた上記導体回路同士の間を接続端子により電気的に接続し,その後上記基板間の間隙を樹脂により封止することを特徴とする多層電子部品搭載基板の製造方法である(請求項1)。 Characterized in that the sealing with, and electrically connecting between the conductor circuits to each other provided on the adjacent said substrate by connecting terminals, by subsequent resin gaps between the substrates the electronic part placed between the substrate a method for manufacturing a multilayer electronic component mounting board according to (claim 1).

【0009】第一発明において,複数の基板を積層し隣合う基板の導体回路同士を接続端子により電気的に接続した後に,基板間の間隙を樹脂封止している。 [0009] In the first invention, after electrically connecting the connection terminal of the conductor circuits to each other of the substrate adjacent laminating a plurality of substrates, and the gap between the substrates sealed with resin. このため,隣合う基板の導体回路は,樹脂により邪魔されることなく,接続端子によって確実に接続する。 Thus, the conductor circuit of the adjacent board, without being obstructed by the resin, securely connected by a connecting pin.

【0010】第二の発明は,導体回路を有する基板を少なくとも2つ積層して,両基板間に電子部品を配置している多層電子部品搭載用基板であって,隣合う上記基板に設けた上記導体回路同士の間は接続端子により電気的に接続されており,上記基板間の間隙は樹脂により封止されており,かつ上記基板間の間隔の高さは10~15 [0010] The second invention is to provide at least two laminated substrate having a conductor circuit and a multilayer electronic component carrier are arranged electronic components between the two substrates, provided adjacent the substrate during between the conductor circuits are electrically connected by the connection terminal, the gap between the substrates is sealed with a resin, and a height of 10 to 15 the spacing between the substrate
0μmであることを特徴とする多層電子部品搭載基板である(請求項6)。 It is a multi-layer electronic part mounting board, which is a 0 .mu.m (claim 6).

【0011】第二発明において,基板間の間隙が上記のごとく狭いため,この間に樹脂を封止するときに,毛細管現象が生じ易い。 [0011] In the second invention, since the gap between the substrates is narrow as described above, when sealing the resin during this time, it tends to cause capillarity. このため,樹脂封止を容易に行うことができる。 Therefore, it is possible to perform the resin sealing easily.

【0012】第三の発明は,導体回路を有する基板を少なくとも2つ積層して,両基板間に電子部品を配置している多層電子部品搭載用基板であって,隣合う上記基板に設けた上記導体回路同士の間は接続端子により電気的に接続されており,上記基板間の間隙は樹脂により封止されており,かつ上記電子部品の上記基板表面からの突出量は150μm以下であることを特徴とする多層電子部品搭載基板である(請求項7)。 [0012] The third invention is to provide at least two laminated substrate having a conductor circuit and a multilayer electronic component carrier are arranged electronic components between the two substrates, provided adjacent the substrate during between the conductor circuits are electrically connected by the connection terminal, that the gap between the substrates is sealed with a resin, and the projecting amount from the substrate surface of the electronic component is 150μm or less it is a multi-layer electronic part mounting board according to claim (claim 7).

【0013】第三発明において,電子部品の基板表面からの突出量は上記のごとく低いため,基板間の間隙を狭くして,樹脂の毛細管現象を生じさせることができる。 [0013] In the third invention, the protruding amount from the substrate surface of the electronic component is lower as described above, by narrowing the gap between the substrates, it is possible to produce a capillary action of the resin.
したがって,両基板間に樹脂を容易に封止することができる。 Thus, the resin can be easily sealed between the substrates.

【0014】 [0014]

【発明の実施の形態】第一発明において,基板に設けられている導体回路は,接続端子を接合するための接合部位を有する。 DETAILED DESCRIPTION OF THE INVENTION In a first invention, a conductor circuit provided on the substrate has a junction for joining the connection terminal. これらの接合部位は,パッド,スルーホールなどである。 These bonding sites, the pad, or the like through holes.

【0015】接続端子は,半田ボール,ピンなどがある。 [0015] The connection terminals, solder balls, pins and the like. たとえば,接続端子が半田ボールの場合には,導体回路の接合部位はパッドである。 For example, if the connection terminals are solder balls, junction conductive circuit is pad. 接続端子がピンの場合には,上記接合部位はスルーホール内壁である。 If connection terminal pins, the bonding site is a through-hole inner walls.

【0016】積層時に隣合う基板は,少なくとも一方に,基板間に収容されるべき電子部品を搭載している。 The substrate adjacent during lamination is at least one, are equipped with electronic components to be accommodated between the substrates.
基板間の間隙を樹脂により封止するにあたっては,両基板間に配置された電子部品及び導体回路が外気から遮断されるように,両基板間に樹脂を充填する。 Gap when the sealed with resin between the substrates, as electronic components and conductor circuit arranged between the two substrates is blocked from the outside air, the resin is filled between the two substrates. 例えば,両基板間の間隙全体に樹脂を充填するか,基板間の間隙の全周縁部を樹脂により囲む。 For example, the resin is filled into the entire gap between the substrates, enclosing the resin entire periphery of the gap between the substrates. 後者の基板間の間隙の全周縁部を樹脂により囲む場合,少なくとも上記接続端子が埋まる程度まで樹脂を充填することが好ましい。 If the entire periphery portion of the gap between the latter substrate surrounded by a resin, it is preferable to fill the resin to such an extent that at least the connection terminal is filled. 樹脂による囲み幅が薄いと,湿気遮断効果が薄れ,電子部品を湿気から保護することができなくなるおそれがあるからである。 When enclosing width by the resin is thin, faded moisture blocking effect, because the electronic components which may be made impossible to protect from moisture.

【0017】基板間を封止する樹脂は,ポリオレフィン系などの熱可塑性樹脂,アクリレート系などのUV硬化樹脂などがある。 The resin for sealing between the substrates, and the like thermoplastic resins, UV curable resins such acrylate-based and polyolefin-based. この中,密着信頼性等の観点から,エポキシ樹脂が好ましい。 This medium, from the viewpoint of adhesion reliability, epoxy resins are preferred.

【0018】上記基板間の間隙を樹脂により封止するにあたっては,積層された上記基板を樹脂浴面に対して垂直方向に立てて,上記基板間の開口端部側を,溶融状態にある樹脂浴に浸すことが好ましい(請求項2)。 [0018] When the gap between the substrates is sealed with resin, to stand in the vertical direction stacked above the substrate to the resin bath surface, an open end side between the substrate, a resin in a molten state it is preferred to immerse the bath (claim 2). これにより,両基板に形成された導体回路が樹脂により汚染されることなく,両基板間の間隙に樹脂を封止することができる。 Thus, without the conductor circuit formed on both substrates from being contaminated by resin, it is possible to seal the resin into the gap between the substrates. この場合,上記開口端部は,樹脂浴の浴面に接する程度か又は浴面から最大1.0mmまで浸る程度にすることが好ましい。 In this case, the open end is preferably to the extent that soak the degree or bath surface in contact with the bath surface of the resin bath to a maximum 1.0 mm. 1.0mmを超えて浸すと,基板に形成した導体回路が樹脂浴により汚れるおそれがあるからである。 Immersion beyond 1.0 mm, because a conductor circuit formed on the substrate is likely to dirty the resin bath.

【0019】積層時に隣合う上記基板間の間隔の高さは10~150μmであることが好ましい(請求項3)。 The height of the spacing between adjacent the substrate during the lamination is preferably 10 ~ 150 [mu] m (claim 3).
両基板間の間隙が上記のごとく狭い場合には,溶融した樹脂が毛細管現象により両基板間の間隙に自ずと進入する。 If the gap between the substrates is narrow as described above, the molten resin is naturally enters the gap between the substrates by capillarity. このため,両基板間への樹脂の封止が容易である。 Therefore, it is easy sealing of the resin to between the two substrates.
基板間の間隙が10μm未満の場合には,のおそれがあり,150μmを超える場合には毛細管現象が起こりにくくなるおそれがある。 If the gap between the substrates is less than 10μm, there is a risk of, when it exceeds 150μm, there is a possibility that hardly occur capillary phenomenon.

【0020】搭載された上記電子部品の上記基板表面からの突出量は150μm以下であることが好ましい(請求項4)。 The protruding amount from the on-board the electronic components of the substrate surface is preferably 150μm or less (claim 4). 電子部品の基板表面からの突出量は上記のごとく低い。 Projecting amount from the substrate surface of the electronic part is low as described above. このため,基板間の間隙を150μm以下と狭くすることができ,上記請求項3の発明と同様に,溶融した樹脂が毛細管現象によって自ずと両基板間に進入させることができる。 Therefore, the gap between the substrates can be narrowed and 150μm or less, in the same manner as the invention of the third aspect, it is possible to molten resin to enter between the naturally both substrates by a capillary phenomenon. したがって,両基板間への樹脂の封止が容易である。 Therefore, it is easy sealing of the resin to between the two substrates. ここで,電子部品の基板表面からの突出量とは,基板の表面から測った電子部品の高さをいう。 Here, the projecting amount from the substrate surface of the electronic component, refers to the height of the electronic component measured from the surface of the substrate. したがって,電子部品が基板の凹部内に搭載されている場合には,電子部品の全高さから,凹部内に埋まっている部分の高さが除かれる。 Therefore, when the electronic component is mounted in a recess in the substrate, the total height of the electronic component, the height of the portion is buried in the recess is removed. 電子部品の基板表面からの突出量が150μmを超える場合には毛細管現象が起こりにくくなるおそれがある。 If the protruding amount from the substrate surface of the electronic component is more than 150μm, there is a possibility that hardly occur capillary phenomenon.

【0021】隣合う上記基板に設けた上記導体回路同士の間を接続端子により電気的に接続するにあたっては, [0021] When electrically connects the adjacent between the conductor circuits to each other provided on the substrate connecting terminal,
上記基板の上記導体回路と上記接続端子との間を,半田を用いて接着することが好ましい(請求項5)。 Between the conductor circuit and the connection terminal of the substrate, it is preferable to bond with solder (claim 5). 接続端子は,積層時に相対する導体回路の接合部位との間に多少の位置ずれがあっても,溶融半田の表面張力によって基板を移動させて接続端子と導体回路とを正しい位置に移動させるセルフアライメント効果が生じる。 Connection terminal moves to some even misalignment, the correct position of the connection terminal and the conductor circuit by moving the substrate by the surface tension of the molten solder between the junction of the opposed conductive circuit when stacked self alignment effect occurs. とくに, In particular,
本発明においては,接続端子を導体回路と接合するときには,両者間に封止樹脂が介在していない。 In the present invention, when bonded to the conductor circuit connection terminals, the sealing resin is not interposed therebetween. このため, For this reason,
樹脂により邪魔されず,上記セルフアライメント効果が生じ易い。 Undisturbed by the resin is likely the self-alignment effect occurs. したがって,基板間の位置合わせが容易である。 Therefore, it is easy to align between substrates.

【0022】第二発明の多層電子部品搭載用基板は,上記第一発明の請求項3の発明を行うことにより得られる。 The multilayer electronic component carrier of the second invention is obtained by carrying out the invention of claim 3 of the first invention. 第三発明の多層電子部品搭載用基板は,上記第一発明の請求項4の発明を行うことにより得られる。 Multilayer electronic component carrier of the third invention is obtained by carrying out the invention of claim 4 of the first invention.

【0023】 [0023]

【実施例】(実施例1)本発明の実施形態に係る多層電子部品搭載用基板及びその製造方法について,図1〜図6を用いて説明する。 For EXAMPLES (Example 1) a multilayer electronic component carrier and a manufacturing method thereof according to embodiments of the present invention will be described with reference to FIGS. 本例の多層電子部品搭載用基板は,図1に示すごとく,5つの基板11〜15からなり,これらの基板の間には,電子部品3を配置している。 Multilayer electronic component carrier according to this embodiment, as shown in FIG. 1, consists of five substrates 11-15, between these substrates are arranged electronic components 3. 最上段の基板11は,導体回路4を有するが,その上面及び下面のいずれにも電子部品を搭載していない。 Uppermost substrate 11 has the conductor circuit 4, not equipped with an electronic component to any of its upper and lower surfaces.
最上段の下側に積層されている基板12〜15は,導体回路4を有するとともに,その上面に電子部品3を搭載している。 Substrate 12-15 which are stacked on the lower side of the uppermost, which has a conductor circuit 4, and mounting an electronic component 3 on its upper surface.

【0024】基板11〜15は,電子部品3を収容するように積層されている。 The substrate 11 to 15, are stacked so as to accommodate the electronic components 3. 各基板11〜15に設けられた導体回路4は,接続端子としての半田ボール2により電気的に接続されている。 Conductor circuits 4 provided in each substrate 11 to 15 are electrically connected by solder balls 2 as a connection terminal. 各基板11〜15の間の間隙の高さHは200μmであり,この間隙は樹脂6により封止されている。 The height H of the gap between the substrates 11 to 15 is 200 [mu] m, the gap is sealed by the resin 6. 電子部品3の基板表面からの突出量tは50μmである。 Protruding amount t of the substrate surface of the electronic component 3 is 50 [mu] m.

【0025】図1,図2に示すごとく,最上段の基板1 [0025] As shown in FIGS. 1 and 2, the uppermost substrate 1
1には,パッド41,43,導体充填穴42及び図示しない配線部からなる導体回路4が設けられている。 The 1, pads 41 and 43, conductor circuit 4 is provided comprising a conductive fill hole 42 and wiring (not shown) section. 基板11の下面に形成したパッド41は,半田ボール2と接合する接合部位である。 Pads 41 formed on the lower surface of the substrate 11 is a junction to be bonded to the solder ball 2. 基板11の上面に形成したパッド43は,外部のマザーボードに接合するための部位である。 Pads 43 formed on the upper surface of the substrate 11 is a portion for joining to an external mother board. 上面のパッド43と下面のパッド41との間は, Between the pad 43 and the lower surface of the pad 41 of the upper surface,
導体充填穴42及び配線部を通じて電気的に接続されている。 Are electrically connected through conductors fill hole 42 and the wiring portion.

【0026】図1,図3に示すごとく,最上段の基板1 [0026] As shown in FIGS. 1 and 3, the uppermost substrate 1
1の下側に積層されている基板12〜15にも,導体回路4が設けられている。 To the substrate 12 to 15 are stacked on the bottom of a conductor circuit 4 is provided. この導体回路4は,基板12〜 The conductor circuit 4, the substrate 12
15の上面に設けたパッド44,配線部45及びボンディングパッド46と,基板12〜15の下面に設けたパッド48と,パッド44,48間を電気的に接続する導体充填穴47とからなる。 Pads 44 provided on the upper surface 15, the wiring portion 45 and the bonding pad 46, the pad 48 provided on the lower surface of the substrate 12 to 15, a conductor filled holes 47. for electrically connecting the pads 44 and 48. ボンディングパッド46には,半田23により電子部品3が接合されている。 The bonding pad 46, the electronic components 3 are joined by solder 23. この電子部品3は,フリップチップである。 The electronic component 3 is a flip chip.

【0027】次に,本例の多層電子部品搭載用基板の製造方法について説明する。 Next, a method for manufacturing a multilayer electronic component carrier of the present embodiment. 最上段の基板11を作製するにあたって,図4に示すごとく,絶縁基板5に,穴あけ,めっき,露光,エッチングなどの手法を用いて,導体充填穴,パッド及び配線部等からなる導体回路4を形成する。 In making the uppermost substrate 11, as shown in FIG. 4, the insulating substrate 5, drilling, plating, exposure, using a technique such as etching, the conductor circuit 4 made of a conductor filled holes, pads and wiring section or the like Form. 絶縁基板5は,ガラスエポキシ樹脂基板である。 Insulating substrate 5, a glass epoxy resin substrate. 基板11の下側の基板12〜15を作製するにあたって,絶縁基板5に上記と同様の手法にて導体回路4を形成する。 In making the lower substrate 12 to 15 of the substrate 11, forming a conductor circuit 4 at the same above technique insulating substrate 5. 図4,図3に示すごとく,基板12〜15の上面には,導体回路4の一部であるパッド44に,半田ボール2を接合する。 4, as shown in FIG. 3, on the upper surface of the substrate 12 to 15, the pad 44 is a part of the conductor circuit 4, to join the solder ball 2.

【0028】次いで,得られた基板11〜15を,上から下へ順に積層する。 [0028] Then, the substrate 11 to 15 obtained, are laminated in this order from top to bottom. 基板12〜15の上面に接合した半田ボール2は,その上の基板11〜14の下面に形成されているパッド41,48に当接させる。 The solder balls 2 which is bonded to the upper surface of the substrate 12 to 15, is brought into contact with the pad 41, 48 formed on the lower surface of the substrate 11 to 14 thereon. 図5に示すごとく,この状態で加熱して半田ボール2を一部溶融させて,当接しているパッド41,48に接合させる。 As shown in FIG. 5, the solder ball 2 is heated in this state by partially melted, thereby joining the abutting pads 41 and 48. これにより,隣合う基板の導体回路間が半田ボール2により電気的に接続される。 Accordingly, conductor circuits of the adjacent substrate are electrically connected by a solder ball 2.

【0029】次いで,図6に示すごとく,半田ボール2 [0029] Then, as shown in FIG. 6, solder balls 2
にて接合された基板11〜15を,樹脂浴61の浴面6 The substrate 11 to 15 which is joined with, the bath surface 6 of the resin bath 61
0に対して垂直方向に立てて,基板間の間隙開口端部1 Upright perpendicularly to 0, the gap opening end 1 between the substrates
0側を,溶融状態にある樹脂浴61に浸す。 0 side is immersed in a resin bath 61 in a molten state. このとき, At this time,
間隙開口端部10は,樹脂浴61の浴面60から1.0 Gap open end 10, from the bath surface 60 of the resin bath 61 1.0
mm浸る程度にする。 To the extent that mm soak. この状態でしばらく放置すると, If for some time is left in this state,
毛細管現象により樹脂浴61の樹脂が間隙開口端部10 Resin in the resin bath 61 is a gap open end by a capillary phenomenon 10
から内部へ進入し,やがて基板間の間隙全体に充満する。 It enters into the interior from the, soon to fill the entire gap between the substrates. これにより,基板11〜15間が樹脂6により封止される。 Thus, while the substrate 11-15 is sealed by the resin 6. 以上により,図1に示す多層電子部品搭載用基板が得られる。 Thus, the multilayer electronic component mounting substrate shown in FIG. 1 is obtained.

【0030】本例において,各基板11〜15に設けた導体回路4を半田ボール2により接続した後に,基板間を樹脂6により封止しているため,導体回路4は,樹脂により邪魔されることなく,半田ボール2によって確実に接続する。 In the present embodiment, after the connection of the conductor circuit 4 provided on the substrates 11 to 15 by the solder ball 2, since the sealing between the substrates by the resin 6, the conductor circuit 4 is disturbed by the resin it not, be reliably connected by solder balls 2. 基板11〜15間の間隙の高さTが上記のごとく狭いため,この間隙に樹脂6を封止するときに, Since the height T of the gap between the substrates 11-15 is narrow as described above, when the sealing resin 6 into the gap,
毛細管現象が生じ易い。 It tends to occur capillary phenomenon. このため,樹脂封止を容易に行うことができる。 Therefore, it is possible to perform the resin sealing easily.

【0031】各基板11〜15の間は半田ボール2により接続している。 [0031] between each of the substrates 11 to 15 are connected by solder balls 2. 半田ボール2は,積層加熱時に一部が溶融して相手側のパッド41,48と接合する。 The solder ball 2 is partially during lamination heat is bonded to the other side of the pad 41 and 48 melt. このため,半田ボール2は,相手側のパッド41,48との間に多少の位置ずれがあっても溶融半田の表面張力によって正しい位置に移動するセルフアライメント効果を起こす。 Therefore, the solder balls 2, even if there is some misalignment between the mating pads 41, 48 causing the self-alignment effect of moving to the correct position by the surface tension of the molten solder. また,半田ボール接合時には,封止用の樹脂が未だ介在していないことから,樹脂により基板の移動が邪魔されず,セルフアライメント効果が生じ易い。 Further, when the solder ball bonding, since the sealing resin has not yet intervening movement of the substrate is not obstructed by the resin, it tends to cause self-alignment effect. したがって,基板間の位置合わせが容易である。 Therefore, it is easy to align between substrates. また,基板間を樹脂により封止するときには,基板11〜15を浴面6 Further, when the inter-substrate is sealed with resin, the bath surface of the substrate 11-15 6
0に垂直に立てて間隙開口端部10のみを僅かに樹脂浴61の中に浸している。 Bathing only gap open end 10 in a slightly resin bath 61 to stand vertically to 0. このため,導体回路4を汚すことなく,樹脂封止作業を行うことができる。 Therefore, without contaminating the conductor circuit 4, it is possible to perform the resin sealing operation.

【0032】なお,本例においては,半田ボール2を予め接合する部分は,図4に示すごとく電子部品3を搭載した側の基板表面であるが,電子部品を搭載していない側の表面であってもよい。 [0032] In the present example, the portion of bonding the solder ball 2 in advance, but a side surface of the substrate mounted with electronic components 3 as shown in FIG. 4, the surface of the side not mounting an electronic component it may be. また,各基板11〜15間の間隙には,下側の基板にのみ搭載された電子部品3を配置しているが,上側及び下側の両基板に搭載された電子部品を配置してもよい。 Further, the gap between the substrates 11 to 15, but are arranged the electronic components 3 mounted only on the lower side of the substrate, it is arranged electronic components mounted on the substrates of the upper and lower good.

【0033】(実施例2)本例は,基板間の樹脂封止を行うにあたって,図7に示すごとく,半田ボール2にて接続された基板11〜15の全体を,樹脂浴61の中に浸している。 [0033] (Example 2) This example, when performing resin sealing between the substrates, as shown in FIG. 7, the entire substrate 11 to 15 which are connected by the solder balls 2, in the resin bath 61 bathing. 基板11〜15は,浴面60に対して僅かに傾斜させて配置し,この状態で静かに樹脂浴61の中に浸す。 Substrate 11-15, and arranged to be slightly inclined with respect to the bath surface 60, gently immersed in the resin bath 61 in this state. すると,基板間に残っている空気が間隙開口端部10から逃げ,そこへ樹脂が充填される。 Then, air remaining between the substrates escapes from the gap open end 10, a resin is filled thereto. なお,予め外形の一辺に切断エリアを設けておき,上記樹脂の充填後に,上記切断エリアを削除することにより,基板表面の導体回路が樹脂により汚染されることを防止することができる。 Incidentally, may be provided a cutting area on one side of the advance profile, after filling of the resin by removing the cutting area, it is possible to prevent the conductor circuit of the substrate surface is contaminated by the resin. 本例においても,基板間の樹脂封止,及び基板間の位置合わせを容易に行うことができる。 In this embodiment, the resin sealing between the substrates, and alignment between the substrates can be easily performed.

【0034】(実施例3)本例は,図8,図9に示すごとく,基板11〜15間の周縁部71のみに樹脂6を充填し,中央部72は樹脂を充填しない例である。 [0034] (Example 3) This example is 8, as shown in FIG. 9, the resin 6 filled only the peripheral portion 71 between the substrates 11-15, center portion 72 is an example not filled with a resin. 樹脂6 Resin 6
は,図8,図9に示すごとく,上記基板12〜15に配設された半田ボール2が埋まる程度まで充填する。 It is 8, as shown in FIG. 9, to fill to the extent that the solder balls 2 disposed on the substrate 12-15 is filled. 本例においては,上記のごとく,基板間の周縁部71に樹脂6を充填している。 In the present embodiment, as described above, filling the resin 6 in the peripheral portion 71 between the substrates. このため,基板間の間隙全体に樹脂を充填した場合と同様に,周縁部71の樹脂により,湿気の侵入を抑制でき,中央部72に収容した電子部品3 Therefore, similarly to the case of filling the resin to the whole gap between the substrates, with a resin of the peripheral edge 71, can suppress penetration of moisture, the electronic component 3 accommodated in the central portion 72
を湿気から保護することができる。 It can be protected from moisture.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】実施例1の多層電子部品搭載用基板の断面図。 FIG. 1 is a cross-sectional view of a multilayer electronic component carrier of Example 1.

【図2】実施例1における,最上段の基板の平面図。 [Figure 2] in Example 1, a plan view of the top of the substrate.

【図3】実施例1における,最上段の基板以外の基板の平面図。 [Figure 3] of Example 1, a plan view of a substrate other than the uppermost substrate.

【図4】実施例1における,積層前の各基板の断面図。 In [4] Example 1, cross-sectional view of the substrate prior to lamination.

【図5】実施例1における,半田ボールにて接続された基板の断面図。 [5] in Example 1, cross-sectional view of a substrate which is connected by solder balls.

【図6】実施例1における,基板間の樹脂封止方法の説明図。 In [6] Example 1, illustration of the resin encapsulation method between the substrate.

【図7】実施例2における,基板間の樹脂封止方法の説明図。 [7] in the second embodiment, illustration of the resin encapsulation method between the substrate.

【図8】実施例3の多層電子部品搭載用基板の断面図。 Figure 8 is a cross-sectional view of a multilayer electronic component carrier of Example 3.

【図9】実施例3における,基板間の樹脂封止状態を示す説明図。 In [9] Example 3, explanatory view showing a resin sealing state between the substrates.

【図10】従来例の多層電子部品搭載用基板の断面図。 [10] Conventional Example sectional view of a multilayer electronic component carrier.

【図11】従来例における,多層電子部品搭載用基板の製造方法を示す説明図。 [11] in a conventional example, explanatory view showing a method for manufacturing a multilayer electronic component carrier.

【符号の説明】 DESCRIPTION OF SYMBOLS

11〜15. 11-15. . . 基板, 2. Board, 2. . . 半田ボール, 3. Solder balls, 3. . . 電子部品, 4. Electronic components, 4. . . 導体回路, 41,43,44,48. Conductor circuits, 41,43,44,48. . . パッド, 5. Pad, 5. . . 絶縁基板, 6. Insulating substrate, 6. . . 樹脂, resin,

フロントページの続き (51)Int.Cl. 7識別記号 FI テーマコート゛(参考) H05K 1/18 H05K 3/46 N 3/28 Q 3/46 H01L 25/08 Z Fターム(参考) 5E314 AA24 BB02 BB13 CC04 FF05 FF21 GG01 5E336 AA04 AA13 AA16 BB03 BB15 BC31 CC32 CC49 CC55 EE01 GG11 5E344 AA01 AA23 AA26 AA28 BB01 BB02 BB04 CC15 CD09 CD12 CD31 DD02 DD14 EE06 EE21 5E346 AA02 AA12 AA15 AA22 AA35 AA41 BB01 BB11 BB16 CC02 CC09 CC31 CC40 EE43 FF37 FF45 GG01 GG25 GG28 GG40 HH07 Of the front page Continued (51) Int.Cl. 7 identification mark FI theme Court Bu (Reference) H05K 1/18 H05K 3/46 N 3/28 Q 3/46 H01L 25/08 Z F -term (reference) 5E314 AA24 BB02 BB13 CC04 FF05 FF21 GG01 5E336 AA04 AA13 AA16 BB03 BB15 BC31 CC32 CC49 CC55 EE01 GG11 5E344 AA01 AA23 AA26 AA28 BB01 BB02 BB04 CC15 CD09 CD12 CD31 DD02 DD14 EE06 EE21 5E346 AA02 AA12 AA15 AA22 AA35 AA41 BB01 BB11 BB16 CC02 CC09 CC31 CC40 EE43 FF37 FF45 GG01 GG25 GG28 GG40 HH07

Claims (7)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 少なくとも2つの基板からなり,両基板間に電子部品を配置している多層電子部品搭載用基板の製造方法において,絶縁基板に導体回路を設けてなる基板を複数準備する工程と,上記基板に,積層時に基板間に配置されるべき電子部品を搭載する工程とを行い,次いで,上記複数の基板を積層して,上記電子部品を上記基板間に配置するとともに,隣合う上記基板に設けた上記導体回路同士の間を接続端子により電気的に接続し, 1. A consists of at least two substrates, the method for manufacturing a multilayer electronic component carrier are arranged electronic components between the substrates, a step for a plurality preparing a substrate formed by providing a conductor circuit on an insulating substrate , on the substrate, performs a step of mounting the electronic components to be placed between the substrates during lamination, then stacking the plurality of substrates, the electronic components as well as arranged between the substrate, adjacent the electrically connected by a connection terminal between the conductor circuits to each other provided on the substrate,
    その後上記基板間の間隙を樹脂により封止することを特徴とする多層電子部品搭載基板の製造方法。 Then a method for manufacturing a multilayer electronic component mounting board, characterized in that the gap between the substrates is sealed with a resin.
  2. 【請求項2】 請求項1において,上記基板間の間隙を樹脂により封止するにあたっては,積層された上記基板を樹脂浴面に対して垂直方向に立てて,上記基板間の開口端部側を,溶融状態にある樹脂浴に浸すことを特徴とする多層電子部品搭載基板の製造方法。 2. The method of claim 1, when sealed with resin a gap between said substrates, upright in the vertical direction stacked above the substrate to the resin bath surface, the open end portion side between the substrate the method of manufacturing a multilayer electronic component mounting board, characterized in that immersion in the resin bath in a molten state.
  3. 【請求項3】 請求項1において,積層時に隣合う上記基板間の間隔の高さは10~150μmであることを特徴とする多層電子部品搭載基板の製造方法。 3. The method of claim 1, a method for manufacturing a multilayer electronic component mounting substrate, wherein the height of the spacing between adjacent the substrate during the lamination is 10 ~ 150 [mu] m.
  4. 【請求項4】 請求項1または2において,搭載された上記電子部品の上記基板表面からの突出量は150μm 4. The method of claim 1 or 2, the protruding amount from the on-board the electronic components of the substrate surface 150μm
    以下であることを特徴とする多層電子部品搭載用基板の製造方法。 Method for manufacturing a multilayer electronic component carrier, wherein the or less.
  5. 【請求項5】 請求項1〜4のいずれか1項において, 5. A claim 1,
    隣合う上記基板に設けた上記導体回路同士の間を接続端子により電気的に接続するにあたっては,上記基板の上記導体回路と上記接続端子との間を,半田を用いて接着することを特徴とする多層電子部品搭載用基板の製造方法。 The order to electrically connect the adjacent connecting terminal between the conductor circuits to each other provided on the substrate, and characterized in that between the conductor circuit and the connection terminal of the substrate, bonding using solder a method for manufacturing a multilayer electronic component mounting substrate.
  6. 【請求項6】 導体回路を有する基板を少なくとも2つ積層して,両基板間に電子部品を配置している多層電子部品搭載用基板であって,隣合う上記基板に設けた上記導体回路同士の間は接続端子により電気的に接続されており,上記基板間の間隙は樹脂により封止されており, 6. At least two laminated substrate having a conductor circuit and a multilayer electronic component carrier are arranged electronic components between the substrates, the conductor circuits to each other provided on the adjacent said substrate between are electrically connected by the connection terminal, the gap between the substrates is sealed with a resin,
    かつ上記基板間の間隔の高さは10~150μmであることを特徴とする多層電子部品搭載基板。 And multi-layer electronic part mounting board, wherein the height of the spacing between the substrates is 10 ~ 150 [mu] m.
  7. 【請求項7】 導体回路を有する基板を少なくとも2つ積層して,両基板間に電子部品を配置している多層電子部品搭載用基板であって,隣合う上記基板に設けた上記導体回路同士の間は接続端子により電気的に接続されており,上記基板間の間隙は樹脂により封止されており, 7. At least two laminated substrate having a conductor circuit and a multilayer electronic component carrier are arranged electronic components between the substrates, the conductor circuits to each other provided on the adjacent said substrate between are electrically connected by the connection terminal, the gap between the substrates is sealed with a resin,
    かつ上記電子部品の上記基板表面からの突出量は150 And projection amount from the substrate surface of the electronic component 150
    μm以下であることを特徴とする多層電子部品搭載基板。 Multi-layer electronic part mounting board, wherein μm or less.
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