JPH10242328A - Circuit board, circuit module having the circuit board and electronic equipment having the circuit module - Google Patents

Circuit board, circuit module having the circuit board and electronic equipment having the circuit module

Info

Publication number
JPH10242328A
JPH10242328A JP4668197A JP4668197A JPH10242328A JP H10242328 A JPH10242328 A JP H10242328A JP 4668197 A JP4668197 A JP 4668197A JP 4668197 A JP4668197 A JP 4668197A JP H10242328 A JPH10242328 A JP H10242328A
Authority
JP
Japan
Prior art keywords
circuit board
solder
semiconductor element
pad
connection terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4668197A
Other languages
Japanese (ja)
Inventor
Itsukou Murakami
壱皇 村上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP4668197A priority Critical patent/JPH10242328A/en
Publication of JPH10242328A publication Critical patent/JPH10242328A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81191Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0284Details of three-dimensional rigid printed circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007Surface contacts, e.g. bumps

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a circuit module which reduces unsoldered zones when semiconductor devices are mounted on a circuit board. SOLUTION: The module comprises semiconductor devices 1 having connection terminals 2, 3 and a circuit board 11 having a surface for mounting the elements 1 and pads 12 to be soldered to the terminals 2, 3. The mounting surface of the board 11 has recesses 12 into which the terminals 2, 3 are entered when the elements are mounted. The recesses 12 have pads 13 coated with solder 14.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は回路基板、この回路
基板を有する回路モジュールおよびこの回路モジュール
を有する電子機器に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board, a circuit module having the circuit board, and an electronic device having the circuit module.

【0002】[0002]

【従来の技術】ポータブルコンピュータのような電子機
器において、半導体ベアチップを回路基板に実装するた
めに半導体ベアチップに設けた接続端子を回路基板に設
けたパッドに接合する方式として、はんだ接合方式があ
る。
2. Description of the Related Art In an electronic device such as a portable computer, there is a solder joining method as a method of joining a connection terminal provided on a semiconductor bare chip to a pad provided on a circuit board in order to mount the semiconductor bare chip on a circuit board.

【0003】このはんだ接合方式は、半導体ベアチップ
に設けたパッドにバンプを形成し(パッドとバンプで接
続端子を構成する。)、この半導体ベアチップの端子形
成面を回路基板におけるパッドを形成した半導体素子実
装面に向き合わせ、半導体ベアチップのバンプの先端を
回路基板のパッドに接触させ、パッドの面に塗布したは
んだを溶融してパッドおよびバンプに固着することによ
り、半導体ベアチップを回路基板に電気的に接続すると
ともに機械的に固定するものである。
In this solder bonding method, a bump is formed on a pad provided on a semiconductor bare chip (connection terminals are formed by the pad and the bump), and a terminal forming surface of the semiconductor bare chip is formed on a semiconductor element having a pad formed on a circuit board. By facing the mounting surface, the tip of the bump of the semiconductor bare chip is brought into contact with the pad of the circuit board, the solder applied to the pad surface is melted and fixed to the pad and the bump, and the semiconductor bare chip is electrically connected to the circuit board. It is connected and mechanically fixed.

【0004】[0004]

【発明が解決しようとする課題】しかし、このような半
導体ベアチップの接続端子をはんだ接合により回路基板
のパッドに接合する方式には、次に述べる理由により、
半導体ベアチップの接続端子と回路基板のパッドとがは
んだによって接合されない、いわゆる未はんだ不良が発
生することがある。
However, the method of joining the connection terminals of the semiconductor bare chip to the pads of the circuit board by soldering for the following reasons is as follows.
A so-called unsoldering defect, in which the connection terminal of the semiconductor bare chip and the pad of the circuit board are not joined by solder, may occur.

【0005】すなわち、はんだを加熱溶融してはんだ接
合を行なう際には、回路基板がはんだとともに加熱され
て半導体ベアチップから遠ざかる方向に反るように変形
することがある。この現象は特に回路基板の縁部に多く
発生する。このため、回路基板の反り部分に位置するパ
ッドが半導体ベアチップから離れる向きに移動して、パ
ッド上で溶融したはんだが半導体ベアチップから離れて
しまい未はんだ不良が発生することがる。
That is, when the solder is joined by heating and melting the solder, the circuit board is sometimes heated together with the solder and deformed so as to warp in a direction away from the semiconductor bare chip. This phenomenon often occurs particularly at the edge of the circuit board. For this reason, the pad located at the warped portion of the circuit board moves in a direction away from the semiconductor bare chip, and the solder melted on the pad separates from the semiconductor bare chip, and unsolder failure may occur.

【0006】さらに、半導体ベアチップに形成したAu
バンプの高さにばらつきがある場合また回路基板のパッ
ドに塗布したはんだの厚さにばらつきがある場合には、
はんだを溶融してAuバンプとパッドとを接合する時
に、Auバンプがパッド上で溶融したはんだに届かず未
はんだ不良が発生することがある。
Further, Au formed on a semiconductor bare chip
If the bump height varies, or if the thickness of the solder applied to the circuit board pads varies,
When the solder is melted to join the Au bump and the pad, the Au bump may not reach the melted solder on the pad and unsolder failure may occur.

【0007】本発明は前記事情に基づいてなされたもの
で、半導体素子をはんだ接合により実装する際における
未はんだ不良の発生を抑えて確実な実装が行なえる回路
基板を提供することを課題とする。
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a circuit board capable of performing reliable mounting while suppressing occurrence of unsoldering defects when mounting a semiconductor element by soldering. .

【0008】本発明は、半導体素子をはんだ接合により
回路基板に実装する際における未はんだ不良の発生を抑
えて確実な実装が行なえる回路モジュールを提供するこ
とを課題とする。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a circuit module in which unsoldering defects can be suppressed when a semiconductor element is mounted on a circuit board by soldering, thereby enabling reliable mounting.

【0009】本発明は、半導体素子をはんだ接合により
回路基板に実装する際における未はんだ不良の発生を抑
えて確実な実装が行なえる回路モジュールを備えた電子
機器を提供することを課題とする。
SUMMARY OF THE INVENTION It is an object of the present invention to provide an electronic device having a circuit module capable of performing reliable mounting while suppressing the occurrence of unsoldering defects when mounting a semiconductor element on a circuit board by soldering.

【0010】[0010]

【課題を解決するための手段】請求項1の発明の回路基
板は、半導体素子を実装する実装面を有し、この実装面
に前記半導体素子が有する接続端子とはんだ接合される
パッドが設けられた回路基板であって、前記実装面に
は、前記半導体素子を実装した時に前記接続端子が入り
込む凹部が形成され、この凹部にはんだが塗布された前
記パッドが設けられていることを特徴とする。
According to a first aspect of the present invention, there is provided a circuit board having a mounting surface on which a semiconductor element is mounted, and a pad which is soldered to a connection terminal of the semiconductor element. A circuit board, wherein the mounting surface is provided with a concave portion into which the connection terminal enters when the semiconductor element is mounted, and the concave portion is provided with the pad coated with solder. .

【0011】この発明の構成によれば、半導体素子の接
続端子が回路基板の凹部に入り込むので、回路基板が反
りを生じた場合における接続端子の変位分、接続端子の
高さが小さい場合における接続端子の高さ不足分および
回路基板のパッドに塗布したはんだの厚さが小さい場合
におけるはんだの厚さ不足分を凹部が吸収することによ
り、接続端子とパッドを凹部の内部ではんだ接合して未
はんだ不良の発生を抑えることができる。
According to the structure of the present invention, since the connection terminal of the semiconductor element enters the recess of the circuit board, the connection when the height of the connection terminal is small by the displacement of the connection terminal when the circuit board is warped. The recess absorbs the shortage of the terminal height and the shortage of the solder when the thickness of the solder applied to the pads of the circuit board is small, so that the connection terminal and the pad cannot be soldered inside the recess. The occurrence of solder failure can be suppressed.

【0012】請求項2の発明は、請求項1に記載の回路
基板において前記凹部は曲面を有することを特徴とす
る。この発明の構成によれば、回路基板に凹部を容易に
形成することができ、また凹部の内部にパッドを容易に
形成することができる。
According to a second aspect of the present invention, in the circuit board according to the first aspect, the concave portion has a curved surface. According to the configuration of the present invention, the concave portion can be easily formed on the circuit board, and the pad can be easily formed inside the concave portion.

【0013】請求項3の発明の回路モジュールは、接続
端子を有する半導体素子と、前記半導体素子を実装する
実装面を有し、この実装面に前記半導体素子が有する接
続端子とはんだ接合されるパッドが設けられた回路基板
とを具備し、前記回路基板の実装面には、前記半導体素
子を実装した時に前記接続端子が入り込む凹部が形成さ
れ、この凹部にはんだが塗布された前記パッドが設けら
れていることを特徴とする。
According to a third aspect of the present invention, there is provided a circuit module having a semiconductor element having a connection terminal, and a mounting surface for mounting the semiconductor element, and a pad which is soldered to the connection terminal of the semiconductor element on the mounting surface. Provided on the mounting surface of the circuit board, a recess in which the connection terminal enters when the semiconductor element is mounted is formed, and the pad coated with solder is provided in the recess. It is characterized by having.

【0014】この発明の構成によれば、半導体素子の接
続端子が回路基板の凹部に入り込むので、回路基板が反
りを生じた場合における接続端子の変位分、接続端子の
高さが小さい場合における接続端子の高さ不足分および
回路基板のパッドに塗布したはんだの厚さが小さい場合
におけるはんだの厚さ不足分を凹部が吸収し、接続端子
とパッドを凹部の内部ではんだ接合して、未はんだ不良
の発生を抑えることができる。
According to the structure of the present invention, since the connection terminal of the semiconductor element enters the recess of the circuit board, the connection when the height of the connection terminal is small by the displacement of the connection terminal when the circuit board is warped. The recess absorbs the insufficient terminal height and the insufficient solder thickness when the thickness of the solder applied to the circuit board pads is small. The occurrence of defects can be suppressed.

【0015】請求項4の発明は、請求項3に記載の回路
モジュールにおいて、前記半導体素子の接続端子はバン
プを有するものであることを特徴とする。この発明の構
成によれば、接続端子にバンプを用いた半導体素子を回
路基板に確実にはんだ接合することができる。
According to a fourth aspect of the present invention, in the circuit module according to the third aspect, the connection terminal of the semiconductor element has a bump. ADVANTAGE OF THE INVENTION According to the structure of this invention, the semiconductor element using the bump for the connection terminal can be reliably solder-joined to a circuit board.

【0016】請求項5の発明は、請求項3に記載の回路
モジュールにおいて、前記半導体素子の接続端子ははん
だボールを有するものであることを特徴とする。この発
明の構成によれば、接続端子にはんだボールを用いた半
導体素子を回路基板に確実にはんだ接合することができ
る。
According to a fifth aspect of the present invention, in the circuit module according to the third aspect, the connection terminal of the semiconductor element has a solder ball. According to the configuration of the present invention, the semiconductor element using the solder ball for the connection terminal can be securely soldered to the circuit board.

【0017】請求項6の発明は、請求項3に記載の回路
モジュールにおいて、前記半導体素子はベアチップであ
ることを特徴とする。この発明の構成によれば、半導体
ベアチップを回路基板に確実にはんだ接合により実装す
ることができる。
According to a sixth aspect of the present invention, in the circuit module according to the third aspect, the semiconductor element is a bare chip. According to the configuration of the present invention, the semiconductor bare chip can be securely mounted on the circuit board by soldering.

【0018】請求項7の発明の電子機器は、ハウジング
と、接続端子を有する半導体素子、前記半導体素子を実
装する実装面を有しこの実装面に前記半導体素子が有す
る接続端子とはんだ接合されるパッドが設けられた回路
基板を備え、前記ハウジングの内部に設けられた回路モ
ジュールとを具備し、前記回路基板の実装面には、前記
半導体素子を実装した時に前記接続端子が入り込む凹部
が形成され、この凹部にはんだが塗布された前記パッド
が設けられていることを特徴とする。
An electronic device according to a seventh aspect of the present invention has a housing, a semiconductor element having a connection terminal, and a mounting surface for mounting the semiconductor element, and the mounting surface is soldered to the connection terminal of the semiconductor element. A circuit board provided with a pad; and a circuit module provided inside the housing.The mounting surface of the circuit board has a recess in which the connection terminal enters when the semiconductor element is mounted. The recess is provided with the pad coated with solder.

【0019】この発明の構成によれば、半導体素子をは
んだ接合により回路基板に実装する際における未はんだ
不良の発生を抑えて確実な実装が行なえる回路モジュー
ルを備えた電子機器を得ることができる。
According to the structure of the present invention, it is possible to obtain an electronic apparatus having a circuit module capable of performing reliable mounting while suppressing the occurrence of unsoldering defects when mounting a semiconductor element on a circuit board by soldering. .

【0020】[0020]

【発明の実施の形態】本発明の第1の実施の形態につい
て図1ないし図3を参照して説明する。この実施の形態
は、ポータブルコンピュータやワードプロセッサのよう
な電子機器に設けた回路モジュールに適用したもので、
半導体素子の一例として半導体ベアチップを用いてい
る。図1ないし図3は電子機器のハウジングの内部に設
けた回路モジュールを示し、図1ははんだ接合する前の
半導体ベアチップと回路基板を示し、図2ははんだ接合
した半導体ベアチップと回路基板を示し、図3ははんだ
接合した半導体ベアチップと反りを生じた回路基板を示
している。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIGS. This embodiment is applied to a circuit module provided in an electronic device such as a portable computer or a word processor.
A semiconductor bare chip is used as an example of a semiconductor element. 1 to 3 show a circuit module provided inside a housing of an electronic device, FIG. 1 shows a semiconductor bare chip and a circuit board before soldering, FIG. 2 shows a semiconductor bare chip and a circuit board soldered, FIG. 3 shows a solder bare semiconductor bare chip and a warped circuit board.

【0021】図1ないし図3において31は電子機器の
ハウジングで、このハウジング1の内部に後述する回路
モジュールが設けられている。次に回路モジュールにつ
いて説明する。
In FIG. 1 to FIG. 3, reference numeral 31 denotes a housing of an electronic apparatus, and a circuit module to be described later is provided inside the housing 1. Next, the circuit module will be described.

【0022】図1ないし図3において1は半導体ベアチ
ップである。この半導体ベアチップ1は図5にも示すよ
うに例えば矩形をなすもので、回路基板11にはんだ接
合して実装する際に回路基板11の実装面11aと向き
合うことになる端子形成面1aには、例えばその周縁部
の全体に沿って複数のパッド2が間隔を存して並べて形
成してあり、これら各パッド2の表面には夫々金からな
るバンプ(以下Auバンプと称する。)3が形成されて
いる。パッド2とAuバンプ3とで接続端子が構成され
ている。
1 to 3, reference numeral 1 denotes a semiconductor bare chip. As shown in FIG. 5, the semiconductor bare chip 1 has a rectangular shape, for example, and has a terminal forming surface 1a facing the mounting surface 11a of the circuit board 11 when soldered and mounted on the circuit board 11. For example, a plurality of pads 2 are formed at intervals along the entire periphery thereof, and a bump (hereinafter, referred to as an Au bump) 3 made of gold is formed on the surface of each pad 2. ing. The pad 2 and the Au bump 3 constitute a connection terminal.

【0023】11は絶縁材料からなる平坦な回路基板
で、この回路基板11に半導体ベアチップ1が実装され
る。回路基板11において半導体ベアチップ1を実装す
る実装面11aには、複数の凹部12が半導体ベアチッ
プ1に設けた複数のAuバンプ3(パッド2)に対応し
て矩形枠条に並んで形成されている。これら複数の凹部
12は半球面形状、すなわち曲面を有する形状をなすも
ので、各凹部12の内面には夫々導電性金属からなるパ
ッド13が形成されている。各凹部12の深さは、半導
体ベアチップ1をはんだ接合により回路基板11に実装
する際に半導体ベアチップ1のAuバンプ3が凹部12
の内部に入り込むことができる大きさである。各パッド
13の面には夫々はんだ14が所定の厚さで塗布されて
いる。
Reference numeral 11 denotes a flat circuit board made of an insulating material, on which the semiconductor bare chip 1 is mounted. On the mounting surface 11a on which the semiconductor bare chip 1 is mounted on the circuit board 11, a plurality of recesses 12 are formed in a rectangular frame corresponding to the plurality of Au bumps 3 (pads 2) provided on the semiconductor bare chip 1. . Each of the plurality of recesses 12 has a hemispherical shape, that is, a shape having a curved surface, and a pad 13 made of a conductive metal is formed on the inner surface of each recess 12. When the semiconductor bare chip 1 is mounted on the circuit board 11 by soldering, the Au bumps 3 of the semiconductor bare chip 1
It is large enough to get inside. Solder 14 is applied to the surface of each pad 13 at a predetermined thickness.

【0024】次に半導体ベアチップ1を回路基板11に
実装する構造について説明する。図2に示すように半導
体ベアチップ1は端子形成面1aを回路基板11の実装
面11aに向き合わせて配置され、端子形成面1aに設
けた複数のAuバンプ3が実装面11aに設けた対向す
る複数の凹部12の内部に入り込んでいる。そして、複
数の凹部12に夫々形成されたパッド13に塗布された
はんだ14が溶融され、各凹部12毎にその凹部12の
パッド13とこの凹部12に入り込んでいるAuバンプ
3に夫々固着している。すなわち、溶融したはんだ14
は凹部12の内部に溜められて凹部12に入り込んでい
るAuバンプ3に固着することになる。これにより半導
体ベアチップ1の各Auバンプ3は回路基板11の各パ
ッド13に機械的に接合されるとともに電気的に接続さ
れる。
Next, a structure for mounting the semiconductor bare chip 1 on the circuit board 11 will be described. As shown in FIG. 2, the semiconductor bare chip 1 is arranged with the terminal forming surface 1a facing the mounting surface 11a of the circuit board 11, and a plurality of Au bumps 3 provided on the terminal forming surface 1a are opposed to each other provided on the mounting surface 11a. It enters the inside of the plurality of recesses 12. Then, the solder 14 applied to the pads 13 respectively formed in the plurality of recesses 12 is melted and fixed to the pads 13 of the recesses 12 and the Au bumps 3 entering the recesses 12 for each of the recesses 12. I have. That is, the molten solder 14
Is fixed to the Au bump 3 that is stored inside the concave portion 12 and enters the concave portion 12. As a result, each Au bump 3 of the semiconductor bare chip 1 is mechanically joined and electrically connected to each pad 13 of the circuit board 11.

【0025】半導体ベアチップ1の端子形成面1aと回
路基板11の実装面11aとの間には絶縁樹脂15がモ
ールドされ、Auバンプ3とパッド13との各接合部を
夫々封止して機械的に補強するとともに外部に対して電
気的絶縁を図っている。
An insulating resin 15 is molded between the terminal forming surface 1a of the semiconductor bare chip 1 and the mounting surface 11a of the circuit board 11, and each of the joints between the Au bumps 3 and the pads 13 is sealed and mechanically. As well as electrical insulation from the outside.

【0026】半導体ベアチップ1を回路基板11に実装
する場合には、回路基板11に形成した各凹部12にパ
ッド13を形成するとともに各パッド13にはんだ14
を塗布し、さらに各はんだ14にワックスを塗布する。
半導体ベアチップ1では各パッド2にAuバンプ3をボ
ールボンダにより形成する。そして、半導体ベアチップ
1を回路基板11に配置し、次いではんだ14を溶融し
て各Auバンプ3と各パッド13をはんだ接合する。
When mounting the semiconductor bare chip 1 on the circuit board 11, pads 13 are formed in each recess 12 formed in the circuit board 11, and solder 14 is
Is applied, and wax is applied to each solder 14.
In the semiconductor bare chip 1, an Au bump 3 is formed on each pad 2 by a ball bonder. Then, the semiconductor bare chip 1 is arranged on the circuit board 11, and then the solder 14 is melted and the Au bumps 3 and the pads 13 are soldered.

【0027】この構造においては、回路基板11に形成
した凹部12が溶融したはんだ14を溜めるはんだ溜り
となり、凹部12に入り込んだ半導体ベアチップ1のA
uバンプ3を確実にはんだ14によりパッド13と接合
する。そして、回路基板11に形成した凹部12の内部
に半導体ベアチップ1のAuバンプ3が入り込むことに
より、凹部12の深さが、回路基板11の反り、Auバ
ンプ3の高さ不足およびはんだ14の厚さ不足によるA
uバンプ3とはんだ14との位置関係の変化を吸収し
て、Auバンプ3の先端が凹部12の内部に位置した状
態ではんだ14がAuバンプ3に固着することができ
る。
In this structure, the recess 12 formed in the circuit board 11 serves as a solder pool for storing the molten solder 14, and the A of the semiconductor bare chip 1 that has entered the recess 12 is formed.
The u bump 3 is securely bonded to the pad 13 by the solder 14. When the Au bumps 3 of the semiconductor bare chip 1 enter the recesses 12 formed in the circuit board 11, the depth of the recesses 12 is reduced due to the warpage of the circuit board 11, the insufficient height of the Au bumps 3, and the thickness of the solder 14. A due to lack of
By absorbing the change in the positional relationship between the u bump 3 and the solder 14, the solder 14 can be fixed to the Au bump 3 while the tip of the Au bump 3 is located inside the recess 12.

【0028】例えば、図3に示すように回路基板11が
はんだ接合時の熱により半導体ベアチップ1から遠ざか
る方向に反りを生じてパッド13がAuバンプ3から遠
ざかる方向に移動した場合には、回路基板11の凹部1
2がパッド13の移動分を吸収してAuバンプ3が凹部
12の内部から外れることがない。このため、Auバン
プ3は凹部12の内部に入り込んだままで凹部12の内
部に溜められた溶融したはんだ14に固着されて未はん
だ不良の発生を抑えることができる。
For example, as shown in FIG. 3, when the circuit board 11 is warped in the direction away from the semiconductor bare chip 1 due to heat at the time of soldering and the pad 13 moves in the direction away from the Au bump 3, 11 recesses 1
2 absorbs the movement of the pad 13 and the Au bump 3 does not come off from the inside of the recess 12. For this reason, the Au bump 3 is fixed to the molten solder 14 stored inside the concave portion 12 while entering the inside of the concave portion 12, so that occurrence of unsoldering defects can be suppressed.

【0029】また、Auバンプ3の高さが小さい場合に
おけるAuバンプ3の高さ不足分を凹部12が吸収し、
Auバンプ3とパッド11が凹部12の内部ではんだ接
合して未はんだ不良の発生を抑えることができる。さら
に、回路基板11のパッド13に塗布したはんだ14の
厚さが小さい場合におけるはんだの厚さ不足分を凹部1
2が吸収し、Auバンプ3とパッド13が凹部12の内
部ではんだ接合して未はんだ不良の発生を抑えることが
できる。
The recess 12 absorbs a shortage of the height of the Au bump 3 when the height of the Au bump 3 is small.
The Au bump 3 and the pad 11 are solder-bonded inside the concave portion 12, so that occurrence of unsoldering defects can be suppressed. Further, when the thickness of the solder 14 applied to the pads 13 of the circuit board 11 is small, the insufficient thickness of the solder
2 is absorbed, and the Au bump 3 and the pad 13 are solder-bonded inside the concave portion 12, so that occurrence of unsoldering defects can be suppressed.

【0030】また、回路基板11に凹部12は半球面形
状、すなわち曲面を有する形状であるから凹部12の形
成が容易であり、且つ凹部12の内部にパッド13を容
易に形成することもできる。
Further, since the concave portion 12 of the circuit board 11 has a hemispherical shape, that is, a shape having a curved surface, the concave portion 12 can be easily formed, and the pad 13 can be easily formed inside the concave portion 12.

【0031】この実施の形態では、接続端子としてバン
プを用いた形式の半導体ベアチップ1を回路基板11に
確実にはんだ接合により実装することができる。また、
この実施の形態では、半導体素子として半導体ベアチッ
プ1を用いて回路基板11に確実にはんだ接合により実
装した回路モジュールを得ることができる。
In this embodiment, the semiconductor bare chip 1 using bumps as connection terminals can be securely mounted on the circuit board 11 by soldering. Also,
In this embodiment, it is possible to obtain a circuit module securely mounted on the circuit board 11 by soldering using the semiconductor bare chip 1 as a semiconductor element.

【0032】図4は第2の実施の形態について示してい
る。この実施の形態は、半導体ベアチップ1に設ける接
続端子としてはんだボールを用いたものであり、図4に
おいて図2と同じ部分は同じ符号を付して示している。
図中21ははんだボールで、このはんだボール21は半
導体ベアチップ1に形成した各パッド2に夫々はんだ2
2を介して接合されている。また、はんだボール21の
表面もはんだ22に覆われている。そして、半導体ベア
チップ1を回路基板11に実装する際には、はんだボー
ル21が回路基板11の凹部12の内部に入り込み、は
んだ14および22の溶融によりはんだボール21とパ
ッド13とが接合される。このため、この実施の形態の
場合もはんだボール21の未はんだ不良の発生を抑える
ことができる。
FIG. 4 shows a second embodiment. In this embodiment, solder balls are used as connection terminals provided on a semiconductor bare chip 1. In FIG. 4, the same parts as those in FIG. 2 are denoted by the same reference numerals.
In the figure, reference numeral 21 denotes a solder ball. The solder ball 21 is attached to each pad 2 formed on the semiconductor bare chip 1 by a solder 2.
2 are joined. The surface of the solder ball 21 is also covered with the solder 22. When the semiconductor bare chip 1 is mounted on the circuit board 11, the solder balls 21 enter the recesses 12 of the circuit board 11, and the solder balls 21 and the pads 13 are joined by melting the solders 14 and 22. For this reason, in the case of this embodiment as well, the occurrence of unsoldering failure of the solder balls 21 can be suppressed.

【0033】そして、前述した各実施の形態の回路モジ
ュールをポータブルコンピュータやワードプロセッサの
ような電子機器のハウジング31の内部に装備すること
により、半導体素子をはんだ接合により回路基板に実装
する際における未はんだ不良の発生を抑えて確実な実装
が行なえる回路モジュールを備えた電子機器を得ること
ができる。
By mounting the circuit module of each of the above-described embodiments inside the housing 31 of an electronic device such as a portable computer or a word processor, the unsoldered soldering when the semiconductor element is mounted on the circuit board by soldering. It is possible to obtain an electronic device including a circuit module capable of performing reliable mounting while suppressing occurrence of defects.

【0034】なお、本発明は前述した実施の形態に限定
されず、種々変形して実施することができる。例えば、
半導体素子としては半導体ベアチップに限定されず、B
GA(ball grid array)などの他の形
式のものを用いることが可能である。また、半導体素子
に設ける接続端子も前述した実施の形態に限定されず、
他の形式のものを用いることが可能である。
The present invention is not limited to the above-described embodiment, but can be implemented with various modifications. For example,
The semiconductor element is not limited to a semiconductor bare chip.
Other types, such as GA (ball grid array), can be used. Also, the connection terminals provided on the semiconductor element are not limited to the above-described embodiment,
Other types can be used.

【0035】[0035]

【発明の効果】以上説明したように本発明によれば、半
導体素子の接続端子が回路基板の凹部に入り込むので、
回路基板が反りを生じた場合における接続端子の変位
分、接続端子の高さが小さい場合における接続端子の高
さ不足分および回路基板のパッドに塗布したはんだの厚
さが小さい場合におけるはんだの厚さ不足分を凹部が吸
収し、接続端子とパッドを凹部の内部ではんだ接合して
未はんだ不良の発生を抑えることができる。このため、
半導体素子をはんだ接合により確実に回路基板に接合で
きる。
As described above, according to the present invention, the connection terminals of the semiconductor element enter the recesses of the circuit board.
The displacement of the connection terminal when the circuit board is warped, the shortage of the connection terminal when the height of the connection terminal is small, and the thickness of the solder when the thickness of the solder applied to the pads of the circuit board is small The shortage is absorbed by the concave portion, and the connection terminal and the pad are solder-bonded inside the concave portion, so that occurrence of unsoldering defects can be suppressed. For this reason,
The semiconductor element can be securely joined to the circuit board by soldering.

【0036】従って、本発明によれば、半導体素子をは
んだ接合により実装する際における未はんだ不良の発生
を抑えて確実な実装が行なえる回路基板、この回路基板
を備えた回路モジュールおよびこの回路モジュールを備
えた電子機器を得ることができる。
Therefore, according to the present invention, a circuit board capable of suppressing the occurrence of unsoldering when mounting a semiconductor element by soldering, and performing reliable mounting, a circuit module having this circuit board, and this circuit module An electronic device provided with:

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施の形態にかかわる回路モジ
ュールを示す断面図。
FIG. 1 is a sectional view showing a circuit module according to a first embodiment of the present invention.

【図2】同実施の形態にかかわる回路モジュールを示す
断面図。
FIG. 2 is an exemplary sectional view showing a circuit module according to the embodiment;

【図3】同実施の形態にかかわる回路モジュールを示す
断面図。
FIG. 3 is an exemplary sectional view showing a circuit module according to the embodiment;

【図4】本発明の第2の実施の形態にかかわる回路モジ
ュールを示す断面図。
FIG. 4 is a sectional view showing a circuit module according to a second embodiment of the present invention.

【図5】半導体ベアチップを示す斜視図。FIG. 5 is a perspective view showing a semiconductor bare chip.

【符号の説明】[Explanation of symbols]

1…半導体ベアチップ(半導体素子)、 2…パッド(接続端子)、 3…Auバンプ(接続端子)、 11…回路基板、 12…凹部、 13…パッド、 14…はんだ、 31…電子機器のハウジング。 DESCRIPTION OF SYMBOLS 1 ... Semiconductor bare chip (semiconductor element), 2 ... Pad (connection terminal), 3 ... Au bump (connection terminal), 11 ... Circuit board, 12 ... recessed part, 13 ... Pad, 14 ... Solder, 31 ... Housing of electronic equipment.

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子を実装する実装面を有し、こ
の実装面に前記半導体素子が有する接続端子とはんだ接
合されるパッドが設けられた回路基板であって、前記実
装面には、前記半導体素子を実装した時に前記接続端子
が入り込む凹部が形成され、この凹部にはんだが塗布さ
れた前記パッドが設けられていることを徴とする回路基
板。
1. A circuit board having a mounting surface on which a semiconductor element is mounted, and a pad to be solder-bonded to a connection terminal of the semiconductor element on the mounting surface. A circuit board, characterized in that a concave portion into which the connection terminal enters when a semiconductor element is mounted is formed, and the pad coated with solder is provided in the concave portion.
【請求項2】 前記凹部は曲面を有するものであること
を特徴とする請求項1に記載の回路基板。
2. The circuit board according to claim 1, wherein the concave portion has a curved surface.
【請求項3】 接続端子を有する半導体素子と、 前記半導体素子を実装する実装面を有し、この実装面に
前記半導体素子が有する接続端子とはんだ接合されるパ
ッドが設けられた回路基板とを具備し、 前記回路基板の実装面には、前記半導体素子を実装した
時に前記接続端子が入り込む凹部が形成され、この凹部
にはんだが塗布された前記パッドが設けられていること
を特徴とする回路モジュール。
3. A semiconductor device having a connection terminal, and a circuit board having a mounting surface on which the semiconductor device is mounted, and a pad provided on the mounting surface with a solder terminal to the connection terminal of the semiconductor device. A circuit, wherein the mounting surface of the circuit board has a concave portion into which the connection terminal enters when the semiconductor element is mounted, and the concave portion is provided with the pad coated with solder. module.
【請求項4】 前記半導体素子の接続端子はバンプを有
するものであることを特徴とする請求項3に記載の回路
モジュール。
4. The circuit module according to claim 3, wherein the connection terminals of the semiconductor element have bumps.
【請求項5】 前記半導体素子の接続端子ははんだボー
ルを有するものであることを特徴とする請求項3に記載
の回路モジュール。
5. The circuit module according to claim 3, wherein the connection terminal of the semiconductor element has a solder ball.
【請求項6】 前記半導体素子はベアチップであること
を特徴とする請求項3に記載の回路モジュール。
6. The circuit module according to claim 3, wherein the semiconductor element is a bare chip.
【請求項7】 ハウジングと、 接続端子を有する半導体素子、前記半導体素子を実装す
る実装面を有しこの実装面に前記半導体素子が有する接
続端子とはんだ接合されるパッドが設けられた回路基板
を備え、前記ハウジングの内部に設けられた回路モジュ
ールとを具備し、 前記回路基板の実装面には、前記半導体素子を実装した
時に前記接続端子が入り込む凹部が形成され、この凹部
にはんだが塗布された前記パッドが設けられていること
を特徴とする電子機器。
7. A circuit board having a housing, a semiconductor element having connection terminals, and a mounting surface on which the semiconductor element is mounted, and a pad provided on the mounting surface to be soldered to the connection terminals of the semiconductor element. A circuit module provided inside the housing, and a concave portion in which the connection terminal enters when the semiconductor element is mounted is formed on a mounting surface of the circuit board, and solder is applied to the concave portion. An electronic device comprising the pad.
JP4668197A 1997-02-28 1997-02-28 Circuit board, circuit module having the circuit board and electronic equipment having the circuit module Pending JPH10242328A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4668197A JPH10242328A (en) 1997-02-28 1997-02-28 Circuit board, circuit module having the circuit board and electronic equipment having the circuit module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4668197A JPH10242328A (en) 1997-02-28 1997-02-28 Circuit board, circuit module having the circuit board and electronic equipment having the circuit module

Publications (1)

Publication Number Publication Date
JPH10242328A true JPH10242328A (en) 1998-09-11

Family

ID=12754132

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4668197A Pending JPH10242328A (en) 1997-02-28 1997-02-28 Circuit board, circuit module having the circuit board and electronic equipment having the circuit module

Country Status (1)

Country Link
JP (1) JPH10242328A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006310477A (en) * 2005-04-27 2006-11-09 Akita Denshi Systems:Kk Semiconductor device and manufacturing method therefor
JP2008021751A (en) * 2006-07-11 2008-01-31 National Institute Of Advanced Industrial & Technology Electrode, semiconductor chip, substrate, connecting structure of electrode for semiconductor chip, and semiconductor module and its manufacturing method
WO2012121373A1 (en) * 2011-03-09 2012-09-13 日立化成工業株式会社 Method for producing package substrate for mounting semiconductor element, package substrate for mounting semiconductor element, and semiconductor package
JP2012190894A (en) * 2011-03-09 2012-10-04 Hitachi Chem Co Ltd Package substrate for mounting semiconductor element, and semiconductor package
JP2021022699A (en) * 2019-07-30 2021-02-18 京セラ株式会社 Wiring substrate and electronic device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006310477A (en) * 2005-04-27 2006-11-09 Akita Denshi Systems:Kk Semiconductor device and manufacturing method therefor
JP2008021751A (en) * 2006-07-11 2008-01-31 National Institute Of Advanced Industrial & Technology Electrode, semiconductor chip, substrate, connecting structure of electrode for semiconductor chip, and semiconductor module and its manufacturing method
WO2012121373A1 (en) * 2011-03-09 2012-09-13 日立化成工業株式会社 Method for producing package substrate for mounting semiconductor element, package substrate for mounting semiconductor element, and semiconductor package
JP2012190894A (en) * 2011-03-09 2012-10-04 Hitachi Chem Co Ltd Package substrate for mounting semiconductor element, and semiconductor package
CN103443916A (en) * 2011-03-09 2013-12-11 日立化成株式会社 Method for producing package substrate for mounting semiconductor element, package substrate for mounting semiconductor element, and semiconductor package
TWI600097B (en) * 2011-03-09 2017-09-21 Hitachi Chemical Co Ltd Manufacturing method of package substrate for mounting semiconductor device, package substrate for mounting semiconductor device, and semiconductor package
JP2021022699A (en) * 2019-07-30 2021-02-18 京セラ株式会社 Wiring substrate and electronic device

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