JPH07297236A - Film and structure for mounting semiconductor element thereon - Google Patents
Film and structure for mounting semiconductor element thereonInfo
- Publication number
- JPH07297236A JPH07297236A JP8664694A JP8664694A JPH07297236A JP H07297236 A JPH07297236 A JP H07297236A JP 8664694 A JP8664694 A JP 8664694A JP 8664694 A JP8664694 A JP 8664694A JP H07297236 A JPH07297236 A JP H07297236A
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor element
- electrode
- mounting
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体素子を実装する絶
縁性フィルムの構成およびこれを利用した半導体素子の
実装構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of an insulating film for mounting a semiconductor element and a mounting structure of a semiconductor element using the insulating film.
【０００２】[0002]
【従来の技術】半導体素子の集積度の向上、および半導
体素子のサイズの増大に伴って、入出力端子数も増大し
ている。図７に示されるように、従来の半導体素子の実
装構造では、半導体素子の入出力端子数の増大に対応す
るため、半導体素子９の周囲四辺に入出力端子用リード
２４が設けられたＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃ
ｋａｇｅ）と呼ばれる構造が一般的に採用されている。
しかしながら、入出力端子数の増大に伴い端子間のリー
ドピッチが狭くなり、基板への高度な実装技術が要求さ
れてきている。2. Description of the Related Art The number of input / output terminals has been increasing with the increase in the degree of integration of semiconductor elements and the increase in size of semiconductor elements. As shown in FIG. 7, in the conventional semiconductor element mounting structure, in order to cope with an increase in the number of input / output terminals of the semiconductor element, QFP (input / output terminal leads 24 provided on the four sides around the semiconductor element 9) are provided. Quad Flat Pac
A structure called a cage) is generally adopted.
However, as the number of input / output terminals has increased, the lead pitch between the terminals has become narrower, and advanced mounting technology on the substrate has been required.
【０００３】このような半導体素子の入出力端子数の増
大に対応して入出力端子のリードピッチを緩和する構造
として、ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）と
呼ばれる実装構造がある。図６に示されるように、ＢＧ
Ａはプラスチック基板１８の両面に回路パターン２０お
よび２１が構成され、半導体９が搭載された面にある半
導体素子９の外部接続用電極とプラスチック基板１８に
設けられた回路パターン２０は細線の金線２２などによ
ってワイヤーボンディングされ電気的に接続されてい
る。プラスチック基板１８の他方の面には、２次元のア
レイ状に配置された球状半田８が回路パターン２１の先
端に設けられており、プラスチック基板１８に設けられ
たスルーホール１９により半導体素子９の外部接続用電
極と球状半田８が電気的に接続されている。さらに、Ｂ
ＧＡ構造の半導体装置と親基板とは、球状半田８を介し
て電気的に接続される。ＢＧＡ構造では、面内に球状半
田８が配列されるので、周囲に配置されるよりも面積を
大きくとることができ、従来の周囲四辺に入出力端子を
設けるＱＦＰのリードピッチに比較して、接続のピッチ
をかなり緩和することができる。As a structure for relaxing the lead pitch of the input / output terminals in response to the increase in the number of input / output terminals of the semiconductor element, there is a mounting structure called BGA (Ball Grid Array). As shown in FIG. 6, BG
In A, the circuit patterns 20 and 21 are formed on both sides of the plastic substrate 18, and the external connection electrode of the semiconductor element 9 on the surface on which the semiconductor 9 is mounted and the circuit pattern 20 provided on the plastic substrate 18 are thin gold wires. It is wire-bonded by 22 or the like and electrically connected. On the other surface of the plastic substrate 18, spherical solders 8 arranged in a two-dimensional array are provided at the tips of the circuit patterns 21, and the through holes 19 provided in the plastic substrate 18 prevent the semiconductor element 9 from outside. The connection electrode and the spherical solder 8 are electrically connected. Furthermore, B
The semiconductor device having the GA structure and the parent substrate are electrically connected via the spherical solder 8. In the BGA structure, since the spherical solder 8 is arranged in the plane, the area can be made larger than that in the surrounding area, and compared to the conventional lead pitch of the QFP in which the input / output terminals are provided on the four sides, The pitch of the connection can be considerably reduced.
【０００４】[0004]
【発明が解決しようとする課題】上述のようなＢＧＡ構
造の半導体装置では以下のような課題がある。The semiconductor device having the BGA structure as described above has the following problems.
【０００５】まず第１に、ＢＧＡ全体の寸法を小型化す
る場合、半導体素子の寸法に対してプラスチック基板へ
の電気的な接続を行うワイヤーボンディングの領域と裏
面に電気的に接続するためのスルーホールの領域が必要
であるため、小型化に限界がある。First, when the size of the entire BGA is reduced, the area of wire bonding for electrically connecting to the plastic substrate and the through for electrically connecting to the back surface are connected to the size of the semiconductor element. There is a limit to miniaturization because a hole area is required.
【０００６】また、ワイヤーボンディングが行えるピッ
チは現状２００μｍ程度であるため、端子数が多くなる
ほど半導体素子の周囲に設けられたワイヤーボンディン
グ領域が大きくなり、小型化の支障となる。Since the pitch at which wire bonding can be performed is currently about 200 μm, the larger the number of terminals, the larger the wire bonding area provided around the semiconductor element, which hinders miniaturization.
【０００７】さらに、裏面への電気的接続のスルーホー
ルは球状半田を構成した部分に設けることができないた
め周囲に配置することになり、小型化の支障となる。Further, since the through hole for electrical connection to the back surface cannot be provided in the portion which constitutes the spherical solder, it is arranged around the through hole, which hinders miniaturization.
【０００８】第２に、ＢＧＡの構造で構成した場合の電
気的な試験に工夫が必要なことである。すなわち、半導
体素子が実装された後に行う電気的試験は信頼性を確保
するために不可欠であるが、球状半田に対し変形を起こ
さないように接触し、かつ電気特性を図るには測定用の
ソケットに工夫が必要であり、狭ピッチになるほど測定
が困難になるという問題がある。球状半田を変形させた
場合、半田高さがばらつくことにより、半導体素子が実
装された基板が親基板に搭載された際に接続不良を起こ
すという問題がある。Secondly, it is necessary to devise an electric test when the BGA structure is used. That is, an electrical test performed after the semiconductor element is mounted is indispensable for ensuring reliability, but in order to make contact with spherical solder so as not to cause deformation and to improve electrical characteristics, a socket for measurement However, there is a problem that the measurement becomes difficult as the pitch becomes narrower. When the spherical solder is deformed, the height of the solder varies, which causes a problem that a connection failure occurs when the substrate on which the semiconductor element is mounted is mounted on the parent substrate.
【０００９】第３に、半導体素子から発熱する熱に対す
る放熱構造に関する課題である。ＢＧＡ構造では、ＢＧ
Ａを搭載する親基板に対して半導体素子の回路面が上向
きとなるため、半導体素子から発生する熱は半導体素子
の裏面から親基板へ放熱するしか手段がない。このた
め、電気的接続以外に放熱用の球状半田を設ける必要性
があり、また親基板の熱伝導率を考慮しなければなら
ず、十分な放熱をとることが困難であるという問題があ
る。Thirdly, there is a problem regarding the heat radiation structure for the heat generated from the semiconductor element. In the BGA structure, BG
Since the circuit surface of the semiconductor element faces upward with respect to the parent board on which A is mounted, there is no choice but to radiate the heat generated from the semiconductor element from the back surface of the semiconductor element to the parent board. Therefore, it is necessary to provide a spherical solder for heat dissipation in addition to the electrical connection, and the thermal conductivity of the parent board must be taken into consideration, so that there is a problem that it is difficult to take sufficient heat dissipation.
【００１０】本発明の半導体素子実装用フィルムと半導
体素子の実装構造は、上記欠点に鑑みて、小型で放熱に
優れ、しかも良好な接続が得られる半導体素子実装用フ
ィルムと半導体素子の実装構造を提供することにある。In view of the above-mentioned drawbacks, the semiconductor element mounting film and the semiconductor element mounting structure of the present invention have a semiconductor element mounting film and a semiconductor element mounting structure which are small in size, excellent in heat dissipation, and excellent in connection. To provide.
【００１１】[0011]
【課題を解決するための手段】上述の課題を解決するた
めに、本発明の半導体素子実装用フィルムは、第１の絶
縁性フィルムの片面の中央の領域に配列された半田から
なる複数の端子と、領域の周囲に形成された複数の第１
の電極と、第１の絶縁性フィルム上に形成され、端子と
電極を接続する第１のリード線と、端子が配列された面
とは反対側の面に形成され、第１の電極に接続される第
２の電極とを備えたことを特徴としている。そして、第
２の電極は第１の絶縁フィルムと端子が配列された面と
は反対側の面に配置された第２の絶縁性フィルムの表面
に形成され、第１の絶縁性フィルムと第２のフィルムの
間に配置された回路パターン層に形成された第２のリー
ド線によって接続されている。さらに、第１の電極及び
前記第２の電極は、第１の絶縁性フィルムと第２の絶縁
性フィルムに形成された孔に導電物質が挿入されて、第
２のリード線に接続されている。In order to solve the above problems, the film for mounting a semiconductor element of the present invention comprises a plurality of terminals made of solder arranged in the central region of one surface of the first insulating film. And a plurality of firsts formed around the area
And a first lead wire that is formed on the first insulating film and connects the terminal and the electrode, and is formed on the surface opposite to the surface on which the terminals are arranged and connected to the first electrode. And a second electrode to be formed. The second electrode is formed on the surface of the second insulating film arranged on the surface opposite to the surface on which the first insulating film and the terminals are arranged. Are connected by a second lead wire formed on the circuit pattern layer disposed between the films. Further, the first electrode and the second electrode are connected to the second lead wire by inserting a conductive material into the holes formed in the first insulating film and the second insulating film. .
【００１２】また、第１の電極及び第２の電極の少なく
ともどちらかは、回路パターン層に形成された電極であ
り、第１の絶縁性フィルム若しくは第２の絶縁性フィル
ムには電極が形成された位置に穴が形成されていること
を特徴としている。第２の電極は、表面に導電物質から
なる突起を有している。At least one of the first electrode and the second electrode is an electrode formed on the circuit pattern layer, and the electrode is formed on the first insulating film or the second insulating film. It is characterized in that holes are formed at different positions. The second electrode has a protrusion made of a conductive material on its surface.
【００１３】また、本発明の半導体素子の実装構造は、
上述の半導体素子実装用フィルムの第２の電極は、半導
体素子の表面に形成された電極用パッドに相対する位置
に形成され、第２の電極と電極パッドが接触して接続さ
れていることを特徴としている。さらに、端子の半田に
より基板の表面に形成された基板電極に固接続されて半
導体実装用フィルムが基板に固定され、半導体素子の電
極が形成された面とは反対の面に内壁面が接触される放
熱部材が、基板の表面に固着されている。The semiconductor element mounting structure of the present invention is
The second electrode of the semiconductor element mounting film described above is formed at a position facing the electrode pad formed on the surface of the semiconductor element, and the second electrode and the electrode pad are in contact with each other and connected. It has a feature. Further, the semiconductor mounting film is fixed to the substrate by being firmly connected to the substrate electrode formed on the surface of the substrate by soldering the terminal, and the inner wall surface is brought into contact with the surface of the semiconductor element opposite to the surface on which the electrode is formed. A heat dissipation member that adheres to the surface of the substrate.
【００１４】[0014]
【実施例】次に、本発明を図面を参照して詳細に説明す
る。The present invention will now be described in detail with reference to the drawings.
【００１５】図３は、本発明に用いる半導体素子実装用
フィルムの正面図である。図２は、図３で示される半導
体素子実装用フィルムに半導体素子が接続された状態の
縦断面図であり、図１は半導体素子が実装された半導体
素子実装用フィルムが親基板に搭載する際に、所定の寸
法に切断された状態を示す正面図および縦断面図であ
る。FIG. 3 is a front view of the semiconductor element mounting film used in the present invention. 2 is a vertical cross-sectional view showing a state in which a semiconductor element is connected to the semiconductor element mounting film shown in FIG. 3, and FIG. 1 shows a case where the semiconductor element mounting film on which the semiconductor element is mounted is mounted on a parent board. FIG. 2 is a front view and a vertical cross-sectional view showing a state of being cut to a predetermined size.
【００１６】半導体素子実装用フィルム１は、絶縁性フ
ィルム２の片面に銅箔が張合わされ、エッチングなどに
より回路パターン４が形成されている。図３では半導体
素子実装用フィルム１を長尺として想定しているが長尺
でなくてもよい。半導体素子用フィルム１の上下には位
置合わせや巻き取りに使用する孔（スプロケットホー
ル）３と半導体素子用フィルム１の中央部周囲には回路
パターン４の銅箔部の一部をリード部５として露出させ
るための孔６が設けられている。ここで、リード部５は
半導体素子９の外部接続用電極１０の上に設けた金属突
起１１との接続のためにＮｉメッキとＡｕメッキなどを
施すことが必要であるが、図面上では省略している。In the semiconductor element mounting film 1, a copper foil is laminated on one surface of an insulating film 2 and a circuit pattern 4 is formed by etching or the like. Although the semiconductor element mounting film 1 is assumed to be long in FIG. 3, it may not be long. Holes (sprocket holes) 3 used for alignment and winding on the top and bottom of the semiconductor element film 1 and a part of the copper foil portion of the circuit pattern 4 as a lead portion 5 around the center of the semiconductor element film 1. A hole 6 for exposing is provided. Here, the lead portion 5 needs to be plated with Ni and Au for connection with the metal projection 11 provided on the external connection electrode 10 of the semiconductor element 9, but it is omitted in the drawing. ing.
【００１７】リード部５の内側には、中央の領域に配置
された球状半田８がリード部５に接続される回路パター
ン４の先端部に設けられている。なお、球状半田８の形
成方法については、定量半田をパターン上にのせ再溶融
させるなどの方法が一般的に知られている。また、半田
再溶融の時の流れ防止のためのレジストをキャリアフィ
ルム１の回路パターン面に施す必要があるが図面では省
略している。リード部５の外側の周囲にはリード部５に
対応した測定用回路パターン７が配置されている。Inside the lead portion 5, a spherical solder 8 arranged in the central region is provided at the tip of the circuit pattern 4 connected to the lead portion 5. As a method of forming the spherical solder 8, a method of placing a fixed amount of solder on a pattern and remelting it is generally known. Further, it is necessary to apply a resist on the circuit pattern surface of the carrier film 1 for preventing the flow at the time of remelting the solder, but it is omitted in the drawing. A measuring circuit pattern 7 corresponding to the lead portion 5 is arranged around the outside of the lead portion 5.
【００１８】次に、図２および図１に示すように、半導
体素子９の外部接続用電極１０の上に形成された金属突
起１１とリード部５が位置合わせされ、熱圧着などの方
法によりリード部５と金属突起１１が接続される。半導
体素子９の外部接続用電極１０に設された金属突起１０
の形成方法については、細線の金ワイヤーを用いててボ
ールを作り熱圧着する方法や、メッキ法により形成する
方法がある。Next, as shown in FIGS. 2 and 1, the metal projection 11 formed on the external connection electrode 10 of the semiconductor element 9 and the lead portion 5 are aligned, and the lead is formed by a method such as thermocompression bonding. The part 5 and the metal projection 11 are connected. Metal projection 10 provided on external connection electrode 10 of semiconductor element 9
As a method of forming, there are a method of forming a ball using a thin gold wire and thermocompression bonding, and a method of forming by a plating method.
【００１９】リード部５と半導体素子９の金属突起１１
が電気的に接続された後、半導体素子用フィルム１に設
けられた測定用回路パターン７により、リード部５と半
導体素子９との電気的特性のチェックや信頼性を確認す
るバーインテストなどが行われる。The lead portion 5 and the metal projection 11 of the semiconductor element 9
After being electrically connected, the measurement circuit pattern 7 provided on the semiconductor element film 1 is used to perform a burn-in test or the like for checking the electrical characteristics of the lead portion 5 and the semiconductor element 9 and for confirming the reliability. Be seen.
【００２０】図１および図４に示されるように、親基板
１２への搭載は半導体素子用フィルム１が半導体素子９
とほぼ同じ寸法でリード部５の端部より切離されて実装
される。親基板１２には球状半田８に対応した接続用回
路パターン１３が形成されており、半導体素子９は裏面
が上向きされて搭載され、リフロー装置などによって加
熱されて球状半田８を再溶融させることにより接続され
る。As shown in FIGS. 1 and 4, the semiconductor element film 1 is mounted on the parent substrate 12 by mounting the semiconductor element film 1 on the semiconductor element 9.
It is mounted by being separated from the end portion of the lead portion 5 with substantially the same size as. A connection circuit pattern 13 corresponding to the spherical solder 8 is formed on the parent substrate 12, and the semiconductor element 9 is mounted with its back surface facing upward, and is heated by a reflow device or the like to remelt the spherical solder 8. Connected.
【００２１】発熱量の大きい半導体素子を使用する場合
には、図４に示すような熱伝導性の高い材料でできたラ
ジエータ１４を半導体素子９の裏面に接触させて配置す
ることで放熱を高めることが可能である。When a semiconductor element having a large heat generation amount is used, a radiator 14 made of a material having high thermal conductivity as shown in FIG. 4 is placed in contact with the back surface of the semiconductor element 9 to enhance heat dissipation. It is possible.
【００２２】図５は、その他の実施例を示す部分断面図
で、絶縁性フィルム２の半導体素子９側に回路パターン
１５と絶縁層１６が形成され、絶縁フィルム２に設けら
れた金属で埋められた孔１７を介して、回路パターン４
と回路パターン１５が接続される構造である。ここで、
回路パターン１５を接地電位とすることで半導体素子９
の回路部分と接地電位と接続されない回路パターン４と
の電気的結合を疎にすることが可能である。また、球状
半田８までの回路パターン４のパターン幅と回路パター
ン１４（接地電位）に挟まれた絶縁性フィルム２の比誘
電率を適宜選択することにより、高周波に対応したマイ
クロストリップラインの回路パターンを構成することも
可能である。また、上記構成で、絶縁性フィルムの回路
パターン１５の電極に相当する位置に穴を設けることに
より半導体素子を実装するフィルムを構成することも可
能である。FIG. 5 is a partial cross-sectional view showing another embodiment, in which the circuit pattern 15 and the insulating layer 16 are formed on the side of the semiconductor film 9 of the insulating film 2 and filled with the metal provided on the insulating film 2. Circuit pattern 4 through the hole 17
And the circuit pattern 15 are connected. here,
By setting the circuit pattern 15 to the ground potential, the semiconductor element 9
It is possible to loosen the electrical coupling between the circuit portion and the circuit pattern 4 which is not connected to the ground potential. Further, by appropriately selecting the pattern width of the circuit pattern 4 up to the spherical solder 8 and the relative permittivity of the insulating film 2 sandwiched between the circuit patterns 14 (ground potential), the circuit pattern of the microstrip line corresponding to a high frequency. Can also be configured. Further, with the above structure, it is possible to form a film on which a semiconductor element is mounted by providing holes at positions corresponding to the electrodes of the circuit pattern 15 of the insulating film.
【００２３】[0023]
【発明の効果】以上説明したように、本発明の半導体装
置では従来のＢＧＡ構造に比較して、ワイヤーボンディ
ングを行う領域と裏面へのスルーホール接続の領域が不
要であるため小型化が可能であり、半導体素子を半導体
素子用フィルムに取り付けた後の試験が半導体素子用フ
ィルムに設けた測定用回路パターンにて実施できるた
め、球状半田の変形を起こすこともなく、特殊な冶工具
も不要である。また発熱量の大きい半導体素子に対して
も自由度の高い放熱構造が採用できる効果がある。As described above, the semiconductor device of the present invention can be downsized as compared with the conventional BGA structure because the area for wire bonding and the area for the through hole connection to the back surface are unnecessary. Yes, since the test after mounting the semiconductor element on the semiconductor element film can be performed with the measurement circuit pattern provided on the semiconductor element film, there is no deformation of the spherical solder and no special jigs and tools are required. is there. Further, there is an effect that a heat dissipation structure having a high degree of freedom can be adopted even for a semiconductor element that generates a large amount of heat.
【図１】本発明の半導体素子実装用フィルムの正面図FIG. 1 is a front view of a film for mounting a semiconductor element of the present invention.
【図２】本発明の半導体素子の実装構造を示す縦断面図FIG. 2 is a vertical sectional view showing a mounting structure of a semiconductor element of the present invention.
【図３】本発明の半導体素子実装用フィルムで、所定の
寸法に切断される前の正面図FIG. 3 is a front view of the film for mounting a semiconductor element of the present invention before it is cut into a predetermined size.
【図４】本発明の半導体素子実装用フィルムが親基板に
実装された状態を示す縦断面図。FIG. 4 is a vertical cross-sectional view showing a state in which the semiconductor element mounting film of the present invention is mounted on a parent board.
【図５】本発明の半導体素子の実装構造他の実施例の縦
断面図FIG. 5 is a vertical cross-sectional view of another embodiment of a semiconductor element mounting structure according to the present invention.
【図６】従来のＢＧＡ構造の正面図と縦断面図FIG. 6 is a front view and a vertical sectional view of a conventional BGA structure.
【図７】従来のＱＦＰ構造の正面図と縦断面図FIG. 7 is a front view and a vertical sectional view of a conventional QFP structure.
１ ・・・ 半導体素子実装用フィルム ２ ・・・ 絶縁性フィルム ３ ・・・ スプロケットホール ４ ・・・ 回路パターン ５ ・・・ リード部 ６ ・・・ 孔 ７ ・・・ 測定用回路パターン ８ ・・・ 球状半田 ９ ・・・ 半導体素子 １０ ・・・ 外部接続用電極 １１ ・・・ 金属突起 １２ ・・・ 親基板 １３ ・・・ 親基板に形成された接続用回路パターン １４ ・・・ ラジエータ １５ ・・・ 回路パターン １６ ・・・ 絶縁層 １７ ・・・ 接続用孔 １８ ・・・ プラスティック基板 １９ ・・・ スルーホール ２０ ・・・ 回路パターン ２１ ・・・ 回路パターン ２２ ・・・ 金線 ２３ ・・・ モールド ２４ ・・・ 入出力端子リード ２５ ・・・ モールド 1 ・ ・ ・ Semiconductor element mounting film 2 ・ ・ ・ Insulating film 3 ・ ・ ・ Sprocket hole 4 ・ ・ ・ Circuit pattern 5 ・ ・ ・ Lead part 6 ・ ・ ・ Hole 7 ・ ・ ・ Measuring circuit pattern 8 ・ ・・ Spherical solder 9 ・ ・ ・ Semiconductor element 10 ・ ・ ・ External connection electrode 11 ・ ・ ・ Metal protrusion 12 ・ ・ ・ Mother board 13 ・ ・ ・ Connecting circuit pattern 14 formed on the mother board 14 ・ ・ ・ Radiator 15 ・・ ・ Circuit pattern 16 ・ ・ ・ Insulating layer 17 ・ ・ ・ Connection hole 18 ・ ・ ・ Plastic substrate 19 ・ ・ ・ Through hole 20 ・ ・ ・ Circuit pattern 21 ・ ・ ・ Circuit pattern 22 ・ ・ ・ Gold wire 23 ・ ・・ Mold 24 ・ ・ ・ Input / output terminal lead 25 ・ ・ ・ Mold
Claims (7)
域に配列された半田からなる複数の端子と、 前記領域の周囲に形成された複数の第１の電極と、 前記第１の絶縁性フィルム上に形成され、前記端子と前
記電極を接続する第１のリード線と、 前記端子が配列された面とは反対側の面に形成され、前
記第１の電極に接続される第２の電極とを備えたことを
特徴とする半導体素子実装用フィルム。1. A plurality of terminals made of solder arranged in a central region of one surface of a first insulating film, a plurality of first electrodes formed around the region, and the first insulating film. A first lead wire that is formed on a conductive film and connects the terminal and the electrode, and a second lead that is formed on a surface opposite to the surface on which the terminals are arranged and is connected to the first electrode. A film for mounting a semiconductor element, comprising:
ルムと前記端子が配列された面とは反対側の面に配置さ
れた第２の絶縁性フィルムの表面に形成され、 前記第１の絶縁性フィルムと前記第２のフィルムの間に
配置された回路パターン層に形成された第２のリード線
によって接続されていることを特徴とする「請求項１」
記載の半導体素子実装用フィルム。2. The second electrode is formed on a surface of a second insulating film disposed on a surface opposite to a surface on which the first insulating film and the terminals are arranged, The first insulating film and the second film are connected by a second lead wire formed in a circuit pattern layer disposed between the second film and the second film.
The film for mounting a semiconductor device as described above.
前記第１の絶縁性フィルムと前記第２の絶縁性フィルム
に形成された孔に導電物質が挿入されて、前記第２のリ
ード線に接続されていることを特徴とする「請求項２」
記載の半導体素子実装用フィルム。3. The first electrode and the second electrode are
A conductive material is inserted into the holes formed in the first insulating film and the second insulating film and connected to the second lead wire.
The film for mounting a semiconductor device as described above.
なくともどちらかは、前記回路パターン層に形成された
電極であり、前記第１の絶縁性フィルム若しくは前記第
２の絶縁性フィルムには前記電極が形成された位置に穴
が形成されていることを特徴とする「請求項２」記載の
半導体素子実装用フィルム。4. At least one of the first electrode and the second electrode is an electrode formed on the circuit pattern layer, and is provided on the first insulating film or the second insulating film. The film for mounting a semiconductor element according to claim 2, wherein a hole is formed at a position where the electrode is formed.
なる突起を有することを特徴とする「請求項３」または
「請求項４」記載の半導体素子実装用フィルム。5. The film for mounting a semiconductor element according to claim 3, wherein the second electrode has a protrusion made of a conductive material on its surface.
前記第２の電極は、半導体素子の表面に形成された電極
用パッドに相対する位置に形成され、 前記第２の電極と前記電極パッドが接触して接続されて
いることを特徴とする半導体素子の実装構造。6. The second electrode according to claim 3 or 4 is formed at a position facing an electrode pad formed on the surface of a semiconductor element, and the second electrode A mounting structure for a semiconductor element, wherein the electrode pads are connected in contact with each other.
に形成された基板電極に固接続されて前記半導体実装用
フィルムが前記基板に固定され、 前記半導体素子の前記電極が形成された面とは反対の面
に内壁面が接触される放熱部材が、前記基板の表面に固
着されていることを特徴とする「請求項６」記載の半導
体素子の実装構造。7. The surface of the semiconductor element on which the electrodes are formed is fixedly connected to the board electrodes formed on the surface of the board by the solder of the terminals to fix the semiconductor mounting film to the board. The semiconductor element mounting structure according to claim 6, wherein a heat dissipation member whose inner wall surface is in contact with the opposite surface is fixed to the surface of the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6086646A JP3033662B2 (en) | 1994-04-25 | 1994-04-25 | Semiconductor element mounting film and semiconductor element mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6086646A JP3033662B2 (en) | 1994-04-25 | 1994-04-25 | Semiconductor element mounting film and semiconductor element mounting structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07297236A true JPH07297236A (en) | 1995-11-10 |
| JP3033662B2 JP3033662B2 (en) | 2000-04-17 |
Family
ID=13892801
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6086646A Expired - Lifetime JP3033662B2 (en) | 1994-04-25 | 1994-04-25 | Semiconductor element mounting film and semiconductor element mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3033662B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09293751A (en) * | 1996-04-25 | 1997-11-11 | Nec Corp | Tape carrier package and connection method |
| US6175151B1 (en) | 1997-01-23 | 2001-01-16 | Seiko Epson Corporation | Film carrier tape, semiconductor assembly, semiconductor device, and method of manufacturing the same, mounted board, and electronic instrument |
| US6475896B1 (en) | 1996-12-04 | 2002-11-05 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
| JP2008294481A (en) * | 1996-12-04 | 2008-12-04 | Seiko Epson Corp | Semiconductor device and method for manufacturing the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0677284A (en) * | 1992-08-27 | 1994-03-18 | Mitsubishi Electric Corp | Semiconductor device |
-
1994
- 1994-04-25 JP JP6086646A patent/JP3033662B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0677284A (en) * | 1992-08-27 | 1994-03-18 | Mitsubishi Electric Corp | Semiconductor device |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09293751A (en) * | 1996-04-25 | 1997-11-11 | Nec Corp | Tape carrier package and connection method |
| JP2008294481A (en) * | 1996-12-04 | 2008-12-04 | Seiko Epson Corp | Semiconductor device and method for manufacturing the same |
| US6475896B1 (en) | 1996-12-04 | 2002-11-05 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
| US6730589B2 (en) | 1996-12-04 | 2004-05-04 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
| US7470979B2 (en) | 1996-12-04 | 2008-12-30 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
| US7511362B2 (en) | 1996-12-04 | 2009-03-31 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
| US7842598B2 (en) | 1996-12-04 | 2010-11-30 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
| US7888260B2 (en) | 1996-12-04 | 2011-02-15 | Seiko Epson Corporation | Method of making electronic device |
| US8115284B2 (en) | 1996-12-04 | 2012-02-14 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board and electronic instrument |
| US8384213B2 (en) | 1996-12-04 | 2013-02-26 | Seiko Epson Corporation | Semiconductor device, circuit board, and electronic instrument |
| US6414382B1 (en) | 1997-01-23 | 2002-07-02 | Seiko Epson Corporation | Film carrier tape, semiconductor assembly, semiconductor device and method of manufacturing the same, mounted board, and electronic instrument |
| US6646338B2 (en) | 1997-01-23 | 2003-11-11 | Seiko Epson Corporation | Film carrier tape, semiconductor assembly, semiconductor device, and method of manufacturing the same, mounted board, and electronic instrument |
| US6175151B1 (en) | 1997-01-23 | 2001-01-16 | Seiko Epson Corporation | Film carrier tape, semiconductor assembly, semiconductor device, and method of manufacturing the same, mounted board, and electronic instrument |
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| Publication number | Publication date |
|---|---|
| JP3033662B2 (en) | 2000-04-17 |
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