JP2002151627A - Semiconductor device and its manufacturing method and method for mounting - Google Patents

Abstract

PROBLEM TO BE SOLVED: To markedly increase external connecting terminals, without increasing the package size. SOLUTION: An external electrode 17 provided in a CSP-type semiconductor device 1 has a bump 16 formed at an electrode 9 for the bump, and a connecting pin 10. The bump 16 is connected to a wiring pattern 5 via the electrode 9 for the bump and a through-hole 9a. The pin 10 is inserted into the hole 9a. One end is connected to a wiring pattern 7 via a conductive adhesive 11, such as solder paste or the like, and the other end is provided to protrude in a length from the electrode 9. Thus, electrodes for two pins are formed at the one external electrode 17.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for increasing the number of pins in a semiconductor device, and more particularly to a CSP (Chip Size).
The present invention relates to a technology effective when applied to increase the number of pins in a semiconductor device such as a package.

[0002]

2. Description of the Related Art According to studies made by the present inventor, as one of surface-mount type semiconductor devices, for example, BGA
(Ball Grid Array). This BG
An A-type semiconductor device is formed by bonding a semiconductor chip electrode mounted on a printed wiring board and a bonding electrode formed on the printed wiring board with a bonding wire, and then sealing the resin to form a package. I have.

In addition, a spherical solder, that is, a so-called solder ball is formed on the back surface of the package instead of the lead for leading out. At the time of mounting a semiconductor device, solder balls are superimposed on an electrode portion formed on a mounting wiring board on which electronic components and the like are mounted, and the solder balls are melted by reflow to be electrically connected.

[0004] As an example describing this type of semiconductor device in detail, see Nikkei B on May 31, 1993.
Published by Company P, Susumu Kayama, Kunihiko Naruse (monitoring), "VLSI Packaging Technology (2)" P173-P178,
This document describes the configuration of a BGA type semiconductor device and the like.

[0005]

However, the present inventor has found that the semiconductor device having the above configuration has the following problems.

In recent years, semiconductor devices have tended to be multi-pin in order to meet market needs for miniaturization and multi-functionality. In response to this trend, miniaturization of solder balls and fine pitch have been performed. I have.

[0007] However, there is a limit to the measures taken, and it is difficult to arrange more solder balls and increase the number of pins of the semiconductor device without changing the package size.

An object of the present invention is to provide a semiconductor device capable of greatly increasing the number of external connection terminals without increasing the package size and the like, and a method of manufacturing and mounting the same.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, in the semiconductor device of the present invention, a semiconductor chip is mounted on one surface of a printed wiring board, and a plurality of external connection terminals connected to chip electrodes provided on the semiconductor chip are provided on the other surface. Semiconductor device,
The printed wiring board has, on one surface on which the semiconductor chip is mounted, a first wiring layer in which first wiring patterns respectively connected to chip electrodes of the semiconductor chip are formed, and a first wiring layer formed above the first wiring layer. A second wiring layer formed with a second wiring pattern connected to each of the chip electrodes of the semiconductor chip via an insulating layer; a through hole to which an arbitrary first wiring pattern is connected; The external connection terminal is inserted into the through hole, one end face is connected to the second wiring pattern, the other end face protrudes from the electrode part, and the outer peripheral face is formed. It comprises an insulated cylindrical external terminal pin and a bump formed on an electrode portion.

Further, in the semiconductor device of the present invention, a semiconductor chip is mounted on one surface of a printed wiring board, and a plurality of external connections electrically connected to chip electrodes provided on the semiconductor chip on the other surface. A semiconductor device provided with terminals, the printed wiring board having a first wiring pattern on one surface on which a semiconductor chip is mounted, the first wiring pattern being connected to a chip electrode of the semiconductor chip, respectively. A second wiring layer on which a second wiring pattern connected to a chip electrode of a semiconductor chip is formed above the first wiring layer via an insulating layer, and an insulating layer above the second wiring layer A third wiring layer on which a third wiring pattern connected to the chip electrode of the semiconductor chip is formed, a through hole to which an arbitrary first wiring pattern is connected, and printed wiring. An external connection terminal is formed on the other surface of the plate and has an electrode portion connected to the through hole. The external connection terminal has a cylindrical shape having one end surface connected to the third wiring pattern and the other end surface protruding from the electrode portion. A conductive pin, a first insulating layer formed on the outer peripheral surface of the conductive pin, a conductive layer formed on the outer peripheral surface of the first insulating layer and connected to the second wiring pattern, and an outer periphery of the conductive layer It comprises a second insulating layer formed on the surface, and comprises external terminal pins inserted into the through holes and bumps formed on the electrode portions.

Further, according to the method of manufacturing a semiconductor device of the present invention, there is provided a step of preparing a semiconductor chip having a chip electrode formed on a surface thereof;
A plurality of bonding electrodes corresponding to the chip electrodes of the semiconductor chip, and first and second wiring patterns respectively connected to the chip electrodes via the bonding electrodes are formed, and the first and second wiring patterns are formed on the other surface through the through holes. A step of preparing a printed wiring board having an electrode portion to which a wiring pattern is connected; a step of preparing a cylindrical external terminal pin having an insulated outer peripheral surface; and a step of joining a semiconductor chip to the printed wiring board. Connecting the chip electrode of the semiconductor chip and the corresponding bonding electrode with a connecting member by a connecting member, forming the semiconductor chip, and the vicinity thereof with a sealing resin with a sealing resin, and forming a sealing portion;
Inserting an external terminal pin into the through hole, connecting one end face of the external terminal pin to the second pattern, and projecting the other end face from the electrode portion, and forming a bump on the electrode portion; Cutting the bumps formed on the electrode portions together with the external terminal pins, and flattening the bumps to form external connection terminals.

Further, a method of manufacturing a semiconductor device according to the present invention
A step of preparing a semiconductor chip having a chip electrode formed on a surface; a plurality of bonding electrodes corresponding to the chip electrodes of the semiconductor chip on one surface on which the semiconductor chip is mounted; and a chip electrode provided via the bonding electrode. And first to third wiring patterns respectively connected to are formed,
A step of preparing a printed wiring board on which an electrode portion to which the first wiring pattern is connected via a through hole is formed on the other surface; and a step of forming a cylindrical conductive pin and an outer peripheral surface of the conductive pin. An external terminal comprising a first insulating layer, a conductive layer formed on the outer peripheral surface of the first insulating layer, and electrically connected to the second wiring pattern, and a second insulating layer formed on the outer peripheral surface of the conductive layer. A step of preparing pins, a step of joining a semiconductor chip to a printed wiring board, a step of connecting a chip electrode of the semiconductor chip and a corresponding bonding electrode with a connecting member, and sealing the semiconductor chip and its vicinity Forming a sealing portion by resin molding with a resin, inserting external terminal pins into the through holes, connecting one end surface of the conductive pins to the third wiring pattern, and forming a conductive layer and a second wiring pattern. And a step of forming a bump on the electrode portion, and a step of cutting the bump formed on the electrode portion together with an external terminal pin, flattening the bump and forming an external connection terminal. .

Further, the method of mounting a semiconductor device according to the present invention is directed to a semiconductor device having a semiconductor chip mounted on a surface of a printed wiring board and having external connection terminals formed of external terminal pins and bumps formed on the back surface of the printed wiring board. A semiconductor device comprising: a preparing step; a first land to which an external terminal pin is connected among external connection terminals; and a second land to which a bump is connected to a peripheral portion of the first land via an insulating layer. A step of preparing a mounting wiring board on which a board electrode corresponding to the external connection electrode is formed; a step of applying flux to the external connection terminal or a board electrode of the mounting wiring board corresponding to the external connection terminal; Connecting the electrodes by reflow.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a cross-sectional view of a semiconductor device according to Embodiment 1 of the present invention, and FIG. 2 is a diagram showing connection pins provided in the semiconductor device according to Embodiment 1 of the present invention.
FIGS. 3 to 11 are schematic diagrams illustrating the manufacturing process in the semiconductor device of FIG. 1, FIG. 12 is a flowchart of the manufacturing process in the semiconductor device of FIG. 1, and FIG. FIG. 2 is an explanatory diagram of lands formed on a mounting board on which the semiconductor device of FIG. 1 is mounted.

In the first embodiment, the semiconductor device 1
Consists of a CSP which is a kind of surface mount type. As shown in FIG. 1, a printed circuit board 2
Is provided.

The printed wiring board 2 is a so-called multilayer printed wiring board. This printed wiring board 2 includes
For example, a substrate core 3 made of a glass cloth substrate or the like is provided.

A bonding electrode 4 and a wiring pattern (first wiring pattern) 5 are formed on one surface of the substrate core 3. The bonding electrodes 4 are formed at predetermined intervals near the periphery of the substrate core 3.

A solder resist 6, which is an insulating layer, is formed on the surface of the substrate core 3 on which the bonding electrodes 4 and the wiring patterns 5 are formed. A wiring pattern (second wiring pattern) 7 is formed on the surface of the solder resist 6, and a solder resist (insulating layer) 8 is also formed on the wiring pattern 7 except for the bonding electrode 4.

On the other surface of the substrate core 3, bump electrodes (electrode portions) 9 are formed at regular intervals in an array. A through hole 9 a is formed in the center of the bump electrode 9. The bonding electrode 4 and the bump electrode 9 are electrically connected to each other via the wiring pattern 5 and the through hole 9a.

Further, cylindrical connection pins (external terminal pins) 10 are inserted into through holes 9a formed in the center of the bump electrodes 9, respectively. The connection pin 10 is longer than the thickness of the printed wiring board 2, and one end is connected to the wiring pattern 7 via a conductive adhesive 11 such as a solder paste, and the other end is connected to the bump electrode 9. It is provided so as to protrude by a certain length. The other bonding electrodes 4 to which the wiring pattern 5 is not connected and the connection pins 10 are electrically connected via the wiring pattern 7, respectively. Further, on the other surface of the substrate core 3 except for the bump electrodes 9, a solder resist is formed as an insulating layer.

A semiconductor chip 12 is bonded to one surface of the substrate core 3, that is, the center of the surface on which the bonding electrodes 4 are formed, via an adhesive 13. A plurality of chip electrodes 12 are provided near the periphery of the semiconductor chip 12.
a are formed at equal intervals.

The chip electrodes 12a and the bonding electrodes 4 of the printed wiring board 2 are respectively bonded by bonding wires 14 such as gold wires.
It is electrically connected.

Further, the peripheral portions of the semiconductor chip 12, the bonding wires 14, and the bonding electrodes 4 mounted on the printed wiring board 2 and the vicinity thereof are sealed with a sealing resin (sealing portion) 15.

The bump electrodes 9 of the printed wiring board 2 have solder bumps (bumps) 16 made of spherical solder.
Are provided respectively, and these solder bumps 16 are provided.
Are the connection pins 1 protruding from the center of the bump electrode 9.
0 is formed.

The external electrodes (external connection terminals) 1 are connected by the connection pins 10 and the solder bumps 16.
7, and one external electrode 17 is provided with electrodes for two pins.

The configuration of the connection pins 10 and the connection state will be described.

As shown in FIG. 2, the connection pin 10 has a structure in which an insulating layer 10b is formed on the outer peripheral surface of a conductive pin 10a made of, for example, an iron-nickel (Fe-Ni) alloy. In addition, the insulating layer 10b is not formed on both end surfaces of the pin 10a. The insulating layer 10b is coated with an insulating resin such as polyimide.

Next, the semiconductor device 1 according to the present embodiment
FIGS. 3 to 11 show a manufacturing method and a mounting method of
Explanation will be made with reference to an explanatory diagram showing an outline of a manufacturing process of the semiconductor device 1 and a flowchart of FIG.

First, a semiconductor chip 12, a printed wiring board 2 on which the semiconductor chip 12 is mounted, and connection pins 10 are prepared. In the printed wiring board 2,
Bonding electrodes 4, wiring patterns 5, 7, bump electrodes 9, through holes 9a, and the like have already been formed.
A conductive adhesive 11 is applied to the wiring pattern 7 in which one end of the connection pin 10 contacts in the through hole 9a of the printed wiring board 2.

Then, an adhesive 13 is applied to the center of the printed wiring board 2 and, as shown in FIG.
2 are joined (step S101). Semiconductor chip 12
In the bonding step, the chip electrode 12a of the semiconductor chip 12 and the bonding electrode 4 of the printed wiring board 2 are respectively bonded by bonding wires 14 in the bonding step, and the printed wiring board 2 to which The connection is made (step S102).

Thereafter, the periphery of the bonding electrodes 4 of the printed wiring board 2, the bonding wires 14, and the semiconductor chip 12 are connected to the sealing resin 15 as shown in FIG.
To form a package. (Step S103).

After the package is formed, the connection pins 10 are inserted into the through holes 9a formed in the printed wiring board 2 as shown in FIG. 6 (step S104).

As shown in FIG. 7, the printed wiring board 2 into which the connection pins 10 have been inserted melts the conductive adhesive 11 by passing through the reflow furnace, and
0 is connected to the wiring pattern 7 (step S105).

Thereafter, as shown in FIG. 8, the printed wiring board 2 is immersed in the solder bath HS. This solder bath HS
Are formed with hemispherical solder holes H arranged at the same intervals as the bump electrodes 9 of the printed wiring board 2.
Molten solder is stored in the solder hole H, and when immersed, the bump electrode 9 and the solder hole H are placed so as to correspond to each other.

Then, when the solder bath HS is cooled and the solder hardens, the printed wiring board 2 is peeled off from the solder bath HS to form solder bumps 16 as shown in FIG. 9 (step S106).

Next, as shown in FIG. 10, about half of the solder bumps 16 formed on the printed wiring board 2 are cut together with the connection pins 10 by ball grinding or the like. 16 is flattened (step S107), and the semiconductor device 1 as shown in FIGS. 1 and 11 is completed (step S10).
8).

Therefore, the semiconductor device 1 is provided with the solder bumps 16 electrically connected to the wiring pattern 5 through the through holes 9a and the connection pins 10 electrically connected to the wiring pattern 7. In other words, an external lead electrode for two pins is formed in one external lead electrode portion.

Next, a mounting technique of the semiconductor device 1 will be described.

The mounting wiring board J on which the semiconductor device 1 is mounted
Is formed with a land (substrate electrode) L on which the external electrode 17 of the semiconductor device 1 overlaps. As shown in FIG. 13, the land L includes a first electrode portion (first land) LD1,
A second electrode portion (second land) LD2 and an insulating layer Z are provided.

A first electrode portion LD1 on which the pin 10a is located is formed at the center of the land L, and an insulating layer Z for insulation is formed around the first electrode portion LD1. The insulating layer Z is, for example, a solder resist. Furthermore, solder bumps 16 are formed on the outer peripheral portion of the insulating layer Z.
Are formed in the second electrode section LD2.

When the semiconductor device 1 is mounted on the mounting wiring board J, a flux is applied to the external electrodes 17 or the lands L, and then the external electrodes 17 of the semiconductor device 1 are connected to the lands L of the mounting wiring board J. And mounted on each,
By performing reflow, the solder bumps 16 are melted and electrically connected.

Thus, according to the first embodiment, 1
Since two external electrodes 17 can provide electrodes for two pins, the number of pins can be increased without increasing the size of the package of the semiconductor device 1.

(Second Embodiment) FIG. 14 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention, and FIG. 15 is a diagram showing connection pins provided in the semiconductor device according to the second embodiment of the present invention. FIG. 16 is an explanatory diagram of a peripheral portion thereof, and FIG. 16 is an explanatory diagram of a land formed on a mounting board on which the semiconductor device of FIG. 14 is mounted.

In the second embodiment, the semiconductor device 1a
The third embodiment is different from the first embodiment in the configuration of the printed wiring board 2a and the external electrodes (external connection terminals) 17a, and is otherwise the same as the first embodiment.

As shown in FIG. 14, the printed wiring board 2a is a multilayer wiring board composed of three wiring layers. The printed circuit board 2a is provided with a substrate core 3 made of, for example, a glass cloth base material.

On one surface of the substrate core 3, a bonding electrode 4 and a wiring pattern 5 are formed.
The bonding electrodes 4 are formed at predetermined intervals near the periphery of the substrate core 3.

On the surface of the substrate core 3 on which the bonding electrodes 4 and the wiring patterns 5 are formed, a solder resist 6 as an insulating layer is formed. A wiring pattern 7 is formed on the surface of the solder resist 6.

On the upper layer of the wiring pattern 7, a wiring pattern (third wiring pattern) is provided via a solder resist 8.
7a are formed. Except for the bonding electrode 4, a solder resist (insulating layer) 8a is also formed on the wiring pattern 7a.

On the other surface of the substrate core 3, bump electrodes 9 are formed at regular intervals in an array, and a through hole 9a is formed in the center. The bonding electrode 4 and the bump electrode 9 are electrically connected to each other via the wiring pattern 5 and the through hole 9a.

Further, cylindrical connection pins 18 are inserted into through holes 9a formed in the center of the bump electrodes 9, respectively. One end of the connection pin 18 is connected to the wiring pattern 7 via a conductive adhesive 11 such as a solder paste.

A wiring pattern 7a is connected to a side surface near one end of the connection pin 18. The connection pin 18 is longer than the thickness of the printed wiring board 2a, and is provided such that the other end protrudes from the bump electrode 9 by a certain length.

The bonding electrode 4 to which the wiring pattern 5 is not connected and the connection pin 18 are electrically connected via the wiring pattern 7, respectively, and the bonding electrode 4 to which the wiring patterns 5 and 7 are not connected. And the connection pin 18 are electrically connected to each other via the wiring pattern 7a.

The bump electrodes 9 of the printed wiring board 2a are provided with solder bumps 16 made of spherical solder, respectively. These solder bumps 16 are connected to connection pins 18 projecting from the center of the bump electrodes 9. It is formed so that it may cover.

The external electrodes 17a are constituted by the connection pins 18 and the solder bumps 16, so that one external electrode 17a is provided with electrodes for three pins.

The configuration and connection state of the connection pins 18 will be described.

As shown in FIG. 15, the connection pins 18
An insulating layer (first insulating layer) 18b is formed on the outer peripheral surface of a conductive pin (conductive pin) 18a made of an iron-nickel alloy or the like.

A conductive layer 18c coated with a conductive member is formed on the outer peripheral surface of the insulating layer 18b, and an insulating layer (second insulating layer) 18d is formed on the outer peripheral portion of the conductive layer 18c.
Is formed.

The conductive layer 18c is formed by, for example, solder plating or the like.
d is a coating of an insulating resin such as polyimide. The insulating layers 18b, 1
8d is not formed, and the insulating layer 18d is not formed on the outer peripheral surface near one end of the pin 18a.

Next, a method of manufacturing the semiconductor device 1a according to the second embodiment will be described.

First, the bonding electrode 4, the wiring patterns 5, 7, 7a, the bump electrode 9, the through hole 9a, etc. are already formed, and the wiring to which one end of the connection pin 18 contacts in the through hole 9a. An adhesive 13 is applied to the central portion of the printed wiring board 2a in which the conductive adhesive 11 is applied to the pattern 7, and the semiconductor chip 12 is joined.

Then, the chip electrode 1 of the semiconductor chip 12
2a and the bonding electrode 4 of the printed wiring board 2a are respectively bonded by bonding wires 14, and are electrically connected.

Thereafter, the periphery of the bonding electrodes 4 of the printed wiring board 2a, the bonding wires 14, and the semiconductor chip 12 are sealed with a sealing resin 15,
A package is formed.

After the package is formed, the connecting pins 18 are inserted into the through holes 9a formed in the printed wiring board 2a. The printed wiring board 2a into which the connecting pins 18 have been inserted melts the conductive adhesive 11 by passing through the reflow furnace, and connects one end face of the connecting pins 18 to the wiring pattern 7 (step S105).

As a result, one end of the connection pin 18 and the wiring pattern 7 are electrically connected, and the outer peripheral surface near the one end of the connection pin 18 and the wiring pattern 7a are electrically connected. Will be connected.

Thereafter, the printed wiring board 2a is immersed in a solder bath HS (FIGS. 8 and 9) to form solder bumps 16, and about half of the solder bumps 16 are connected to connection pins 18 by ball grinding or the like. Cutting with
By flattening the mounting surface of the solder bump 16, the semiconductor device 1a is completed.

Therefore, in the semiconductor device 1a, the solder bumps 16 electrically connected to the wiring pattern 5 via the through holes 9a, the pins 18a electrically connected to the wiring pattern 7, and the electrical connection between the wiring pattern 7a and the The conductive layer 18c to be electrically connected is provided, and external lead electrodes for three pins are formed in one external electrode 17a.

The land La of the mounting wiring board J on which the semiconductor device 1a is mounted will be described.

As shown in FIG. 16, the land La formed on the mounting wiring board J on which the semiconductor device 1a is mounted has a first electrode portion LD3, a second electrode portion LD4, and a third electrode portion LD.
5 and insulating layers Z1 and Z2.

A first electrode portion LD3 where the pin 18a is located is formed at the center of the land L, and an insulating layer Z1 for insulation is formed around the first electrode portion LD3. A second electrode portion LD4 where the conductive layer 18c is located is formed on the outer peripheral portion of the insulating layer Z1, and the second electrode portion LD4
Is formed with an insulating layer Z2 at the outer peripheral portion.

These insulating layers Z1 and Z2 are, for example, solder resists. Further, a second electrode portion LD5 where the solder bump 16 is located is formed on the outer peripheral portion of the insulating layer Z2.

Then, the semiconductor device 1a is mounted on the mounting wiring board J.
When mounting on the external electrode 17a or the land L
After the flux is applied to a, the external electrodes 17a are superimposed and mounted on the lands La of the mounting wiring board J, respectively, reflowed, and the solder bumps 16 are melted and electrically connected.

As a result, in the second embodiment,
Since an electrode for three pins can be provided by one external electrode 17a, it is possible to cope with an increase in the number of pins without increasing the size of the package of the semiconductor device 1a.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the first and second embodiments, 1
Two external electrodes are provided with an electrode for two pins and an electrode for three pins. However, the printed wiring board of the semiconductor device is multi-layered with four or more layers, and the connection pins are correspondingly provided. An insulating layer and a conductive layer may be formed, and four or more pins may be provided by one external electrode.

[0078]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, two or three pins of electrodes can be provided by one external connection terminal, so that the number of pins can be increased without increasing the package size of the semiconductor device. Can be increased.

(2) In the present invention, a low-cost and high-performance semiconductor device can be realized by the above (1).

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is an explanatory diagram of connection pins provided in the semiconductor device according to the first embodiment of the present invention and peripheral portions thereof;

FIG. 3 is an explanatory view schematically showing a manufacturing process in the semiconductor device of FIG. 1;

FIG. 4 is an explanatory view of the semiconductor device manufacturing process following FIG. 3;

FIG. 5 is an explanatory view of the semiconductor device manufacturing process following FIG. 4;

FIG. 6 is an explanatory view of the manufacturing process of the semiconductor device, following FIG. 5;

FIG. 7 is an explanatory view of the semiconductor device manufacturing process following FIG. 6;

FIG. 8 is an explanatory view of the manufacturing process of the semiconductor device, following FIG. 7;

FIG. 9 is an explanatory view of the semiconductor device manufacturing process following FIG. 8;

FIG. 10 is an explanatory diagram of the semiconductor device manufacturing process following FIG. 9;

FIG. 11 is an explanatory view of the semiconductor device manufacturing process following FIG. 10;

FIG. 12 is a flowchart of a manufacturing process in the semiconductor device of FIG. 1;

FIG. 13 is an explanatory diagram of lands formed on a mounting board on which the semiconductor device of FIG. 1 is mounted.

FIG. 14 is a sectional view of a semiconductor device according to a second embodiment of the present invention;

FIG. 15 is an explanatory diagram of connection pins provided in a semiconductor device according to a second embodiment of the present invention and peripheral portions thereof.

FIG. 16 is an explanatory diagram of lands formed on a mounting board on which the semiconductor device of FIG. 14 is mounted.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1, 1a Semiconductor device 2, 2a Printed wiring board 3 Substrate core 4 Bonding electrode 5 Wiring pattern (first wiring pattern) 6 Solder resist 7 Wiring pattern (second wiring pattern) 7a Wiring pattern (third wiring pattern) 8, 8a Solder resist (insulating layer) 9 Bump electrode (electrode part) 9a Through hole 10 Connecting pin (external terminal pin) 10a Pin 10b Insulating layer 11 Conductive adhesive 12 Semiconductor chip 12a Chip electrode 13 Adhesive 14 Bonding wire 15 Seal Resin stopper (sealing part) 16 Solder bump (bump) 17 External electrode (external connection terminal) 17a External electrode 18 Connection pin 18a Pin (conductive pin) 18b Insulating layer (first insulating layer) 18c Conducting layer 18d Insulating layer (Second insulating layer) HS solder bath H solder hole J mounting wiring board Land (substrate electrode) La lands LD1 first electrode portion (first land) LD3 first electrode portion LD2 second electrode portion (second lands) LD4 second electrode portion LD5 third electrode portion Z, Z1, Z2 insulating layer

Claims (5)

[Claims] 1. A semiconductor device having a semiconductor chip mounted on one surface of a printed wiring board and a plurality of external connection terminals connected to chip electrodes provided on the semiconductor chip on the other surface, A first wiring layer in which a first wiring pattern connected to a chip electrode of the semiconductor chip is formed on one surface of the printed wiring board on which the semiconductor chip is mounted; A second wiring layer formed with a second wiring pattern connected to a chip electrode of the semiconductor chip via an insulating layer, a through-hole connected to an arbitrary first wiring pattern, An electrode portion formed on the back surface of the substrate and connected to the through hole, wherein the external connection terminal is inserted into the through hole, and one end surface is the second wiring The external terminal pins are joined to the turns and electrically connected to each other, the other end faces of the external terminal pins protrude from the electrode section, and the outer peripheral face is insulated. The external terminal pins are formed of bumps formed on the electrode sections. Semiconductor device. 2. A semiconductor device having a semiconductor chip mounted on one surface of a printed wiring board and a plurality of external connection terminals electrically connected to chip electrodes provided on the semiconductor chip on the other surface. A first wiring layer on the one surface of the printed wiring board on which the semiconductor chip is mounted, the first wiring layer having first wiring patterns respectively connected to chip electrodes of the semiconductor chip; A second wiring layer formed with a second wiring pattern connected to the chip electrode of the semiconductor chip via an insulating layer above the layer, and an insulating layer above the second wiring layer. A third wiring layer on which a third wiring pattern connected to each of the chip electrodes of the semiconductor chip is formed; a through hole to which each of the first wiring patterns is connected; An electrode portion formed on the other surface of the wire substrate and connected to the through hole, wherein the external connection terminal has one end surface connected to the third wiring pattern, and the other end surface connected to the electrode portion. A protruding cylindrical conductive pin,
A first insulating layer formed on the outer peripheral surface of the conductive pin, a conductive layer formed on the outer peripheral surface of the first insulating layer and connected to the second wiring pattern, and formed on the outer peripheral surface of the conductive layer; A semiconductor device comprising: an external terminal pin inserted into the through hole; and a bump formed on the electrode portion. A step of preparing a semiconductor chip having a chip electrode formed on a surface thereof; and a plurality of bonding electrodes corresponding to chip electrodes of the semiconductor chip on one surface on which the semiconductor chip is mounted. Printed wiring in which first and second wiring patterns respectively connected to the chip electrodes via electrodes are formed, and an electrode portion connected to the first wiring pattern via through holes is formed on the other surface. A step of preparing a substrate; a step of preparing a columnar external terminal pin having an insulated outer peripheral surface; a step of bonding the semiconductor chip to the printed wiring board; and a chip electrode of the semiconductor chip and a corresponding electrode. A step of connecting the bonding electrode with a connection member; Forming a sealing portion, inserting the external terminal pin into the through hole, connecting one end surface of the external terminal pin and the second pattern, and connecting the other end surface from the electrode portion. Protruding; forming a bump on the electrode portion; cutting the bump formed on the electrode portion together with the external terminal pin; flattening the bump to form an external connection terminal. A method for manufacturing a semiconductor device, comprising: 4. A step of preparing a semiconductor chip having a chip electrode formed on a surface thereof; and a plurality of bonding electrodes corresponding to chip electrodes of the semiconductor chip on one surface on which the semiconductor chip is mounted. Printed wiring in which first to third wiring patterns respectively connected to the chip electrodes via electrodes are formed, and on the other surface, electrode portions to which the first wiring patterns are connected via through holes are formed. A step of preparing a substrate; a columnar conductive pin; a first insulating layer formed on an outer peripheral surface of the conductive pin; and an electric conductor formed on the outer peripheral surface of the first insulating layer and electrically connected to the second wiring pattern. Preparing external terminal pins comprising a conductive layer to be electrically connected and a second insulating layer formed on the outer peripheral surface of the conductive layer; and attaching the semiconductor chip to the printed wiring board. A bonding step; a step of connecting a chip electrode of the semiconductor chip and the corresponding bonding electrode with a connection member; and a step of resin-molding the semiconductor chip and its vicinity with a sealing resin to form a sealing portion. Inserting the external terminal pin into the through-hole, connecting one end face of the conductive pin to the third wiring pattern, and connecting the conductive layer to the second wiring pattern. Forming a bump on the electrode portion, and cutting the bump formed on the electrode portion together with the external terminal pin, and flattening the bump to form an external connection terminal. A method for manufacturing a semiconductor device. 5. A step of preparing a semiconductor device in which a semiconductor chip is mounted on a front surface of a printed wiring board, and an external connection terminal including a conductive pin and a bump is formed on a back surface of the printed wiring board; A first land to which the conductive pin is connected, and a second land to which the bump is connected to a peripheral portion of the first land via an insulating layer, wherein an external connection electrode of the semiconductor device is provided. A step of preparing a mounting wiring board on which a substrate electrode corresponding to the above is formed; a step of applying a flux to the external connection terminal or a board electrode of the mounting wiring board corresponding to the external connection terminal; Connecting the substrate electrode and the substrate electrode by reflow.