JPH0677284A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0677284A JPH0677284A JP4228798A JP22879892A JPH0677284A JP H0677284 A JPH0677284 A JP H0677284A JP 4228798 A JP4228798 A JP 4228798A JP 22879892 A JP22879892 A JP 22879892A JP H0677284 A JPH0677284 A JP H0677284A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- semiconductor device
- semiconductor element
- insulating tape
- bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、例えばバンプ状電極を
有する半導体素子を備えた半導体装置に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a semiconductor element having, for example, bump electrodes.
【０００２】[0002]
【従来の技術】従来の半導体装置を図４を参照しながら
説明する。同図において、１はダイパッド２上に固定さ
れた半導体素子、３はこの半導体素子１の表面に形成さ
れた電極１Ａとリードフレーム４とを電気的に接続する
金線ワイヤー等の金属配線、５は上記半導体素子１、ダ
イパッド２、金属配線３及びリードフレーム４のインナ
ーリード部を封止する樹脂モールドである。2. Description of the Related Art A conventional semiconductor device will be described with reference to FIG. In the figure, 1 is a semiconductor element fixed on a die pad 2, 3 is a metal wiring such as a gold wire wire for electrically connecting an electrode 1A formed on the surface of the semiconductor element 1 and a lead frame 4, 5 Is a resin mold for sealing the semiconductor element 1, the die pad 2, the metal wiring 3, and the inner lead portion of the lead frame 4.
【０００３】そして、従来の上記構成を有する半導体装
置を製造するには、金属系のロー材あるいは樹脂系のロ
ー材などを用いて半導体素子１をダイパッド２上に載置
固定した後、半導体素子１の電極１Ａとリードフレーム
４のインナーリード部とを金属配線３によって電気的に
接続し、然る後、これらの各部材を樹脂モールド５によ
って密封することによって半導体装置を製造するように
している。In order to manufacture the conventional semiconductor device having the above-mentioned structure, the semiconductor element 1 is mounted and fixed on the die pad 2 by using a metal-based brazing material or a resin-based brazing material. The electrode 1A of No. 1 and the inner lead portion of the lead frame 4 are electrically connected by the metal wiring 3, and thereafter, these respective members are sealed with the resin mold 5 to manufacture the semiconductor device. .
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、従来の
半導体装置は、上述のように、ダイパッド２上に固定さ
れた半導体素子１とその周囲に位置するリードフレーム
４とを金属配線３によって接続し、しかもこれらの各部
材を樹脂モールド５によって封止してその大きさが半導
体素子１よりもかなり大きなサイズになるため、このよ
うな半導体装置を基板に実装すると、１個の半導体装置
が基板上で占めるスペースが広くなって半導体装置の実
装密度を高めることができず、延いては近年益々小型化
する電子機器の需要に応えられないという課題があっ
た。また、従来の半導体装置をリードフレームを介して
基板上に実装した場合、温度サイクルをかけると、温度
によるリードフレームと基板との間に熱膨張差を生じ、
このような熱膨張を繰り返すことによってこれら両者間
に熱的なストレスを生じてリードフレーム４と基板（図
示せず）との接合部が損傷するなどして電気的信頼性が
低下するという課題があった。However, in the conventional semiconductor device, as described above, the semiconductor element 1 fixed on the die pad 2 and the lead frame 4 located around the semiconductor element 1 are connected by the metal wiring 3. Moreover, since each of these members is sealed by the resin mold 5 and has a size considerably larger than the semiconductor element 1, when such a semiconductor device is mounted on the substrate, one semiconductor device is mounted on the substrate. There has been a problem that the space occupied by the semiconductor device cannot be increased and the packaging density of the semiconductor device cannot be increased, and thus the demand for electronic devices which are becoming smaller and smaller in recent years cannot be met. Further, when a conventional semiconductor device is mounted on a substrate via a lead frame, a temperature cycle causes a thermal expansion difference between the lead frame and the substrate due to temperature,
By repeating such thermal expansion, thermal stress is generated between the two, and the joint between the lead frame 4 and the substrate (not shown) is damaged, which lowers the electrical reliability. there were.
【０００５】本発明は、上記課題を解決するためになさ
れたもので、半導体装置の大きさを半導体素子の大きさ
と略同レベルの大きさに小型化してその実装密度を格段
に高めることができ、しかも温度サイクルによる影響を
受けず信頼性の高い半導体装置を提供することを目的と
している。The present invention has been made in order to solve the above problems, and the size of a semiconductor device can be reduced to a size substantially equal to the size of a semiconductor element, and the packaging density can be significantly increased. Moreover, it is an object of the present invention to provide a highly reliable semiconductor device which is not affected by the temperature cycle.
【０００６】[0006]
【課題を解決するための手段】本発明の半導体装置は、
表面に形成された第１の電極を有する半導体素子と、こ
の半導体素子の第１の電極に対応させて表面に形成され
た第２の電極、この第２の電極の反対側の面に形成され
た実装用電極及びこれら両電極を電気的に接続するよう
に形成された配線をそれぞれ有する絶縁テープとを備
え、上記第１の電極と上記第２の電極とを電気的に接合
して構成されたものである。The semiconductor device of the present invention comprises:
A semiconductor element having a first electrode formed on the surface, a second electrode formed on the surface corresponding to the first electrode of the semiconductor element, and formed on a surface opposite to the second electrode. A mounting electrode and an insulating tape each having wiring formed so as to electrically connect the both electrodes, and the first electrode and the second electrode are electrically joined to each other. It is a thing.
【０００７】[0007]
【作用】本発明によれば、半導体素子の第１の電極を絶
縁テープの第２の電極に電気的に接合すれば、この半導
体素子の第１の電極を絶縁テープの第２の電極及び配線
を介して絶縁テープの裏面に位置する実装用電極に電気
的に接続することができ、半導体装置の実装スペースを
略半導体素子のスペース分だけで済ますことができる。According to the present invention, when the first electrode of the semiconductor element is electrically joined to the second electrode of the insulating tape, the first electrode of the semiconductor element is connected to the second electrode of the insulating tape and the wiring. It is possible to electrically connect to the mounting electrode located on the back surface of the insulating tape via the, and the mounting space of the semiconductor device can be substantially the space for the semiconductor element.
【０００８】[0008]
【実施例】以下、図１〜図３に示す実施例に基づいて本
発明を説明する。尚、各図中、図１は本発明の半導体装
置の一実施例を示す図で、同図（ａ）はその側面図、同
図（ｂ）はその平面図、図２は本発明の半導体装置の他
の実施例を示す図で、同図（ａ）はその側面図、同図
（ｂ）はその平面図、図３は本発明の半導体装置の更に
他の実施例を示す側面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on the embodiments shown in FIGS. 1 is a diagram showing an embodiment of the semiconductor device of the present invention. FIG. 1 (a) is a side view thereof, FIG. 1 (b) is a plan view thereof, and FIG. 2 is a semiconductor device of the present invention. FIG. 3 is a view showing another embodiment of the device, FIG. 3A is a side view thereof, FIG. 3B is a plan view thereof, and FIG. 3 is a side view showing still another embodiment of the semiconductor device of the present invention. is there.
【０００９】実施例１．本実施例の半導体装置は、図１
に示すように、表面に形成された第１の電極であるバン
プ状電極１１Ａを有する半導体素子１１と、この半導体
素子１１のバンプ状電極１１Ａに対応させて表面に形成
された第２の電極である電極１２Ａ、この電極１２Ａの
反対側の面、即ち裏面に形成された実装用電極１２Ｂ及
びこれら両電極１２Ａ、１２Ｂを電気的に接続するよう
に形成された金属配線１２Ｃをそれぞれ有する絶縁テー
プ１２とを備え、上記バンプ状電極１１Ａと上記電極１
２Ａとは電気的に接合されて構成されている。Embodiment 1. The semiconductor device of this embodiment is shown in FIG.
As shown in, a semiconductor element 11 having a bump-shaped electrode 11A which is a first electrode formed on the surface and a second electrode formed on the surface corresponding to the bump-shaped electrode 11A of the semiconductor element 11 are formed. An insulating tape 12 having a certain electrode 12A, a mounting electrode 12B formed on the surface opposite to the electrode 12A, that is, a back surface, and a metal wiring 12C formed so as to electrically connect both electrodes 12A, 12B. And the bump-shaped electrode 11A and the electrode 1
It is configured to be electrically joined to 2A.
【００１０】即ち、上記バンプ状電極１１Ａは、図１
（ａ）、（ｂ）に示すように、上記半導体素子１１に形
成された回路の電極取り出し部分に表面から突出させた
金属によって複数形成され、また、上記電極１２Ａは上
記絶縁テープ１２の表面にバンプ状電極１１Ａに対応さ
せて複数形成され、これらの両電極１１Ａ、１２Ａはそ
れぞれ加熱圧着、超音波等を印加することによってこれ
らの電極１１Ａ、１２Ａの少なくとも一方を溶融させて
電気的に接続されている。また、上記実装用電極１２Ｂ
は上記絶縁テープ１２の表面から裏面へ貫通し裏面から
突出するように形成されている。そして、この実装用電
極１２Ｂは上記絶縁テープ１２の表面に形成された金属
配線１２Ｃを介して電極１２Ａに電気的に接続されてい
る。That is, the bump-shaped electrode 11A is as shown in FIG.
As shown in (a) and (b), a plurality of electrodes 12A are formed on the surface of the insulating tape 12 at the electrode lead-out portion of the circuit formed in the semiconductor element 11, and the electrodes 12A are formed on the surface of the insulating tape 12. A plurality of electrodes 11A and 12A are formed corresponding to the bump-shaped electrodes 11A, and these electrodes 11A and 12A are electrically connected by melting at least one of the electrodes 11A and 12A by applying thermocompression bonding or ultrasonic waves. ing. In addition, the mounting electrode 12B
Are formed so as to penetrate from the front surface to the back surface of the insulating tape 12 and project from the back surface. The mounting electrode 12B is electrically connected to the electrode 12A via a metal wiring 12C formed on the surface of the insulating tape 12.
【００１１】従って、上記半導体装置を基板（図示せ
ず）に実装する際には、実装用電極１２Ｃを基板の対応
箇所に接続することによって簡単に実装することができ
る。Therefore, when the semiconductor device is mounted on a substrate (not shown), it can be easily mounted by connecting the mounting electrodes 12C to corresponding portions of the substrate.
【００１２】以上説明したように本実施例によれば、半
導体素子１１の表面に形成されたバンプ状電極１１Ａを
絶縁テープ１２の表面に形成された電極１２Ａに電気的
に接続することによって半導体装置を構成することがで
きるため、絶縁テープ１２の実装用電極１２Ｃの位置を
適宜設定することによって半導体装置の占めるスペース
を半導体素子１１の占めるスペースと略同レベルの大き
さの半導体装置を作製することができ、延いては従来の
半導体装置に比べてその実装面積を格段に省スペース化
することができ、その実装密度を高めることができる。As described above, according to the present embodiment, the bump-shaped electrode 11A formed on the surface of the semiconductor element 11 is electrically connected to the electrode 12A formed on the surface of the insulating tape 12 to form a semiconductor device. Therefore, by appropriately setting the position of the mounting electrode 12C of the insulating tape 12, the space occupied by the semiconductor device can be manufactured to be approximately the same level as the space occupied by the semiconductor element 11. As a result, the mounting area of the semiconductor device can be significantly reduced as compared with the conventional semiconductor device, and the mounting density can be increased.
【００１３】また、本実施例によれば、実装電極１２Ｂ
が絶縁テープ１２に設けられているため、温度サイクル
による半導体装置と基板との熱膨張差があっても、これ
ら両者間の熱的ストレスが絶縁テープ１２によって緩和
されるため基板との接続部の寿命を長くすることがで
き、高い電気的信頼性を保持することができる。Further, according to this embodiment, the mounting electrode 12B is
Since the insulating tape 12 is provided on the insulating tape 12, even if there is a difference in thermal expansion between the semiconductor device and the substrate due to the temperature cycle, the insulating tape 12 relieves the thermal stress between them and the connecting portion of the substrate. The life can be extended and high electrical reliability can be maintained.
【００１４】更に、本実施例によれば、金属配線１２Ｃ
のパターンを適宜変更することによって実装用電極１２
Ｂを任意の位置に設けることができるため、半導体装置
の電極位置の標準化に対応させることができ、半導体素
子１１のバンプ状電極１１Ａが実装用電極１２Ｂの位置
に制約されることがなく、延いては半導体素子１１の電
気的特性を向上させることができる。Further, according to this embodiment, the metal wiring 12C
By appropriately changing the pattern of the mounting electrode 12
Since B can be provided at an arbitrary position, it can correspond to the standardization of the electrode position of the semiconductor device, and the bump-shaped electrode 11A of the semiconductor element 11 is not restricted by the position of the mounting electrode 12B, and can be extended. In addition, the electrical characteristics of the semiconductor element 11 can be improved.
【００１５】実施例２．本実施例の半導体装置は、図２
（ａ）、（ｂ）に示すように、絶縁テープ１２の面積を
半導体素子１１の専有面積に略等しくすると共に、実装
用電極１２Ｂがこの面積内に入るように金属配線１２Ｃ
によって接続した以外は実施例１と同様に構成されてい
る。従って、本実施例によれば、実施例１の場合よりも
実装面積を小さくすることができより高密度実装をする
ことができる他、実施例１と同様の作用効果を期するこ
とができる。Example 2. The semiconductor device of this embodiment is shown in FIG.
As shown in (a) and (b), the area of the insulating tape 12 is made substantially equal to the area occupied by the semiconductor element 11, and the metal wiring 12C is arranged so that the mounting electrode 12B is within this area.
The configuration is the same as that of the first embodiment except that the connection is made by. Therefore, according to the present embodiment, the mounting area can be made smaller than that of the first embodiment, and higher density mounting can be achieved, and the same effect as that of the first embodiment can be expected.
【００１６】実施例３．本実施例の半導体装置は、図３
に示すように、絶縁テープ１２を半導体素子１１より広
く形成すると共にその端部近傍を上方、即ち半導体素子
１１側へ隆起するように湾曲させて隆起部１２Ｄを作
り、端部に実装用電極１２Ｂを設けた以外は上記各実施
例に準じて構成されている。従って、本実施例によれ
ば、絶縁テープ１２の隆起部１２Ｄによって上記各実施
例の場合よりも熱的ストレスをより一層緩和することが
できる他、上記各実施例と同様の作用効果を期すること
ができる。Embodiment 3. The semiconductor device of this embodiment is shown in FIG.
2, the insulating tape 12 is formed wider than the semiconductor element 11, and the vicinity of the end portion is curved upwardly, that is, curved so as to be raised toward the semiconductor element 11 side to form a raised portion 12D, and the mounting electrode 12B is formed at the end portion. It is configured in accordance with each of the above-described examples except that the above is provided. Therefore, according to the present embodiment, the thermal stress can be further alleviated by the raised portion 12D of the insulating tape 12 as compared with the case of each of the above-described embodiments, and the same effect as each of the above-described embodiments is expected. be able to.
【００１７】尚、本発明は、上記各実施例に何等制限さ
れるものではなく、半導体素子のバンプ状電極に対応さ
せて表面に形成された電極、この電極の反対側の面に形
成された実装用電極及びこれら両電極を電気的に接続す
るように形成された配線をそれぞれ有する絶縁テープを
用いた半導体装置であれば、全て本発明に包含される。It should be noted that the present invention is not limited to the above-described embodiments, and the electrode is formed on the surface corresponding to the bump-like electrode of the semiconductor element, and is formed on the surface opposite to the electrode. The present invention includes all semiconductor devices using an insulating tape having mounting electrodes and wirings formed so as to electrically connect these electrodes.
【００１８】[0018]
【発明の効果】以上説明したように本発明によれば、半
導体素子の第１の電極に接続する第２の電極、基板への
実装用電極及びこれら両電極を接続する配線をそれぞれ
一体的に設けた絶縁テープを用いて半導体装置を構成し
たため、半導体装置の大きさを半導体素子の大きさと略
同レベルに小型化して実装密度を格段に高めることがで
き、しかも温度サイクルによる影響を受けず信頼性の高
い半導体装置を提供することができる。As described above, according to the present invention, the second electrode connected to the first electrode of the semiconductor element, the mounting electrode on the substrate, and the wiring connecting these two electrodes are integrally formed. Since the semiconductor device is configured using the provided insulating tape, the size of the semiconductor device can be reduced to about the same level as the size of the semiconductor element, and the packaging density can be significantly increased, and it is reliable without being affected by the temperature cycle. A highly reliable semiconductor device can be provided.
【図１】本発明の半導体装置の一実施例を示す図で、同
図（ａ）はその側面図、同図（ｂ）はその平面図であ
る。1A and 1B are views showing an embodiment of a semiconductor device of the present invention, in which FIG. 1A is a side view thereof and FIG. 1B is a plan view thereof.
【図２】本発明の半導体装置の他の実施例を示す図で、
同図（ａ）はその側面図、同図（ｂ）はその平面図であ
る。FIG. 2 is a diagram showing another embodiment of the semiconductor device of the present invention,
The figure (a) is the side view, and the figure (b) is the top view.
【図３】本発明の半導体装置の更に他の実施例を示す側
面図である。FIG. 3 is a side view showing still another embodiment of the semiconductor device of the present invention.
【図４】従来の半導体装置の一例を示す側面図である。FIG. 4 is a side view showing an example of a conventional semiconductor device.
１１ 半導体素子 １１Ａ バンプ状電極（第１の電極） １２ 絶縁テープ １２Ａ 電極（第２の電極） １２Ｂ 実装用電極 １２Ｃ 金属配線 11 semiconductor element 11A bump-like electrode (first electrode) 12 insulating tape 12A electrode (second electrode) 12B mounting electrode 12C metal wiring
Claims (1)
導体素子と、この半導体素子の上記第１の電極に対応さ
せて表面に形成された第２の電極、この第２の電極の反
対側の面に形成された実装用電極及びこれら両電極を電
気的に接続するように形成された配線をそれぞれ有する
絶縁テープとを備え、上記第１の電極と上記第２の電極
とを電気的に接合してなることを特徴とする半導体装
置。1. A semiconductor element having a first electrode formed on the surface, a second electrode formed on the surface corresponding to the first electrode of the semiconductor element, and the opposite of the second electrode. A mounting electrode formed on the side surface and an insulating tape each having wiring formed so as to electrically connect these two electrodes, and the first electrode and the second electrode are electrically connected. A semiconductor device characterized by being bonded to
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22879892A JP3295457B2 (en) | 1992-08-27 | 1992-08-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22879892A JP3295457B2 (en) | 1992-08-27 | 1992-08-27 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0677284A true JPH0677284A (en) | 1994-03-18 |
| JP3295457B2 JP3295457B2 (en) | 2002-06-24 |
Family
ID=16882025
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22879892A Expired - Fee Related JP3295457B2 (en) | 1992-08-27 | 1992-08-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3295457B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07297236A (en) * | 1994-04-25 | 1995-11-10 | Nec Corp | Film and structure for mounting semiconductor element thereon |
| JPH07321157A (en) * | 1994-05-25 | 1995-12-08 | Nec Corp | Felxible film and semiconductor device equipped with it |
| JPH07326644A (en) * | 1994-05-31 | 1995-12-12 | Nec Corp | Tape carrier and semiconductor device using the same |
-
1992
- 1992-08-27 JP JP22879892A patent/JP3295457B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07297236A (en) * | 1994-04-25 | 1995-11-10 | Nec Corp | Film and structure for mounting semiconductor element thereon |
| JPH07321157A (en) * | 1994-05-25 | 1995-12-08 | Nec Corp | Felxible film and semiconductor device equipped with it |
| US5905303A (en) * | 1994-05-25 | 1999-05-18 | Nec Corporation | Method for manufacturing bump leaded film carrier type semiconductor device |
| JPH07326644A (en) * | 1994-05-31 | 1995-12-12 | Nec Corp | Tape carrier and semiconductor device using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3295457B2 (en) | 2002-06-24 |
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