JPS63229842A - Package for surface mounting - Google Patents
Package for surface mountingInfo
- Publication number
- JPS63229842A JPS63229842A JP6518687A JP6518687A JPS63229842A JP S63229842 A JPS63229842 A JP S63229842A JP 6518687 A JP6518687 A JP 6518687A JP 6518687 A JP6518687 A JP 6518687A JP S63229842 A JPS63229842 A JP S63229842A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- hole
- printed wiring
- package
- pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004020 conductor Substances 0.000 claims abstract description 34
- 239000000463 material Substances 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 14
- 229910000679 solder Inorganic materials 0.000 abstract description 13
- 238000000034 method Methods 0.000 abstract description 9
- 239000000758 substrate Substances 0.000 abstract description 3
- 230000002950 deficient Effects 0.000 abstract 1
- 238000003780 insertion Methods 0.000 description 9
- 230000037431 insertion Effects 0.000 description 8
- 239000000969 carrier Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- 229910000906 Bronze Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000010974 bronze Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、各種の半導体素子を搭載して使用される半導
体パッケージに関し、特にプリント配線板上に高密度に
実装される、チップキャリア型の表面実装用パッケージ
に関するものである。Detailed Description of the Invention (Field of Industrial Application) The present invention relates to semiconductor packages used with various semiconductor elements mounted thereon, and in particular to chip carrier type semiconductor packages that are mounted in high density on printed wiring boards. The present invention relates to a surface mount package.
（従来の技術）
表面実装用パッケージとしては、第４図に示したような
チップキャリア、あるいは第５図に示したようなフラッ
トパッケージが知られている。近年の半導体素子はその
高集積化が進み、それに伴なってこの種の半導体素子を
搭載するためのパッケージについても、多数の入出力端
子が必要とされるようになってきている。(Prior Art) As a surface mounting package, a chip carrier as shown in FIG. 4 or a flat package as shown in FIG. 5 are known. 2. Description of the Related Art In recent years, semiconductor devices have become highly integrated, and as a result, a large number of input/output terminals are required for packages for mounting these types of semiconductor devices.
従来のチップキャリア及びフラットパッケージは、半導
体素子を搭載した基材の外周にしか入出力端子を配列し
ておらず、入出力端子が２００以トのものになると、パ
ッケージが大面積化しプリント配線板に対する実装密度
が低下してしまうという問題があった。このような高端
子数のパッケージについては、第６図に示したようなピ
ングリットアレイか適している。Conventional chip carriers and flat packages have input/output terminals arranged only around the outer periphery of the base material on which the semiconductor element is mounted, and when the number of input/output terminals exceeds 200, the package area becomes large and printed wiring boards are required. There was a problem in that the packaging density for the For such a package with a high number of terminals, a pin grid array as shown in FIG. 6 is suitable.
ところが、ピングリッドアレイにおいては、これが実装
されるプリント配線板には、パッケージに配置された導
体ピンが挿入されるべき多数のスルーホールを有してい
ることが条件となるため、当該プリント配線板に多大な
スルーホール加工を施こさなければならないだけでなく
、当該プリント配線板側の実装密度か多数のスルーホー
ルの分だけ低くなる。However, in a pin grid array, the printed wiring board on which it is mounted must have a large number of through holes into which the conductor pins arranged in the package are inserted. Not only does a large amount of through-hole processing have to be performed on the board, but also the mounting density on the printed wiring board side is lowered by the large number of through-holes.
このような問題と、前述した半導体素子自体の高密度化
に伴なって、プリント配線板の表面に形成した導体回路
に、電子部品を直接接続する表面実装方式が増加してき
ている。In response to these problems and the above-mentioned increase in the density of semiconductor devices themselves, surface mounting methods in which electronic components are directly connected to conductive circuits formed on the surface of printed wiring boards are increasing.
最近、このような表面実装用パッケージにおいて、多数
の入出力端子を設け、高密度な実装を目的とした実装方
法としては、第７図に示したようなチップキャリアの実
装方法が開示されている。Recently, a chip carrier mounting method as shown in FIG. 7 has been disclosed as a mounting method for providing a large number of input/output terminals in such a surface mount package for the purpose of high-density mounting. .
（特開昭６０−４９６９７号公報）
これは、チップキャリア（２１）のプリント配線板（３
１）への接続用導体バッド（２４）を、チップキャリア
（２１）の底面内側に形成したことにより、小形で高密
度な実装を可俺としたものである。(Unexamined Japanese Patent Publication No. 60-49697) This is a printed wiring board (3) of a chip carrier (21).
By forming the conductor pad (24) for connection to 1) on the inside of the bottom surface of the chip carrier (21), compact and high-density packaging is made possible.
しかし、前述のチップキャリアを含め、従来のチップキ
ャリアにおいては、プリント配線板への接続方法に問題
がある。従来の接続方法は、チップキャリアの導体パッ
ドとそれに対応するプリント配線板の導体バットとの間
に、直接半田を溶融させて接続していたため、チップキ
ャリアに搭載された半導体チップの発熱により、チップ
キャリア及びプリント配線板の温度が上昇し、チップキ
ャリアとプリント配線板との熱膨張率及び熱容量の差に
よって、チップキャリアとプリント配線板とを接続して
いる半田に歪を生じ、時間の経過とともにその部分で接
続不良が発生するようになる。このような問題を解決す
るために、第８図に示したようなチップキャリアの実装
方法が開示されている。（特開昭６０−８９９４号公報
）これは、チップキャリア（２１）とプリント配線板（
３１）との間に、接続用半田（２２）より高さあるいは
粒径が小さく、且つ融点が前記半田（２２）より高い金
属部材（２３）を介在させ、チップキャリア（２１）と
プリント配線板（３１）との接続高さを制御したことに
よって、前記半田（２２）にかかる剪断応力を小さくし
、接続不良を減少させたものである。However, conventional chip carriers, including the above-mentioned chip carrier, have problems in the way they are connected to printed wiring boards. The conventional connection method involved directly melting solder between the conductor pads of the chip carrier and the corresponding conductor butts of the printed wiring board. As the temperature of the carrier and the printed wiring board increases, the difference in thermal expansion coefficient and heat capacity between the chip carrier and the printed wiring board causes distortion in the solder connecting the chip carrier and the printed wiring board, and over time A connection failure will occur in that part. In order to solve this problem, a method for mounting a chip carrier as shown in FIG. 8 has been disclosed. (Japanese Unexamined Patent Publication No. 60-8994) This is a chip carrier (21) and a printed wiring board (
A metal member (23) which is smaller in height or grain size than the connecting solder (22) and has a higher melting point than the solder (22) is interposed between the chip carrier (21) and the printed wiring board. By controlling the height of the connection with the solder (31), the shear stress applied to the solder (22) is reduced and connection failures are reduced.
しかしながら、この実装方法において、チップキャリア
とプリント配線板との間に介在させた金属部材は、チッ
プキャリアとプリント配線板との導通を目的としておら
ず、前述した高密度実装の要望に対しては不適であった
。However, in this mounting method, the metal member interposed between the chip carrier and the printed wiring board is not intended for electrical conduction between the chip carrier and the printed wiring board, and it is not possible to meet the above-mentioned demand for high-density mounting. It was inappropriate.
（発明が解決しようとする問題点）
本発明は、前述した２つの問題点、すなわち従来のチッ
プキャリアでは、基材の外周にしか入出力端子を配列し
ていないため、多数の入出力端子を必要とする場合、プ
リント配線板への実装密度が低下してしまうという問題
点と、プリント配線板への実装方法において、従来の方
法ではチップキャリア側の導体パッドとそれに対応する
プリント配線板側の導体パットとを、直接半田により接
合するため、チップキャリアとプリント配線板の熱膨張
率及び熱容量の差によって、半導体チップ動作中の発熱
により接合半田に物理的障害が生じ、接続不良を起こし
やすいという問題点との両方を同時に解５株しようとす
るものである。(Problems to be Solved by the Invention) The present invention solves the two problems mentioned above, namely, in conventional chip carriers, input/output terminals are arranged only on the outer periphery of the base material. If necessary, there is a problem that the mounting density on the printed wiring board decreases, and in the mounting method on the printed wiring board, in the conventional method, the conductor pad on the chip carrier side and the corresponding one on the printed wiring board side are Because the conductor pads are directly joined by solder, the difference in thermal expansion coefficient and heat capacity between the chip carrier and the printed wiring board causes physical damage to the solder joint due to heat generated during semiconductor chip operation, which is likely to cause connection failures. This is an attempt to solve both problems and problems at the same time.
（問題点を解決するための手段）
以上のような問題点を解決するために本発明が採った手
段は、第１図〜第３図に示した実施例に従つて説明する
と、半導体素子（８）を搭載してプリント配線板（１１
）上に実装される表面実装用パッケージであって、この
表面実装用パッケージの基材の、前記プリント配線板（
１１）上に形成された導体パッド（１２）に対応する位
置に、スルホール（４）及び前記基材の端面に位置する
側面スルホール（５）を設け、前記スルホールには前記
導体パッド（１２）に半田接合される面（３ａ）をその
先端に有する導体ピン（３）を挿入し、さらに前記側面
スルホール（５）の底面及び前記導体ピン（３）の先端
に半田バンブを形成することである。(Means for Solving the Problems) The means taken by the present invention to solve the above problems will be explained according to the embodiments shown in FIGS. 1 to 3. 8) and printed wiring board (11).
), the surface mounting package being mounted on the printed wiring board (
11) A through hole (4) and a side through hole (5) located on the end surface of the base material are provided at a position corresponding to the conductor pad (12) formed on the base material, and the through hole has a through hole that corresponds to the conductor pad (12). A conductor pin (3) having a surface (3a) to be soldered is inserted at its tip, and further a solder bump is formed on the bottom of the side through hole (5) and the tip of the conductor pin (3).
（発明の作用）
本発明が以Ｅのような手段を採ることによって以下のよ
うな作用がある。(Actions of the Invention) By adopting the measures described in E below, the present invention has the following effects.
本発明による表面実装用パッケージ（１）は、プリント
配線板（！１）上に形成された導体バッド（１２）に接
合する入出力端子を、ｍ１記表面実装用パッケージ（１
）の外周及びその内側にも設けたことにより、多数の入
出力端子を必要とする表面実装用パッケージにおいて、
小形で高密度な実装が可崗となった。また、本発明によ
る表面実装用パッケージ（１）においては、前記の内側
の入出力端子を、前記表面実装用パッケージにスルホー
ル（４）を設け、とのスルホール（４）に導体ピン（３
）の一部を挿入した構造にすることにより、前記プリン
ト配線板（１１）に￥装した際、当該表面実装用パッケ
ージ（１）は、各導体ピン（３）が外に出た分だけ前記
プリント配線板（１１）とは空間（１３）ができ、これ
により前記表面実装用パッケージ（１）の熱放散性が良
好となり、前記表面実装用パッケージ（１）と前記プリ
ント配線板（１１）との熱膨張率及び熱容贋の差によっ
て生じていた接合半田の歪が小さくなり、その部分での
接続不良が少なくなる。The surface mount package (1) according to the present invention has an input/output terminal connected to a conductor pad (12) formed on a printed wiring board (!1).
) is also provided on the outer periphery and inside it, making it ideal for surface mount packages that require a large number of input/output terminals.
Small size and high-density mounting are now possible. Furthermore, in the surface mount package (1) according to the present invention, a through hole (4) is provided in the surface mount package to connect the inner input/output terminal, and a conductor pin (3) is provided in the through hole (4).
), when mounted on the printed wiring board (11), the surface mount package (1) has a structure in which a portion of the conductor pins (3) are inserted. A space (13) is formed between the printed wiring board (11), which improves the heat dissipation properties of the surface mount package (1), and allows the surface mount package (1) and the printed wiring board (11) to have good heat dissipation properties. The distortion of the joint solder caused by the difference in the coefficient of thermal expansion and thermal capacity of the two is reduced, and the number of connection failures at that part is reduced.
（実施例）
次に、本発明を図面に示した具体的な実施例に基づいて
詳細に説明する。第１図には本発明に係る表面実装用パ
ッケージ（１）の縦断面図か示しである。(Example) Next, the present invention will be described in detail based on a specific example shown in the drawings. FIG. 1 is a longitudinal sectional view of a surface mounting package (1) according to the present invention.
この表面実装用パッケージ（１）は、基材（７）にスル
ーホール（４）と側面スルーホール（５）を形成し、前
記スルーホール（４）には導体ピン（３）を挿入し、前
記側面スルーホール（５）の底面及び前記導体ピン（３
）の先端にバンブ（２）を形成したものである。This surface mount package (1) has a through hole (4) and a side through hole (5) formed in a base material (7), a conductor pin (3) is inserted into the through hole (4), and a conductor pin (3) is inserted into the through hole (4). The bottom of the side through hole (5) and the conductor pin (3)
) with a bump (2) formed at the tip.
実施例１
ｔ５１図において、基材（７）は、ガラスエポキシ基板
を使用し、導体ピン（３）は、リン青銅によって形成し
たものを使用した。この導体ピン（３）は、第２図（Ａ
）に示したように、基材（７）側の各スルーホール（４
）に挿入されるための挿入部（３Ｃ）と、ピン中央付近
には、前記挿入ｆｆ１ｉ（３Ｃ）より大径の鍔（３ｂ）
、さらにプリント配線板（１１）上に形成された導体パ
ッド（１２）に半田接合されるための接合面（３ａ）か
らなっている。前記挿入部（３Ｃ）には、前記スルーホ
ール（４）へ容易に挿入するために、テーパー面を施し
た。前記鍔（３ｂ）は、前記挿入部（３Ｃ）より大径で
あるため、前記スルーホール（４）に前記導体ピン（３
）を挿入した際に、前記鍔（３ｂ）により前記導体ピン
（３）が係止され、第３図に示した空間（１３）の分だ
け前記基材（７）はプリント配線板（１１）から離れた
構造となる。バンプ（２）は、本実施例において、５ｎ
６０％の溶融半田に浸漬することによって形成したもの
である。Example 1 In the t51 diagram, the base material (7) used was a glass epoxy board, and the conductor pins (3) were made of phosphor bronze. This conductor pin (3) is
), each through hole (4) on the base material (7) side
), and a collar (3b) with a larger diameter than the insertion ff1i (3C) near the center of the pin.
, and further comprises a bonding surface (3a) for being soldered to a conductive pad (12) formed on a printed wiring board (11). The insertion portion (3C) was provided with a tapered surface for easy insertion into the through hole (4). Since the collar (3b) has a larger diameter than the insertion portion (3C), the conductor pin (3) is inserted into the through hole (4).
), the conductor pin (3) is locked by the collar (3b), and the base material (7) is inserted into the printed wiring board (11) by the space (13) shown in FIG. The structure is separated from the In this example, the bump (2) is 5n
It was formed by immersion in 60% molten solder.
実施例２
第１図において基材（７）は、ガラストリアジン基板を
使用し、導体ピン（３）は、コバールによって形成した
ものを使用した。この導体ピン（３）は、第２図ＣＢ）
に示したように、基材（７）側の各スルーホール（４）
に挿入されるための挿入部（３ｃ）と、前記挿入部（３
ｃ）より大径の支柱部（３ｄ）からなっており、この支
柱部（３ｄ）の図示下側面（３ａ）が接合面となってい
る。バンプ（２）は、実施例１と同様にして形成したも
のである。Example 2 In FIG. 1, the base material (7) used was a glass triazine substrate, and the conductor pins (3) were made of Kovar. This conductor pin (3) is
As shown, each through hole (4) on the base material (7) side
an insertion section (3c) to be inserted into the insertion section (3c);
c) It consists of a pillar part (3d) with a larger diameter, and the lower side surface (3a) of this pillar part (3d) in the figure serves as a joint surface. The bump (2) was formed in the same manner as in Example 1.
実施例３
第１図において基材（７）は、ガラスポリイミド基板を
使用し、導体ピン（３）は、４２７０イによって形成し
たものを使用した。この導体ピン（コ）は、第２図（Ｃ
）に示したように、基材（７）側の各スルーホール（４
）に挿入されるための挿入部（３ｃ）と、前記挿入部（
３ｃ）より大径の支柱部（３ｅ）からなっており、この
支柱部（３ｅ）の図示下側面（３ａ）か接合面となって
いる。ハンプ（２）は、実施例１と同様にして形成した
ものである。Example 3 In FIG. 1, the base material (7) used was a glass polyimide substrate, and the conductor pins (3) were made of 4270I. This conductor pin (C) is
), each through hole (4) on the base material (7) side
), an insertion portion (3c) for being inserted into the insertion portion (
3c) It consists of a support portion (3e) having a larger diameter, and the lower side surface (3a) in the figure of this support portion (3e) is the joint surface. The hump (2) was formed in the same manner as in Example 1.
（発明の効果）
第３図は、本発明による表面実装用パッケージ（１）に
、半導体素子（８）をダイボンディング及びワイヤーボ
ンディングを経てエポキシ樹脂（１０）で封市した状態
の表面実装用パッケージを、プリント配線板（ｉｔ）に
実装した状態の縦断面図である。(Effects of the Invention) FIG. 3 shows a surface mount package (1) according to the present invention in which a semiconductor element (8) is sealed with an epoxy resin (10) through die bonding and wire bonding. FIG. 2 is a vertical cross-sectional view of the device mounted on a printed wiring board (IT).
第３図に示したように、本発明による表面実装用パッケ
ージ（１）とプリント配線板（１１）とは、前記導体ピ
ン（３）を介して空間（１３）が形成され、この空間（
１３）により半導体素子（８）の動作中に発生する熱を
放散しやすくするため、前記表面実装用パッケージ（１
）と前記プリント配線板との熱膨張率及び熱容量の差に
よって生じる接合部（１４）での歪による接続不良か少
なくなり、高信頼度の表面実装を行うことができろ。ま
た、表面実装用パッケージ（１）をプリント配線板（１
１）に半田接合によって実装した場合、そのフラックス
やフラックス残渣の除去が容易にてきる。さらに、本発
明による表面実装用パッケージにおいては、入出力端子
を基材（７）の外周だけでなく、その内側にも配置した
ことによって、多数の入出力端子を必要とするパッケー
ジにおいても表面実装が可能となった。As shown in FIG. 3, a space (13) is formed between the surface mount package (1) and the printed wiring board (11) according to the present invention through the conductor pins (3).
13) to facilitate the dissipation of heat generated during the operation of the semiconductor element (8).
) and the printed wiring board due to the difference in thermal expansion coefficient and heat capacity, there will be fewer connection failures due to distortion at the joint (14), and highly reliable surface mounting can be performed. In addition, the surface mount package (1) is attached to the printed wiring board (1).
When mounting in 1) by soldering, the flux and flux residue can be easily removed. Furthermore, in the surface mount package according to the present invention, since the input/output terminals are arranged not only on the outer periphery of the base material (7) but also on the inside thereof, it is possible to use the surface mount package in a package that requires a large number of input/output terminals. became possible.
第１図は本発明による表面実装用パッケージの縦断面図
、第２図（Ａ）はこの表面実装用パッケージに使用され
る導体ピンの拡大斜視図、第２図（Ｂ）はこの表面実装
用パッケージに使用される別の導体ピンの拡大斜視図、
第２図（Ｃ）はこの表面実装用パッケージに使用される
さらに別の導体ピンの拡大斜視図、第３図は本発明によ
る表面実装用パッケージに半導体素子を搭載しプリント
配線板に実装した状態の縦断面図、第４図〜第６図は従
来のパッケージをそれぞれ示す縦断面図、第７図及び第
８図はそれぞれ従来のチップキャリア搭載方法の一実施
例を示す縦断面図である。
符号の説明
（１）・・・本発明による表面実装用パッケージ、（２
）、（２２）・・・半田、（３）導体ピン、（３ａ ）
＝接合面、（３ｂ ）−・・鍔、 （３ｃ）＝−挿入
部、（：１ｄ）（３ｅ）・・・支柱部、（４）・・・ス
ルーホール、（５）・・・側面スルーホール、（６）・
・・半導体搭載用凹部、（７）・・・基材、（８）−・
・半導体素子、（９）・・・ボンディングワイヤー、（
１０） −・・封ＩＥ用エポキシ樹脂、（１１）、（：
１１）・・・プリント配線板、（１２）、（２４） 、
（：１２）・・・導体バッド、（Ｉ３）・・・空間、（
１４）・・・接合部、（２１）−・・チップキャリア、
（２３）・・・金属部材。
第４図
第５図
第６図
第７図 第８図FIG. 1 is a vertical cross-sectional view of a surface mount package according to the present invention, FIG. 2 (A) is an enlarged perspective view of a conductor pin used in this surface mount package, and FIG. 2 (B) is a An enlarged perspective view of different conductor pins used in the package,
FIG. 2(C) is an enlarged perspective view of yet another conductor pin used in this surface mount package, and FIG. 3 is a state in which a semiconductor element is mounted on the surface mount package according to the present invention and mounted on a printed wiring board. FIGS. 4 to 6 are longitudinal sectional views showing a conventional package, and FIGS. 7 and 8 are longitudinal sectional views showing an example of a conventional chip carrier mounting method, respectively. Explanation of symbols (1)...Surface mounting package according to the present invention, (2
), (22)...solder, (3) conductor pin, (3a)
= joint surface, (3b) - tsuba, (3c) = -insertion part, (:1d) (3e) - pillar part, (4) - through hole, (5) - side through hole Hall, (6)・
・・Semiconductor mounting recess, (7) ・Base material, (8) −・
・Semiconductor element, (9)...bonding wire, (
10) - Epoxy resin for sealing IE, (11), (:
11)...Printed wiring board, (12), (24),
(:12)...Conductor pad, (I3)...Space, (
14)...Joint part, (21)-...Chip carrier,
(23)...Metal member. Figure 4 Figure 5 Figure 6 Figure 7 Figure 8
Claims (1)
面実装用パッケージであって、この表面実装用パッケー
ジの基材の、前記プリント配線板上に形成された導体回
路の接続部に対応する位置に、スルーホールと前記基材
の端面に位置する側面スルホールを設け、前記スルーホ
ールには接合される面をその先端に有する導体ピンを挿
入し、前記側面スルーホールの底面及び前記導体ピンの
先端にバンプを形成したことを特徴とする表面実装用パ
ッケージ。A surface mount package that is mounted with a semiconductor element and mounted on a printed wiring board, and a position of a base material of this surface mount package that corresponds to a connection part of a conductor circuit formed on the printed wiring board. A through hole and a side through hole located on the end surface of the base material are provided, a conductor pin having a surface to be joined at its tip is inserted into the through hole, and the bottom surface of the side through hole and the tip of the conductor pin are inserted into the through hole. A surface mount package characterized by having bumps formed on the surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62065186A JPH0777243B2 (en) | 1987-03-19 | 1987-03-19 | Surface mount package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62065186A JPH0777243B2 (en) | 1987-03-19 | 1987-03-19 | Surface mount package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63229842A true JPS63229842A (en) | 1988-09-26 |
| JPH0777243B2 JPH0777243B2 (en) | 1995-08-16 |
Family
ID=13279637
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62065186A Expired - Lifetime JPH0777243B2 (en) | 1987-03-19 | 1987-03-19 | Surface mount package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0777243B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02102738U (en) * | 1989-01-31 | 1990-08-15 | ||
| JPH0438873A (en) * | 1990-06-04 | 1992-02-10 | Sharp Corp | Color sensor |
| JPH07226457A (en) * | 1994-01-28 | 1995-08-22 | Internatl Business Mach Corp <Ibm> | Electronic package and its preparation |
| JPH098168A (en) * | 1995-06-21 | 1997-01-10 | Nec Corp | Semiconductor device |
| EP1776001A2 (en) * | 1997-01-30 | 2007-04-18 | Ibiden Co., Ltd. | Printed wiring board and manufacturing method therefor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49123271A (en) * | 1973-03-28 | 1974-11-26 | ||
| JPS51132765A (en) * | 1975-05-14 | 1976-11-18 | Hitachi Ltd | Semiconductor device |
-
1987
- 1987-03-19 JP JP62065186A patent/JPH0777243B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49123271A (en) * | 1973-03-28 | 1974-11-26 | ||
| JPS51132765A (en) * | 1975-05-14 | 1976-11-18 | Hitachi Ltd | Semiconductor device |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02102738U (en) * | 1989-01-31 | 1990-08-15 | ||
| JPH0438873A (en) * | 1990-06-04 | 1992-02-10 | Sharp Corp | Color sensor |
| JPH07226457A (en) * | 1994-01-28 | 1995-08-22 | Internatl Business Mach Corp <Ibm> | Electronic package and its preparation |
| JP3057477B2 (en) * | 1994-01-28 | 2000-06-26 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Electronic package and manufacturing method thereof |
| JPH098168A (en) * | 1995-06-21 | 1997-01-10 | Nec Corp | Semiconductor device |
| EP1776001A2 (en) * | 1997-01-30 | 2007-04-18 | Ibiden Co., Ltd. | Printed wiring board and manufacturing method therefor |
| EP1776001A3 (en) * | 1997-01-30 | 2007-06-06 | Ibiden Co., Ltd. | Printed wiring board and manufacturing method therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0777243B2 (en) | 1995-08-16 |
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