JPH098168A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH098168A JPH098168A JP7154845A JP15484595A JPH098168A JP H098168 A JPH098168 A JP H098168A JP 7154845 A JP7154845 A JP 7154845A JP 15484595 A JP15484595 A JP 15484595A JP H098168 A JPH098168 A JP H098168A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- mounting
- solder
- insulating substrate
- stud
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、外部端子である球状の
半田バンプがパッケージ底面に格子上に配置される表面
実装型のＢＧＡタイプの半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface mount type BGA type semiconductor device in which spherical solder bumps, which are external terminals, are arranged in a grid on the bottom surface of a package.
【０００２】[0002]
【従来の技術】従来の半導体装置には、高集積化に対応
した表面実装型のパッケージとして、ＬＣＣ（リードレ
スチップキャリア）、フラットパッケージ、ＰＧＡ（ピ
ングリッドアレイ）、ＢＧＡ（ボールグリッドアレイ）
などが知られている。これら表面実装型のパッケージの
うち、ＢＧＡタイプの半導体装置は、球状の半田バンプ
からなる多数の外部端子がパッケージ底面に格子状に配
置された形状をなしており、実装する基板にスルーホー
ルを形成する必要がないため、より高密度な実装が要求
される場合などで使用されている。ここでは、このＢＧ
Ａタイプの半導体装置を例にして従来の半導体装置につ
いて説明する。2. Description of the Related Art Conventional semiconductor devices include LCCs (leadless chip carriers), flat packages, PGAs (pin grid arrays), and BGAs (ball grid arrays) as surface mount type packages compatible with high integration.
Etc. are known. Among these surface mount packages, the BGA type semiconductor device has a shape in which a large number of external terminals composed of spherical solder bumps are arranged in a grid pattern on the bottom surface of the package, and through holes are formed on a substrate to be mounted. Since it is not necessary to do so, it is used when higher density mounting is required. Here, this BG
A conventional semiconductor device will be described by taking an A type semiconductor device as an example.
【０００３】図４は従来の半導体装置の構成を示す断面
図である。また、図５は図４に示した半導体装置を基板
に実装したときの様子を示す図であり、同図（ａ）は半
田バンプの拡大断面図、同図（ｂ）は半田バンプがつぶ
れた様子を示す拡大断面図である。FIG. 4 is a sectional view showing the structure of a conventional semiconductor device. 5A and 5B are diagrams showing a state in which the semiconductor device shown in FIG. 4 is mounted on a substrate. FIG. 5A is an enlarged cross-sectional view of the solder bump, and FIG. 5B is a crushed solder bump. It is an expanded sectional view showing a situation.
【０００４】図４において、ＢＧＡタイプの半導体装置
は、任意の機能を有する回路等が形成された半導体素子
１０１が絶縁基板１０２上にマウント材１０３によって
接着固定されている。絶縁基板１０２の上面には導電配
線１０６が形成され、半導体素子１０１上に設けられた
パッド（不図示）と絶縁基板１０２上の導電配線１０６
とがそれぞれボンディングワイヤ１０４によって電気的
に接続されている。また、ボンディングワイヤ１０４に
よって導電配線１０６と接続された半導体素子１０１は
モールド樹脂１０５によって封止されている。導電配線
１０６はそれぞれ絶縁基板１０２の上面から底面に渡っ
て形成されたスルーホール１０７に接続され、スルーホ
ール１０７を介して絶縁基板１０２の底面に導出されて
いる。絶縁基板１０２の底面に導出された導電配線１０
６は格子状に配置された外部端子用パッド１０８にそれ
ぞれ配線され、外部端子用パッド１０８には、あらかじ
め定められた径で加工された球状の半田バンプ１０９が
それぞれリフローによって融着されている。In FIG. 4, in a BGA type semiconductor device, a semiconductor element 101 on which a circuit having an arbitrary function is formed is adhesively fixed to an insulating substrate 102 by a mount material 103. Conductive wiring 106 is formed on the upper surface of the insulating substrate 102, and pads (not shown) provided on the semiconductor element 101 and the conductive wiring 106 on the insulating substrate 102 are formed.
And are electrically connected by a bonding wire 104. The semiconductor element 101 connected to the conductive wiring 106 by the bonding wire 104 is encapsulated by the mold resin 105. The conductive wirings 106 are respectively connected to through holes 107 formed from the upper surface to the bottom surface of the insulating substrate 102, and led out to the bottom surface of the insulating substrate 102 via the through holes 107. Conductive wiring 10 led out to the bottom surface of the insulating substrate 102
6 are respectively wired to external terminal pads 108 arranged in a grid pattern, and spherical solder bumps 109 processed to have a predetermined diameter are fused to the external terminal pads 108 by reflow.
【０００５】ここで、スルーホール１０７は０．２〜
０．３ｍｍの径で形成され、そのランド径は０．４〜
０．５ｍｍで形成されている。また、半田バンプ１０９
には約０．７６ｍｍの直径で球状に加工された鉛錫共晶
半田が用いられ、銀の混入や鉛の割合の増減によって溶
解温度が１８３℃から２００℃の範囲に設定されてい
る。Here, the through hole 107 is 0.2 to
It is formed with a diameter of 0.3 mm and the land diameter is 0.4 ~
It is formed with 0.5 mm. In addition, the solder bump 109
A lead-tin eutectic solder that is spherically processed with a diameter of about 0.76 mm is used as the soldering material, and the melting temperature is set in the range of 183 ° C. to 200 ° C. by mixing silver and increasing or decreasing the proportion of lead.
【０００６】このような構成において、従来のＢＧＡタ
イプの半導体装置を実装する際には、実装基板１１３上
の半導体装置の各半田バンプ１０９に対応する位置に、
それぞれ半田ペーストを印刷塗布して実装用パッド１１
２を形成し、その上に半導体装置をリフローによって実
装する。このとき、球状の半田バンプ１０９と実装用パ
ッド１１２とは互いに溶融して混ざり合い、図５（ａ）
に示すような形状となる。この接続部分の高さは実装用
パッド１１２の径や、供給する半田ペーストの量によっ
て、実装前の半田バンプ１０９の高さの約半分から３分
の２程度になる。また、半導体装置の重量の片寄り、あ
るいはリフロー時の振動、傾き、エアーの当たり具合等
によって半導体装置の取付け高さに片寄りが生じた場
合、接続部分は図５（ｂ）に示すように潰れた形状にな
る。With such a structure, when a conventional BGA type semiconductor device is mounted, the mounting substrate 113 is mounted at a position corresponding to each solder bump 109 of the semiconductor device.
Solder paste is printed and applied to each of the mounting pads 11
2 is formed, and the semiconductor device is mounted thereon by reflow. At this time, the spherical solder bumps 109 and the mounting pads 112 are melted and mixed with each other, as shown in FIG.
The shape is as shown in. The height of this connection portion is about half to two-thirds of the height of the solder bump 109 before mounting, depending on the diameter of the mounting pad 112 and the amount of solder paste supplied. Further, when the weight of the semiconductor device is deviated, or the mounting height of the semiconductor device is deviated due to vibration, inclination, air hitting at the time of reflow, etc., the connection portion is as shown in FIG. 5B. It becomes a crushed shape.
【０００７】ここで、半導体装置が実装されて動作する
場合、半導体装置が発熱することによって実装基板１１
３と半導体装置との接続部分に熱膨張差による応力が働
く。この応力は接続部分が潰れる程大きくなり、実装基
板１１２や半導体装置との境界付近のくびれ１１４に集
中して働き、最悪の場合、接続部分が破断することがあ
る。特に、取付け高さに片寄りがある半導体装置の場
合、その端部やコーナー部では潰れが大きくなって応力
が集中し、破断が起こりやすい。Here, when the semiconductor device is mounted and operates, the mounting substrate 11 is generated by heat generation of the semiconductor device.
Stress due to the difference in thermal expansion acts on the connection portion between the semiconductor device 3 and the semiconductor device. This stress increases as the connection portion is crushed, and acts on the constriction 114 near the boundary between the mounting substrate 112 and the semiconductor device, and in the worst case, the connection portion may break. In particular, in the case of a semiconductor device in which the mounting height is deviated, the edges and corners of the semiconductor device are more likely to be crushed, stress is concentrated, and fracture is likely to occur.
【０００８】これらの不具合を防止するため、一般に実
装基板１１２と半導体装置との熱膨張率を近づけて応力
が小さくなるように設計されるが、構成材料や構造の違
いから熱膨張率を等しくすることは困難である。したが
って、半導体装置の放熱特性を良くして温度上昇を抑え
たり、取付け高さを一定にして熱応力を小さくする等の
対策が採られている。In order to prevent these problems, the mounting substrate 112 and the semiconductor device are generally designed so that the thermal expansion coefficients thereof are close to each other to reduce the stress, but the thermal expansion coefficients are made equal due to the difference in the constituent materials and the structure. Is difficult. Therefore, measures have been taken such as improving the heat dissipation characteristics of the semiconductor device to suppress the temperature rise, and fixing the mounting height to reduce the thermal stress.
【０００９】そこで、これらの対策の具体的方法とし
て、図６に示すように絶縁基板２０２にスルーホール２
０７を設け、このスルーホール２０７に導体ピン２１０
を挿入して、導体ピン２１０を覆うように半田バンプ２
０９を形成する半導体装置が提案されている（特開昭６
３−２２９８４２号公報参照）。Therefore, as a concrete method of these measures, as shown in FIG. 6, the through hole 2 is formed in the insulating substrate 202.
07 is provided, and the conductor pin 210 is provided in the through hole 207.
Insert the solder bumps 2 to cover the conductor pins 210.
A semiconductor device for forming No. 09 has been proposed (Japanese Patent Application Laid-Open No. Sho 6-1994).
(See JP-A-3-229842).
【００１０】このような構成にすると、導体ピンをそれ
ぞれ実装基板に突き当てるように実装することで、実装
基板との間に片寄りのない一定幅の空間を設けることが
できるため、半導体装置の放熱特性が良好になり、半導
体装置と実装する基板との熱膨張差及び熱容量差による
応力が小さくなって接続不良が減少する。With such a structure, by mounting the conductor pins so as to abut the mounting board, a space having a constant width can be provided between the mounting board and the mounting board, so that the semiconductor device can be manufactured. The heat dissipation characteristics are improved, the stress due to the difference in thermal expansion and the difference in heat capacity between the semiconductor device and the substrate to be mounted is reduced, and the connection failure is reduced.
【００１１】[0011]
【発明が解決しようとする課題】しかしながら上記のよ
うな従来の半導体装置では、スルーホールを形成するこ
とにより導体配線の実装面積に制約を受け、多ピン、狭
ピッチ化に対する設計に限界が生じていた。これは、半
導体素子を搭載した部位には導体ピンが配置できないこ
と、およびスルーホールの径がおよそ０．２〜０．５ｍ
ｍであることから、そのランドの径が０．５〜０．８ｍ
ｍになり、導体ピンの配置ピッチを１．２７ｍｍとする
と導体ピン間の配線本数が３本以下に制限されてしまう
ことによる。配線本数を増やすためには導体ピン径を小
さくする方法などが考えられるが、絶縁基板にスルーホ
ールを空けるためのドリル径も小さくなるためスルーホ
ール形成のコストが高くなって実用的でない。However, in the conventional semiconductor device as described above, the through-hole formation restricts the mounting area of the conductor wiring, and there is a limit to the design for a large number of pins and a narrow pitch. It was This is because the conductor pin cannot be arranged in the portion where the semiconductor element is mounted, and the diameter of the through hole is approximately 0.2 to 0.5 m.
Since it is m, the diameter of the land is 0.5 to 0.8 m
This is because when the arrangement pitch of the conductor pins is 1.27 mm, the number of wires between the conductor pins is limited to 3 or less. In order to increase the number of wirings, a method of reducing the diameter of the conductor pin may be considered, but the diameter of the drill for forming a through hole in the insulating substrate is also small, which increases the cost of forming the through hole and is not practical.
【００１２】また、予めスルーホールに導体ピンを挿入
しておく必要があるため、モールド封入機で半導体素子
を封止する際に導体ピンが障害になり、自動機による封
止工程が複雑になっていた。さらに、封止する際に加え
る熱によって導体ピンを固定している半田の溶融や導体
ピンの酸化などの不具合が発生するため、モールド樹脂
による半導体素子の封止が困難であった。Further, since it is necessary to insert the conductor pin into the through hole in advance, the conductor pin becomes an obstacle when the semiconductor element is sealed by the mold encapsulation machine, and the sealing process by the automatic machine becomes complicated. Was there. Further, heat applied during the sealing causes problems such as melting of the solder fixing the conductor pins and oxidation of the conductor pins, which makes it difficult to seal the semiconductor element with the mold resin.
【００１３】また、ＢＧＡに使用される絶縁基板の厚さ
は０．３６ｍｍ、および０．５６ｍｍが主流であり、ス
ルーホールの内壁にメッキされた銅の厚さは十数μｍか
ら３０μｍと一定ではないため、導体ピンを絶縁基板に
垂直に固定することが難しく、ピンの取付け方向の安定
性が悪いという問題もあった。The thickness of the insulating substrate used for the BGA is mainly 0.36 mm and 0.56 mm, and the thickness of the copper plated on the inner wall of the through hole is not constant from a dozen μm to 30 μm. Since it is not present, it is difficult to fix the conductor pin vertically to the insulating substrate, and there is a problem that the stability of the mounting direction of the pin is poor.
【００１４】さらに、実装した半導体装置を何等かの原
因で取り外す必要が生じた場合、導体ピンが半導体装置
の絶縁基板から抜け落ちてしまうため、再実装すること
が不可能であった。Further, when it becomes necessary to remove the mounted semiconductor device for some reason, the conductor pins fall off from the insulating substrate of the semiconductor device, making it impossible to remount the semiconductor device.
【００１５】本発明は上記したような従来の技術が有す
る問題点を解決するためになされたものであり、実装時
の取付け高さを所望する値に維持することで接続部分に
対する応力を減らして取付け不良を防止し、かつ、再実
装することが可能なＢＧＡタイプの半導体装置を提供す
ることを目的とする。The present invention has been made in order to solve the problems of the above-mentioned conventional techniques, and reduces the stress on the connecting portion by maintaining the mounting height at the time of mounting at a desired value. It is an object of the present invention to provide a BGA type semiconductor device capable of preventing mounting failure and remounting.
【００１６】[0016]
【課題を解決するための手段】上記目的を達成するため
本発明の半導体装置は、表面実装型の半導体装置であっ
て、絶縁基板の実装面上に形成された複数のパッドに、
それぞれ前記絶縁基板の実装面に対して直角方向に予め
定められた長さを持つスタッドピンが固定され、前記ス
タッドピンを覆うようにしてそれぞれ球状のはんだバン
プが形成されていることを特徴とする。To achieve the above object, a semiconductor device of the present invention is a surface mount type semiconductor device, wherein a plurality of pads formed on a mounting surface of an insulating substrate are
Stud pins each having a predetermined length in a direction perpendicular to the mounting surface of the insulating substrate are fixed, and spherical solder bumps are formed so as to cover the stud pins. .
【００１７】このとき、前記スタッドピンは前記パッド
にはんだで固定され、前記スタッドピンを固定するはん
だの融点は、前記はんだバンプの融点よりも高くてもよ
く、前記スタッドピンを固定するはんだの融点は２２５
℃以上であることが望ましい。At this time, the stud pin is fixed to the pad with solder, and the melting point of the solder that fixes the stud pin may be higher than the melting point of the solder bump. Is 225
It is desirable that the temperature is not less than ° C.
【００１８】[0018]
【作用】上記のように構成された本発明の半導体装置
は、半導体装置を実装基板上に実装する際、スタッドピ
ンが実装基板にそれぞれ突き当たるように実装される。
スタッドピンは、絶縁基板の実装面に対して直角方向に
予め定められた長さを持っているので、実装基板に対す
る半導体装置の取付け高さを片寄りのない一定の高さに
保持することができる。The semiconductor device of the present invention configured as described above is mounted such that when the semiconductor device is mounted on the mounting board, the stud pins abut the mounting board.
Since the stud pin has a predetermined length in a direction perpendicular to the mounting surface of the insulating substrate, it is possible to maintain the mounting height of the semiconductor device on the mounting substrate at a constant height without deviation. it can.
【００１９】また、スタッドピンを固定するはんだの融
点を、はんだバンプの融点よりも高くすることで、半導
体装置を実装基板に実装する場合や実装した半導体装置
を取り外す場合に、スタッドピンを固定するはんだが溶
融することがない。したがって、スタッドピンが位置ず
れを起こしたり、絶縁基板から外れることがない。Further, by making the melting point of the solder for fixing the stud pin higher than the melting point of the solder bump, the stud pin is fixed when the semiconductor device is mounted on the mounting board or when the mounted semiconductor device is removed. The solder never melts. Therefore, the stud pin will not be displaced and will not come off from the insulating substrate.
【００２０】[0020]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。Next, embodiments of the present invention will be described with reference to the drawings.
【００２１】図１は本発明の半導体装置の構成を示す図
であり、同図（ａ）は装置全体の断面図、同図（ｂ）は
半田バンプの拡大断面図である。また、図２は図１に示
した半導体装置を基板に実装したときの様子を示す要部
拡大断面図である。FIG. 1 is a diagram showing the structure of a semiconductor device of the present invention. FIG. 1 (a) is a sectional view of the entire device, and FIG. 1 (b) is an enlarged sectional view of a solder bump. Further, FIG. 2 is an enlarged cross-sectional view of an essential part showing a state in which the semiconductor device shown in FIG. 1 is mounted on a substrate.
【００２２】図１（ａ）において、絶縁基板２上には、
任意の機能を有する回路等が形成された半導体素子１が
マウント材３によって接着固定されている。絶縁基板２
の上面には導電配線６が形成され、半導体素子１上に設
けられたパッド（不図示）と絶縁基板２上の導電配線６
とがそれぞれボンディングワイヤ４によって電気的に接
続されている。また、ボンディングワイヤ４によって導
電配線６と接続された半導体素子１はモールド樹脂５に
よって封止されている。導電配線６はそれぞれ絶縁基板
２の上面から底面に渡って形成されたスルーホール７に
接続され、スルーホール７を介して絶縁基板２の底面に
導出されている。絶縁基板２の底面に導出された導電配
線６は格子状に配置された外部端子用パッド８にそれぞ
れ配線され、外部端子用パッド８には、それぞれ鉄−ニ
ッケル系合金、銅系合金、または鉛錫系合金によって製
造されたスタッドピン１０が半田によって固定されてい
る。スタッドピン１０は図１（ｂ）に示すように座面を
有した形状であり、この座面によって外部端子用パッド
８に対して直角方向に安定して固定される。In FIG. 1A, on the insulating substrate 2,
The semiconductor element 1 on which a circuit having an arbitrary function is formed is adhesively fixed by a mount material 3. Insulating substrate 2
Conductive wiring 6 is formed on the upper surface of the pad, and the conductive wiring 6 on the insulating substrate 2 and the pad (not shown) provided on the semiconductor element 1 are formed.
And are electrically connected by a bonding wire 4, respectively. Further, the semiconductor element 1 connected to the conductive wiring 6 by the bonding wire 4 is sealed by the mold resin 5. The conductive wirings 6 are respectively connected to through holes 7 formed from the upper surface to the bottom surface of the insulating substrate 2 and led to the bottom surface of the insulating substrate 2 via the through holes 7. The conductive wirings 6 led out to the bottom surface of the insulating substrate 2 are respectively wired to external terminal pads 8 arranged in a grid pattern, and the external terminal pads 8 are respectively provided with an iron-nickel alloy, a copper alloy, or lead. A stud pin 10 made of a tin-based alloy is fixed by solder. The stud pin 10 has a seat surface as shown in FIG. 1B, and is stably fixed to the external terminal pad 8 in a direction perpendicular to the seat surface by the seat surface.
【００２３】また、スタッドピン１０には、球状の半田
バンプ９がそれぞれスタッドピン１０を覆うようにして
設けられており、スタッドピン１０の固定後に転写リフ
ローまたはディッピング等によって形成される。この球
状の半田バンプ９には鉛錫共晶半田が用いられ、銀の混
入や鉛の割合の増減によって溶融温度が１８３〜２００
℃の範囲に設定されている。The stud pins 10 are provided with spherical solder bumps 9 so as to cover the stud pins 10, respectively, and are formed by transfer reflow or dipping after the stud pins 10 are fixed. Lead-tin eutectic solder is used for the spherical solder bumps 9, and the melting temperature is 183 to 200 depending on the mixture of silver and the increase / decrease in the proportion of lead.
It is set in the range of ° C.
【００２４】また、スタッドピン１０を取り付ける外部
端子用パッド８の直径は０．５〜０．８ｍｍであり、予
めニッケル、錫、または半田メッキ等がなされている。
この外部端子用パッド８にスタッドピン１０を取り付け
るための固定用半田１１には、半田バンプ９を形成する
ための半田よりも高い融点を持つ半田が選択され、一般
にリフローの温度が２２５度以下であることから、融点
が２２５度以上のものを用いている。The diameter of the external terminal pad 8 to which the stud pin 10 is attached is 0.5 to 0.8 mm, and nickel, tin, or solder plating or the like is performed in advance.
A solder having a melting point higher than that of the solder for forming the solder bump 9 is selected as the fixing solder 11 for attaching the stud pin 10 to the external terminal pad 8, and generally, when the reflow temperature is 225 degrees or less. Therefore, a material having a melting point of 225 degrees or higher is used.
【００２５】このような構成において、本実施例の半導
体装置を実装する場合、図２に示すようにスタッドピン
１０を実装基板１３の実装用パッド１２にそれぞれ突き
当てるようにして実装する。このとき、スタッドピン１
０の長さをそれぞれ同じにしておけば、実装後の半導体
装置の取付け高さを片寄りのない一定の高さに保持する
ことができる。したがって、半導体装置の放熱特性が向
上し、半導体装置と実装基板１３との接続部分にかかる
応力を軽減させることができるため、接続不良が低減し
て半導体装置の信頼性が向上する。また、スタッドピン
１０を使用することにより従来例のような導体ピンを取
り付けるためのスルーホールが不要になるため、高密度
の配線が可能になる。In the case of mounting the semiconductor device of this embodiment in such a structure, the stud pins 10 are mounted so as to abut against the mounting pads 12 of the mounting substrate 13 as shown in FIG. At this time, stud pin 1
By setting the lengths of 0 to be the same, the mounting height of the semiconductor device after mounting can be maintained at a constant height without deviation. Therefore, the heat dissipation characteristic of the semiconductor device is improved, and the stress applied to the connection portion between the semiconductor device and the mounting substrate 13 can be reduced, so that the connection failure is reduced and the reliability of the semiconductor device is improved. Further, since the use of the stud pins 10 eliminates the need for through holes for attaching the conductor pins as in the conventional example, high density wiring is possible.
【００２６】さらに、スタッドピン１０を取り付けてい
る固定用半田１１の融点が半田バンプ９の融点よりも高
いため、半導体装置を実装する場合や実装した半導体装
置を取り外す場合に固定用半田１１が溶融することな
い。よって、スタッドピン１０の位置ずれや絶縁基板２
からの脱落がなくなる。半田バンプ９の一部は半導体装
置を取り外す際に実装用パッド１２にとられてしまうた
め、元の形状を留めておくことは困難であるが、スタッ
ドピン１０がそのまま残っているため、スタッドピン１
０に半田を補充することで半導体装置の再実装が可能に
なる。Further, since the melting point of the fixing solder 11 to which the stud pin 10 is attached is higher than the melting point of the solder bump 9, the fixing solder 11 melts when mounting the semiconductor device or when removing the mounted semiconductor device. There is nothing to do. Therefore, the displacement of the stud pin 10 and the insulating substrate 2
No more dropping out. It is difficult to keep the original shape because a part of the solder bump 9 is taken off by the mounting pad 12 when the semiconductor device is removed, but the stud pin 10 remains as it is, so 1
By replenishing 0 with solder, the semiconductor device can be remounted.
【００２７】なお、スタッドピンの形状は絶縁基板に固
定する際の姿勢を安定させるために座面を有しているの
が好ましく、図１（ｂ）に示した形状の他に図３（ａ）
に示すような長いピンを有したスタッドピン２０、図３
（ｂ）に示すような略円錐形状のスタッドピン３０、ま
たは図３（ｃ）に示すような糸車形状のスタッドピン３
０などを用いてもよい。The shape of the stud pin preferably has a seat surface for stabilizing the posture when it is fixed to the insulating substrate. In addition to the shape shown in FIG. )
Stud pin 20 with a long pin as shown in FIG. 3, FIG.
A substantially conical stud pin 30 as shown in (b) or a spinning wheel-shaped stud pin 3 as shown in FIG. 3 (c).
You may use 0 etc.
【００２８】また、本実施例ではＢＧＡを例にして説明
したが、ＢＧＡに限らず、リード付き当てタイプのバッ
トリードＰＧＡ（以下Ｂ／ＬＰＧＡと称す）タイプにも
適用することができる。Ｂ／ＬＰＧＡは直径が０．２ｍ
ｍ、長さが２ｍｍ程度の鉄ニッケル系合金、または銅合
金からなるリードピンがパッケージ底面に格子状に配列
されたものである。リードピンには一般に金または半田
がメッキされており、実装する際には、実装後の接続部
分の強度や信頼性を増すため、予備半田を行ってから実
装される。ここで、リードピンに予備半田からなる半田
バンプを設け、リードピンの取り付けを融点の高い半田
で行えば上記ＢＧＡと同様の効果を得ることができる。Further, in the present embodiment, the BGA has been described as an example, but the present invention is not limited to the BGA but can be applied to a butted lead PGA (hereinafter referred to as B / LPGA) type with a lead. B / LPGA has a diameter of 0.2 m
The lead pins made of iron-nickel alloy or copper alloy having a length of m and a length of about 2 mm are arranged in a lattice pattern on the bottom surface of the package. The lead pins are generally plated with gold or solder. When mounting, in order to increase the strength and reliability of the connection portion after mounting, preliminary soldering is performed before mounting. Here, if a solder bump made of preliminary solder is provided on the lead pin and the lead pin is attached with a solder having a high melting point, the same effect as that of the BGA can be obtained.
【００２９】[0029]
【発明の効果】本発明は、以上説明したように構成され
ているので、以下に記載する効果を奏する。Since the present invention is configured as described above, it has the following effects.
【００３０】請求項１に記載のものにおいては、半導体
装置にスタッドピンを設けることで、実装基板に実装し
た半導体装置の取付け高さを片寄りのない一定の高さに
保持することができる。したがって、半導体装置の放熱
特性が向上し、半導体装置と実装基板との接続部分にか
かる応力を軽減させることができるため、接続不良が低
減して信頼性が向上する。また、導体ピンを取り付ける
ためのスルーホールが不要になるため、高密度の配線が
可能になる。According to the first aspect of the present invention, by providing the semiconductor device with the stud pin, the mounting height of the semiconductor device mounted on the mounting board can be maintained at a constant height without deviation. Therefore, the heat dissipation characteristic of the semiconductor device is improved, and the stress applied to the connection portion between the semiconductor device and the mounting substrate can be reduced, so that the connection failure is reduced and the reliability is improved. Further, since a through hole for attaching the conductor pin is not necessary, high density wiring is possible.
【００３１】請求項２および３に記載のものにおいて
は、スタッドピンを固定するはんだの融点をはんだバン
プの融点よりも高くすることで、半導体装置を実装する
場合や実装した半導体装置を取り外す場合にスタッドピ
ンが位置ずれを起こしたり、絶縁基板から外れることが
ない。したがって、半導体装置を取り外してもスタッド
ピンがそのまま残っているため、スタッドピンに半田を
補充することで半導体装置の再実装が可能になる。特
に、請求項３のものにおいては、はんだバンプをリフロ
ーで形成することができる。According to the second and third aspects of the present invention, the melting point of the solder for fixing the stud pin is set higher than the melting point of the solder bump, so that the semiconductor device is mounted or the mounted semiconductor device is removed. The stud pins will not be displaced and will not come off the insulating substrate. Therefore, even if the semiconductor device is removed, the stud pin remains as it is, so that the semiconductor device can be remounted by replenishing the stud pin with solder. Particularly, in the third aspect, the solder bump can be formed by reflow.
【図１】本発明の半導体装置の構成を示す図であり、同
図（ａ）は装置全体の断面図、同図（ｂ）は半田バンプ
の拡大断面図である。FIG. 1 is a diagram showing a configuration of a semiconductor device of the present invention, FIG. 1A is a sectional view of the entire device, and FIG. 1B is an enlarged sectional view of a solder bump.
【図２】図１に示した半導体装置を基板に実装したとき
の様子を示す要部拡大断面図である。FIG. 2 is an enlarged sectional view of an essential part showing a state when the semiconductor device shown in FIG. 1 is mounted on a substrate.
【図３】本発明の半導体装置で使用するスタッドピンの
形状例を示した拡大断面図である。FIG. 3 is an enlarged cross-sectional view showing a shape example of a stud pin used in the semiconductor device of the present invention.
【図４】従来の半導体装置の構成を示す断面図である。FIG. 4 is a sectional view showing a configuration of a conventional semiconductor device.
【図５】図４に示した半導体装置を基板に実装したとき
の様子を示す図であり、同図（ａ）は半田バンプの拡大
断面図、同図（ｂ）は半田バンプがつぶれた様子を示す
拡大断面図である。5A and 5B are diagrams showing a state in which the semiconductor device shown in FIG. 4 is mounted on a substrate. FIG. 5A is an enlarged sectional view of a solder bump, and FIG. 5B is a state in which the solder bump is crushed. It is an expanded sectional view showing.
【図６】従来の熱応力を小さくする対策が採られた半導
体装置の構成を示す断面図である。FIG. 6 is a cross-sectional view showing a configuration of a semiconductor device in which a conventional measure for reducing thermal stress is taken.
１ 半導体素子 ２ 絶縁基板 ３ マウント材 ４ ボンディングワイヤ ５ モールド樹脂 ６ 導電配線 ７ スルーホール ８ 外部端子用パッド ９ 半田バンプ １０、２０、３０、４０ スタッドピン １１ 固定用ハンダ １２ 実装用パッド １３ 実装基板 1 Semiconductor Element 2 Insulating Board 3 Mounting Material 4 Bonding Wire 5 Mold Resin 6 Conductive Wiring 7 Through Hole 8 External Terminal Pad 9 Solder Bumps 10, 20, 30, 40 Stud Pin 11 Fixing Solder 12 Mounting Pad 13 Mounting Board
Claims (3)
ぞれ前記絶縁基板の実装面に対して直角方向に予め定め
られた長さを持つスタッドピンが固定され、 前記スタッドピンを覆うようにしてそれぞれ球状のはん
だバンプが形成されていることを特徴とする半導体装
置。1. A surface-mount type semiconductor device, wherein a plurality of pads formed on a mounting surface of an insulating substrate are provided with predetermined lengths in a direction perpendicular to the mounting surface of the insulating substrate. A semiconductor device having stud pins held therein and spherical solder bumps formed so as to cover the stud pins.
記スタッドピンを固定するはんだの融点は、前記はんだ
バンプの融点よりも高いことを特徴とする半導体装置。2. The semiconductor device according to claim 1, wherein the stud pin is fixed to the pad with solder, and a melting point of the solder fixing the stud pin is higher than a melting point of the solder bump. Semiconductor device.
上であることを特徴とする半導体装置。3. The semiconductor device according to claim 2, wherein the solder for fixing the stud pin has a melting point of 225 ° C. or higher.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7154845A JP2699932B2 (en) | 1995-06-21 | 1995-06-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7154845A JP2699932B2 (en) | 1995-06-21 | 1995-06-21 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH098168A true JPH098168A (en) | 1997-01-10 |
| JP2699932B2 JP2699932B2 (en) | 1998-01-19 |
Family
ID=15593160
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7154845A Expired - Lifetime JP2699932B2 (en) | 1995-06-21 | 1995-06-21 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2699932B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990051221A (en) * | 1997-12-19 | 1999-07-05 | 김영환 | How to Form Solder Balls in a Ball Grid Array Package |
| JP2010012509A (en) * | 2008-07-07 | 2010-01-21 | Honda Motor Co Ltd | Solder joining structure of power unit and its joining method |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109742034A (en) * | 2014-01-26 | 2019-05-10 | 清华大学 | A kind of encapsulating structure, packaging method and the template used in packaging method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63229842A (en) * | 1987-03-19 | 1988-09-26 | Ibiden Co Ltd | Package for surface mounting |
| JPH02102738U (en) * | 1989-01-31 | 1990-08-15 | ||
| JPH07130909A (en) * | 1993-11-04 | 1995-05-19 | Ibiden Co Ltd | Aluminum nitride multi-layer board |
-
1995
- 1995-06-21 JP JP7154845A patent/JP2699932B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63229842A (en) * | 1987-03-19 | 1988-09-26 | Ibiden Co Ltd | Package for surface mounting |
| JPH02102738U (en) * | 1989-01-31 | 1990-08-15 | ||
| JPH07130909A (en) * | 1993-11-04 | 1995-05-19 | Ibiden Co Ltd | Aluminum nitride multi-layer board |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990051221A (en) * | 1997-12-19 | 1999-07-05 | 김영환 | How to Form Solder Balls in a Ball Grid Array Package |
| JP2010012509A (en) * | 2008-07-07 | 2010-01-21 | Honda Motor Co Ltd | Solder joining structure of power unit and its joining method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2699932B2 (en) | 1998-01-19 |
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