JP3305577B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP3305577B2
JP3305577B2 JP16625096A JP16625096A JP3305577B2 JP 3305577 B2 JP3305577 B2 JP 3305577B2 JP 16625096 A JP16625096 A JP 16625096A JP 16625096 A JP16625096 A JP 16625096A JP 3305577 B2 JP3305577 B2 JP 3305577B2
Authority
JP
Japan
Prior art keywords
semiconductor device
semiconductor element
mounting
mounting joint
corners
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP16625096A
Other languages
Japanese (ja)
Other versions
JPH1012763A (en
Inventor
祥司 植垣
伸 松田
歩 岡崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP16625096A priority Critical patent/JP3305577B2/en
Publication of JPH1012763A publication Critical patent/JPH1012763A/en
Application granted granted Critical
Publication of JP3305577B2 publication Critical patent/JP3305577B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は回路基板に対して複
数のほぼ球状の実装用継手端子によりフリップチップ実
装される半導体装置における実装用継手端子の配置利用
に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arrangement and use of mounting joint terminals in a semiconductor device which is flip-chip mounted on a circuit board by a plurality of substantially spherical mounting joint terminals.

【0002】[0002]

【従来の技術】回路基板に対してフリップチップ実装法
により実装される半導体装置の中でも高密度実装に対応
するためのいわゆるボールグリッドアレイ(BGA)型
の半導体装置は、半導体素子とその半導体素子を収容す
る半導体素子収納用パッケージとから成り、その半導体
素子収納用パッケージの下面には複数の半田バンプ等の
ほぼ球状の実装用継手端子が最外部が方形環状になるよ
うに格子状あるいは重囲状に配列して形成されており、
実装にあたってはそれら実装用継手端子が半導体素子収
納用パッケージ内部で半導体素子の信号・電源・接地電
極と接続されるとともに回路基板上の電極パッドに実装
接続されて、半導体素子と回路基板との間で信号や電源
の供給および接地との導通が行なわれる。
2. Description of the Related Art Among semiconductor devices mounted on a circuit board by a flip-chip mounting method, a so-called ball grid array (BGA) type semiconductor device for coping with high-density mounting includes a semiconductor element and the semiconductor element. A semiconductor device housing package to be housed, and a substantially spherical mounting joint terminal such as a plurality of solder bumps is formed on the lower surface of the semiconductor device housing package in a lattice shape or a double-walled shape so that the outermost portion becomes a square ring. Are formed in an array,
When mounting, the mounting joint terminals are connected to the signal, power, and ground electrodes of the semiconductor element inside the semiconductor element storage package, and are also mounted and connected to the electrode pads on the circuit board, and the connection between the semiconductor element and the circuit board is made. Supply of a signal or power and conduction with the ground.

【0003】このようなBGA型の半導体装置において
は、半導体素子および回路基板の高集積化・高密度化に
対応して微弱な信号に対する多数の信号線の接続をでき
るだけ短い配線長で行なうため、方形環状に配列された
最外部の実装用継手端子は信号線の接続用に使用するこ
とが一般に要請されており、最外部の実装用継手端子は
すべて信号用端子として設計され使用されていた。
In such a BGA type semiconductor device, a large number of signal lines for weak signals are connected with a wiring length as short as possible in accordance with high integration and high density of semiconductor elements and circuit boards. It is generally required that the outermost mounting joint terminals arranged in a square ring be used for connection of signal lines, and all outermost mounting joint terminals have been designed and used as signal terminals.

【0004】また、高集積度の半導体素子を収容した高
信頼性の半導体装置においては通常はセラミック製の半
導体素子収納用パッケージが用いられ、一方、回路基板
には、耐衝撃性等の機械的特性や耐薬品性等の化学的特
性が優れておりかつ低コストであることから、通常はガ
ラスエポキシ基板が用いられていた。
In a highly reliable semiconductor device containing a highly integrated semiconductor device, a package for housing a semiconductor device made of ceramic is usually used. On the other hand, a mechanical board such as impact resistance is used for a circuit board. A glass epoxy substrate is usually used because of its excellent properties and chemical properties such as chemical resistance and low cost.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、セラミ
ック製の半導体素子収納用パッケージを用いたBGA型
の半導体装置をガラスエポキシを用いた回路基板にフリ
ップチップ実装した場合等のように、半導体装置の熱膨
張率が小さくて回路基板の熱膨張率が大きく、それらの
熱膨張率の差が大きい場合には、実装時の工程における
温度変化あるいは使用時の半導体素子からの発熱や使用
環境による温度変化などによって熱膨張率の差に起因す
る応力が実装用継手端子にかかり、その結果、特に最大
の応力がかかる最外部の方形環状の四隅のいずれかの実
装用継手端子において接続部にクラックが入ったり断線
したりしやすくなり、その結果その実装用継手端子での
回路基板との電気的な接続がとれなくなることがあると
いう問題点があった。
However, such as in the case where a BGA type semiconductor device using a package for housing a semiconductor element made of ceramic is flip-chip mounted on a circuit board using glass epoxy, the heat of the semiconductor device may be reduced. If the coefficient of thermal expansion is small and the coefficient of thermal expansion of the circuit board is large and the difference between the coefficients of thermal expansion is large, temperature changes during the mounting process, heat generated by the semiconductor elements during use, and temperature changes due to the use environment, etc. The stress caused by the difference in the coefficient of thermal expansion is applied to the mounting joint terminal, and as a result, cracks may occur in the connection part, especially at one of the four outermost square annular mounting joint terminals where the maximum stress is applied. There is a problem that disconnection is likely to occur, and as a result, electrical connection with the circuit board at the mounting joint terminal may not be established. .

【0006】また、最外部の方形環状の四隅の実装用継
手端子のいずれかにはそのように電気的な接続不良が発
生しやすく、接続不良が発生した場合にはその実装用継
手端子に割り当てられた固有の電気信号が伝送されなく
なって半導体装置の故障となることから、実装後の半導
体装置の信頼性が低くなってしまいやすいという問題点
もあった。
[0006] In addition, such an electrical connection failure is likely to occur at any of the outermost square annular four corner mounting joint terminals, and if a connection failure occurs, it is assigned to the mounting joint terminal. There is also a problem that the reliability of the semiconductor device after mounting is apt to be lowered because the semiconductor device fails because the specific electric signal is not transmitted and the semiconductor device fails.

【0007】本発明はこのような問題点に鑑みて案出さ
れたものであり、その目的は、BGA型の半導体装置に
ついて、熱膨張率の差が大きい半導体装置と回路基板と
の間でフリップチップ実装を行なった場合であっても、
最外部の方形環状の配列の四隅のいずれかの実装用継手
端子の接続不良による故障が発生しにくく、実装後の信
頼性が高い半導体装置を提供することにある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to flip a BGA type semiconductor device between a semiconductor device having a large difference in thermal expansion coefficient and a circuit board. Even if the chip is mounted,
An object of the present invention is to provide a semiconductor device which is less likely to fail due to poor connection of any of the mounting joint terminals at the four corners of the outermost rectangular ring array and has high reliability after mounting.

【0008】[0008]

【課題を解決するための手段】本発明の半導体装置は、
半導体素子と、その半導体素子を収容する凹部が上面に
形成された半導体素子収納用パッケージと、その半導体
素子収納用パッケージの下面の前記凹部を取り囲む領域
にその最外部が方形環状に配列された、前記半導体素子
の信号電極、電源電極または接地電極が接続される複数
個のほぼ球状の実装用継手端子とから成り、前記半導体
素子の電源電極または接地電極を前記方形環状の四隅に
位置する実装用継手端子に接続するとともに、前記半導
体素子の電源電極および接地電極を前記方形環状の四隅
以外に位置する実装用継手端子にも接続したことを特徴
とするものである。
According to the present invention, there is provided a semiconductor device comprising:
A semiconductor element, a semiconductor element housing package in which a recess for housing the semiconductor element is formed on the upper surface, and the outermost part is arranged in a square ring shape in a region surrounding the recess on the lower surface of the semiconductor element housing package; A signal electrode of the semiconductor element, a plurality of substantially spherical mounting joint terminals to which a power supply electrode or a ground electrode is connected, and a power supply electrode or a ground electrode of the semiconductor element positioned at the four corners of the rectangular ring. In addition to the connection to the joint terminal, the power supply electrode and the ground electrode of the semiconductor element are also connected to the mounting joint terminals located at positions other than the four corners of the rectangular ring.

【0009】また本発明の半導体装置は、上記構成の半
導体装置において、前記半導体素子の電源電極または接
地電極を前記方形環状の四隅に位置する実装用継手端子
に隣接する最外部の実装用継手端子にも接続したことを
特徴とするものである。
Further, in the semiconductor device of the present invention, the power supply electrode or the ground electrode of the semiconductor element is an outermost mounting joint terminal adjacent to the mounting joint terminal located at the four corners of the rectangular ring. It is also characterized in that it is also connected to.

【0010】[0010]

【発明の実施の形態】次に本発明を添付図面に基づき説
明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the accompanying drawings.

【0011】図1は本発明の半導体装置の一実施形態を
示す下面図である。同図に示す半導体装置1において、
破線で示した2は半導体素子であり、その下面には半導
体素子2の電極(信号電極・電源電極または接地電極)
3が複数個配列されている。
FIG. 1 is a bottom view showing one embodiment of the semiconductor device of the present invention. In the semiconductor device 1 shown in FIG.
Reference numeral 2 denotes a semiconductor element, which is indicated by a broken line. Electrodes (signal electrode, power supply electrode, or ground electrode) of the semiconductor element 2 are provided on the lower surface.
3 are arranged in plurality.

【0012】4は半導体素子2をその上面に形成された
凹部5内に収容する半導体素子収納用パッケージであ
り、半導体素子収納用パッケージ4の下面の凹部5を取
り囲む領域にはその最外部が方形環状に配列され半導体
素子2の電極3が接続される複数個のほぼ球状の実装用
継手端子6が配列されている。
Numeral 4 denotes a semiconductor element housing package for housing the semiconductor element 2 in a recess 5 formed on the upper surface thereof. The outermost area of the package surrounding the recess 5 on the lower surface of the semiconductor element housing package 4 is rectangular. A plurality of substantially spherical mounting joint terminals 6 arranged in a ring and connected to the electrodes 3 of the semiconductor element 2 are arranged.

【0013】また、図2はこの半導体装置1を回路基板
に実装した状態を示す断面図であり、図1と同様の箇所
には同じ符号を付してある。同図において9は半導体素
子収納用パッケージ4の蓋体であり、半導体素子収納用
パッケージ4の凹部5に半導体素子2を実装した後、凹
部5を覆うようにして封止樹脂やロウ材等によって取着
することにより、半導体素子2を封止して収容するため
のものである。なお、半導体素子収納用パッケージ4の
上面に実装した半導体素子2を直接に樹脂によって封止
した場合などは、蓋体9は必ずしも必要とするものでは
ない。
FIG. 2 is a cross-sectional view showing a state where the semiconductor device 1 is mounted on a circuit board, and the same parts as those in FIG. 1 are denoted by the same reference numerals. In FIG. 1, reference numeral 9 denotes a cover of the semiconductor element housing package 4. After the semiconductor element 2 is mounted in the recess 5 of the semiconductor element housing package 4, the sealing member or the brazing material is used to cover the recess 5. By attaching, the semiconductor element 2 is sealed and accommodated. When the semiconductor element 2 mounted on the upper surface of the semiconductor element housing package 4 is directly sealed with resin, the lid 9 is not always necessary.

【0014】10は半導体装置1がフリップチップ実装さ
れる回路基板であり、その上面に配設された実装用電極
パッド(図示せず)に実装用継手端子6を接続すること
により、半導体素子2の信号電極・電源電極・接地電極
が回路基板10の信号配線・電源配線・接地配線と電気的
に接続される。
Reference numeral 10 denotes a circuit board on which the semiconductor device 1 is flip-chip mounted, and the mounting joint terminals 6 are connected to mounting electrode pads (not shown) provided on the upper surface of the circuit board, whereby the semiconductor element 2 is mounted. Are electrically connected to the signal wiring, power supply wiring, and ground wiring of the circuit board 10.

【0015】そして、本発明の半導体装置1は、実装用
継手端子6のうち最外部の方形環状の四隅に位置する実
装用継手端子7に半導体素子2の電極3のうち電源電極
または接地電極を接続するとともに、それら最外部の方
形環状の四隅に位置する実装用継手端子7以外の実装用
継手端子6に半導体素子2の電極3のうち電源電極およ
び接地電極を接続したことを特徴とする。
In the semiconductor device 1 of the present invention, the power supply electrode or the ground electrode of the electrodes 3 of the semiconductor element 2 is connected to the mounting joint terminals 7 located at the four outermost rectangular annular corners of the mounting joint terminals 6. In addition to the connection, the power supply electrode and the ground electrode of the electrodes 3 of the semiconductor element 2 are connected to the mounting joint terminals 6 other than the mounting joint terminals 7 located at the four outermost rectangular annular corners.

【0016】これにより本発明の半導体装置1によれ
ば、実装時の工程における温度変化あるいは使用時の半
導体素子2からの発熱や使用環境による温度変化などに
よって半導体装置1の半導体素子収納用パッケージ4と
回路基板10との熱膨張率の差に起因する応力が発生し、
その最大の応力が最外部の方形環状の四隅に位置する実
装用継手端子7にかかることにより実装用継手端子7の
いずれかに接続不良が発生した場合でも、その実装用継
手端子7には半導体素子2の信号電極が接続されていな
いことから半導体素子2にまたは半導体素子2から固有
の電気信号が伝送されなくなるということがない。ま
た、実装用継手端子7の接続不良が電源または接地に対
するものであっても方形環状の四隅以外に位置する実装
用継手端子6によって電源の供給および接地との導通が
確保されるので、半導体装置1の故障が生じることがな
くなり、実装後の信頼性が高い半導体装置1となる。
As a result, according to the semiconductor device 1 of the present invention, the semiconductor device housing package 4 of the semiconductor device 1 is caused by a temperature change in a mounting process, a heat generation from the semiconductor device 2 during use, or a temperature change due to a use environment. And stress due to the difference in the coefficient of thermal expansion between the circuit board 10 and
Even if a connection failure occurs in any one of the mounting joint terminals 7 due to the maximum stress being applied to the mounting joint terminals 7 located at the outermost four corners of the square ring, the mounting joint terminal 7 has a semiconductor. Since the signal electrode of the element 2 is not connected, transmission of a unique electric signal to or from the semiconductor element 2 does not occur. Further, even if the connection failure of the mounting joint terminal 7 is to the power supply or the ground, the supply of the power and the continuity with the ground are ensured by the mounting joint terminal 6 located at other than the four corners of the rectangular ring. 1 does not occur, and the semiconductor device 1 has high reliability after mounting.

【0017】また本発明の半導体装置1によれば、最外
部の方形環状の四隅に位置する実装用継手端子7がすべ
て接続不良となった最悪の場合であっても、方形環状の
四隅以外に位置する実装用継手端子6によって電源の供
給および接地との導通が確保されるので、やはり半導体
装置1の故障が生じることはなく、実装後の信頼性が高
い半導体装置1となる。
Further, according to the semiconductor device 1 of the present invention, even in the worst case where all of the mounting joint terminals 7 located at the outermost four corners of the rectangular ring have a poor connection, they are not limited to the four corners of the rectangular ring. Since the supply of power and conduction with the ground are ensured by the located mounting joint terminal 6, the semiconductor device 1 does not fail, and the semiconductor device 1 has high reliability after mounting.

【0018】また、本発明の半導体装置1は、上記の構
成に加えて、半導体素子2の電源電極または接地電極を
方形環状の四隅に位置する実装用継手端子7に隣接する
最外部の実装用継手端子8にも接続したことを特徴とす
る。
Further, in addition to the above configuration, the semiconductor device 1 of the present invention further comprises a power supply electrode or a ground electrode of the semiconductor element 2 mounted on the outermost mounting terminal 7 adjacent to the mounting joint terminals 7 located at the four corners of the rectangular ring. It is characterized in that it is also connected to the joint terminal 8.

【0019】このような本発明の半導体装置1によれ
ば、半導体装置1の半導体素子収納用パッケージ4と回
路基板10との熱膨張率の差が非常に大きく、それにより
応力が大きくなって最外部の方形環状の四隅に位置する
実装用継手端子7に隣接する最外部の実装用継手端子8
のいずれかにまで接続不良が発生するような場合であっ
ても、接続不良の発生が及んでいないそれら隣接する実
装用継手端子8あるいは方形環状の四隅以外に位置する
実装用継手端子6によって電源の供給および接地との導
通が確保されるので、半導体装置1の故障が生じること
はなく、実装後の信頼性が高い半導体装置1となる。
According to the semiconductor device 1 of the present invention, the difference in the coefficient of thermal expansion between the semiconductor element housing package 4 and the circuit board 10 of the semiconductor device 1 is very large, so that the stress becomes large, Outermost mounting joint terminals 8 adjacent to mounting joint terminals 7 located at four corners of the outer rectangular ring
In the case where a connection failure occurs up to any of the above, the power is supplied by the adjacent mounting joint terminal 8 or the mounting joint terminal 6 located at a position other than the four corners of the rectangular ring where the connection failure has not occurred. Supply and ground conduction are ensured, so that no failure of the semiconductor device 1 occurs and the semiconductor device 1 has high reliability after mounting.

【0020】本発明の半導体装置1において、半導体素
子2としては、例えばSi基板に形成されたICやLS
I等が用いられる。
In the semiconductor device 1 of the present invention, the semiconductor element 2 is, for example, an IC or LS formed on a Si substrate.
I and the like are used.

【0021】半導体素子収納用パッケージ4には、熱膨
張率の小さいものとしては、例えば酸化アルミニウム質
焼結体・ムライト質焼結体・炭化珪素質焼結体・窒化ア
ルミニウム質焼結体・ガラスセラミックス質焼結体等の
絶縁基体にタングステン・モリブデン・マンガン・銅等
の金属から成るメタライズ配線層が形成されたセラミッ
クス製のBGA型パッケージ、あるいはチップサイズパ
ッケージ(CSP)等がある。一方、熱膨張率が大きい
ものとしては、例えばガラスエポキシ樹脂から成る絶縁
基体と銅の配線とから成るプリント配線板等がある。
The package having a small coefficient of thermal expansion includes, for example, a sintered body of aluminum oxide, a sintered body of mullite, a sintered body of silicon carbide, a sintered body of aluminum nitride, and glass. There is a ceramic BGA type package in which a metallized wiring layer made of a metal such as tungsten, molybdenum, manganese or copper is formed on an insulating base such as a ceramic sintered body, or a chip size package (CSP). On the other hand, as a material having a large coefficient of thermal expansion, for example, there is a printed wiring board formed of an insulating base made of glass epoxy resin and copper wiring.

【0022】実装用継手端子6は、半導体素子収納用パ
ッケージ4の下面に、上記メタライズ配線層と接続され
ている接続パッドに低融点の鉛−錫半田や銅等から成る
ほぼ球状の端子が、ロウ付けや導電性樹脂により、半導
体装置1の仕様に応じて所望の寸法ならびに配列(格子
状や種々の重囲状等)に形成される。
The mounting joint terminal 6 has a substantially spherical terminal made of low melting point lead-tin solder, copper, or the like on a connection pad connected to the metallized wiring layer on the lower surface of the semiconductor element housing package 4. By the brazing or the conductive resin, the semiconductor device 1 is formed in a desired size and arrangement (a lattice shape, various surrounding shapes, etc.) according to the specification of the semiconductor device 1.

【0023】蓋体9はアルミナセラミックやFe−Ni
−Co合金・42アロイ等から成り、半導体素子2を封止
用樹脂にて封止する場合は、例えばエポキシ等の樹脂を
用いればよい。
The cover 9 is made of alumina ceramic or Fe-Ni.
When the semiconductor element 2 is sealed with a sealing resin, a resin such as epoxy may be used.

【0024】半導体装置1がフリップチップ実装される
回路基板10は、熱膨張率が大きいものとしては、例えば
ガラスエポキシ樹脂の絶縁基体と銅配線とから成る多層
プリント配線板等がある。一方、熱膨張率が小さいもの
としては、酸化アルミニウム質焼結体やムライト質焼結
体・炭化珪素質焼結体・窒化アルミニウム質焼結体・ガ
ラスセラミック質焼結体等の絶縁基体にタングステンや
マンガン・モリブデン・銅等から成るメタライズ配線層
が形成されたセラミック製のBGA型パッケージあるい
はCSP等がある。
The circuit board 10 on which the semiconductor device 1 is flip-chip mounted has a large coefficient of thermal expansion, for example, a multilayer printed wiring board composed of an insulating base of glass epoxy resin and copper wiring. On the other hand, as a material having a low coefficient of thermal expansion, an insulating substrate such as an aluminum oxide sintered body, a mullite sintered body, a silicon carbide sintered body, an aluminum nitride sintered body, and a glass ceramic sintered body is used. And a ceramic BGA type package or CSP on which a metallized wiring layer made of manganese, molybdenum, copper or the like is formed.

【0025】また、半導体装置1と回路基板10との間に
は、実装後に必要に応じてアンダーフィル材としてフィ
ラーを含有する熱硬化性樹脂等を充填してもよい。
In addition, the space between the semiconductor device 1 and the circuit board 10 may be filled with a thermosetting resin containing a filler as an underfill material if necessary after mounting.

【0026】かくして本発明の半導体装置1によれば、
回路基板10との熱膨張率の差が大きいために温度変化に
よる応力が実装用継手端子6にかかって実装用継手端子
7あるいは実装用継手端子8の接続不良が発生した場合
であっても、半導体装置1の故障が生じることがなくな
り、実装後の信頼性が高い半導体装置1となる。
Thus, according to the semiconductor device 1 of the present invention,
Even when a stress due to a temperature change is applied to the mounting joint terminal 6 due to a large difference in coefficient of thermal expansion from the circuit board 10 and connection failure of the mounting joint terminal 7 or the mounting joint terminal 8 occurs, No failure of the semiconductor device 1 occurs and the semiconductor device 1 has high reliability after mounting.

【0027】なお、本発明は上述の実施形態に限定され
るものではなく、本発明の要旨を逸脱しない範囲で種々
の変更・改良などを加えることは何ら差し支えない。
It should be noted that the present invention is not limited to the above-described embodiment, and that various changes and improvements can be made without departing from the scope of the present invention.

【0028】[0028]

【発明の効果】本発明の半導体装置によれば、半導体素
子と、その半導体素子を収容する凹部が上面に形成され
た半導体素子収納用パッケージと、その半導体素子収納
用パッケージの下面の前記凹部を取り囲む領域にその最
外部が方形環状に配列された、前記半導体素子の信号電
極、電源電極または接地電極が接続される複数個のほぼ
球状の実装用継手端子とから成る半導体装置について、
実装用継手端子のうち最外部の方形環状の四隅に位置す
る実装用継手端子に半導体素子の電極のうち電源電極ま
たは接地電極を接続するとともに、それら最外部の方形
環状の四隅に位置する実装用継手端子以外の実装用継手
端子に半導体素子の電極のうち電源電極および接地電極
を接続したことから、熱膨張率の差が大きい回路基板と
の間でフリップチップ実装を行なった場合に、実装時の
工程における温度変化あるいは使用時の半導体素子から
の発熱や使用環境による温度変化などによって半導体装
置の半導体素子収納用パッケージと回路基板との熱膨張
率の差に起因する応力が発生し、その最大の応力が最外
部の方形環状の四隅に位置する実装用継手端子にかかる
ことにより実装用継手端子のいずれかに接続不良が発生
しても、その実装用継手端子には半導体素子の信号電極
が接続されていないので半導体素子にまたは半導体素子
から固有の電気信号が伝送されなくなるということがな
くなった。また、実装用継手端子の接続不良が電源また
は接地に対するものであっても方形環状の四隅以外に位
置する実装用継手端子によって電源の供給および接地と
の導通が確保できた。その結果、最外部の方形環状の配
列の四隅のいずれかの実装用継手端子の接続不良による
故障が発生しにくく、実装後の信頼性が高い半導体装置
を提供することができた。
According to the semiconductor device of the present invention, a semiconductor device, a semiconductor device housing package having a recess for housing the semiconductor device formed on the upper surface, and the recess on the lower surface of the semiconductor device housing package are provided. A semiconductor device comprising a plurality of substantially spherical mounting joint terminals to which a signal electrode of the semiconductor element, a power supply electrode or a ground electrode is connected, the outermost of which is arranged in a rectangular ring in a surrounding area,
Connect the power supply electrode or the ground electrode among the electrodes of the semiconductor element to the mounting joint terminals located at the outermost square annular corners of the mounting joint terminals, and mount them at the outermost square annular four corners. Since the power supply electrode and the ground electrode of the semiconductor element electrodes are connected to the mounting joint terminals other than the joint terminals, the flip-chip mounting with the circuit board with a large difference in the coefficient of thermal expansion is performed when mounting. The stress caused by the difference in the coefficient of thermal expansion between the semiconductor device housing package of the semiconductor device and the circuit board occurs due to the temperature change in the process, heat generated by the semiconductor device during use, and temperature change due to the use environment. Even if a connection failure occurs at one of the mounting joint terminals due to the stress applied to the mounting joint terminals located at the four corners of the outermost rectangular ring, Intrinsic electrical signal to the semiconductor element or the semiconductor element because the signal electrodes not connected semiconductor element is no longer that no longer transmitted to the joint pin. In addition, even if the connection failure of the mounting joint terminal was caused by the power supply or the ground, the supply of the power and the continuity with the ground could be ensured by the mounting joint terminal located outside the four corners of the rectangular ring. As a result, a failure due to a connection failure of any of the mounting joint terminals at any of the four corners of the outermost rectangular annular array is unlikely to occur, and a highly reliable semiconductor device after mounting can be provided.

【0029】また本発明の半導体装置によれば、最外部
の方形環状の四隅に位置する実装用継手端子がすべて接
続不良となった最悪の場合であっても、方形環状の四隅
以外に位置する実装用継手端子によって電源の供給およ
び接地との導通が確保されるので、故障が生じることが
なく、実装後の信頼性が高い半導体装置を提供すること
ができた。
Further, according to the semiconductor device of the present invention, even in the worst case where all of the mounting joint terminals located at the outermost four corners of the rectangular ring have a poor connection, they are located at positions other than the four corners of the rectangular ring. Since the supply of power and conduction with the ground are ensured by the mounting joint terminal, no failure occurs and a highly reliable semiconductor device after mounting can be provided.

【0030】また、本発明の半導体装置によれば、上記
の構成に加えて、半導体素子の電源電極または接地電極
を方形環状の四隅に位置する実装用継手端子に隣接する
最外部の実装用継手端子にも接続したことから、半導体
装置の半導体素子収納用パッケージと回路基板との熱膨
張率の差が非常に大きく、それにより応力が大きくなっ
て最外部の方形環状の四隅に位置する実装用継手端子に
隣接する最外部の実装用継手端子のいずれかにまで接続
不良が発生するような場合であっても、接続不良の発生
が及んでいないそれら隣接する実装用継手端子あるいは
方形環状の四隅以外に位置する実装用継手端子によって
電源の供給および接地との導通が確保でき、故障が生じ
ることはなく、実装後の信頼性が高い半導体装置を提供
することができた。
According to the semiconductor device of the present invention, in addition to the above configuration, the power supply electrode or the ground electrode of the semiconductor element is mounted on the outermost mounting joint adjacent to the mounting joint terminals located at the four corners of the rectangular ring. Since the terminals are also connected, the difference in the coefficient of thermal expansion between the semiconductor device housing package of the semiconductor device and the circuit board is very large, which increases the stress and causes the outermost square ring to be mounted at the four corners of the square ring. Even if a connection failure occurs at any of the outermost mounting joint terminals adjacent to the joint terminal, those adjacent mounting joint terminals or square annular four corners where the connection failure has not occurred The connection between the power supply and the ground can be ensured by the mounting joint terminals located at positions other than the above, no failure occurs, and a highly reliable semiconductor device after mounting can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体装置の一実施形態を示す下面図
である。
FIG. 1 is a bottom view showing one embodiment of a semiconductor device of the present invention.

【図2】本発明の半導体装置の一実施形態を示す断面図
である。
FIG. 2 is a cross-sectional view showing one embodiment of the semiconductor device of the present invention.

【符号の説明】[Explanation of symbols]

1・・・半導体装置 2・・・半導体素子 3・・・電極(信号電極・電源電極または接地電極) 4・・・半導体素子収納用パッケージ 6・・・実装用継手端子 7・・・最外部の方形環状の四隅に位置する実装用継手
端子 8・・・最外部の方形環状の四隅に位置する実装用継手
端子に隣接する最外部の実装用継手端子
DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 2 ... Semiconductor element 3 ... Electrode (signal electrode / power supply electrode or ground electrode) 4 ... Package for semiconductor element accommodation 6 ... Joint terminal for mounting 7 ... Outermost Mounting joint terminals located at the four corners of the rectangular ring 8... Outermost mounting joint terminals adjacent to the mounting joint terminals located at the four outermost square annular corners

フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 23/12 Continuation of front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 23/12

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 半導体素子と、該半導体素子を収容する
凹部が上面に形成された半導体素子収納用パッケージ
と、該半導体素子収納用パッケージの下面の前記凹部を
取り囲む領域にその最外部が方形環状に配列された、
記半導体素子の信号電極、電源電極または接地電極が接
続される複数個のほぼ球状の実装用継手端子とから成
、前記半導体素子の電源電極または接地電極を前記方
形環状の四隅に位置する実装用継手端子に接続するとと
もに、前記半導体素子の電源電極および接地電極を前記
方形環状の四隅以外に位置する実装用継手端子にも接続
したことを特徴とする半導体装置。
1. A semiconductor device and a semiconductor device for accommodating the semiconductor device.
A semiconductor element housing package having a recess formed on the upper surface , and the recess on the lower surface of the semiconductor element housing package.
Its outermost in the area surrounding are arranged in a square annular, the signal electrode of the semiconductor element, and a plurality of substantially spherical mounting joint terminal of the power electrode or ground electrode connected adult
Ri, together with the connecting power electrodes or ground electrode of the semiconductor element mounting fitting pins located on the four corners of the rectangular annular, for mounting which is located the power and ground electrodes of the semiconductor element other than the four corners of the rectangular annular A semiconductor device which is also connected to a joint terminal.
【請求項2】 前記半導体素子の電源電極または接地電
極を前記方形環状の四隅に位置する実装用継手端子に隣
接する最外部の実装用継手端子にも接続したことを特徴
とする請求項1記載の半導体装置。
2. A power supply electrode or a ground electrode of the semiconductor element is also connected to an outermost mounting joint terminal adjacent to the mounting joint terminal located at the four corners of the rectangular ring. Semiconductor device.
JP16625096A 1996-06-26 1996-06-26 Semiconductor device Expired - Fee Related JP3305577B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16625096A JP3305577B2 (en) 1996-06-26 1996-06-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16625096A JP3305577B2 (en) 1996-06-26 1996-06-26 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH1012763A JPH1012763A (en) 1998-01-16
JP3305577B2 true JP3305577B2 (en) 2002-07-22

Family

ID=15827907

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16625096A Expired - Fee Related JP3305577B2 (en) 1996-06-26 1996-06-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JP3305577B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4274013B2 (en) * 2004-03-18 2009-06-03 セイコーエプソン株式会社 Manufacturing method of substrate assembly, substrate assembly

Also Published As

Publication number Publication date
JPH1012763A (en) 1998-01-16

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