JP3045940B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which protects an integrated circuit portion of a semiconductor device, secures an electrical connection between an external device and the semiconductor device, and enables the most high-density mounting. It relates to a manufacturing method. The semiconductor device of the present invention facilitates miniaturization of industrial electronic devices such as information communication devices, office electronic devices, home electronic devices, measuring devices, and assembly robots, medical electronic devices, and electronic toys. is there.

[0002]

2. Description of the Related Art A conventional semiconductor device will be described below with reference to the drawings. FIG. 11 is a cross-sectional view showing a conventional semiconductor device called a quad flat pack (QFP). The configuration of a conventional semiconductor device will be described with reference to FIG.

In a conventional semiconductor device, external electrode terminals are provided on a side surface of a semiconductor package as shown in the figure, and a semiconductor element 1 having electrodes (not shown) on its surface insulates ceramic or the like. It is mounted in a recess 3 of a semiconductor package 2 as a base. A wire bond area 4 is formed around the recess 3 on which the semiconductor element 1 of the semiconductor package 2 is mounted, and a wiring electrode 5 is formed on the semiconductor element 1 in the wire bond area 4. It is formed corresponding to the electrode. Then, the wiring electrode 5 in the wire bond area 4 and the electrode on the semiconductor element 1 are electrically and physically connected by a thin wire 6 such as a gold wire (Au). Also, wire bond area 4
An external electrode terminal 7 is formed on a side surface of the semiconductor package 2 for conduction between the wiring electrode 5 and the outside. Then, a lid 8 is attached for the purpose of protecting the connection portion and the like by the semiconductor element 1 and the thin wire 6.

Next, a conventional method for manufacturing a semiconductor device comprises a die bonding step, a wire bonding step, and a sealing step.

First, a die bonding step will be described with reference to FIG. The semiconductor element 1 is bonded and mounted to a recess 3 of a semiconductor package 2 using a ceramic or the like as an insulating base with a conductive adhesive known as a silver paste. This step is performed by an apparatus called a die bonder.

Next, the wire bonding step will be described with reference to FIG. In order to electrically and physically connect the electrode provided on the surface of the semiconductor element 1 mounted on the semiconductor package 2 and the wiring electrode 5 of the wire bond area 4 provided on the semiconductor package 2, gold (A)
u) or a thin wire 6 of aluminum (Al).
This step is performed by an apparatus called a wire bonder.

Finally, the sealing step will be described with reference to FIG. In the above process, the electrode provided on the surface of the semiconductor element 1 with the thin wire 6 of gold (Au) or aluminum (Al) and the wiring electrode 5 of the wire bond area 4 provided on the semiconductor package 2 are electrically and physically connected. After that, in order to protect the connection portion of the semiconductor element 1 and the thin wire 6 and the like, the semiconductor device 1 is sealed with the cover 8 so as to cover the recess 3 of the semiconductor package 2. The lid 8 is attached to the semiconductor package 2 with an adhesive and sealed.

Further, the types of semiconductor packages of the conventional semiconductor device can be roughly classified into two types.

First, there is a ceramic package. Ceramic packages are further classified into laminated ceramic packages and glass-sealed ceramic packages.

[0010] In the laminated type ceramic package, fine holes are formed in the green sheet by mechanical processing at necessary positions on the wiring, a conductive paste is filled into the holes, and a circuit is printed and formed. The package is laminated and fired in a reducing atmosphere to form a package body.

In a glass-sealed ceramic package, a low-melting glass is applied to the upper surface of a package body, a lead frame is attached, and the low-melting glass is melted in a heating furnace to join the package body and the lead frame. Then, a gold (Au) paste or the like is applied to a central portion where the semiconductor element is mounted. The most commonly used is a plastic package. In this type of package, a semiconductor element is mounted on a lead frame, and after electrical connection is made by a wire bonding method, the package is held in a hollow portion of a mold and mainly made of a thermosetting resin such as an epoxy resin. After the resin has flowed in, it is cured. For both the ceramic package and the plastic package, a wire bonding method using a fine Au or Al wire for electrical connection between the semiconductor element and the package is mainly used. In the case of the mounting method using this wire bonding method, it is necessary to provide a wiring region for connecting a wire to a peripheral portion where the semiconductor element is attached, which has been an obstacle to miniaturization of a package.

Further, a package using a flip-chip mounting method for mounting a semiconductor element directly on a circuit board has been studied. Packages using the flip-chip mounting method include a case where ceramic is used as a substrate material of the package (Japanese Patent Application Laid-Open No. 62-118549) and a case where a resin base material is used as a substrate material (Japanese Patent Application Laid-Open No. 63-65656). ) Are being considered. One of the features of the flip-chip mounting type package that has been studied in the past is that, like the ceramic package of the conventional wire bonding method, the part where the semiconductor element is mounted is hollow, so the semiconductor element is mounted after the semiconductor element is mounted. A lid made of metal, ceramic, or the like is attached by a method such as using solder, low-melting glass, or an Au-Sn alloy as a joining material, or using a method such as resistance pressure welding. Can be With the miniaturization and high performance of electronic devices, the semiconductor package is required to increase the number of external electrodes and reduce the size and thickness of the semiconductor package body.

[0013]

However, in the above-mentioned conventional semiconductor device, the wiring layer of the semiconductor package body is made finer, multilayered, the mounting direction of the external electrode terminals is made multidirectional, and the distance between the external electrode terminals is made finer. In general, a wire bonding method is used as an electrical connection method between a semiconductor element and a semiconductor package. Therefore, 2.0 mm around the semiconductor element is used as a region for forming an internal electrode terminal which is an electrode for wiring a fine wire around the semiconductor device, and 2.0 mm around the wire bond area is used as a region for attaching a lid. Are required respectively. For this reason, it is impossible to make the area of the semiconductor package approximately equal to the size of the semiconductor element, and it is not possible to satisfy the demand for miniaturization and thinning of the semiconductor package body.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is possible to reduce the size and thickness of an area required for mounting a semiconductor element and to suppress the fineness of the interval between external electrode terminals of a semiconductor package.
It is an object of the present invention to provide a semiconductor device having an external terminal configuration having no problem in mechanical strength.

[0015]

In order to solve the above problems, a semiconductor device according to the present invention has the following configuration. That is, a semiconductor carrier made of an insulating substrate
A, and the semiconductor carrier and the bumps are joined via a bump.
Between the semiconductor element and the semiconductor carrier and the semiconductor element;
A semiconductor device comprising a sealing resin that seals a gap.
Wherein the semiconductor carrier is a semiconductor bonded to the first surface.
A plurality of wiring electrodes corresponding to the electrodes on the element, and the first surface
Bottom connected with multiple wiring electrodes
And external terminals integrated in the
Having an opening similar in shape to that of the semiconductor
A semiconductor carrier consisting of a laminated substrate smaller than the element.
Thus, the semiconductor element is located on an electrode on the surface of the semiconductor element.
Bumps are formed on the substrate, and the bumps are
Bonding with a plurality of wiring electrodes on the first surface of the semiconductor carrier
The sealing resin is the semiconductor element.
A gap between the element and the semiconductor carrier;
Sealing resin filling and covering the peripheral portion and the opening
Is a semiconductor device.

Further, in the manufacturing method, a first step of forming a bump on the electrode on the surface of the semiconductor element, a second step of supplying a conductive adhesive to the bump on the semiconductor element, a whole outer shape similar to the shape opposite the first surface having an opening and a second surface, the entire outer shape the semiconductor
A plurality of wiring electrodes are formed on the first surface, and a plurality of electrode pads connected to the wiring electrodes on the first surface by internal wiring are formed on the second surface; After the wiring electrodes on the first surface of the semiconductor carriers integrated and arranged in a shape and the bumps on the semiconductor element to which the conductive adhesive is supplied are brought into correspondence with each other, the conductive adhesive is heated. A third step of curing, and a sealing resin is injected through a similar opening provided in the center of the semiconductor carrier to fill a space between the semiconductor element and the semiconductor carrier, and then a peripheral part of the semiconductor element is filled. And a fourth step of filling and covering the opening and sealing with resin.

[0017]

According to the above construction, the semiconductor carrier has an opening in the center, a wiring electrode corresponding to the semiconductor element to be joined is formed around the first surface, and the first electrode is formed on the second surface.
The wiring pads on the surface and the conductive vias inside the semiconductor carrier are internally arranged and connected in a grid pattern with electrode pads which are internally routed and connected. The semiconductor element is bonded to the semiconductor carrier by a flip-chip method and electrically connected. Since the connection is made, the wire bonding area that was necessary for electrically connecting the semiconductor element is not required, and the sealing resin is penetrated between the semiconductor carrier and the semiconductor element and is cured by heat. Since the semiconductor element can be protected and the lid does not need to be mounted, the lid mounting area can be eliminated, and the semiconductor device can be downsized.

An opening is provided at the center of the semiconductor carrier, and the opening reduces the strain of the semiconductor carrier due to the mutual shear stress at the time of joining the semiconductor carrier and the semiconductor element. Defects such as misalignment between the semiconductor device and the semiconductor element can be eliminated.

In the manufacturing method, the sealing resin is filled into the gap between the semiconductor carrier and the semiconductor element while extruding air (nitrogen) as bubbles by injecting the sealing resin from the opening of the semiconductor carrier. Can be filled without leaving any bubbles.

[0020]

An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line A1-A2 of the semiconductor device according to the present embodiment shown in FIG. FIG. 3 is a bottom view of the semiconductor device according to the present embodiment.

Referring to FIGS. 1, 2 and 3, the semiconductor device according to this embodiment has a semiconductor element 12 mounted on a semiconductor carrier 11 by a flip-chip method. 1
The gap between 1 and the semiconductor element 12 is sealed with a sealing resin 13.

Next, a detailed structure of the semiconductor device according to this embodiment will be described with reference to FIG.

The semiconductor carrier 11 has an opening 1 at the center.
4 having a semiconductor element 12 bonded to the periphery on the first surface.
Are formed on the second surface, and an electrode pad 16 made of a metallized metal layer connected to the wiring electrode 15 on the first surface by a conductive via (not shown) inside the semiconductor carrier is formed on the second surface. They are arranged in a grid. The electrode pad 16 is an external terminal that is electrically connected to the outside.

The semiconductor element 12 has an electrode 17 formed on the periphery, a bump 18 of gold (Au) or the like formed on the electrode 17, and a conductive adhesive 19 provided on the bump 18. Yes, using a multi-pin microcomputer chip as an example. In addition, as the conductive adhesive 19,
In consideration of reliability, thermal stress, etc., for example, epoxy resin as a binder and gold-palladium (A
It is an adhesive made of u-Pd) alloy. The bumps 18 formed on the semiconductor element 12 are two-step projection bumps formed by a wire bonding method. The two-step projections can hold the conductive adhesive 19 by a transfer method, and are bonded to the semiconductor carrier 11. At this time, it is possible to prevent the excess conductive adhesive 19 from protruding to the fine pitch wiring electrodes 15 on the semiconductor carrier 11.

In the semiconductor device according to this embodiment, the semiconductor carrier 12 is provided on the bumps 18 of the semiconductor chip 12 by the flip chip method.
9 joined together. And semiconductor carrier 1
The gap between the semiconductor element 1 and the semiconductor element 12, the periphery of the semiconductor element 12, and the opening 14 of the semiconductor carrier 11 are filled and covered with an epoxy-based sealing resin 13.

In the semiconductor device of this embodiment, the semiconductor carrier 11 has an opening 14 at the center,
4, the semiconductor carrier 11 and the semiconductor element 12 are relieved of strain applied to the central portion of the semiconductor carrier 11 due to mutual shear stress at the time of joining. Can be eliminated. In the present embodiment, the location where the opening 14 is provided is the central portion of the semiconductor carrier 11, but the location is not limited to the central portion as long as strain can be reduced. In this embodiment, the semiconductor carrier 1
By forming an opening similar to the outer shape of the semiconductor carrier 11 at the center of the semiconductor device 1, the strain on the semiconductor carrier 11 and the semiconductor element 12 after joining is reduced, and the joining failure is significantly reduced. be able to.

The semiconductor carrier 11 of the semiconductor device of the present embodiment has a wiring electrode 15 corresponding to the semiconductor element 12 to be joined on the periphery of the first surface, and the first surface on the second surface. An electrode pad 16 made of a metallized metal layer connected by a conductive via (not shown) inside the semiconductor carrier to the upper wiring electrode 15 is integrated and arranged in a grid, and the wiring electrode 15 on the first surface is Semiconductor carrier 11
The electrode pads 16, which are external terminals, are arranged on the entire bottom surface of the semiconductor carrier 11 because they are internally routed by conductive vias and are arranged in a grid pattern as electrode pads 16 on the second surface, which is the bottom surface. As a result, the degree of integration of the electrodes can be improved, and the size of the semiconductor carrier 11 can be reduced to substantially the same as the size of the semiconductor element 12 to be joined.

The semiconductor carrier 11 has a multilayer circuit board configuration using ceramic as an insulating substrate, and inside the conductive vias of the respective layers, the wiring electrodes 15 on the first surface are sequentially turned to the bottom surface which is the second surface. The wiring electrodes 15 are well arranged and are arranged in a lattice pattern on the bottom surface. The wiring electrodes 15 on the first surface can be formed at a higher density due to the higher density of conducting vias, the number of layers in a multilayer circuit board configuration, and the like. The electrode pads 16 can be integrated and arranged on the second surface which is the bottom surface, and the electrode pads 16 can be integrated and arranged according to the semiconductor element 12 to be mounted.

FIG. 4 is a plan view showing a semiconductor device according to a second embodiment of the present invention, FIG. 5 is a sectional view taken along the line B1-B2 of FIG. 4, and FIG. 6 is a bottom view.

In this embodiment, the semiconductor carrier 11
The semiconductor device 12 and the semiconductor device 12 have the same size, and the other configuration is the same as the configuration shown in the first embodiment. However, the electrodes 17 around the semiconductor element 12 are of a double arrangement, and an example is a multi-pin microcomputer chip.

In the semiconductor carrier 11 of the semiconductor device according to the present embodiment, the wiring electrode 15 corresponding to the semiconductor element 12 to be bonded is formed around the first surface, and the first surface is formed on the second surface. An electrode pad 16 made of a metallized metal layer connected by a conductive via (not shown) inside the semiconductor carrier to the upper wiring electrode 15 is integrated and arranged in a grid, and the wiring electrode 15 on the first surface is Semiconductor carrier 1
1, the conductive vias are internally routed at a higher density than the structure shown in the first embodiment, and are integrated and arranged in a grid pattern as electrode pads 16 on the second surface which is the bottom surface. Electrode pads, which are external terminals, can be arranged on the entire bottom surface of the semiconductor carrier 11 to improve the degree of integration of the electrodes and reduce the size of the semiconductor carrier to the size of the semiconductor element 12 to be joined. it can. Therefore, the semiconductor device according to the present embodiment is a semiconductor device capable of realizing a size substantially equal to the mounted semiconductor element.

Next, a third embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIGS. FIG. 7 is a plan view showing a semiconductor device according to the present embodiment, and FIG.
FIG. 9 is a sectional view taken along the line C2, and FIG. 9 is a bottom view.

The present embodiment shows a configuration in which a small-pin, large-capacity memory chip using a LOC (lead-on-chip) type package, which has been increasing in recent years, is used as the semiconductor element 12 and mounted. is there. In the present embodiment, since the semiconductor element 12 is a small-pin large-capacity memory chip, the number of electrodes on the semiconductor element 12 is smaller than that of the microcomputer chip such as the microcomputer chip shown in the first and second embodiments. In the semiconductor carrier 11, the wiring electrodes 15 on the first surface are similarly routed internally to the second surface, which is the bottom surface, so that the number of the electrode pads 1
6 can be arranged in a grid on the bottom surface. Therefore, as shown in the figure, the semiconductor carrier 11 can be configured with a smaller size than the semiconductor element 12, and the first embodiment,
A semiconductor device realizing a chip size larger than that of the second embodiment can be configured. By making the semiconductor carrier 11 smaller than the semiconductor element 12, higher-density mounting becomes possible. 8 and 9, the semiconductor carrier 11
The opening 14 and the conductive adhesive 19 are omitted in the figure.

Next, a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention will be described with reference to the drawings.

FIG. 10 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to this embodiment, which is performed by different steps. First, FIG.
The first step of forming a bump on a peripheral electrode on a semiconductor element will be described. The bumps 18 are formed on the semiconductor element 12 by forming gold (A) in a capillary of a wire bonder on the electrode 17 on the semiconductor element 12.
u) The gold ball formed at the tip of the wire is
The lower part 18a of the two-step projection is first formed by heat-pressing the upper electrode 17. The upper step 18b of the two-step projection is formed by a gold loop formed by continuously moving the capillary. In this state, the bumps are merely two-step projections. Therefore, the bumps are formed by adjusting the bump heights and leveling by applying pressure to flatten the tops of the bumps.

Next, referring to FIG. 10B, a second step of supplying a conductive adhesive 19 to the bumps 18 on the semiconductor element 12 formed in the first step will be described. A conductive adhesive 19 containing gold-palladium (Au-Pd) as a conductive material is applied to a rotating disk by a doctor blade method to a suitable thickness, and the bump 18
The semiconductor element 12 on which is formed is pressed against the disk with the bumps 18 facing down and then pulled up, and a conductive adhesive 19 is supplied to the bumps 18 (transfer method). Semiconductor element 12
Since the upper bump 18 is a bump having a two-step projection shape, the conductive adhesive 19 can be reliably held in a certain amount by the shape thereof, and sagging and protrusion can be prevented. As described above, the conductive adhesive 19 may be, for example, an epoxy resin as a binder and a gold-palladium (Au-Pd) as a conductive filler in consideration of reliability, thermal stress, and the like.
An adhesive made of an alloy is used.

Next, referring to FIG. 10C, a third step of the flip chip mounting will be described. The third step is
The semiconductor element 12 and the semiconductor carrier 11 having a multilayer circuit board configuration using ceramic as an insulating base are joined by a flip-chip method, which is a method of joining the semiconductor element 12 with its surface facing down. The semiconductor carrier 11 has an opening 14 at the center thereof and has a multilayer circuit board configuration, in which wiring electrodes 15 on the first surface are sequentially formed on the second surface by conductive vias of each layer. The electrode pads 16 are efficiently routed to a certain bottom surface, and the electrode pads 16 are integrated and arranged in a lattice pattern on the bottom surface. The wiring electrodes 15 on one surface can be integrated and arranged as electrode pads 16 on the second surface which is the bottom surface. The arrangement of the wiring electrodes 15 on the first surface is provided corresponding to the electrodes 17 (bumps 18) on the semiconductor element 12 to be joined. The wiring electrode 15 on the first surface of the semiconductor carrier 11 and the semiconductor element 1
After the two conductive bumps 18 to which the conductive adhesive 19 has been supplied are joined with good positional accuracy, they are thermally cured at a certain temperature. Epoxy resin as a binder and gold-palladium (Au) as a conductive filler as the conductive adhesive 19
-Pd) When an adhesive made of an alloy is used, 100 ° C.
The bonding is completed by heating at a temperature of 1 hour and further at a temperature of 120 ° C. for 2 hours.

Next, a fourth step showing the sealing step will be described with reference to FIG. After bonding the semiconductor carrier 11 and the semiconductor element 12, the epoxy-based sealing resin 13
Is injected from the nozzle 20 through the opening 14 provided at the center of the semiconductor carrier 11 to fill and cover the gap between the semiconductor carrier 11 and the semiconductor element 12, the periphery of the semiconductor element 12, and the opening 14 of the semiconductor carrier 11. And sealing. When the gap between the semiconductor carrier 11 and the semiconductor element 12 is filled by injecting the nozzle 20 of the sealing resin 13 from the opening 14, bubbles are prevented from remaining in the gap, and highly airtight resin sealing is performed. Can do it. That is, by injecting the sealing resin 13 from the opening 14, the sealing resin 13 is pushed out of the semiconductor carrier 1 while pushing out the air that becomes bubbles.
Since the gap between the semiconductor element 12 and the semiconductor element 12 is filled, air bubbles can be filled without remaining. Since the gap between the semiconductor carrier 11 and the semiconductor element 12 is about 100 μm, which is a very small gap, this method is effective. The priority of the sealing is the semiconductor carrier 11
After the gap between the semiconductor element 12 and the opening 14 is filled, the periphery of the semiconductor element 12 is covered. By this sealing order, resin sealing can be performed without leaving air bubbles between the semiconductor carrier 11 and the semiconductor element 12. After the sealing resin 13 is filled and covered, the sealing resin 13 is cured at a constant temperature in an oven to complete the sealing.

The sealing resin 13 is made of an epoxy resin such as aluminum nitride (Al) which is a high thermal conductive ceramic.
N) or silicon nitride (SiN) added as a filler is used. The semiconductor element 12 is the semiconductor carrier 1
When the sealing resin 13 is supplied to the peripheral end of the semiconductor element 12, the sealing resin 13 sufficiently reaches the back surface of the semiconductor element 12, Contact angle between the resin and the sealing resin 13 is 6
It seals so that it may become a small angle of 0 degrees or less.

Through the above steps, a semiconductor device as shown in FIG. In addition, the semiconductor carrier 1
By using a semiconductor carrier having an opening 14 which is similar to the outer shape of the semiconductor carrier 11 in the opening 14 provided in the first step, when the sealing resin 13 is injected in the sealing step of the fourth step, Since the sealing resin 13 uniformly enters the gap between the semiconductor carrier 11 and the semiconductor element 12, uniform sealing can be achieved. By the uniform sealing, the surplus sealing resin 13 does not overflow from the gap between the semiconductor carrier 11 and the semiconductor element 12, and the sealing failure can be suppressed.

As described above, according to the present embodiment, the semiconductor element 1 having the opening 14 at the center and
2, an electrode pad made of a metallized metal layer connected to the wiring electrode 15 on the first surface by a conductive via (not shown) inside the semiconductor carrier 11 on the second surface. The semiconductor element 12 is mounted by the flip-chip method using the semiconductor carriers 11 in which the semiconductor elements 16 are arranged in a grid pattern, so that a semiconductor device having the same size as the semiconductor element can be realized. It can be made thinner. Further, by forming the opening 14 in the center of the semiconductor carrier 11, the distortion at the time of joining the semiconductor carrier 11 and the semiconductor element 12 can be reduced, and the shape of the opening 14 can be reduced.
By making the shape similar to 1, the effect of reducing distortion can be enhanced.

In the manufacturing method, the opening 14 is formed in the center of the semiconductor carrier 11 so that the sealing resin 13 can be injected from the opening, and the semiconductor carrier 1
Even if the sealing resin 13 is filled in the gap between the semiconductor device 12 and the semiconductor element 12, resin sealing with no air bubbles and excellent airtightness can be performed. Further, by making the shape of the opening 14 similar to that of the semiconductor carrier 11, the sealing resin 13 can be uniformly introduced into the gap between the semiconductor carrier 11 and the semiconductor element 12 when the sealing resin 13 is injected and filled. The extra sealing resin 13 is used for the semiconductor carrier 11 and the semiconductor element 1.
2 does not overflow, and poor sealing can be suppressed.

[0043]

According to the present invention, the wire bonding area which has been required so far for connecting the semiconductor element is no longer necessary, and the area for mounting the electrode pads as external terminals uses the entire bottom surface of the semiconductor carrier. Therefore, the semiconductor device can be made extremely small. Also, by forming an opening in the center of the semiconductor carrier, it is possible to reduce the distortion at the time of joining the semiconductor element with the semiconductor element joined to the semiconductor carrier, and by making the shape of the opening similar to the semiconductor carrier. , Can enhance the effect of reducing distortion. Further, in the manufacturing method, by forming an opening in the center of the semiconductor carrier, the sealing resin can be injected from the opening,
Even if resin is filled in the gap between the semiconductor carrier and the semiconductor element, resin sealing with no air bubbles and excellent airtightness can be performed.

[Brief description of the drawings]

FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a bottom view showing the semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a plan view showing a semiconductor device according to a second embodiment of the present invention;

FIG. 5 is a sectional view showing a semiconductor device according to a second embodiment of the present invention;

FIG. 6 is a bottom view showing a semiconductor device according to a second embodiment of the present invention;

FIG. 7 is a plan view showing a semiconductor device according to a third embodiment of the present invention.

FIG. 8 is a sectional view showing a semiconductor device according to a third embodiment of the present invention;

FIG. 9 is a bottom view showing a semiconductor device according to a third embodiment of the present invention;

FIG. 10 is a process chart showing a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.

FIG. 11 is a sectional view showing a conventional semiconductor device.

FIG. 12 is a process chart showing a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Semiconductor package 3 Depressed part 4 Wire bond area 5 Wiring electrode 6 Fine wire 7 External electrode terminal 8 Lid 11 Semiconductor carrier 12 Semiconductor element 13 Sealing resin 14 Opening 15 Wiring electrode 16 Electrode pad 17 Electrode 18 Bump 19 Conductivity Adhesive 20 nozzle

Continuation of the front page (56) References JP-A-6-204272 (JP, A) JP-A-1-125544 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21 / 60

Claims (2)

(57) [Claims] 1. A semiconductor carrier comprising an insulating substrate,
A semiconductor device comprising: a semiconductor element bonded to the semiconductor carrier via a bump; and a sealing resin sealing a gap between the semiconductor carrier and the semiconductor element, wherein the semiconductor carrier has a first surface. A plurality of wiring electrodes corresponding to the electrodes on the semiconductor element to be bonded to the semiconductor element, and external terminals connected to the plurality of wiring electrodes on the first surface by being internally routed and integrated and arranged on the bottom surface; Similar to its outer shape
Having an opening having a shape similar to that of the semiconductor element.
A semiconductor carrier comprising a laminated substrate having a smaller size,
The semiconductor element is a semiconductor element in which a bump is formed on an electrode on a surface of the semiconductor element, and the bump is bonded to a plurality of wiring electrodes on a first surface of the semiconductor carrier by a conductive adhesive. A semiconductor device, wherein the resin is a sealing resin that fills and covers a gap between the semiconductor element and the semiconductor carrier, and a peripheral portion and the opening of the semiconductor element. 2. A bump is formed on an electrode on a surface of a semiconductor element.
A first step to be performed and a bump on the semiconductor element
The second step of supplying the conductive adhesive and the whole outer shape in the center
Opposing first and second surfaces having openings similar in shape to
Having an overall shape smaller than that of the semiconductor element,
A plurality of wiring electrodes are formed on the first surface, and a plurality of wiring electrodes are formed on the second surface.
On the upper side, the wiring electrode on the first surface is internally routed and connected.
A plurality of continuous electrode pads are arranged in a grid in a half
A wiring electrode on the first surface of the conductor carrier;
The bumps to which the conductive adhesive is supplied on the semiconductor chip.
And then thermally curing the conductive adhesive.
3 steps and a sealing resin is provided at the center of the semiconductor carrier.
The semiconductor element and the
After filling the gap with the semiconductor carrier, the semiconductor element
To fill and cover the periphery and the opening with a resin.
Manufacturing a semiconductor device, comprising:
Construction method.