JP3314574B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP3314574B2
JP3314574B2 JP5632895A JP5632895A JP3314574B2 JP 3314574 B2 JP3314574 B2 JP 3314574B2 JP 5632895 A JP5632895 A JP 5632895A JP 5632895 A JP5632895 A JP 5632895A JP 3314574 B2 JP3314574 B2 JP 3314574B2
Authority
JP
Japan
Prior art keywords
chip
metal plate
analog
digital
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP5632895A
Other languages
Japanese (ja)
Other versions
JPH08255868A (en
Inventor
善造 小田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP5632895A priority Critical patent/JP3314574B2/en
Publication of JPH08255868A publication Critical patent/JPH08255868A/en
Application granted granted Critical
Publication of JP3314574B2 publication Critical patent/JP3314574B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

Abstract

PURPOSE: To obtain a robust resin sealed multichip IC package having high heat dissipation properties in which a plurality of IC chips are set in a single package. CONSTITUTION: An analog IC chip 11 and a digital IC chip 12 are bonded, on the rear surface thereof, to individual metal plates 21, 22. The metal plates 21, 22 are exposed from sealing resin 1 on the side opposite to the IC chip mounting side. When the metal plates 21, 22 are fed with power and operated, heat is dissipated from the exposed surface into the air. Since the mounting base of the analog IC chip 11, i.e., the metal plate 21, is electrically separated completely from the mounting base of the digital IC chip 12, i.e., the metal plate 22, no noise propagate on the metal plates from the digital IC chip 12 to the analog IC chip 11 to cause deterioration in the performance of the circuit during the operation.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は半導体装置およびその製
造方法に関し、ことに複数の集積回路(以下、ICと記
す)チップを単一のパッケージとして樹脂封止し、放熱
性を高めた半導体装置およびその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device in which a plurality of integrated circuit (hereinafter, referred to as IC) chips are resin-sealed as a single package to enhance heat dissipation. And its manufacturing method.

【0002】[0002]

【従来の技術】図2は特開昭63−244747号公報
に記された構造を簡略表記したものである。図2におい
て2個のICチップ10はダイパッドである金属板20
とともに一体に樹脂封止されている。1は封止樹脂、2
はリード、3は配線基板、4はICチップの表面に設け
られた電極と配線基板の表面に設けられた電極とを接続
する金属細線、5は接着剤である。接着剤としては熱抵
抗の低い導電性のものが用いられるのが普通である。I
Cチップ10のうち1個はダイパッドである金属板20
に直接接着されているが、他の1個は配線基板3により
ダイパット20と絶縁されている。このようにチップ搭
載面を分ける例としてアナログ回路とディジタル回路が
ある。アナログ回路とディジタル回路とではノイズを避
けるために別々の電源、グランドを使用するのが一般的
である。アナログICチップとディジタルICチップと
を単一のICパッケージとして樹脂封止する場合、お互
いの電源、グランドを分離するため単一の金属板にアナ
ログICチップとディジタルICチップとを熱抵抗の低
い導電性接着剤で接着する事はできないので、図2に示
したように一方のICチップを配線基板3を介してダイ
パッド20に接着せざるをえない。この結果として配線
基板3を介してダイパッド20に接着されたICチップ
からの放熱が悪くなる。もちろん両方のICチップを配
線基板3を介さずにダイパッド20に接着することは実
装技術的には可能であるが、アナログ回路とディジタル
回路で同一の電源またはグランドを使うことになり、共
通の電源またはグランドを通ってディジタル回路からア
ナログ回路へノイズが伝達されるので電気回路の性能が
悪くなる。
2. Description of the Related Art FIG. 2 is a simplified representation of the structure described in JP-A-63-244747. In FIG. 2, two IC chips 10 are metal plates 20 as die pads.
Together with resin sealing. 1 is a sealing resin, 2
Is a lead, 3 is a wiring board, 4 is a thin metal wire for connecting an electrode provided on the surface of the IC chip to an electrode provided on the surface of the wiring board, and 5 is an adhesive. As the adhesive, a conductive material having low heat resistance is generally used. I
One of the C chips 10 is a metal plate 20 which is a die pad.
The other one is insulated from the die pad 20 by the wiring board 3. An example of dividing the chip mounting surface in this way is an analog circuit and a digital circuit. Generally, separate power supplies and grounds are used for the analog circuit and the digital circuit in order to avoid noise. When an analog IC chip and a digital IC chip are resin-encapsulated as a single IC package, the analog IC chip and the digital IC chip are connected to a single metal plate so as to separate power and ground from each other. Since it is not possible to adhere with an adhesive, one of the IC chips has to be adhered to the die pad 20 via the wiring board 3 as shown in FIG. As a result, heat radiation from the IC chip adhered to the die pad 20 via the wiring board 3 deteriorates. Of course, it is possible in terms of packaging technology to bond both IC chips to the die pad 20 without passing through the wiring board 3, but the same power supply or ground is used for the analog circuit and the digital circuit, and a common power supply is used. Alternatively, noise is transmitted from the digital circuit to the analog circuit through the ground, so that the performance of the electric circuit deteriorates.

【0003】[0003]

【発明が解決しようとする課題】複数のICチップ、特
に電源、グランドのいずれか一方または両方が異なる異
種のICチップを単一のパッケージに封止する場合に、
いずれか一方のICチップはプリント配線板等の絶縁性
基板を介して金属板に非導電性の接着をするが、非導電
性の接着をされたICチップからの放熱が悪いという問
題がある。また、いずれか一方のICチップをプリント
配線板等の絶縁性基板を介さずに金属板に導電性の接着
をした場合は、ノイズにより電気回路の性能が悪くなる
という問題がある。
When a plurality of IC chips, in particular, different kinds of IC chips having different one or both of a power supply and a ground are sealed in a single package,
One of the IC chips adheres non-conductively to the metal plate via an insulating substrate such as a printed wiring board. However, there is a problem that heat radiation from the IC chip adhered non-conductively is poor. Further, when one of the IC chips is electrically conductively bonded to a metal plate without passing through an insulating substrate such as a printed wiring board, there is a problem that the performance of an electric circuit is deteriorated due to noise.

【0004】本発明の目的はかかる課題を解決し、複数
の異種のICチップを単一のICパッケージに内蔵し、
ノイズに強く、放熱性の高い樹脂封止ICパッケージを
提供することにある。
[0004] An object of the present invention is to solve such a problem and to incorporate a plurality of different types of IC chips into a single IC package.
An object of the present invention is to provide a resin-sealed IC package that is resistant to noise and has high heat dissipation.

【0005】[0005]

【課題を解決するための手段】本発明の半導体装置の製
造方法は、第1の集積回路チップと、第2の集積回路チ
ップと、該第1の集積回路チップの裏面に接着された第
1の金属板と、該第2の集積回路チップの裏面に接着さ
れた第2の金属板と、該第1の集積回路チップおよび該
第2の集積回路チップを各々内蔵するデバイスホールが
設けられ該第1の金属板および該第2の金属板に接着さ
れた配線基板と、該集積回路チップの表面に設けられた
電極群と該配線基板の表面に設けられた電極群とを接続
する金属細線群とを含んでなる回路ブロックを準備する
工程と、該回路ブロックを樹脂封止用金型内に該第1の
金属板と該第2の金属板の表面が該金型の内面に接する
ように載置し、該金型内に封止用樹脂を注入する工程と
を含んでなる半導体装置の製造方法において、該第1の
金属板と該第2の金属板とで形成される間隙の方向に封
止用樹脂の流入する方向を概略一致させることを特徴と
する。
A method of manufacturing a semiconductor device according to the present invention comprises a first integrated circuit chip, a second integrated circuit chip, and a first integrated circuit chip bonded to the back surface of the first integrated circuit chip. A metal plate, a second metal plate adhered to the back surface of the second integrated circuit chip, and device holes respectively containing the first integrated circuit chip and the second integrated circuit chip. A wiring board adhered to the first metal plate and the second metal plate; a thin metal wire connecting an electrode group provided on the surface of the integrated circuit chip to an electrode group provided on the surface of the wiring board; And a step of preparing a circuit block including the group, and placing the circuit block in a resin sealing mold so that the surfaces of the first metal plate and the second metal plate are in contact with the inner surface of the mold. And injecting a sealing resin into the mold. The method of manufacturing a device, and wherein the match schematically the direction of flow of the gap sealing resin in the direction of which is formed by the first metal plate and the second metal plate.

【0006】[0006]

【0007】[0007]

【作用】例えばアナログICチップとディジタルICチ
ップといった異種のICチップのいずれもがプリント配
線基板等の絶縁性基板を介さず熱抵抗の低い導電性接着
剤により各々金属板(載置台)に接着され、金属板の一
部は封止樹脂から露出されているので、アナログICチ
ップ、ディジタルICチップ間のノイズの伝達を防ぎ、
アナログICチップおよびディジタルICチップが動作
時に発生する熱は熱伝導の良い導電性接着剤を介してダ
イパッドの金属板から放熱される。
Both of different types of IC chips, such as an analog IC chip and a digital IC chip, are each bonded to a metal plate (mounting table) by a conductive adhesive having a low thermal resistance without passing through an insulating substrate such as a printed wiring board. Since a part of the metal plate is exposed from the sealing resin, it prevents noise transmission between the analog IC chip and the digital IC chip,
The heat generated during the operation of the analog IC chip and the digital IC chip is radiated from the metal plate of the die pad via a conductive adhesive having good heat conductivity.

【0008】[0008]

【実施例】図1に本発明によるICパッケージの断面図
を示す。図1において、11、12はそれぞれ第1、第
2のICチップであり、本例では11はアナログICチ
ップ、12はディジタルICチップ、21はアナログI
Cチップを載置固定する金属板、22はディジタルIC
チップを載置固定する金属板である。アナログICチッ
プ11は接着剤5により金属板21に接着されている。
同様にディジタルICチップ12は接着剤5により金属
板22に接着されている。3は一枚の配線基板で、アナ
ログICチップ11、ディジタルICチップ12を載置
する領域には、各々のチップが無理なく搭載できる大き
さの(チップサイズより片側1mm程度大きい)デバイ
スホール6が設けられている。配線基板3は接着剤5に
より金属板21、22と接着されている。従って金属板
21、22の平面的な大きさはこのデバイスホールの周
辺の少なくとも3点で配線基板3と重なる大きさにす
る。配線基板3の下面7のデバイスホール周辺には銅箔
の上にニッケルメッキ、さらにその上に金メッキが施さ
れた複数の電極(図示せず)があり、ICチップ上の対
応する電極(図示せず)と金属細線4で結ばれている。
また、図示してないが配線基板3には所望の回路機能を
実現すべく設計された金属配線が少なくとも下面7には
あり、前記配線基板下面7の電極、あるいはリード2と
電気的に接続している。また、必要に応じて上面8およ
び配線基板内にも金属配線が設けられ、これらの配線を
電気的に接続するバイアホールが設けられる。2はリー
ドでICパッケージ内の回路を外部回路と電気的に接続
する。リードは金属で、材質としては42アロイあるい
は銅アロイが用いられる。リード2の曲げ方向は金属板
21、22の露出部がパッケージ搭載板側にこないよう
に図示した向きに曲げるのが普通である。金属板21、
22の露出部がパッケージ搭載板側に来た場合は、放熱
フィンを露出部に付加して更に放熱性能を上げることが
不可能になる。1は封止樹脂で、ICチップ11、1
2、配線基板3、金属細線4などを外部からの機械的衝
撃から保護する。金属板21、22のICチップを搭載
した面と反対の面は封止樹脂1から露出している。この
ためアナログICチップ11、ディジタルICチップ1
2に電源が印加され動作するときに発する熱を空気中に
容易に放出できる。また、アナログICチップ11の載
置台である金属板21、ディジタルICチップ12の載
置台である金属板は電気的に完全に分離されているので
ICの動作時に金属板を通してディジタルICチップ1
2のノイズがアナログICチップ11に伝搬して回路の
性能を落とす事がない。
1 is a sectional view of an IC package according to the present invention. In FIG. 1, reference numerals 11 and 12 denote first and second IC chips, respectively. In this example, 11 is an analog IC chip, 12 is a digital IC chip, and 21 is an analog IC chip.
Metal plate for mounting and fixing C chip, 22 is a digital IC
A metal plate on which the chip is mounted and fixed. The analog IC chip 11 is adhered to the metal plate 21 by the adhesive 5.
Similarly, the digital IC chip 12 is bonded to the metal plate 22 by the adhesive 5. Reference numeral 3 denotes a single wiring board. In a region where the analog IC chip 11 and the digital IC chip 12 are mounted, a device hole 6 large enough to mount each chip without difficulty (about 1 mm larger on one side than the chip size) is provided. Is provided. The wiring board 3 is bonded to the metal plates 21 and 22 with the adhesive 5. Therefore, the planar size of the metal plates 21 and 22 is set to a size that overlaps the wiring board 3 at at least three points around the device hole. Around the device hole on the lower surface 7 of the wiring board 3, there are a plurality of electrodes (not shown) formed by nickel plating on a copper foil and further gold plating on the copper foil, and corresponding electrodes (not shown) on an IC chip. ) And a thin metal wire 4.
Although not shown, at least the lower surface 7 of the wiring board 3 has metal wiring designed to realize a desired circuit function, and is electrically connected to the electrode or the lead 2 of the lower surface 7 of the wiring board. ing. Also, metal wiring is provided on the upper surface 8 and the wiring board as necessary, and via holes for electrically connecting these wirings are provided. 2 is a lead for electrically connecting a circuit in the IC package to an external circuit. The lead is made of metal, and is made of 42 alloy or copper alloy. The bending direction of the lead 2 is generally bent in the illustrated direction such that the exposed portions of the metal plates 21 and 22 do not come to the package mounting plate side. Metal plate 21,
When the exposed portion 22 comes to the package mounting plate side, it becomes impossible to further increase the heat radiation performance by adding a heat radiation fin to the exposed portion. Reference numeral 1 denotes a sealing resin;
2. Protect the wiring board 3, the thin metal wires 4 and the like from external mechanical shocks. The surfaces of the metal plates 21 and 22 opposite to the surface on which the IC chip is mounted are exposed from the sealing resin 1. Therefore, the analog IC chip 11, the digital IC chip 1
2 can be easily released into the air when power is applied to the device and the device operates. Further, the metal plate 21 serving as the mounting table for the analog IC chip 11 and the metal plate serving as the mounting table for the digital IC chip 12 are completely separated electrically.
The noise of No. 2 does not propagate to the analog IC chip 11 to lower the performance of the circuit.

【0009】本発明による半導体装置は以下のように製
造する。
The semiconductor device according to the present invention is manufactured as follows.

【0010】(1)まず、所望の回路機能を得るべく設
計された配線、バイアホールと、金属細線を接続するパ
ッドおよびリードを接続するパッドが表面端部に設けら
れるとともに、その中にアナログICチップを入れる為
のデバイスホール6と、その中にディジタルICチップ
を入れる為のデバイスホール6が開けられたプリント基
板3を用意する。前記パッドはいずれも銅箔の上にニッ
ケルメッキが、更にその上に金メッキが施されている。
プリント基板3の基材としてはポリイミドやBTレジン
などのFR−5以上の耐熱性にすぐれたものが望まし
い。この理由は、後の工程で加熱することが必要だから
である。
(1) First, wiring and via holes designed to obtain a desired circuit function, pads for connecting thin metal wires, and pads for connecting leads are provided at the end of the surface, and an analog IC is provided therein. A printed circuit board 3 having a device hole 6 for inserting a chip and a device hole 6 for inserting a digital IC chip therein is prepared. Each of the pads is provided with a nickel plating on a copper foil and a gold plating thereon.
It is desirable that the substrate of the printed circuit board 3 be made of polyimide, BT resin, or the like, which has excellent heat resistance of FR-5 or more. The reason for this is that heating is required in a later step.

【0011】(2)次いで、図4(a)に示すようにリ
ードフレーム40の錫メッキを施されたリード内端と前
記のプリント基板表面端部に設けられ金メッキの施され
たパッドとを熱圧着して接続する。金ー錫共晶合金は融
点が高いので後の工程における高温に耐えられるととも
に信頼性も高く接着強度も強い。他の接続方法としては
Sn90%Pb10%,液相線融点が220℃程度の高
融点半田を用いる方法もある。高融点半田を用いる理由
は後の工程で加熱することが必要だからである。また別
の方法としては、リード内端のメッキを金メッキ(リー
ド材質が42アロイの場合)または銀メッキ(リード材
質が銅アロイの場合)とし、前記プリント基板裏面端部
をタブ吊りリードに接着したのち、リード内端とプリン
ト基板表面端部に設けられ金メッキの施されたパッドと
を金細線で接続する方法もある。
(2) Then, as shown in FIG. 4 (a), the inner ends of the tin-plated leads of the lead frame 40 and the gold-plated pads provided on the surface ends of the printed circuit board are heated. Crimp and connect. The gold-tin eutectic alloy has a high melting point so that it can withstand high temperatures in later steps, and has high reliability and high bonding strength. As another connection method, there is a method using a high melting point solder having Sn 90% Pb 10% and a liquidus melting point of about 220 ° C. The reason why the high melting point solder is used is that it is necessary to heat in a later step. As another method, gold plating (when the lead material is 42 alloy) or silver plating (when the lead material is copper alloy) is applied to the inner end of the lead, and the back end of the printed circuit board is bonded to the tab suspension lead. After that, there is also a method of connecting the inner ends of the leads and the pads provided on the surface end of the printed circuit board and provided with gold plating with gold fine wires.

【0012】(3)次いで、図4(b)に示すように2
枚の金属板21、22を前記プリント基板3に接着剤5
を使って接着する。エポキシ系の接着剤をプリント基板
のデバイスホール周辺部に塗布し、金属板をアナログI
Cチップ用のデバイスホール、ディジタルICチップ用
のデバイスホールをそれぞれ塞ぐように配置したのち1
00〜200℃・1時間ほど加熱乾燥し固着した。
(3) Next, as shown in FIG.
The two metal plates 21 and 22 are attached to the printed circuit board 3 with an adhesive 5
Glue using Epoxy adhesive is applied around the device hole of the printed circuit board, and the metal plate is
After arranging so as to cover the device hole for the C chip and the device hole for the digital IC chip, respectively,
It was dried by heating at 00 to 200 ° C. for about 1 hour to fix it.

【0013】(4)次いで、金属板21、22がプリン
ト基板3のデバイスホール6により露出した面に銀ペー
ストなどの導電性接着剤を用いてアナログICチップ、
ディジタルICチップを接着する。
(4) Next, an analog IC chip is formed on the surfaces of the printed circuit board 3 where the metal plates 21 and 22 are exposed by the device holes 6 by using a conductive adhesive such as silver paste.
Adhere the digital IC chip.

【0014】金属板がデバイスホールにより露出した部
分に銀ペーストを塗布し、アナログICチップ、ディジ
タルICチップを搭載したのち100〜200℃・1時
間ほど加熱乾燥し固着した。
A silver paste was applied to a portion where the metal plate was exposed by the device hole, and after mounting an analog IC chip and a digital IC chip, it was heated and dried at 100 to 200 ° C. for 1 hour to be fixed.

【0015】(5)次いで、図4(c)に示すようにI
Cチップ11、12の表面に設けられた電極と配線基板
の表面に設けられた電極とを金属細線4で接続する。金
属細線としては直径30ミクロンメートルの金線を用い
超音波併用熱圧着法で接続した。他にもアルミ線を超音
波法で接続する方法や、TABリードを用いて接続する
方法もある。
(5) Next, as shown in FIG.
The electrodes provided on the surfaces of the C chips 11 and 12 and the electrodes provided on the surface of the wiring board are connected by the thin metal wires 4. As a thin metal wire, a gold wire having a diameter of 30 μm was used and connected by a thermocompression bonding method using ultrasonic waves. In addition, there are a method of connecting an aluminum wire by an ultrasonic method and a method of connecting by using a TAB lead.

【0016】(6)以上の工程を経たリードフレーム
を、図4(d)に示すように樹脂封止用モールド金型3
0に前記金属板21、22の表面が金型の内面に接する
ように装填し、樹脂封止する。この時、図3に示すよう
に金属板21と金属板22とでできる間隙23の方向と
封止用樹脂の流入する方向24を一致させる。(図3で
は左下から右上の方向になる。)こうする事により樹脂
の流入がスムーズにでき空洞等の発生を抑えることがで
きる。なお、図3において30はモールド金型、40は
リードフレームである。封止方法としては最も一般的な
トランスファモールド法を、モールド材としてはやはり
一般的でよく使われているクレゾールノボラック系のエ
ポキシ樹脂を用いた。パッケージ厚みを薄くするような
場合は、クラックの発生しにくいビフェニール系のモー
ルド材が適する。
(6) The lead frame having undergone the above-described steps is mounted on a resin mold 3 as shown in FIG.
0 is mounted so that the surfaces of the metal plates 21 and 22 are in contact with the inner surface of the mold, and are sealed with a resin. At this time, as shown in FIG. 3, the direction of the gap 23 formed between the metal plate 21 and the metal plate 22 matches the direction 24 in which the sealing resin flows. (In FIG. 3, the direction is from the lower left to the upper right.) By doing so, the inflow of the resin can be made smooth and the occurrence of cavities and the like can be suppressed. In FIG. 3, reference numeral 30 denotes a mold, and reference numeral 40 denotes a lead frame. The most common transfer molding method was used as a sealing method, and a cresol novolak-based epoxy resin, which is also commonly used, was used as a molding material. In the case where the package thickness is reduced, a biphenyl-based molding material that is less likely to crack is suitable.

【0017】(7)次いで、図4(e)に示すようにリ
ードフレームは通常の手段によってフレームおよびダム
バーが切断除去され、外部リード2は所望の形状に成形
される。
(7) Next, as shown in FIG. 4 (e), the frame and the dam bar are cut and removed from the lead frame by ordinary means, and the external lead 2 is formed into a desired shape.

【0018】[0018]

【発明の効果】アナログICチップ、ディジタルICチ
ップが単一のパッケージに封止でき、アナログ回路、デ
ィジタル回路で電源、グランドが分離されているため、
アナログ回路にディジタル回路のノイズが影響すること
がない。また、放熱性に優れているため高速で動作する
消費電力の大きいICでもチップの動作温度が上昇しな
いので性能が落ちることがない。
As described above, the analog IC chip and the digital IC chip can be sealed in a single package, and the power supply and the ground are separated in the analog circuit and the digital circuit.
The analog circuit is not affected by the noise of the digital circuit. In addition, even in an IC that operates at high speed and consumes a large amount of power because of its excellent heat dissipation, the operating temperature of the chip does not increase, so that the performance does not decrease.

【0019】また、樹脂封止工程においてアナログIC
チップのダイパッドである金属板とディジタルICチッ
プのダイパッドである金属板とでできる間隙の方向と封
止用樹脂の流入する方向を一致させたので、空洞等の発
生を抑えることができ信頼性の高い半導体装置を製造す
ることができる。
In the resin sealing step, an analog IC
Since the direction of the gap between the metal plate, which is the die pad of the chip, and the metal plate, which is the die pad of the digital IC chip, is matched with the direction in which the sealing resin flows, the generation of cavities and the like can be suppressed, and reliability can be reduced. A high semiconductor device can be manufactured.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例。ICパッケージの断面図。FIG. 1 shows an embodiment of the present invention. FIG. 2 is a cross-sectional view of an IC package.

【図2】従来例。ICパッケージの断面図。FIG. 2 is a conventional example. FIG. 2 is a cross-sectional view of an IC package.

【図3】本発明の実施例。樹脂封止工程における樹脂の
流入を説明する平面図。
FIG. 3 shows an embodiment of the present invention. FIG. 4 is a plan view for explaining inflow of resin in a resin sealing step.

【図4】本発明の実施例。製造工程を説明する図。FIG. 4 shows an embodiment of the present invention. The figure explaining a manufacturing process.

【符号の説明】[Explanation of symbols]

1 封止樹脂 2 リード 3 配線基板 4 金属細線 5 接着剤 6 デバイスホール 7 配線基板の下面 8 配線基板の上面 11 アナログICチップ 12 ディジタルICチップ 20 ダイパッドである金属板 21 アナログICチップのダイパッドである金属板 22 ディジタルICチップのダイパッドである金属板 30 モールド金型 40 リードフレーム DESCRIPTION OF SYMBOLS 1 Encapsulation resin 2 Lead 3 Wiring board 4 Fine metal wire 5 Adhesive 6 Device hole 7 Lower surface of wiring substrate 8 Upper surface of wiring substrate 11 Analog IC chip 12 Digital IC chip 20 Metal plate which is a die pad 21 A die pad of an analog IC chip Metal plate 22 Metal plate as die pad of digital IC chip 30 Mold 40 Lead frame

フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 21/56 H01L 23/34 - 23/473 H01L 25/00 - 25/18 Continuation of the front page (58) Field surveyed (Int. Cl. 7 , DB name) H01L 21/56 H01L 23/34-23/473 H01L 25/00-25/18

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 第1の集積回路チップと、 第2の集積回路チップと、 該第1の集積回路チップの裏面に接着された第1の金属
板と、 該第2の集積回路チップの裏面に接着された第2の金属
板と、 該第1の集積回路チップおよび該第2の集積回路チップ
を各々内蔵するデバイスホールが設けられ該第1の金属
板および該第2の金属板に接着された配線基板と、 該集積回路チップの表面に設けられた電極群と該配線基
板の表面に設けられた電極群とを接続する金属細線群と
を含んでなる回路ブロックを準備する工程と、 該回路ブロックを樹脂封止用金型内に該第1の金属板と
該第2の金属板の表面が該金型の内面に接するように載
置し、該金型内に封止用樹脂を注入する工程とを含んで
なる半導体装置の製造方法において、 該第1の金属板と該第2の金属板とで形成される間隙の
方向に封止用樹脂の流入する方向を概略一致させること
を特徴とする半導体装置の製造方法。
A first integrated circuit chip; a second integrated circuit chip; a first metal plate adhered to a back surface of the first integrated circuit chip; and a back surface of the second integrated circuit chip A second metal plate adhered to the first integrated circuit chip, and device holes respectively containing the first integrated circuit chip and the second integrated circuit chip are provided, and are bonded to the first metal plate and the second metal plate. Preparing a circuit block including a wiring substrate, and an electrode group provided on the surface of the integrated circuit chip and a thin metal wire group connecting the electrode group provided on the surface of the wiring substrate; The circuit block is placed in a mold for resin sealing such that the surfaces of the first metal plate and the second metal plate are in contact with the inner surface of the mold, and the resin for sealing is placed in the mold. Implanting a semiconductor device, the method comprising the steps of: The method of manufacturing a semiconductor device, characterized in that to substantially aligned with the direction of flow of the sealing resin in the direction of the gap formed by the second metal plate.
JP5632895A 1995-03-15 1995-03-15 Method for manufacturing semiconductor device Expired - Fee Related JP3314574B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5632895A JP3314574B2 (en) 1995-03-15 1995-03-15 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5632895A JP3314574B2 (en) 1995-03-15 1995-03-15 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH08255868A JPH08255868A (en) 1996-10-01
JP3314574B2 true JP3314574B2 (en) 2002-08-12

Family

ID=13024128

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5632895A Expired - Fee Related JP3314574B2 (en) 1995-03-15 1995-03-15 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP3314574B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6473310B1 (en) * 2000-02-18 2002-10-29 Stmicroelectronics S.R.L. Insulated power multichip package
US6867493B2 (en) * 2000-11-15 2005-03-15 Skyworks Solutions, Inc. Structure and method for fabrication of a leadless multi-die carrier
JP4667666B2 (en) * 2001-07-16 2011-04-13 ローム株式会社 Chip array module
JP2009170785A (en) * 2008-01-18 2009-07-30 Renesas Technology Corp Semiconductor device

Also Published As

Publication number Publication date
JPH08255868A (en) 1996-10-01

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