JP2009170785A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which is made compact and stably operates. <P>SOLUTION: The semiconductor device is a semiconductor device having a plurality of chips sealed in one package, and includes a die pad 500, an A/D converter 100 which is mounted on the die pad 500 and has a circuit for conversion from an analog signal to a digital signal, an image processor 200 which is mounted on the die pad 500 and has a circuit for processing at least the digital signal, a wire 700B connecting the A/D converter 100 and image processor 200 to each other to transmit the digital signal between the A/D converter 100 and image processor 200, and a sealing resin 900 sealing the A/D converter 100 mounted on the die pad 500 and an MCU 200. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a plurality of LSI chips are sealed in one package to form a SiP (System in Package).

  Japanese Patent Application Laid-Open No. 11-340421 (Patent Document 1) describes an LSI device in which input / output terminals are arranged side by side along opposite sides of a logic chip and a memory chip. ing.

  Japanese Patent Laid-Open No. 6-232196 (Patent Document 2) describes a semiconductor device in which pads located on opposite sides of a main chip and a sub chip mounted on an island are connected via wires. Has been.

  Further, in Japanese Patent Laid-Open No. 8-288453 (Patent Document 3), the first semiconductor chip mounted on the wiring board and the second and third semiconductor chips are provided on opposite sides, respectively. A semiconductor device in which pads are connected via wires is described.

  Japanese Patent Application Laid-Open No. 5-114693 (Patent Document 4) discloses a semiconductor device in which pads provided on opposite sides of a plurality of semiconductor chips mounted on a bed are connected via bonding wires. Are listed.

  Japanese Laid-Open Patent Publication No. 10-93009 (Patent Document 5) describes a semiconductor chip module in which pads adjacent to each other in two bare chip LSIs mounted on an MCM substrate are connected via bonding wires. .

  Japanese Laid-Open Patent Publication No. 6-61406 (Patent Document 6) describes a semiconductor device in which electrodes located on opposite sides of two chips mounted on an island of a lead frame are connected by connection leads. ing.

  Japanese Patent Laid-Open No. 2007-318060 (Patent Document 7) discloses a digital chip and an analog chip in an SiP (System in Package) type semiconductor device in order to reduce the influence of digital noise from the digital chip to the analog chip. It is described that a structure is often taken on the same plane.

Japanese Patent Laying-Open No. 2003-124236 (Patent Document 8) discloses a technique for reducing interference of electromagnetic wave noise between an analog element and a digital element in a stack package in which the analog element and the digital element are accommodated in the same package. In addition, it is described that a material made of a composite material including an organic material having adhesiveness and a soft magnetic material is used as an adhesive material for bonding an analog element and a digital element.
Japanese Patent Laid-Open No. 11-340421 JP-A-6-232196 JP-A-8-288453 Japanese Patent Laid-Open No. 5-114693 JP 10-93009 A JP-A-6-61406 JP 2007-318060 A JP 2003-124236 A

  A semiconductor device can be reduced in size by housing a circuit that handles analog signals (analog circuit) and a circuit that handles digital signals (digital circuit) in one package.

  However, in consideration of the size and operation reliability of the semiconductor device, it has been sufficiently studied so far whether it is optimal to store the analog circuit and the digital circuit in one package in any form. Absent.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device that is downsized and operates stably.

  A semiconductor device according to an embodiment of the present invention is a semiconductor device in which a plurality of chips are sealed in one package, and is a first chip mounted on a base material and formed with an analog circuit. A second chip that is mounted on a base material, at least a digital circuit is formed, and that is configured with transistors having a line width smaller than that of the transistors that configure the first chip, and the first chip and the second chip A connecting portion for transmitting a digital signal between the first chip and the second chip, and a sealing portion for sealing the first chip and the second chip mounted on the substrate Prepare.

  In digital circuits, the number of transistors tends to increase as the number of functions increases. A semiconductor chip on which a circuit for processing a digital signal is integrated can be reduced in size along with transistor miniaturization technology. An analog circuit is easily affected by noise due to the nature of handling an analog signal, and in particular, as the transistor becomes finer, the tendency of the analog circuit is impaired, and the reliability of the operation of the analog circuit is impaired. However, the number of transistors is small because analog circuits are not required to have more functions than digital circuits.

Therefore, instead of configuring the analog circuit and the digital circuit with one semiconductor chip,
Transistors each composed of separate first and second semiconductor chips, having a SiP structure in which the first and second semiconductor chips are sealed with resin, and having a smaller line width than the transistors constituting the first semiconductor chip Thus, by configuring the second semiconductor chip, the second semiconductor chip can be reduced in chip size, while the first chip can guarantee its stable operation and can also suppress the chip size. Therefore, according to this embodiment, it is possible to provide a semiconductor device that is downsized and operates stably.

  Embodiments of the present invention will be described below. Note that the same or corresponding parts are denoted by the same reference numerals, and the description thereof may not be repeated.

  Note that in the embodiments described below, when referring to the number, amount, and the like, the scope of the present invention is not necessarily limited to the number, amount, and the like unless otherwise specified. In the following embodiments, each component is not necessarily essential for the present invention unless otherwise specified. In addition, when there are a plurality of embodiments below, it is planned from the beginning to appropriately combine the configurations of the embodiments unless otherwise specified.

  FIG. 1 is a block diagram showing a schematic configuration of an image display apparatus including a semiconductor device according to an embodiment of the present invention. Referring to FIG. 1, an image display device 1 according to the present embodiment is, for example, a liquid crystal display (LCD), and includes an A / D converter (Analog-to-Digital Converter) 100 and a CPU. An image processor 200 including a (Central Processing Unit), a timing controller 300, an LCD driver 350, a DRAM 400, and a nonvolatile memory (flash memory) 450, each of which is realized by a single semiconductor chip. The

  The A / D converter 100 includes an analog-digital conversion circuit that converts an analog electric signal into a digital electric signal. An image signal which is an analog signal is input to the A / D converter 100 (arrow A in FIG. 1). The A / D converter 100 converts the input analog signal into a digital signal, and outputs the digital image signal to the image processor 200 (arrow B in FIG. 1). There is no exchange of analog signals between the image processor 200 and the A / D converter 100.

  The image processor 200 includes a logic circuit and performs various logic processes on the input digital signal. Examples of processing performed here include YC separation, IP (Interlace / Progressive) conversion, NR (noise reduction), and the like. Note that YC separation means that a luminance signal (Y signal) and a color signal (C signal) included in a video signal are separated, and IP conversion means that an interlace signal is applied to a progressive display device. It means that the signal is converted into a suitable signal, and NC means that the sound data is analyzed and noise components are cut.

  The image processor 200 performs various processes including the above-described processes on the digital signal input from the A / D converter 100, and outputs the processed digital signal to the timing controller 300 (in FIG. 1). Arrow C1). The timing controller 300 controls the timing of outputting an image signal to a display that displays an image. The LCD driver 350 receives an image signal whose timing is controlled from the timing controller 300 and displays an image on the display.

  The DRAM 400 is connected to the image processor 200. The DRAM 400 is a buffer memory that can temporarily store digital signal data and processed digital signal data received by the image processor 200 from the A / D converter 100. Bidirectional digital signals are exchanged between the image processor 200 and the DRAM 400 (arrow D in FIG. 1). Various codes are stored in the nonvolatile memory 450, and the image processor 200 reads the codes from the nonvolatile memory 450 (arrow C2 in FIG. 1) and executes the codes. Although not shown, various other control signals are exchanged between the image processor 200 and each of the other three chips connected thereto.

  In the semiconductor device according to the present embodiment, three semiconductor chips of the A / D converter 100, the image processor 200, and the DRAM 400 shown in FIG. Package) structure.

  FIG. 2 is a top view showing the appearance of the semiconductor device, and FIG. 3 is a schematic diagram showing the arrangement of semiconductor chips in the semiconductor device and the connection of bonding wires to which the semiconductor chips are connected. FIG. 4 is a top view showing a part of the lead frame in the semiconductor device together with the arrangement of the semiconductor chips. FIG. 5 is a cross-sectional view taken along the line VV in FIGS. 2 and 4.

  Referring to FIG. 2, the semiconductor device according to the present embodiment is provided with external terminals 800A and 800C arranged along the four sides of the main body sealed with sealing resin 900 and having gull-wing-shaped tips. This is a so-called QFP (Quad Flat Package) type package.

  As will be described later, the connection between the A / D converter 100 and the outside is performed by an external terminal 800A provided on one side of the apparatus, and the external terminal 800C provided on the other three sides is connected to the image processor 200 and the outside. Used to connect to.

  3 to 5, a semiconductor device according to the present embodiment includes an A / D converter 100 (analog chip), an image processor 200 (digital chip) having a chip area larger than that of the A / D converter 100, It includes a DRAM 400 (buffer unit) that is stacked on the image processor 200 and connected to the image processor 200 via a wire 700D. The lead frame used in the present semiconductor device is formed of a conductor such as copper, for example. The lead frame includes two die pads 500 (base material) on which the A / D converter 100 and the image processor 200 are respectively mounted, a connecting portion 520 that connects these die pads, and four outer parts of the semiconductor device that are connected to the die pad 500. Four suspension leads 510A to 510D each extending toward the corner, three ground bars GND2 connected between two suspension leads adjacent to the three suspension leads 510A, 510C, 510D, and an A / D converter 100-the image processor 200 is connected, and a wire 700B (connection unit) that transmits a digital signal between the A / D converter 100 and the image processor 200, and the A / D converter 100 and the image via the wires 700A and 700C. External terminals 80 respectively connected to the processor 200 A, (in Fig. 4, it shows the inner lead portions within the encapsulating resin connected respectively to external terminals) 800C and a. In the semiconductor device, the die pad 500, the suspension leads 510A to 510D, the connecting portion 520, and the ground bar GND2 are integrally formed.

  The semiconductor device includes a lead frame portion excluding the external terminal portion of the lead frame, a sealing resin 900 (sealing portion) that seals the A / D converter 100, the image processor 200, and the DRAM 300. Consists of.

  In this embodiment, the A / D converter 100 and the image processor 200 are manufactured with different process rules (line width of the MOS transistor, specifically, the gate width of the MOS transistor). . Specifically, the A / D converter 100 that is an analog chip is manufactured by a 180 nm process, and the image processor 200 that is a digital chip is manufactured by a 90 nm process smaller than the A / D converter 100. In other words, digital chips are manufactured with finer process rules than analog chips. Since a digital chip processes multifunctional logic signals, the number of transistors is larger than that of an analog chip. Therefore, the semiconductor device can be miniaturized by manufacturing the digital chip by a fine process. On the other hand, an analog chip handles analog signals, so that operation reliability is stricter than a digital chip for miniaturization. Therefore, in an analog chip, a more stable operation of a semiconductor device can be ensured by applying a larger process rule to a digital chip. Moreover, since the analog chip has fewer transistors than the logic chip, the chip does not become so large as to hinder downsizing of the semiconductor device. The analog chip and the digital chip may be manufactured according to the same process rule.

  The semiconductor device according to the present embodiment is mounted on a mounting board in the liquid crystal display device together with the nonvolatile memory 450. In this embodiment, by forming a semiconductor device by forming a plurality of chips into SiP, the semiconductor device can be easily mounted on a mounting board and the semiconductor device itself can be downsized. The timing controller 300 and the LCD driver 350 are usually mounted on a liquid crystal panel.

  As shown in FIG. 4, the A / D converter 100 has a substantially quadrangular shape, and the pad portions 110 </ b> A, 110 </ b> A are arranged in areas near two opposite sides (sides located on the left and right in FIG. 4). 110B. Similar to the A / D converter 100, the image processor 200 has a substantially quadrangular shape. The image processor 200 is mounted on the lead frame 500 so as to be positioned on the same plane as the A / D converter 100. That is, the semiconductor device according to the present embodiment has a structure (“flat placement” structure) in which A / D converter 100 and image processor 200 are arranged in the main surface direction of lead frame 500. . The image processor 200 has a pad portion 210B in a region located in the vicinity of the side facing the A / D converter 100 (the side located on the left side in FIG. 4), and is in the vicinity of the side and the pad portion 21B. A pad portion 210C is provided in a region located in the vicinity of the other two sides and the other three sides. The DRAM 400, like the A / D converter 100 and the image processor 200, has a substantially quadrangular shape and has a pad 410D in an area located near one side (the side located on the right side in the example of FIG. 4). Have Further, the image processor 200 has a pad 210D at a portion facing the pad 410D. Each pad portion is formed with a plurality of pads.

  A wire 700A (see FIG. 4) that connects the A / D converter 100 and each external terminal 800A is connected to the A / D converter 100 in the pad portion 110A. The wire 700A transmits an analog image signal input from the external terminal 800A to the A / D converter 100 via the pad unit 110A.

  A wire 700B (see FIG. 4) that connects the A / D converter 100 and the image processor 200 is connected to the A / D converter 100 in the pad portion 110B, and is connected to the image processor 200 in the pad portion 210B. The wire 700B transmits a digital image signal output from the A / D converter 100 via the pad unit 110B to the image processor 200 via the pad unit 210B.

  A wire 700C (see FIG. 4) that connects the image processor 200 and each external terminal 800C is connected to the image processor 200 at the pad portion 210C. The wire 700C transmits various processed digital image signals output from the image processor 200 via the pad 210D to the external terminal 800C.

  A wire 700D (see FIG. 5) that connects the image processor 200 and the DRAM 400 is connected to the image processor 200 in the pad portion 210D, and is connected to the DRAM 400 via the pad portion 410D. The wire 700D is responsible for transmission of data exchanged bidirectionally between the image processor 200 and the DRAM 400.

  In FIG. 4, a plated portion 810 is formed on the tip side of each external terminal 800 </ b> A, 800 </ b> C and the hatched portion of the ground bar GND <b> 2. For convenience of illustration, only the plating portion 810 in one external terminal 800C is shown, but the same plating portion 810 is formed in the other external terminals 800A and 800C.

  As shown in FIG. 4, a ground line terminal GND1 and a power line terminal Vdd1 are provided so as to be sandwiched between a plurality of external terminals 800A for analog image signals. The A / D converter 100 is connected to the ground line terminal GND1 and the power line terminal Vdd1 through wires. As shown in FIGS. 4 and 5, a ground line terminal GND2 and a power line terminal Vdd2 are provided between the die pad 500 and a plurality of external terminals 800C for digital image signals. The image processor 200 is connected to the ground line terminal GND2 and the power line terminal Vdd2 via wires.

  The tips of the inner leads (external terminals) are arranged in an approximately octagonal shape as a whole, and the semiconductor A / D converter 100 and the image processor 200 are surrounded by the external terminals 800A and 800C. Here, external terminals 800A for inputting analog image signals to the A / D converter 100 are intensively arranged on two sides of the substantially octagon located on the left side in FIG. On the other hand, external terminals 800C for exchanging digital signals with the outside of the apparatus including the output of digital image signals from the image processor 200 are concentrated on the remaining six sides located on the upper side, lower side and right side in FIG. Are arranged. As described above, in the semiconductor device according to the present embodiment, the region where the external terminal 800A for inputting an analog signal is formed is separated from the region where the external terminal 800C for outputting a digital signal is formed. Is formed. By doing in this way, it can suppress that the digital noise contained in a digital signal influences an analog signal.

  When two semiconductor chips (A / D converter 100 and image processor 200) are SiPs having a flat structure, in this embodiment, the area of the bonding portion of the die pad to which each semiconductor chip is bonded is viewed from above. A die pad smaller than the entire area of the semiconductor chip is employed.

  The die pad 500 on which the A / D converter 100 is mounted has a portion having a width W1 in the same direction as one side of the A / D converter 100 (long side direction in the figure). The die pad 500 on which the image processor 200 is mounted has a portion having a width W2 in the same direction as the width W1 and in the same direction as one side (long side direction in the figure) of the image processor 200. The connecting portion 520 has a width W3 in the same direction as the widths W1 and W2 in a portion where the A / D converter 100 and the image processor 200 are not joined. The width W3 is shorter than the widths W1 and W2.

  The die pad 500 on which the A / D converter 100 is mounted has a shape that is supported at three points by one connecting portion 520 and two suspension leads 510A and 510B, and the die pad 500 on which the image processor 200 is mounted is The connecting portion 520 and the two suspension leads 510C and 510D form a shape supported at three points.

  In the present embodiment, the “flat placement” structure in which the A / D converter 100 and the image processor 200 are arranged in the main surface direction of the lead frame 500 is illustrated, but the scope of the present invention is limited to this. Without limitation, the A / D converter 100 and the image processor 200 are arranged so as to overlap each other as long as the wire for transferring an analog signal and the wire for transferring a digital signal are separated to an extent that allows the influence of digital noise. A “stacked” structure may be employed.

  The analog chip is not limited to the A / D converter 100 of the present embodiment as long as it inputs or outputs a logic signal and processes an analog signal in the circuit or performs an analog circuit operation. . The analog chip may be, for example, a DAC (Digital-to-Analog Converter) having a digital-analog conversion circuit that receives a digital signal, converts it into an analog signal, and outputs the analog signal, or a PLL (Phase-locked loop) circuit. It may have, an audio switch function, and an audio multiplex switching function.

  On the other hand, the logic chip is not limited to the image processor 200 of the present embodiment as long as it is a logic IC that outputs or inputs a digital signal to and from an analog chip and mainly processes the digital signal. It is not excluded that a circuit for processing an analog signal is built in the logic chip as long as the process rules constituting the logic chip are acceptable in terms of operation reliability.

  In the present embodiment, a QFP (Quad Flat Package) in which external terminals (pins) for signal input / output are arranged on the outer periphery is illustrated, but the present invention is arranged in a lattice form as shown in FIG. The present invention may also be applied to a BGA (Ball Grid Array) type semiconductor device using ball-shaped solder electrodes as external terminals. That is, in the modification shown in FIG. 6, the A / D converter 100 (analog chip) and the image processor 200 (digital chip) are mounted on a substrate 1000 (base material) on which the solder balls 1100 are formed on the back surface. ing. The DRAM 400 (buffer unit) is stacked on the image processor 200 as in the examples of FIGS.

  In the present embodiment, a liquid crystal display device (LCD) is exemplified as the image display device 1, but instead of this, for example, a plasma display (PDP: Plasma Display Panel) may be used. Furthermore, the present invention is not limited to a semiconductor device for an image display device, and can be applied to any other device.

  Although the embodiments of the present invention have been described above, the embodiments disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a block diagram illustrating a schematic configuration of an image display device including a semiconductor device according to an embodiment of the present invention. FIG. 2 is a top view illustrating an appearance of a semiconductor device included in the image display device illustrated in FIG. 1. 1 is a plan view conceptually showing a semiconductor device according to an embodiment of the present invention. It is a top view which shows the semiconductor device which concerns on one embodiment of this invention. It is VV sectional drawing in FIG.2 and FIG.4. It is sectional drawing which shows the modification of the semiconductor device which concerns on one embodiment of this invention.

Explanation of symbols

  1 Image display device, 100 A / D converter, 110A, 110B, 210B, 210C, 210D, 410D Pad part, 200 Image processor, 300 Timing controller, 350 LCD driver, 400 DRAM, 450 Non-volatile memory, 500 Die pad, 510 Hanging Lead, 600 board, 700A, 700B, 700C, 700D wire, 800A, 800C external terminal, 810 plated portion, 900 sealing resin, 1000 substrate, 1100 solder ball, GND1 ground wire terminal, GND2 ground ground bar, Vdd1, Vdd2 Power supply terminal.

Claims (5)

A semiconductor device in which a plurality of chips are sealed in one package,
A substrate;
A first chip mounted on the substrate and formed with a circuit for processing analog signals;
A second chip that is mounted on the substrate and has a circuit for processing at least a digital signal, and is configured by a transistor having a smaller line width than a transistor that configures the first chip;
A connection part for connecting the first chip and the second chip and transmitting a digital signal between the first chip and the second chip;
A semiconductor device comprising: a sealing portion that seals the first chip and the second chip mounted on the base material.   The semiconductor device according to claim 1, wherein the first chip and the second chip are provided on a main surface of the base material so as to be aligned in a main surface direction of the base material. A buffer unit for temporarily storing digital signal data to be processed by the second chip;
The semiconductor device according to claim 2, wherein the buffer unit is stacked on the second chip.   4. The semiconductor device according to claim 1, further comprising an external terminal that inputs an analog signal from outside or outputs the analog signal to the outside, and the external terminal is connected to the first chip. 5. The first chip has a first side and a second side facing each other;
A first pad connected to an external terminal is formed on the first side;
5. The semiconductor device according to claim 1, wherein a second pad portion connected to the second chip via the connection portion is formed on the second side.

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